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9d9f78ed MT |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> | |
4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Simple multiplexer clock implementation | |
11 | */ | |
12 | ||
9d9f78ed MT |
13 | #include <linux/clk-provider.h> |
14 | #include <linux/module.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/err.h> | |
18 | ||
19 | /* | |
20 | * DOC: basic adjustable multiplexer clock that cannot gate | |
21 | * | |
22 | * Traits of this clock: | |
23 | * prepare - clk_prepare only ensures that parents are prepared | |
24 | * enable - clk_enable only ensures that parents are enabled | |
25 | * rate - rate is only affected by parent switching. No clk_set_rate support | |
26 | * parent - parent is adjustable through clk_set_parent | |
27 | */ | |
28 | ||
9d9f78ed MT |
29 | static u8 clk_mux_get_parent(struct clk_hw *hw) |
30 | { | |
31 | struct clk_mux *mux = to_clk_mux(hw); | |
497295af | 32 | int num_parents = clk_hw_get_num_parents(hw); |
9d9f78ed MT |
33 | u32 val; |
34 | ||
35 | /* | |
36 | * FIXME need a mux-specific flag to determine if val is bitwise or numeric | |
37 | * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 | |
38 | * to 0x7 (index starts at one) | |
39 | * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so | |
40 | * val = 0x4 really means "bit 2, index starts at bit 0" | |
41 | */ | |
aa514ce3 | 42 | val = clk_readl(mux->reg) >> mux->shift; |
ce4f3313 PDS |
43 | val &= mux->mask; |
44 | ||
45 | if (mux->table) { | |
46 | int i; | |
47 | ||
48 | for (i = 0; i < num_parents; i++) | |
49 | if (mux->table[i] == val) | |
50 | return i; | |
51 | return -EINVAL; | |
52 | } | |
9d9f78ed MT |
53 | |
54 | if (val && (mux->flags & CLK_MUX_INDEX_BIT)) | |
55 | val = ffs(val) - 1; | |
56 | ||
57 | if (val && (mux->flags & CLK_MUX_INDEX_ONE)) | |
58 | val--; | |
59 | ||
ce4f3313 | 60 | if (val >= num_parents) |
9d9f78ed MT |
61 | return -EINVAL; |
62 | ||
63 | return val; | |
64 | } | |
9d9f78ed MT |
65 | |
66 | static int clk_mux_set_parent(struct clk_hw *hw, u8 index) | |
67 | { | |
68 | struct clk_mux *mux = to_clk_mux(hw); | |
69 | u32 val; | |
70 | unsigned long flags = 0; | |
71 | ||
3837bd27 | 72 | if (mux->table) { |
ce4f3313 | 73 | index = mux->table[index]; |
3837bd27 | 74 | } else { |
ce4f3313 | 75 | if (mux->flags & CLK_MUX_INDEX_BIT) |
6793b3cd | 76 | index = 1 << index; |
ce4f3313 PDS |
77 | |
78 | if (mux->flags & CLK_MUX_INDEX_ONE) | |
79 | index++; | |
80 | } | |
9d9f78ed MT |
81 | |
82 | if (mux->lock) | |
83 | spin_lock_irqsave(mux->lock, flags); | |
661e2180 SB |
84 | else |
85 | __acquire(mux->lock); | |
9d9f78ed | 86 | |
ba492e90 HZ |
87 | if (mux->flags & CLK_MUX_HIWORD_MASK) { |
88 | val = mux->mask << (mux->shift + 16); | |
89 | } else { | |
aa514ce3 | 90 | val = clk_readl(mux->reg); |
ba492e90 HZ |
91 | val &= ~(mux->mask << mux->shift); |
92 | } | |
9d9f78ed | 93 | val |= index << mux->shift; |
aa514ce3 | 94 | clk_writel(val, mux->reg); |
9d9f78ed MT |
95 | |
96 | if (mux->lock) | |
97 | spin_unlock_irqrestore(mux->lock, flags); | |
661e2180 SB |
98 | else |
99 | __release(mux->lock); | |
9d9f78ed MT |
100 | |
101 | return 0; | |
102 | } | |
9d9f78ed | 103 | |
822c250e | 104 | const struct clk_ops clk_mux_ops = { |
9d9f78ed MT |
105 | .get_parent = clk_mux_get_parent, |
106 | .set_parent = clk_mux_set_parent, | |
e366fdd7 | 107 | .determine_rate = __clk_mux_determine_rate, |
9d9f78ed MT |
108 | }; |
109 | EXPORT_SYMBOL_GPL(clk_mux_ops); | |
110 | ||
c57acd14 TF |
111 | const struct clk_ops clk_mux_ro_ops = { |
112 | .get_parent = clk_mux_get_parent, | |
113 | }; | |
114 | EXPORT_SYMBOL_GPL(clk_mux_ro_ops); | |
115 | ||
264b3171 | 116 | struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, |
2893c379 SH |
117 | const char * const *parent_names, u8 num_parents, |
118 | unsigned long flags, | |
ce4f3313 PDS |
119 | void __iomem *reg, u8 shift, u32 mask, |
120 | u8 clk_mux_flags, u32 *table, spinlock_t *lock) | |
9d9f78ed MT |
121 | { |
122 | struct clk_mux *mux; | |
264b3171 | 123 | struct clk_hw *hw; |
0197b3ea | 124 | struct clk_init_data init; |
ba492e90 | 125 | u8 width = 0; |
264b3171 | 126 | int ret; |
ba492e90 HZ |
127 | |
128 | if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { | |
129 | width = fls(mask) - ffs(mask) + 1; | |
130 | if (width + shift > 16) { | |
131 | pr_err("mux value exceeds LOWORD field\n"); | |
132 | return ERR_PTR(-EINVAL); | |
133 | } | |
134 | } | |
9d9f78ed | 135 | |
27d54591 | 136 | /* allocate the mux */ |
1e28733e | 137 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); |
0b910402 | 138 | if (!mux) |
9d9f78ed | 139 | return ERR_PTR(-ENOMEM); |
9d9f78ed | 140 | |
0197b3ea | 141 | init.name = name; |
c57acd14 TF |
142 | if (clk_mux_flags & CLK_MUX_READ_ONLY) |
143 | init.ops = &clk_mux_ro_ops; | |
144 | else | |
145 | init.ops = &clk_mux_ops; | |
f7d8caad | 146 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
147 | init.parent_names = parent_names; |
148 | init.num_parents = num_parents; | |
149 | ||
9d9f78ed MT |
150 | /* struct clk_mux assignments */ |
151 | mux->reg = reg; | |
152 | mux->shift = shift; | |
ce4f3313 | 153 | mux->mask = mask; |
9d9f78ed MT |
154 | mux->flags = clk_mux_flags; |
155 | mux->lock = lock; | |
ce4f3313 | 156 | mux->table = table; |
31df9db9 | 157 | mux->hw.init = &init; |
9d9f78ed | 158 | |
264b3171 SB |
159 | hw = &mux->hw; |
160 | ret = clk_hw_register(dev, hw); | |
161 | if (ret) { | |
27d54591 | 162 | kfree(mux); |
264b3171 SB |
163 | hw = ERR_PTR(ret); |
164 | } | |
27d54591 | 165 | |
264b3171 SB |
166 | return hw; |
167 | } | |
168 | EXPORT_SYMBOL_GPL(clk_hw_register_mux_table); | |
169 | ||
170 | struct clk *clk_register_mux_table(struct device *dev, const char *name, | |
171 | const char * const *parent_names, u8 num_parents, | |
172 | unsigned long flags, | |
173 | void __iomem *reg, u8 shift, u32 mask, | |
174 | u8 clk_mux_flags, u32 *table, spinlock_t *lock) | |
175 | { | |
176 | struct clk_hw *hw; | |
177 | ||
178 | hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents, | |
179 | flags, reg, shift, mask, clk_mux_flags, | |
180 | table, lock); | |
181 | if (IS_ERR(hw)) | |
182 | return ERR_CAST(hw); | |
183 | return hw->clk; | |
9d9f78ed | 184 | } |
5cfe10bb | 185 | EXPORT_SYMBOL_GPL(clk_register_mux_table); |
ce4f3313 PDS |
186 | |
187 | struct clk *clk_register_mux(struct device *dev, const char *name, | |
2893c379 SH |
188 | const char * const *parent_names, u8 num_parents, |
189 | unsigned long flags, | |
ce4f3313 PDS |
190 | void __iomem *reg, u8 shift, u8 width, |
191 | u8 clk_mux_flags, spinlock_t *lock) | |
192 | { | |
193 | u32 mask = BIT(width) - 1; | |
194 | ||
195 | return clk_register_mux_table(dev, name, parent_names, num_parents, | |
196 | flags, reg, shift, mask, clk_mux_flags, | |
197 | NULL, lock); | |
198 | } | |
5cfe10bb | 199 | EXPORT_SYMBOL_GPL(clk_register_mux); |
4e3c021f | 200 | |
264b3171 SB |
201 | struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, |
202 | const char * const *parent_names, u8 num_parents, | |
203 | unsigned long flags, | |
204 | void __iomem *reg, u8 shift, u8 width, | |
205 | u8 clk_mux_flags, spinlock_t *lock) | |
206 | { | |
207 | u32 mask = BIT(width) - 1; | |
208 | ||
209 | return clk_hw_register_mux_table(dev, name, parent_names, num_parents, | |
210 | flags, reg, shift, mask, clk_mux_flags, | |
211 | NULL, lock); | |
212 | } | |
213 | EXPORT_SYMBOL_GPL(clk_hw_register_mux); | |
214 | ||
4e3c021f KK |
215 | void clk_unregister_mux(struct clk *clk) |
216 | { | |
217 | struct clk_mux *mux; | |
218 | struct clk_hw *hw; | |
219 | ||
220 | hw = __clk_get_hw(clk); | |
221 | if (!hw) | |
222 | return; | |
223 | ||
224 | mux = to_clk_mux(hw); | |
225 | ||
226 | clk_unregister(clk); | |
227 | kfree(mux); | |
228 | } | |
229 | EXPORT_SYMBOL_GPL(clk_unregister_mux); | |
264b3171 SB |
230 | |
231 | void clk_hw_unregister_mux(struct clk_hw *hw) | |
232 | { | |
233 | struct clk_mux *mux; | |
234 | ||
235 | mux = to_clk_mux(hw); | |
236 | ||
237 | clk_hw_unregister(hw); | |
238 | kfree(mux); | |
239 | } | |
240 | EXPORT_SYMBOL_GPL(clk_hw_unregister_mux); |