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e1bd55e5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9d9f78ed MT |
2 | /* |
3 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
4 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> | |
5 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
9d9f78ed MT |
7 | * Simple multiplexer clock implementation |
8 | */ | |
9 | ||
9d9f78ed MT |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/err.h> | |
15 | ||
16 | /* | |
17 | * DOC: basic adjustable multiplexer clock that cannot gate | |
18 | * | |
19 | * Traits of this clock: | |
20 | * prepare - clk_prepare only ensures that parents are prepared | |
21 | * enable - clk_enable only ensures that parents are enabled | |
22 | * rate - rate is only affected by parent switching. No clk_set_rate support | |
23 | * parent - parent is adjustable through clk_set_parent | |
24 | */ | |
25 | ||
77deb66d JB |
26 | int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, |
27 | unsigned int val) | |
9d9f78ed | 28 | { |
497295af | 29 | int num_parents = clk_hw_get_num_parents(hw); |
9d9f78ed | 30 | |
77deb66d | 31 | if (table) { |
ce4f3313 PDS |
32 | int i; |
33 | ||
34 | for (i = 0; i < num_parents; i++) | |
77deb66d | 35 | if (table[i] == val) |
ce4f3313 PDS |
36 | return i; |
37 | return -EINVAL; | |
38 | } | |
9d9f78ed | 39 | |
77deb66d | 40 | if (val && (flags & CLK_MUX_INDEX_BIT)) |
9d9f78ed MT |
41 | val = ffs(val) - 1; |
42 | ||
77deb66d | 43 | if (val && (flags & CLK_MUX_INDEX_ONE)) |
9d9f78ed MT |
44 | val--; |
45 | ||
ce4f3313 | 46 | if (val >= num_parents) |
9d9f78ed MT |
47 | return -EINVAL; |
48 | ||
49 | return val; | |
50 | } | |
77deb66d | 51 | EXPORT_SYMBOL_GPL(clk_mux_val_to_index); |
9d9f78ed | 52 | |
77deb66d | 53 | unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index) |
9d9f78ed | 54 | { |
77deb66d | 55 | unsigned int val = index; |
9d9f78ed | 56 | |
77deb66d JB |
57 | if (table) { |
58 | val = table[index]; | |
3837bd27 | 59 | } else { |
77deb66d JB |
60 | if (flags & CLK_MUX_INDEX_BIT) |
61 | val = 1 << index; | |
ce4f3313 | 62 | |
77deb66d JB |
63 | if (flags & CLK_MUX_INDEX_ONE) |
64 | val++; | |
ce4f3313 | 65 | } |
9d9f78ed | 66 | |
77deb66d JB |
67 | return val; |
68 | } | |
69 | EXPORT_SYMBOL_GPL(clk_mux_index_to_val); | |
70 | ||
71 | static u8 clk_mux_get_parent(struct clk_hw *hw) | |
72 | { | |
73 | struct clk_mux *mux = to_clk_mux(hw); | |
74 | u32 val; | |
75 | ||
76 | val = clk_readl(mux->reg) >> mux->shift; | |
77 | val &= mux->mask; | |
78 | ||
79 | return clk_mux_val_to_index(hw, mux->table, mux->flags, val); | |
80 | } | |
81 | ||
82 | static int clk_mux_set_parent(struct clk_hw *hw, u8 index) | |
83 | { | |
84 | struct clk_mux *mux = to_clk_mux(hw); | |
85 | u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); | |
86 | unsigned long flags = 0; | |
87 | u32 reg; | |
88 | ||
9d9f78ed MT |
89 | if (mux->lock) |
90 | spin_lock_irqsave(mux->lock, flags); | |
661e2180 SB |
91 | else |
92 | __acquire(mux->lock); | |
9d9f78ed | 93 | |
ba492e90 | 94 | if (mux->flags & CLK_MUX_HIWORD_MASK) { |
77deb66d | 95 | reg = mux->mask << (mux->shift + 16); |
ba492e90 | 96 | } else { |
77deb66d JB |
97 | reg = clk_readl(mux->reg); |
98 | reg &= ~(mux->mask << mux->shift); | |
ba492e90 | 99 | } |
77deb66d JB |
100 | val = val << mux->shift; |
101 | reg |= val; | |
102 | clk_writel(reg, mux->reg); | |
9d9f78ed MT |
103 | |
104 | if (mux->lock) | |
105 | spin_unlock_irqrestore(mux->lock, flags); | |
661e2180 SB |
106 | else |
107 | __release(mux->lock); | |
9d9f78ed MT |
108 | |
109 | return 0; | |
110 | } | |
9d9f78ed | 111 | |
4ad69b80 JB |
112 | static int clk_mux_determine_rate(struct clk_hw *hw, |
113 | struct clk_rate_request *req) | |
114 | { | |
115 | struct clk_mux *mux = to_clk_mux(hw); | |
116 | ||
117 | return clk_mux_determine_rate_flags(hw, req, mux->flags); | |
118 | } | |
119 | ||
822c250e | 120 | const struct clk_ops clk_mux_ops = { |
9d9f78ed MT |
121 | .get_parent = clk_mux_get_parent, |
122 | .set_parent = clk_mux_set_parent, | |
4ad69b80 | 123 | .determine_rate = clk_mux_determine_rate, |
9d9f78ed MT |
124 | }; |
125 | EXPORT_SYMBOL_GPL(clk_mux_ops); | |
126 | ||
c57acd14 TF |
127 | const struct clk_ops clk_mux_ro_ops = { |
128 | .get_parent = clk_mux_get_parent, | |
129 | }; | |
130 | EXPORT_SYMBOL_GPL(clk_mux_ro_ops); | |
131 | ||
264b3171 | 132 | struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, |
2893c379 SH |
133 | const char * const *parent_names, u8 num_parents, |
134 | unsigned long flags, | |
ce4f3313 PDS |
135 | void __iomem *reg, u8 shift, u32 mask, |
136 | u8 clk_mux_flags, u32 *table, spinlock_t *lock) | |
9d9f78ed MT |
137 | { |
138 | struct clk_mux *mux; | |
264b3171 | 139 | struct clk_hw *hw; |
0197b3ea | 140 | struct clk_init_data init; |
ba492e90 | 141 | u8 width = 0; |
264b3171 | 142 | int ret; |
ba492e90 HZ |
143 | |
144 | if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { | |
145 | width = fls(mask) - ffs(mask) + 1; | |
146 | if (width + shift > 16) { | |
147 | pr_err("mux value exceeds LOWORD field\n"); | |
148 | return ERR_PTR(-EINVAL); | |
149 | } | |
150 | } | |
9d9f78ed | 151 | |
27d54591 | 152 | /* allocate the mux */ |
1e28733e | 153 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); |
0b910402 | 154 | if (!mux) |
9d9f78ed | 155 | return ERR_PTR(-ENOMEM); |
9d9f78ed | 156 | |
0197b3ea | 157 | init.name = name; |
c57acd14 TF |
158 | if (clk_mux_flags & CLK_MUX_READ_ONLY) |
159 | init.ops = &clk_mux_ro_ops; | |
160 | else | |
161 | init.ops = &clk_mux_ops; | |
f7d8caad | 162 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
163 | init.parent_names = parent_names; |
164 | init.num_parents = num_parents; | |
165 | ||
9d9f78ed MT |
166 | /* struct clk_mux assignments */ |
167 | mux->reg = reg; | |
168 | mux->shift = shift; | |
ce4f3313 | 169 | mux->mask = mask; |
9d9f78ed MT |
170 | mux->flags = clk_mux_flags; |
171 | mux->lock = lock; | |
ce4f3313 | 172 | mux->table = table; |
31df9db9 | 173 | mux->hw.init = &init; |
9d9f78ed | 174 | |
264b3171 SB |
175 | hw = &mux->hw; |
176 | ret = clk_hw_register(dev, hw); | |
177 | if (ret) { | |
27d54591 | 178 | kfree(mux); |
264b3171 SB |
179 | hw = ERR_PTR(ret); |
180 | } | |
27d54591 | 181 | |
264b3171 SB |
182 | return hw; |
183 | } | |
184 | EXPORT_SYMBOL_GPL(clk_hw_register_mux_table); | |
185 | ||
186 | struct clk *clk_register_mux_table(struct device *dev, const char *name, | |
187 | const char * const *parent_names, u8 num_parents, | |
188 | unsigned long flags, | |
189 | void __iomem *reg, u8 shift, u32 mask, | |
190 | u8 clk_mux_flags, u32 *table, spinlock_t *lock) | |
191 | { | |
192 | struct clk_hw *hw; | |
193 | ||
194 | hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents, | |
195 | flags, reg, shift, mask, clk_mux_flags, | |
196 | table, lock); | |
197 | if (IS_ERR(hw)) | |
198 | return ERR_CAST(hw); | |
199 | return hw->clk; | |
9d9f78ed | 200 | } |
5cfe10bb | 201 | EXPORT_SYMBOL_GPL(clk_register_mux_table); |
ce4f3313 PDS |
202 | |
203 | struct clk *clk_register_mux(struct device *dev, const char *name, | |
2893c379 SH |
204 | const char * const *parent_names, u8 num_parents, |
205 | unsigned long flags, | |
ce4f3313 PDS |
206 | void __iomem *reg, u8 shift, u8 width, |
207 | u8 clk_mux_flags, spinlock_t *lock) | |
208 | { | |
209 | u32 mask = BIT(width) - 1; | |
210 | ||
211 | return clk_register_mux_table(dev, name, parent_names, num_parents, | |
212 | flags, reg, shift, mask, clk_mux_flags, | |
213 | NULL, lock); | |
214 | } | |
5cfe10bb | 215 | EXPORT_SYMBOL_GPL(clk_register_mux); |
4e3c021f | 216 | |
264b3171 SB |
217 | struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, |
218 | const char * const *parent_names, u8 num_parents, | |
219 | unsigned long flags, | |
220 | void __iomem *reg, u8 shift, u8 width, | |
221 | u8 clk_mux_flags, spinlock_t *lock) | |
222 | { | |
223 | u32 mask = BIT(width) - 1; | |
224 | ||
225 | return clk_hw_register_mux_table(dev, name, parent_names, num_parents, | |
226 | flags, reg, shift, mask, clk_mux_flags, | |
227 | NULL, lock); | |
228 | } | |
229 | EXPORT_SYMBOL_GPL(clk_hw_register_mux); | |
230 | ||
4e3c021f KK |
231 | void clk_unregister_mux(struct clk *clk) |
232 | { | |
233 | struct clk_mux *mux; | |
234 | struct clk_hw *hw; | |
235 | ||
236 | hw = __clk_get_hw(clk); | |
237 | if (!hw) | |
238 | return; | |
239 | ||
240 | mux = to_clk_mux(hw); | |
241 | ||
242 | clk_unregister(clk); | |
243 | kfree(mux); | |
244 | } | |
245 | EXPORT_SYMBOL_GPL(clk_unregister_mux); | |
264b3171 SB |
246 | |
247 | void clk_hw_unregister_mux(struct clk_hw *hw) | |
248 | { | |
249 | struct clk_mux *mux; | |
250 | ||
251 | mux = to_clk_mux(hw); | |
252 | ||
253 | clk_hw_unregister(hw); | |
254 | kfree(mux); | |
255 | } | |
256 | EXPORT_SYMBOL_GPL(clk_hw_unregister_mux); |