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Merge tag 'asm-generic-fixes-6.1-1' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / clk / clk-lmk04832.c
CommitLineData
3bc61cfd
LB		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
4 * Pin compatible with the LMK0482x family
5 *
6 * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf
7 *
8 * Copyright (c) 2020, Xiphos Systems Corp.
9 *
10 */
11
12#include <linux/bitfield.h>
13#include <linux/clk.h>
14#include <linux/clk-provider.h>
15#include <linux/debugfs.h>
16#include <linux/device.h>
17#include <linux/gcd.h>
18#include <linux/gpio/consumer.h>
19#include <linux/module.h>
20#include <linux/uaccess.h>
21#include <linux/regmap.h>
22#include <linux/spi/spi.h>
23
24/* 0x000 - 0x00d System Functions */
25#define LMK04832_REG_RST3W 0x000
26#define LMK04832_BIT_RESET BIT(7)
27#define LMK04832_BIT_SPI_3WIRE_DIS BIT(4)
28#define LMK04832_REG_POWERDOWN 0x002
29#define LMK04832_REG_ID_DEV_TYPE 0x003
30#define LMK04832_REG_ID_PROD_MSB 0x004
31#define LMK04832_REG_ID_PROD_LSB 0x005
32#define LMK04832_REG_ID_MASKREV 0x006
33#define LMK04832_REG_ID_VNDR_MSB 0x00c
34#define LMK04832_REG_ID_VNDR_LSB 0x00d
35
36/* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
37#define LMK04832_REG_CLKOUT_CTRL0(ch) (0x100 + (ch >> 1) * 8)
38#define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0)
39#define LMK04832_REG_CLKOUT_CTRL1(ch) (0x101 + (ch >> 1) * 8)
6181baa1 40#define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0)
3bc61cfd
LB		 41#define LMK04832_REG_CLKOUT_CTRL2(ch) (0x102 + (ch >> 1) * 8)
42#define LMK04832_BIT_CLKOUTX_Y_PD BIT(7)
6181baa1
LB		 43#define LMK04832_BIT_DCLKX_Y_DDLY_PD BIT(4)
44#define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2)
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LB		 45#define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0)
46#define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8)
47#define LMK04832_BIT_CLKOUT_SRC_MUX BIT(5)
48#define LMK04832_REG_CLKOUT_CTRL3(ch) (0x103 + (ch >> 1) * 8)
49#define LMK04832_BIT_DCLKX_Y_PD BIT(4)
50#define LMK04832_BIT_DCLKX_Y_DCC BIT(2)
6181baa1 51#define LMK04832_BIT_DCLKX_Y_HS BIT(0)
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LB		 52#define LMK04832_REG_CLKOUT_CTRL4(ch) (0x104 + (ch >> 1) * 8)
53#define LMK04832_BIT_SCLK_PD BIT(4)
6181baa1
LB		 54#define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2)
55#define LMK04832_REG_SCLKX_Y_ADLY(ch) (0x105 + (ch >> 1) * 8)
56#define LMK04832_REG_SCLKX_Y_DDLY(ch) (0x106 + (ch >> 1) * 8)
57#define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0)
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LB		 58#define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8)
59#define LMK04832_BIT_CLKOUT_FMT(ch) (ch % 2 ? 0xf0 : 0x0f)
60#define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00
61#define LMK04832_VAL_CLKOUT_FMT_LVDS 0x01
62#define LMK04832_VAL_CLKOUT_FMT_HSDS6 0x02
63#define LMK04832_VAL_CLKOUT_FMT_HSDS8 0x03
64#define LMK04832_VAL_CLKOUT_FMT_LVPECL1600 0x04
65#define LMK04832_VAL_CLKOUT_FMT_LVPECL2000 0x05
66#define LMK04832_VAL_CLKOUT_FMT_LCPECL 0x06
67#define LMK04832_VAL_CLKOUT_FMT_CML16 0x07
68#define LMK04832_VAL_CLKOUT_FMT_CML24 0x08
69#define LMK04832_VAL_CLKOUT_FMT_CML32 0x09
70#define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV 0x0a
71#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF 0x0b
72#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV 0x0c
73#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR 0x0d
74#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV 0x0e
75#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR 0x0f
76
77/* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
78#define LMK04832_REG_VCO_OSCOUT 0x138
79#define LMK04832_BIT_VCO_MUX GENMASK(6, 5)
80#define LMK04832_VAL_VCO_MUX_VCO0 0x00
81#define LMK04832_VAL_VCO_MUX_VCO1 0x01
82#define LMK04832_VAL_VCO_MUX_EXT 0x02
83#define LMK04832_REG_SYSREF_OUT 0x139
6181baa1 84#define LMK04832_BIT_SYSREF_REQ_EN BIT(6)
3bc61cfd 85#define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0)
6181baa1
LB		 86#define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00
87#define LMK04832_VAL_SYSREF_MUX_RECLK 0x01
88#define LMK04832_VAL_SYSREF_MUX_PULSER 0x02
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LB		 89#define LMK04832_VAL_SYSREF_MUX_CONTINUOUS 0x03
90#define LMK04832_REG_SYSREF_DIV_MSB 0x13a
91#define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0)
92#define LMK04832_REG_SYSREF_DIV_LSB 0x13b
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LB		 93#define LMK04832_REG_SYSREF_DDLY_MSB 0x13c
94#define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0)
95#define LMK04832_REG_SYSREF_DDLY_LSB 0x13d
96#define LMK04832_REG_SYSREF_PULSE_CNT 0x13e
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LB		 97#define LMK04832_REG_FB_CTRL 0x13f
98#define LMK04832_BIT_PLL2_RCLK_MUX BIT(7)
99#define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00
100#define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN 0x01
101#define LMK04832_BIT_PLL2_NCLK_MUX BIT(5)
102#define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P 0x00
103#define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX 0x01
104#define LMK04832_BIT_FB_MUX_EN BIT(0)
105#define LMK04832_REG_MAIN_PD 0x140
106#define LMK04832_BIT_PLL1_PD BIT(7)
107#define LMK04832_BIT_VCO_LDO_PD BIT(6)
108#define LMK04832_BIT_VCO_PD BIT(5)
109#define LMK04832_BIT_OSCIN_PD BIT(4)
110#define LMK04832_BIT_SYSREF_GBL_PD BIT(3)
111#define LMK04832_BIT_SYSREF_PD BIT(2)
112#define LMK04832_BIT_SYSREF_DDLY_PD BIT(1)
113#define LMK04832_BIT_SYSREF_PLSR_PD BIT(0)
114#define LMK04832_REG_SYNC 0x143
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LB		 115#define LMK04832_BIT_SYNC_CLR BIT(7)
116#define LMK04832_BIT_SYNC_1SHOT_EN BIT(6)
117#define LMK04832_BIT_SYNC_POL BIT(5)
3bc61cfd 118#define LMK04832_BIT_SYNC_EN BIT(4)
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LB		 119#define LMK04832_BIT_SYNC_MODE GENMASK(1, 0)
120#define LMK04832_VAL_SYNC_MODE_OFF 0x00
121#define LMK04832_VAL_SYNC_MODE_ON 0x01
122#define LMK04832_VAL_SYNC_MODE_PULSER_PIN 0x02
123#define LMK04832_VAL_SYNC_MODE_PULSER_SPI 0x03
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LB		 124#define LMK04832_REG_SYNC_DIS 0x144
125
126/* 0x146 - 0x14a CLKin Control */
127#define LMK04832_REG_CLKIN_SEL0 0x148
128#define LMK04832_REG_CLKIN_SEL1 0x149
129#define LMK04832_REG_CLKIN_RST 0x14a
130#define LMK04832_BIT_SDIO_RDBK_TYPE BIT(6)
131#define LMK04832_BIT_CLKIN_SEL_MUX GENMASK(5, 3)
132#define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK 0x06
133#define LMK04832_BIT_CLKIN_SEL_TYPE GENMASK(2, 0)
134#define LMK04832_VAL_CLKIN_SEL_TYPE_OUT 0x03
135
136/* 0x14b - 0x152 Holdover */
137
138/* 0x153 - 0x15f PLL1 Configuration */
139
140/* 0x160 - 0x16e PLL2 Configuration */
141#define LMK04832_REG_PLL2_R_MSB 0x160
142#define LMK04832_BIT_PLL2_R_MSB GENMASK(3, 0)
143#define LMK04832_REG_PLL2_R_LSB 0x161
144#define LMK04832_REG_PLL2_MISC 0x162
145#define LMK04832_BIT_PLL2_MISC_P GENMASK(7, 5)
146#define LMK04832_BIT_PLL2_MISC_REF_2X_EN BIT(0)
147#define LMK04832_REG_PLL2_N_CAL_0 0x163
148#define LMK04832_BIT_PLL2_N_CAL_0 GENMASK(1, 0)
149#define LMK04832_REG_PLL2_N_CAL_1 0x164
150#define LMK04832_REG_PLL2_N_CAL_2 0x165
151#define LMK04832_REG_PLL2_N_0 0x166
152#define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0)
153#define LMK04832_REG_PLL2_N_1 0x167
154#define LMK04832_REG_PLL2_N_2 0x168
6181baa1 155#define LMK04832_REG_PLL2_DLD_CNT_MSB 0x16a
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LB		 156#define LMK04832_REG_PLL2_DLD_CNT_LSB 0x16b
157#define LMK04832_REG_PLL2_LD 0x16e
158#define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3)
159#define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD 0x02
160#define LMK04832_BIT_PLL2_LD_TYPE GENMASK(2, 0)
161#define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP 0x03
162
163/* 0x16F - 0x555 Misc Registers */
164#define LMK04832_REG_PLL2_PD 0x173
165#define LMK04832_BIT_PLL2_PRE_PD BIT(6)
166#define LMK04832_BIT_PLL2_PD BIT(5)
167#define LMK04832_REG_PLL1R_RST 0x177
168#define LMK04832_REG_CLR_PLL_LOST 0x182
169#define LMK04832_REG_RB_PLL_LD 0x183
170#define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184
171#define LMK04832_REG_RB_DAC_VAL_LSB 0x185
172#define LMK04832_REG_RB_HOLDOVER 0x188
173#define LMK04832_REG_SPI_LOCK 0x555
174
175enum lmk04832_device_types {
176 LMK04832,
177};
178
179/**
180 * lmk04832_device_info - Holds static device information that is specific to
181 * the chip revision
182 *
183 * pid: Product Identifier
184 * maskrev: IC version identifier
185 * num_channels: Number of available output channels (clkout count)
186 * vco0_range: {min, max} of the VCO0 operating range (in MHz)
187 * vco1_range: {min, max} of the VCO1 operating range (in MHz)
188 */
189struct lmk04832_device_info {
190 u16 pid;
191 u8 maskrev;
192 size_t num_channels;
193 unsigned int vco0_range[2];
194 unsigned int vco1_range[2];
195};
196
197static const struct lmk04832_device_info lmk04832_device_info[] = {
198 [LMK04832] = {
199 .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */
200 .maskrev = 0x70,
201 .num_channels = 14,
202 .vco0_range = { 2440, 2580 },
203 .vco1_range = { 2945, 3255 },
204 },
205};
206
207enum lmk04832_rdbk_type {
208 RDBK_CLKIN_SEL0,
209 RDBK_CLKIN_SEL1,
210 RDBK_RESET,
211};
212
213struct lmk_dclk {
214 struct lmk04832 *lmk;
215 struct clk_hw hw;
216 u8 id;
217};
218
219struct lmk_clkout {
220 struct lmk04832 *lmk;
221 struct clk_hw hw;
222 bool sysref;
223 u32 format;
224 u8 id;
225};
226
227/**
228 * struct lmk04832 - The LMK04832 device structure
229 *
230 * @dev: reference to a struct device, linked to the spi_device
231 * @regmap: struct regmap instance use to access the chip
6181baa1
LB		 232 * @sync_mode: operational mode for SYNC signal
233 * @sysref_mux: select SYSREF source
234 * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
235 * mode.
236 * @sysref_ddly: SYSREF digital delay value
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LB		 237 * @oscin: PLL2 input clock
238 * @vco: reference to the internal VCO clock
239 * @sclk: reference to the internal sysref clock (SCLK)
240 * @vco_rate: user provided VCO rate
241 * @reset_gpio: reference to the reset GPIO
242 * @dclk: list of internal device clock references.
243 * Each pair of clkout clocks share a single device clock (DCLKX_Y)
244 * @clkout: list of output clock references
245 * @clk_data: holds clkout related data like clk_hw* and number of clocks
246 */
247struct lmk04832 {
248 struct device *dev;
249 struct regmap *regmap;
250
6181baa1
LB		 251 unsigned int sync_mode;
252 unsigned int sysref_mux;
253 unsigned int sysref_pulse_cnt;
254 unsigned int sysref_ddly;
255
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LB		 256 struct clk *oscin;
257 struct clk_hw vco;
258 struct clk_hw sclk;
259 unsigned int vco_rate;
260
261 struct gpio_desc *reset_gpio;
262
263 struct lmk_dclk *dclk;
264 struct lmk_clkout *clkout;
265 struct clk_hw_onecell_data *clk_data;
266};
267
268static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg)
269{
270 switch (reg) {
271 case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV:
3bc61cfd 272 case LMK04832_REG_ID_VNDR_MSB:
3bc61cfd 273 case LMK04832_REG_ID_VNDR_LSB:
3bc61cfd 274 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
3bc61cfd 275 case LMK04832_REG_PLL2_LD:
3bc61cfd 276 case LMK04832_REG_PLL2_PD:
3bc61cfd 277 case LMK04832_REG_PLL1R_RST:
3bc61cfd 278 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
3bc61cfd 279 case LMK04832_REG_RB_HOLDOVER:
3bc61cfd
LB		 280 case LMK04832_REG_SPI_LOCK:
281 return true;
282 default:
283 return false;
284 };
285};
286
287static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
288{
289 switch (reg) {
290 case LMK04832_REG_RST3W:
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LB		 291 case LMK04832_REG_POWERDOWN:
292 return true;
293 case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV:
3bc61cfd 294 case LMK04832_REG_ID_VNDR_MSB:
3bc61cfd
LB		 295 case LMK04832_REG_ID_VNDR_LSB:
296 return false;
297 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
3bc61cfd 298 case LMK04832_REG_PLL2_LD:
3bc61cfd 299 case LMK04832_REG_PLL2_PD:
3bc61cfd 300 case LMK04832_REG_PLL1R_RST:
3bc61cfd 301 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
3bc61cfd 302 case LMK04832_REG_RB_HOLDOVER:
3bc61cfd
LB		 303 case LMK04832_REG_SPI_LOCK:
304 return true;
305 default:
306 return false;
307 };
308};
309
310static const struct regmap_config regmap_config = {
311 .name = "lmk04832",
312 .reg_bits = 16,
313 .val_bits = 8,
314 .use_single_read = 1,
315 .use_single_write = 1,
316 .read_flag_mask = 0x80,
317 .write_flag_mask = 0x00,
318 .readable_reg = lmk04832_regmap_rd_regs,
319 .writeable_reg = lmk04832_regmap_wr_regs,
320 .cache_type = REGCACHE_NONE,
321 .max_register = LMK04832_REG_SPI_LOCK,
322};
323
324static int lmk04832_vco_is_enabled(struct clk_hw *hw)
325{
326 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
327 unsigned int tmp;
328 int ret;
329
330 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
331 if (ret)
332 return ret;
333
334 return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) |
335 FIELD_GET(LMK04832_BIT_VCO_PD, tmp) |
336 FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp));
337}
338
339static int lmk04832_vco_prepare(struct clk_hw *hw)
340{
341 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
342 int ret;
343
344 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
345 LMK04832_BIT_PLL2_PRE_PD |
346 LMK04832_BIT_PLL2_PD,
347 0x00);
348 if (ret)
349 return ret;
350
351 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
352 LMK04832_BIT_VCO_LDO_PD |
353 LMK04832_BIT_VCO_PD |
354 LMK04832_BIT_OSCIN_PD, 0x00);
355}
356
357static void lmk04832_vco_unprepare(struct clk_hw *hw)
358{
359 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
360
361 regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
362 LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD,
363 0xff);
364
365 /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */
366 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
367 LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff);
368}
369
370static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
371 unsigned long prate)
372{
373 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
374 unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
375 unsigned int pll2_n, p, pll2_r;
376 unsigned int pll2_misc;
377 unsigned long vco_rate;
378 u8 tmp[3];
379 int ret;
380
381 ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc);
382 if (ret)
383 return ret;
384
385 p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc);
386
387 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3);
388 if (ret)
389 return ret;
390
391 pll2_n = FIELD_PREP(0x030000, tmp[0]) |
392 FIELD_PREP(0x00ff00, tmp[1]) |
393 FIELD_PREP(0x0000ff, tmp[2]);
394
395 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2);
396 if (ret)
397 return ret;
398
399 pll2_r = FIELD_PREP(0x0f00, tmp[0]) |
400 FIELD_PREP(0x00ff, tmp[1]);
401
402 vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN,
403 pll2_misc)) * pll2_n * pll2_p[p] / pll2_r;
404
405 return vco_rate;
406};
407
408/**
409 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
410 *
411 * @lmk: Reference to the lmk device
412 * @rate: Desired output rate for the VCO
413 *
414 * The LMK04832 has 2 internal VCO, each with independent operating ranges.
415 * Use the device_info structure to determine which VCO to use based on rate.
416 *
417 * Returns VCO_MUX value or negative errno.
418 */
419static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
420{
421 struct spi_device *spi = to_spi_device(lmk->dev);
422 const struct lmk04832_device_info *info;
423 unsigned long mhz = rate / 1000000;
424
425 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
426
427 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1])
428 return LMK04832_VAL_VCO_MUX_VCO0;
429
430 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1])
431 return LMK04832_VAL_VCO_MUX_VCO1;
432
433 dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate);
434 return -ERANGE;
435}
436
437/**
438 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
439 *
440 * @prate: parent rate to the PLL2, usually OSCin
441 * @rate: Desired output rate for the VCO
442 * @n: reference to PLL2_N
443 * @p: reference to PLL2_P
444 * @r: reference to PLL2_R
445 *
446 * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is
447 * recommended in the datasheet because a higher phase detector frequencies
448 * makes the design of wider loop bandwidth filters possible.
449 *
450 * the VCO rate can be calculated using the following expression:
451 *
452 * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
453 *
454 * Returns vco rate or negative errno.
455 */
456static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate,
457 unsigned int *n, unsigned int *p,
458 unsigned int *r)
459{
460 unsigned int pll2_n, pll2_p, pll2_r;
461 unsigned long num, div;
462
463 /* Set PLL2_P to a fixed value to simplify optimizations */
464 pll2_p = 2;
465
466 div = gcd(rate, prate);
467
468 num = DIV_ROUND_CLOSEST(rate, div);
469 pll2_r = DIV_ROUND_CLOSEST(prate, div);
470
471 if (num > 4) {
472 pll2_n = num >> 2;
473 } else {
474 pll2_r = pll2_r << 2;
475 pll2_n = num;
476 }
477
478 if (pll2_n < 1 || pll2_n > 0x03ffff)
479 return -EINVAL;
480 if (pll2_r < 1 || pll2_r > 0xfff)
481 return -EINVAL;
482
483 *n = pll2_n;
484 *p = pll2_p;
485 *r = pll2_r;
486
487 return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r);
488}
489
490static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
491 unsigned long *prate)
492{
493 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
494 unsigned int n, p, r;
495 long vco_rate;
496 int ret;
497
498 ret = lmk04832_check_vco_ranges(lmk, rate);
499 if (ret < 0)
500 return ret;
501
502 vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
503 if (vco_rate < 0) {
2cdee50e 504 dev_err(lmk->dev, "PLL2 parameters out of range\n");
3bc61cfd
LB		 505 return vco_rate;
506 }
507
508 if (rate != vco_rate)
509 return -EINVAL;
510
511 return vco_rate;
512};
513
514static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
515 unsigned long prate)
516{
517 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
518 unsigned int n, p, r;
519 long vco_rate;
520 int vco_mux;
521 int ret;
522
523 vco_mux = lmk04832_check_vco_ranges(lmk, rate);
524 if (vco_mux < 0)
525 return vco_mux;
526
527 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
528 LMK04832_BIT_VCO_MUX,
529 FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux));
530 if (ret)
531 return ret;
532
533 vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
534 if (vco_rate < 0) {
2cdee50e 535 dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
3bc61cfd
LB		 536 return vco_rate;
537 }
538
539 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB,
540 LMK04832_BIT_PLL2_R_MSB,
541 FIELD_GET(0x000700, r));
542 if (ret)
543 return ret;
544
545 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB,
546 FIELD_GET(0x0000ff, r));
547 if (ret)
548 return ret;
549
550 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
551 LMK04832_BIT_PLL2_MISC_P,
552 FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p));
553 if (ret)
554 return ret;
555
556 /*
557 * PLL2_N registers must be programmed after other PLL2 dividers are
2cdee50e 558 * programmed to ensure proper VCO frequency calibration
3bc61cfd
LB		 559 */
560 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
561 FIELD_GET(0x030000, n));
562 if (ret)
563 return ret;
564 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1,
565 FIELD_GET(0x00ff00, n));
566 if (ret)
567 return ret;
568
569 return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2,
570 FIELD_GET(0x0000ff, n));
571};
572
573static const struct clk_ops lmk04832_vco_ops = {
574 .is_enabled = lmk04832_vco_is_enabled,
575 .prepare = lmk04832_vco_prepare,
576 .unprepare = lmk04832_vco_unprepare,
577 .recalc_rate = lmk04832_vco_recalc_rate,
578 .round_rate = lmk04832_vco_round_rate,
579 .set_rate = lmk04832_vco_set_rate,
580};
581
582/*
583 * lmk04832_register_vco - Initialize the internal VCO and clock distribution
584 * path in PLL2 single loop mode.
585 */
586static int lmk04832_register_vco(struct lmk04832 *lmk)
587{
588 const char *parent_names[1];
589 struct clk_init_data init;
590 int ret;
591
592 init.name = "lmk-vco";
593 parent_names[0] = __clk_get_name(lmk->oscin);
594 init.parent_names = parent_names;
595
596 init.ops = &lmk04832_vco_ops;
597 init.num_parents = 1;
598
599 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
600 LMK04832_BIT_VCO_MUX,
601 FIELD_PREP(LMK04832_BIT_VCO_MUX,
602 LMK04832_VAL_VCO_MUX_VCO1));
603 if (ret)
604 return ret;
605
606 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL,
607 LMK04832_BIT_PLL2_RCLK_MUX |
608 LMK04832_BIT_PLL2_NCLK_MUX,
609 FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX,
610 LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)|
611 FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX,
612 LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P));
613 if (ret)
614 return ret;
615
616 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
617 LMK04832_BIT_PLL2_MISC_REF_2X_EN,
618 LMK04832_BIT_PLL2_MISC_REF_2X_EN);
619 if (ret)
620 return ret;
621
622 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD,
623 FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX,
624 LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) |
625 FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE,
626 LMK04832_VAL_PLL2_LD_TYPE_OUT_PP));
627 if (ret)
628 return ret;
629
630 lmk->vco.init = &init;
631 return devm_clk_hw_register(lmk->dev, &lmk->vco);
632}
633
6181baa1
LB		 634static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
635{
636 int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
637 unsigned int sclkx_y_ddly = 10;
638 unsigned int dclkx_y_ddly;
639 unsigned int dclkx_y_div;
640 unsigned int sysref_ddly;
641 unsigned int dclkx_y_hs;
642 unsigned int lsb, msb;
643 int ret;
644
645 ret = regmap_update_bits(lmk->regmap,
646 LMK04832_REG_CLKOUT_CTRL2(id),
647 LMK04832_BIT_DCLKX_Y_DDLY_PD,
648 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0));
649 if (ret)
650 return ret;
651
652 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb);
653 if (ret)
654 return ret;
655
656 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb);
657 if (ret)
658 return ret;
659
660 sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb;
661
662 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb);
663 if (ret)
664 return ret;
665
666 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb);
667 if (ret)
668 return ret;
669
670 dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
671
672 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb);
673 if (ret)
674 return ret;
675
676 dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb);
677
678 dclkx_y_ddly = sysref_ddly + 1 -
679 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] -
680 dclkx_y_hs + sclkx_y_ddly;
681
682 if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) {
683 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n",
684 dclkx_y_ddly);
685 return -EINVAL;
686 }
687
688 ret = regmap_write(lmk->regmap,
689 LMK04832_REG_SCLKX_Y_DDLY(id),
690 FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly));
691 if (ret)
692 return ret;
693
694 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id),
695 FIELD_GET(0x00ff, dclkx_y_ddly));
696 if (ret)
697 return ret;
698
699 dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, "
700 "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n",
701 id, sysref_ddly, dclkx_y_ddly,
702 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7],
703 dclkx_y_hs, sclkx_y_ddly);
704
705 return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id),
706 LMK04832_BIT_DCLKX_Y_DDLY_MSB,
707 FIELD_GET(0x0300, dclkx_y_ddly));
708}
709
710/** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
711 * and dclk
712 *
713 * @lmk: Reference to the lmk device
714 *
715 * The synchronization sequence:
716 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
717 * (8.3.3.1 How to enable SYSREF)
718 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
719 *
720 * Returns 0 or negative errno.
721 */
722static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk)
723{
724 int ret;
725 int i;
726
727 /* 1. (optional) mute all sysref_outputs during synchronization */
728 /* 2. Enable and write device clock digital delay to applicable clocks */
729 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
730 LMK04832_BIT_SYSREF_DDLY_PD,
731 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0));
732 if (ret)
733 return ret;
734
735 for (i = 0; i < lmk->clk_data->num; i += 2) {
736 ret = lmk04832_clkout_set_ddly(lmk, i);
737 if (ret)
738 return ret;
739 }
740
741 /*
742 * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC,
743 * and clear SYSREF_REQ_EN (see 6.)
744 */
745 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
746 LMK04832_BIT_SYSREF_REQ_EN |
747 LMK04832_BIT_SYSREF_MUX,
748 FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) |
749 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
750 LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC));
751 if (ret)
752 return ret;
753
754 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
755 LMK04832_BIT_SYNC_MODE,
756 FIELD_PREP(LMK04832_BIT_SYNC_MODE,
757 LMK04832_VAL_SYNC_MODE_ON));
758 if (ret)
759 return ret;
760
761 /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */
762 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
763 if (ret)
764 return ret;
765
766 /*
767 * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock
768 * distribution path cycles (VCO cycles), then back to 0. In
769 * PLL2-only use case, this will be complete in less than one SPI
770 * transaction. If SYSREF local digital delay is not used, this step
771 * can be skipped.
772 */
773 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
774 LMK04832_BIT_SYNC_CLR,
775 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01));
776 if (ret)
777 return ret;
778
779 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
780 LMK04832_BIT_SYNC_CLR,
781 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
782 if (ret)
783 return ret;
784
785 /*
786 * 6. Toggle SYNC_POL state between inverted and not inverted.
787 * If you use an external signal on the SYNC pin instead of toggling
788 * SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX
789 * does not shift into continuous SYSREF mode.
790 */
791 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
792 LMK04832_BIT_SYNC_POL,
793 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01));
794 if (ret)
795 return ret;
796
797 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
798 LMK04832_BIT_SYNC_POL,
799 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
800 if (ret)
801 return ret;
802
803 /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */
804 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
805 if (ret)
806 return ret;
807
808 /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */
809 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
810 LMK04832_BIT_SYSREF_MUX,
811 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
812 lmk->sysref_mux));
813 if (ret)
814 return ret;
815
816 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
817 LMK04832_BIT_SYNC_MODE,
818 FIELD_PREP(LMK04832_BIT_SYNC_MODE,
819 lmk->sync_mode));
820 if (ret)
821 return ret;
822
823 /*
824 * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs
825 * during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state,
826 * or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional
827 * option.
828 */
829
830 /*
831 * 10. (optional) To reduce power consumption, after the synchronization
832 * event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the
833 * digital delay counters (which are only used immediately after the
834 * SYNC pulse to delay the output by some number of VCO counts).
835 */
836
837 return ret;
838}
839
3bc61cfd
LB		 840static int lmk04832_sclk_is_enabled(struct clk_hw *hw)
841{
842 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
843 unsigned int tmp;
844 int ret;
845
846 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
847 if (ret)
848 return ret;
849
850 return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp);
851}
852
853static int lmk04832_sclk_prepare(struct clk_hw *hw)
854{
855 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
856
857 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
858 LMK04832_BIT_SYSREF_PD, 0x00);
859}
860
861static void lmk04832_sclk_unprepare(struct clk_hw *hw)
862{
863 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
864
865 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
866 LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD);
867}
868
869static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw,
870 unsigned long prate)
871{
872 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
873 unsigned int sysref_div;
874 u8 tmp[2];
875 int ret;
876
877 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2);
878 if (ret)
879 return ret;
880
881 sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 |
882 tmp[1];
883
884 return DIV_ROUND_CLOSEST(prate, sysref_div);
885}
886
887static long lmk04832_sclk_round_rate(struct clk_hw *hw, unsigned long rate,
888 unsigned long *prate)
889{
890 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
891 unsigned long sclk_rate;
892 unsigned int sysref_div;
893
894 sysref_div = DIV_ROUND_CLOSEST(*prate, rate);
895 sclk_rate = DIV_ROUND_CLOSEST(*prate, sysref_div);
896
897 if (sysref_div < 0x07 || sysref_div > 0x1fff) {
898 dev_err(lmk->dev, "SYSREF divider out of range\n");
899 return -EINVAL;
900 }
901
902 if (rate != sclk_rate)
903 return -EINVAL;
904
905 return sclk_rate;
906}
907
908static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate,
909 unsigned long prate)
910{
911 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
912 unsigned int sysref_div;
913 int ret;
914
915 sysref_div = DIV_ROUND_CLOSEST(prate, rate);
916
917 if (sysref_div < 0x07 || sysref_div > 0x1fff) {
918 dev_err(lmk->dev, "SYSREF divider out of range\n");
919 return -EINVAL;
920 }
921
922 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB,
923 FIELD_GET(0x1f00, sysref_div));
924 if (ret)
925 return ret;
926
6181baa1 927 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
3bc61cfd 928 FIELD_GET(0x00ff, sysref_div));
6181baa1
LB		 929 if (ret)
930 return ret;
931
932 ret = lmk04832_sclk_sync_sequence(lmk);
933 if (ret)
934 dev_err(lmk->dev, "SYNC sequence failed\n");
935
936 return ret;
3bc61cfd
LB		 937}
938
939static const struct clk_ops lmk04832_sclk_ops = {
940 .is_enabled = lmk04832_sclk_is_enabled,
941 .prepare = lmk04832_sclk_prepare,
942 .unprepare = lmk04832_sclk_unprepare,
943 .recalc_rate = lmk04832_sclk_recalc_rate,
944 .round_rate = lmk04832_sclk_round_rate,
945 .set_rate = lmk04832_sclk_set_rate,
946};
947
948static int lmk04832_register_sclk(struct lmk04832 *lmk)
949{
950 const char *parent_names[1];
951 struct clk_init_data init;
952 int ret;
953
954 init.name = "lmk-sclk";
955 parent_names[0] = clk_hw_get_name(&lmk->vco);
956 init.parent_names = parent_names;
957
958 init.ops = &lmk04832_sclk_ops;
959 init.flags = CLK_SET_RATE_PARENT;
960 init.num_parents = 1;
961
962 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
963 LMK04832_BIT_SYSREF_MUX,
964 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
6181baa1
LB		 965 lmk->sysref_mux));
966 if (ret)
967 return ret;
968
969 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB,
970 FIELD_GET(0x00ff, lmk->sysref_ddly));
971 if (ret)
972 return ret;
973
974 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB,
975 FIELD_GET(0x1f00, lmk->sysref_ddly));
976 if (ret)
977 return ret;
978
979 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT,
980 ilog2(lmk->sysref_pulse_cnt));
3bc61cfd
LB		 981 if (ret)
982 return ret;
983
984 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
6181baa1 985 LMK04832_BIT_SYSREF_DDLY_PD |
3bc61cfd 986 LMK04832_BIT_SYSREF_PLSR_PD,
6181baa1
LB		 987 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) |
988 FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0));
3bc61cfd
LB		 989 if (ret)
990 return ret;
991
6181baa1
LB		 992 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC,
993 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) |
994 FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) |
995 FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode));
3bc61cfd
LB		 996 if (ret)
997 return ret;
998
999 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
1000 if (ret)
1001 return ret;
1002
1003 lmk->sclk.init = &init;
1004 return devm_clk_hw_register(lmk->dev, &lmk->sclk);
1005}
1006
1007static int lmk04832_dclk_is_enabled(struct clk_hw *hw)
1008{
1009 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1010 struct lmk04832 *lmk = dclk->lmk;
1011 unsigned int tmp;
1012 int ret;
1013
1014 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1015 &tmp);
1016 if (ret)
1017 return ret;
1018
1019 return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp);
1020}
1021
1022static int lmk04832_dclk_prepare(struct clk_hw *hw)
1023{
1024 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1025 struct lmk04832 *lmk = dclk->lmk;
1026
1027 return regmap_update_bits(lmk->regmap,
1028 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1029 LMK04832_BIT_DCLKX_Y_PD, 0x00);
1030}
1031
1032static void lmk04832_dclk_unprepare(struct clk_hw *hw)
1033{
1034 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1035 struct lmk04832 *lmk = dclk->lmk;
1036
1037 regmap_update_bits(lmk->regmap,
1038 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1039 LMK04832_BIT_DCLKX_Y_PD, 0xff);
1040}
1041
1042static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw,
1043 unsigned long prate)
1044{
1045 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1046 struct lmk04832 *lmk = dclk->lmk;
1047 unsigned int dclk_div;
1048 unsigned int lsb, msb;
1049 unsigned long rate;
1050 int ret;
1051
1052 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1053 &lsb);
1054 if (ret)
1055 return ret;
1056
1057 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1058 &msb);
1059 if (ret)
1060 return ret;
1061
1062 dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
1063 rate = DIV_ROUND_CLOSEST(prate, dclk_div);
1064
1065 return rate;
1066};
1067
1068static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
1069 unsigned long *prate)
1070{
1071 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1072 struct lmk04832 *lmk = dclk->lmk;
1073 unsigned long dclk_rate;
1074 unsigned int dclk_div;
1075
1076 dclk_div = DIV_ROUND_CLOSEST(*prate, rate);
1077 dclk_rate = DIV_ROUND_CLOSEST(*prate, dclk_div);
1078
1079 if (dclk_div < 1 || dclk_div > 0x3ff) {
1080 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1081 return -EINVAL;
1082 }
1083
1084 if (rate != dclk_rate)
1085 return -EINVAL;
1086
1087 return dclk_rate;
1088};
1089
1090static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
1091 unsigned long prate)
1092{
1093 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1094 struct lmk04832 *lmk = dclk->lmk;
1095 unsigned int dclk_div;
1096 int ret;
1097
1098 dclk_div = DIV_ROUND_CLOSEST(prate, rate);
1099
1100 if (dclk_div > 0x3ff) {
1101 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1102 return -EINVAL;
1103 }
1104
2cdee50e 1105 /* Enable Duty Cycle Correction */
3bc61cfd
LB		 1106 if (dclk_div == 1) {
1107 ret = regmap_update_bits(lmk->regmap,
1108 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1109 LMK04832_BIT_DCLKX_Y_DCC,
1110 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1));
1111 if (ret)
1112 return ret;
1113 }
1114
6181baa1
LB		 1115 /*
1116 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC
1117 * procedure requires to first program Divide-by-4 and then back to
1118 * Divide-by-2 or Divide-by-3 before doing SYNC.
1119 */
1120 if (dclk_div == 2 || dclk_div == 3) {
1121 ret = regmap_update_bits(lmk->regmap,
1122 LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1123 LMK04832_BIT_DCLK_DIV_MSB, 0x00);
1124 if (ret)
1125 return ret;
1126
1127 ret = regmap_write(lmk->regmap,
1128 LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04);
1129 if (ret)
1130 return ret;
1131 }
1132
3bc61cfd
LB		 1133 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1134 FIELD_GET(0x0ff, dclk_div));
1135 if (ret)
1136 return ret;
1137
6181baa1 1138 ret = regmap_update_bits(lmk->regmap,
3bc61cfd
LB		 1139 LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1140 LMK04832_BIT_DCLK_DIV_MSB,
1141 FIELD_GET(0x300, dclk_div));
6181baa1
LB		 1142 if (ret)
1143 return ret;
1144
1145 ret = lmk04832_sclk_sync_sequence(lmk);
1146 if (ret)
1147 dev_err(lmk->dev, "SYNC sequence failed\n");
1148
1149 return ret;
3bc61cfd
LB		 1150};
1151
1152static const struct clk_ops lmk04832_dclk_ops = {
1153 .is_enabled = lmk04832_dclk_is_enabled,
1154 .prepare = lmk04832_dclk_prepare,
1155 .unprepare = lmk04832_dclk_unprepare,
1156 .recalc_rate = lmk04832_dclk_recalc_rate,
1157 .round_rate = lmk04832_dclk_round_rate,
1158 .set_rate = lmk04832_dclk_set_rate,
1159};
1160
1161static int lmk04832_clkout_is_enabled(struct clk_hw *hw)
1162{
1163 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1164 struct lmk04832 *lmk = clkout->lmk;
1165 unsigned int clkoutx_y_pd;
1166 unsigned int sclkx_y_pd;
1167 unsigned int tmp;
1168 u32 enabled;
1169 int ret;
1170 u8 fmt;
1171
1172 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1173 &clkoutx_y_pd);
1174 if (ret)
1175 return ret;
1176
1177 enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd);
1178
1179 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1180 &tmp);
1181 if (ret)
1182 return ret;
1183
1184 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1185 ret = regmap_read(lmk->regmap,
1186 LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1187 &sclkx_y_pd);
1188 if (ret)
1189 return ret;
1190
1191 enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd);
1192 }
1193
1194 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1195 &tmp);
1196 if (ret)
1197 return ret;
1198
1199 if (clkout->id % 2)
1200 fmt = FIELD_GET(0xf0, tmp);
1201 else
1202 fmt = FIELD_GET(0x0f, tmp);
1203
1204 return enabled && !fmt;
1205}
1206
1207static int lmk04832_clkout_prepare(struct clk_hw *hw)
1208{
1209 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1210 struct lmk04832 *lmk = clkout->lmk;
1211 unsigned int tmp;
1212 int ret;
1213
1214 if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN)
1215 dev_err(lmk->dev, "prepared %s but format is powerdown\n",
1216 clk_hw_get_name(hw));
1217
1218 ret = regmap_update_bits(lmk->regmap,
1219 LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1220 LMK04832_BIT_CLKOUTX_Y_PD, 0x00);
1221 if (ret)
1222 return ret;
1223
1224 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1225 &tmp);
1226 if (ret)
1227 return ret;
1228
1229 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1230 ret = regmap_update_bits(lmk->regmap,
1231 LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1232 LMK04832_BIT_SCLK_PD, 0x00);
1233 if (ret)
1234 return ret;
1235 }
1236
1237 return regmap_update_bits(lmk->regmap,
1238 LMK04832_REG_CLKOUT_FMT(clkout->id),
1239 LMK04832_BIT_CLKOUT_FMT(clkout->id),
1240 clkout->format << 4 * (clkout->id % 2));
1241}
1242
1243static void lmk04832_clkout_unprepare(struct clk_hw *hw)
1244{
1245 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1246 struct lmk04832 *lmk = clkout->lmk;
1247
1248 regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1249 LMK04832_BIT_CLKOUT_FMT(clkout->id),
1250 0x00);
1251}
1252
1253static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index)
1254{
1255 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1256 struct lmk04832 *lmk = clkout->lmk;
1257
1258 return regmap_update_bits(lmk->regmap,
1259 LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1260 LMK04832_BIT_CLKOUT_SRC_MUX,
1261 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1262 index));
1263}
1264
1265static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw)
1266{
1267 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1268 struct lmk04832 *lmk = clkout->lmk;
1269 unsigned int tmp;
1270 int ret;
1271
1272 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1273 &tmp);
1274 if (ret)
1275 return ret;
1276
1277 return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp);
1278}
1279
1280static const struct clk_ops lmk04832_clkout_ops = {
1281 .is_enabled = lmk04832_clkout_is_enabled,
1282 .prepare = lmk04832_clkout_prepare,
1283 .unprepare = lmk04832_clkout_unprepare,
1284 .set_parent = lmk04832_clkout_set_parent,
1285 .get_parent = lmk04832_clkout_get_parent,
1286};
1287
1288static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
1289{
1290 char name[] = "lmk-clkoutXX";
1291 char dclk_name[] = "lmk-dclkXX_YY";
1292 const char *parent_names[2];
1293 struct clk_init_data init;
1294 int dclk_num = num / 2;
1295 int ret;
1296
1297 if (num % 2 == 0) {
1298 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
1299 init.name = dclk_name;
1300 parent_names[0] = clk_hw_get_name(&lmk->vco);
1301 init.ops = &lmk04832_dclk_ops;
1302 init.flags = CLK_SET_RATE_PARENT;
1303 init.num_parents = 1;
1304
1305 lmk->dclk[dclk_num].id = num;
1306 lmk->dclk[dclk_num].lmk = lmk;
1307 lmk->dclk[dclk_num].hw.init = &init;
1308
1309 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw);
1310 if (ret)
1311 return ret;
1312 } else {
1313 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num);
1314 }
1315
1316 if (of_property_read_string_index(lmk->dev->of_node,
1317 "clock-output-names",
1318 num, &init.name)) {
1319 sprintf(name, "lmk-clkout%02d", num);
1320 init.name = name;
1321 }
1322
1323 parent_names[0] = dclk_name;
1324 parent_names[1] = clk_hw_get_name(&lmk->sclk);
1325 init.parent_names = parent_names;
1326 init.ops = &lmk04832_clkout_ops;
1327 init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
1328 init.num_parents = ARRAY_SIZE(parent_names);
1329
1330 lmk->clkout[num].id = num;
1331 lmk->clkout[num].lmk = lmk;
1332 lmk->clkout[num].hw.init = &init;
1333 lmk->clk_data->hws[num] = &lmk->clkout[num].hw;
1334
1335 /* Set initial parent */
1336 regmap_update_bits(lmk->regmap,
1337 LMK04832_REG_CLKOUT_SRC_MUX(num),
1338 LMK04832_BIT_CLKOUT_SRC_MUX,
1339 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1340 lmk->clkout[num].sysref));
1341
1342 return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw);
1343}
1344
1345static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
1346{
1347 int reg;
1348 int ret;
1349
1350 dev_info(lmk->dev, "setting up 4-wire mode\n");
1351 ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
1352 LMK04832_BIT_SPI_3WIRE_DIS);
1353 if (ret)
1354 return ret;
1355
1356 switch (rdbk_pin) {
1357 case RDBK_CLKIN_SEL0:
1358 reg = LMK04832_REG_CLKIN_SEL0;
1359 break;
1360 case RDBK_CLKIN_SEL1:
1361 reg = LMK04832_REG_CLKIN_SEL1;
1362 break;
1363 case RDBK_RESET:
1364 reg = LMK04832_REG_CLKIN_RST;
1365 break;
1366 default:
1367 return -EINVAL;
1368 }
1369
1370 return regmap_write(lmk->regmap, reg,
1371 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
1372 LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
1373 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
1374 LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
1375}
1376
1377static int lmk04832_probe(struct spi_device *spi)
1378{
1379 const struct lmk04832_device_info *info;
1380 int rdbk_pin = RDBK_CLKIN_SEL1;
1381 struct device_node *child;
1382 struct lmk04832 *lmk;
1383 u8 tmp[3];
1384 int ret;
1385 int i;
1386
1387 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
1388
1389 lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL);
1390 if (!lmk)
1391 return -ENOMEM;
1392
1393 lmk->dev = &spi->dev;
1394
1395 lmk->oscin = devm_clk_get(lmk->dev, "oscin");
1396 if (IS_ERR(lmk->oscin)) {
1397 dev_err(lmk->dev, "failed to get oscin clock\n");
1398 return PTR_ERR(lmk->oscin);
1399 }
1400
1401 ret = clk_prepare_enable(lmk->oscin);
1402 if (ret)
1403 return ret;
1404
1405 lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
1406 GPIOD_OUT_LOW);
1407
1408 lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
1409 sizeof(struct lmk_dclk), GFP_KERNEL);
b424f73b
WH		 1410 if (!lmk->dclk) {
1411 ret = -ENOMEM;
3bc61cfd
LB		 1412 goto err_disable_oscin;
1413 }
1414
1415 lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
1416 sizeof(*lmk->clkout), GFP_KERNEL);
b424f73b
WH		 1417 if (!lmk->clkout) {
1418 ret = -ENOMEM;
3bc61cfd
LB		 1419 goto err_disable_oscin;
1420 }
1421
1422 lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
1423 info->num_channels),
1424 GFP_KERNEL);
b424f73b
WH		 1425 if (!lmk->clk_data) {
1426 ret = -ENOMEM;
3bc61cfd
LB		 1427 goto err_disable_oscin;
1428 }
1429
1430 device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
1431
6181baa1
LB		 1432 lmk->sysref_ddly = 8;
1433 device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);
1434
1435 lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS;
1436 device_property_read_u32(lmk->dev, "ti,sysref-mux",
1437 &lmk->sysref_mux);
1438
1439 lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF;
1440 device_property_read_u32(lmk->dev, "ti,sync-mode",
1441 &lmk->sync_mode);
1442
1443 lmk->sysref_pulse_cnt = 4;
1444 device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
1445 &lmk->sysref_pulse_cnt);
1446
3bc61cfd
LB		 1447 for_each_child_of_node(lmk->dev->of_node, child) {
1448 int reg;
1449
1450 ret = of_property_read_u32(child, "reg", &reg);
1451 if (ret) {
1452 dev_err(lmk->dev, "missing reg property in child: %s\n",
1453 child->full_name);
1454 of_node_put(child);
1455 goto err_disable_oscin;
1456 }
1457
1458 of_property_read_u32(child, "ti,clkout-fmt",
1459 &lmk->clkout[reg].format);
1460
1461 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0
1462 && reg != 8 && reg != 10)
1463 dev_err(lmk->dev, "invalid format for clkout%02d\n",
1464 reg);
1465
1466 lmk->clkout[reg].sysref =
1467 of_property_read_bool(child, "ti,clkout-sysref");
1468 }
1469
1470 lmk->regmap = devm_regmap_init_spi(spi, &regmap_config);
1471 if (IS_ERR(lmk->regmap)) {
1472 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n",
1473
1474 __func__, PTR_ERR(lmk->regmap));
1475 ret = PTR_ERR(lmk->regmap);
1476 goto err_disable_oscin;
1477 }
1478
1479 regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET);
1480
1481 if (!(spi->mode & SPI_3WIRE)) {
1482 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk",
1483 &rdbk_pin);
1484 ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin);
1485 if (ret)
1486 goto err_disable_oscin;
1487 }
1488
1489 regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3);
1490 if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) {
1491 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n",
1492 tmp[0] << 8 | tmp[1], tmp[2]);
1493 ret = -EINVAL;
1494 goto err_disable_oscin;
1495 }
1496
1497 ret = lmk04832_register_vco(lmk);
1498 if (ret) {
1499 dev_err(lmk->dev, "failed to init device clock path\n");
1500 goto err_disable_oscin;
1501 }
1502
1503 if (lmk->vco_rate) {
1504 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate);
1505 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
1506 if (ret) {
1507 dev_err(lmk->dev, "failed to set VCO rate\n");
1508 goto err_disable_vco;
1509 }
1510 }
1511
1512 ret = lmk04832_register_sclk(lmk);
1513 if (ret) {
1514 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
1515 goto err_disable_vco;
1516 }
1517
1518 for (i = 0; i < info->num_channels; i++) {
1519 ret = lmk04832_register_clkout(lmk, i);
1520 if (ret) {
1521 dev_err(lmk->dev, "failed to register clk %d\n", i);
1522 goto err_disable_vco;
1523 }
1524 }
1525
1526 lmk->clk_data->num = info->num_channels;
1527 ret = of_clk_add_hw_provider(lmk->dev->of_node, of_clk_hw_onecell_get,
1528 lmk->clk_data);
1529 if (ret) {
1530 dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
1531 goto err_disable_vco;
1532 }
1533
1534 spi_set_drvdata(spi, lmk);
1535
1536 return 0;
1537
1538err_disable_vco:
1539 clk_disable_unprepare(lmk->vco.clk);
1540
1541err_disable_oscin:
1542 clk_disable_unprepare(lmk->oscin);
1543
1544 return ret;
1545}
1546
a0386bba 1547static void lmk04832_remove(struct spi_device *spi)
3bc61cfd
LB		 1548{
1549 struct lmk04832 *lmk = spi_get_drvdata(spi);
1550
1551 clk_disable_unprepare(lmk->oscin);
1552 of_clk_del_provider(spi->dev.of_node);
3bc61cfd
LB		 1553}
1554static const struct spi_device_id lmk04832_id[] = {
1555 { "lmk04832", LMK04832 },
bf68fdfd 1556 {}
3bc61cfd
LB		 1557};
1558MODULE_DEVICE_TABLE(spi, lmk04832_id);
1559
1560static const struct of_device_id lmk04832_of_id[] = {
1561 { .compatible = "ti,lmk04832" },
bf68fdfd 1562 {}
3bc61cfd 1563};
bf68fdfd 1564MODULE_DEVICE_TABLE(of, lmk04832_of_id);
3bc61cfd
LB		 1565
1566static struct spi_driver lmk04832_driver = {
1567 .driver = {
1568 .name = "lmk04832",
bf68fdfd 1569 .of_match_table = lmk04832_of_id,
3bc61cfd
LB		 1570 },
1571 .probe = lmk04832_probe,
1572 .remove = lmk04832_remove,
1573 .id_table = lmk04832_id,
1574};
1575module_spi_driver(lmk04832_driver);
1576
1577MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>");
1578MODULE_DESCRIPTION("Texas Instruments LMK04832");
1579MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)