[linux-2.6-block.git] / drivers / clk / clk-highbank.c

/*
 * Copyright 2011-2012 Calxeda, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>

#define HB_PLL_LOCK_500		0x20000000
#define HB_PLL_LOCK		0x10000000
#define HB_PLL_DIVF_SHIFT	20
#define HB_PLL_DIVF_MASK	0x0ff00000
#define HB_PLL_DIVQ_SHIFT	16
#define HB_PLL_DIVQ_MASK	0x00070000
#define HB_PLL_DIVR_SHIFT	8
#define HB_PLL_DIVR_MASK	0x00001f00
#define HB_PLL_RANGE_SHIFT	4
#define HB_PLL_RANGE_MASK	0x00000070
#define HB_PLL_BYPASS		0x00000008
#define HB_PLL_RESET		0x00000004
#define HB_PLL_EXT_BYPASS	0x00000002
#define HB_PLL_EXT_ENA		0x00000001

#define HB_PLL_VCO_MIN_FREQ	2133000000
#define HB_PLL_MAX_FREQ		HB_PLL_VCO_MIN_FREQ
#define HB_PLL_MIN_FREQ		(HB_PLL_VCO_MIN_FREQ / 64)

#define HB_A9_BCLK_DIV_MASK	0x00000006
#define HB_A9_BCLK_DIV_SHIFT	1
#define HB_A9_PCLK_DIV		0x00000001

struct hb_clk {
        struct clk_hw	hw;
	void __iomem	*reg;
	char *parent_name;
};
#define to_hb_clk(p) container_of(p, struct hb_clk, hw)

static int clk_pll_prepare(struct clk_hw *hwclk)
	{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 reg;

	reg = readl(hbclk->reg);
	reg &= ~HB_PLL_RESET;
	writel(reg, hbclk->reg);

	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
		;
	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
		;

	return 0;
}

static void clk_pll_unprepare(struct clk_hw *hwclk)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 reg;

	reg = readl(hbclk->reg);
	reg |= HB_PLL_RESET;
	writel(reg, hbclk->reg);
}

static int clk_pll_enable(struct clk_hw *hwclk)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 reg;

	reg = readl(hbclk->reg);
	reg |= HB_PLL_EXT_ENA;
	writel(reg, hbclk->reg);

	return 0;
}

static void clk_pll_disable(struct clk_hw *hwclk)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 reg;

	reg = readl(hbclk->reg);
	reg &= ~HB_PLL_EXT_ENA;
	writel(reg, hbclk->reg);
}

static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
					 unsigned long parent_rate)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	unsigned long divf, divq, vco_freq, reg;

	reg = readl(hbclk->reg);
	if (reg & HB_PLL_EXT_BYPASS)
		return parent_rate;

	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
	vco_freq = parent_rate * (divf + 1);

	return vco_freq / (1 << divq);
}

static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
			u32 *pdivq, u32 *pdivf)
{
	u32 divq, divf;
	unsigned long vco_freq;

	if (rate < HB_PLL_MIN_FREQ)
		rate = HB_PLL_MIN_FREQ;
	if (rate > HB_PLL_MAX_FREQ)
		rate = HB_PLL_MAX_FREQ;

	for (divq = 1; divq <= 6; divq++) {
		if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
			break;
	}

	vco_freq = rate * (1 << divq);
	divf = (vco_freq + (ref_freq / 2)) / ref_freq;
	divf--;

	*pdivq = divq;
	*pdivf = divf;
}

static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
			       unsigned long *parent_rate)
{
	u32 divq, divf;
	unsigned long ref_freq = *parent_rate;

	clk_pll_calc(rate, ref_freq, &divq, &divf);

	return (ref_freq * (divf + 1)) / (1 << divq);
}

static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
			    unsigned long parent_rate)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 divq, divf;
	u32 reg;

	clk_pll_calc(rate, parent_rate, &divq, &divf);

	reg = readl(hbclk->reg);
	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
		/* Need to re-lock PLL, so put it into bypass mode */
		reg |= HB_PLL_EXT_BYPASS;
		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);

		writel(reg | HB_PLL_RESET, hbclk->reg);
		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
		writel(reg | HB_PLL_RESET, hbclk->reg);
		writel(reg, hbclk->reg);

		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
			;
		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
			;
		reg |= HB_PLL_EXT_ENA;
		reg &= ~HB_PLL_EXT_BYPASS;
	} else {
		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
		reg &= ~HB_PLL_DIVQ_MASK;
		reg |= divq << HB_PLL_DIVQ_SHIFT;
		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
	}
	writel(reg, hbclk->reg);

	return 0;
}

static const struct clk_ops clk_pll_ops = {
	.prepare = clk_pll_prepare,
	.unprepare = clk_pll_unprepare,
	.enable = clk_pll_enable,
	.disable = clk_pll_disable,
	.recalc_rate = clk_pll_recalc_rate,
	.round_rate = clk_pll_round_rate,
	.set_rate = clk_pll_set_rate,
};

static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
						   unsigned long parent_rate)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
	return parent_rate / div;
}

static const struct clk_ops a9periphclk_ops = {
	.recalc_rate = clk_cpu_periphclk_recalc_rate,
};

static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
						unsigned long parent_rate)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;

	return parent_rate / (div + 2);
}

static const struct clk_ops a9bclk_ops = {
	.recalc_rate = clk_cpu_a9bclk_recalc_rate,
};

static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
					     unsigned long parent_rate)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 div;

	div = readl(hbclk->reg) & 0x1f;
	div++;
	div *= 2;

	return parent_rate / div;
}

static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
				   unsigned long *parent_rate)
{
	u32 div;

	div = *parent_rate / rate;
	div++;
	div &= ~0x1;

	return *parent_rate / div;
}

static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
				unsigned long parent_rate)
{
	struct hb_clk *hbclk = to_hb_clk(hwclk);
	u32 div;

	div = parent_rate / rate;
	if (div & 0x1)
		return -EINVAL;

	writel(div >> 1, hbclk->reg);
	return 0;
}

static const struct clk_ops periclk_ops = {
	.recalc_rate = clk_periclk_recalc_rate,
	.round_rate = clk_periclk_round_rate,
	.set_rate = clk_periclk_set_rate,
};

static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
{
	u32 reg;
	struct clk *clk;
	struct hb_clk *hb_clk;
	const char *clk_name = node->name;
	const char *parent_name;
	struct clk_init_data init;
	struct device_node *srnp;
	int rc;

	rc = of_property_read_u32(node, "reg", &reg);
	if (WARN_ON(rc))
		return NULL;

	hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
	if (WARN_ON(!hb_clk))
		return NULL;

	/* Map system registers */
	srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
	hb_clk->reg = of_iomap(srnp, 0);
	BUG_ON(!hb_clk->reg);
	hb_clk->reg += reg;

	of_property_read_string(node, "clock-output-names", &clk_name);

	init.name = clk_name;
	init.ops = ops;
	init.flags = 0;
	parent_name = of_clk_get_parent_name(node, 0);
	init.parent_names = &parent_name;
	init.num_parents = 1;

	hb_clk->hw.init = &init;

	clk = clk_register(NULL, &hb_clk->hw);
	if (WARN_ON(IS_ERR(clk))) {
		kfree(hb_clk);
		return NULL;
	}
	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	return clk;
}

static void __init hb_pll_init(struct device_node *node)
{
	hb_clk_init(node, &clk_pll_ops);
}
CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);

static void __init hb_a9periph_init(struct device_node *node)
{
	hb_clk_init(node, &a9periphclk_ops);
}
CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);

static void __init hb_a9bus_init(struct device_node *node)
{
	struct clk *clk = hb_clk_init(node, &a9bclk_ops);
	clk_prepare_enable(clk);
}
CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);

static void __init hb_emmc_init(struct device_node *node)
{
	hb_clk_init(node, &periclk_ops);
}
CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
Commit	Line	Data
8d4d9f52 RH	1	/*
	2	* Copyright 2011-2012 Calxeda, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/slab.h>
	19	#include <linux/err.h>
	20	#include <linux/clk-provider.h>
	21	#include <linux/io.h>
	22	#include <linux/of.h>
26cae166	23	#include <linux/of_address.h>
8d4d9f52 RH	24
	25	#define HB_PLL_LOCK_500 0x20000000
	26	#define HB_PLL_LOCK 0x10000000
	27	#define HB_PLL_DIVF_SHIFT 20
	28	#define HB_PLL_DIVF_MASK 0x0ff00000
	29	#define HB_PLL_DIVQ_SHIFT 16
	30	#define HB_PLL_DIVQ_MASK 0x00070000
	31	#define HB_PLL_DIVR_SHIFT 8
	32	#define HB_PLL_DIVR_MASK 0x00001f00
	33	#define HB_PLL_RANGE_SHIFT 4
	34	#define HB_PLL_RANGE_MASK 0x00000070
	35	#define HB_PLL_BYPASS 0x00000008
	36	#define HB_PLL_RESET 0x00000004
	37	#define HB_PLL_EXT_BYPASS 0x00000002
	38	#define HB_PLL_EXT_ENA 0x00000001
	39
	40	#define HB_PLL_VCO_MIN_FREQ 2133000000
	41	#define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ
	42	#define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64)
	43
	44	#define HB_A9_BCLK_DIV_MASK 0x00000006
	45	#define HB_A9_BCLK_DIV_SHIFT 1
	46	#define HB_A9_PCLK_DIV 0x00000001
	47
	48	struct hb_clk {
	49	struct clk_hw hw;
	50	void __iomem *reg;
	51	char *parent_name;
	52	};
	53	#define to_hb_clk(p) container_of(p, struct hb_clk, hw)
	54
	55	static int clk_pll_prepare(struct clk_hw *hwclk)
	56	{
	57	struct hb_clk *hbclk = to_hb_clk(hwclk);
	58	u32 reg;
	59
	60	reg = readl(hbclk->reg);
	61	reg &= ~HB_PLL_RESET;
	62	writel(reg, hbclk->reg);
	63
	64	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
	65	;
	66	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
	67	;
	68
	69	return 0;
	70	}
	71
	72	static void clk_pll_unprepare(struct clk_hw *hwclk)
	73	{
	74	struct hb_clk *hbclk = to_hb_clk(hwclk);
	75	u32 reg;
	76
	77	reg = readl(hbclk->reg);
	78	reg \|= HB_PLL_RESET;
	79	writel(reg, hbclk->reg);
	80	}
	81
	82	static int clk_pll_enable(struct clk_hw *hwclk)
	83	{
	84	struct hb_clk *hbclk = to_hb_clk(hwclk);
	85	u32 reg;
	86
	87	reg = readl(hbclk->reg);
88	reg \|= HB_PLL_EXT_ENA;
89	writel(reg, hbclk->reg);
90
91	return 0;
92	}
93
94	static void clk_pll_disable(struct clk_hw *hwclk)
95	{
96	struct hb_clk *hbclk = to_hb_clk(hwclk);
97	u32 reg;
98
99	reg = readl(hbclk->reg);
100	reg &= ~HB_PLL_EXT_ENA;
101	writel(reg, hbclk->reg);
102	}
103
104	static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
105	unsigned long parent_rate)
106	{
107	struct hb_clk *hbclk = to_hb_clk(hwclk);
108	unsigned long divf, divq, vco_freq, reg;
109
110	reg = readl(hbclk->reg);
111	if (reg & HB_PLL_EXT_BYPASS)
112	return parent_rate;
113
114	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
115	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
116	vco_freq = parent_rate * (divf + 1);
117
118	return vco_freq / (1 << divq);
119	}
120
121	static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
122	u32 pdivq, u32 pdivf)
123	{
124	u32 divq, divf;
125	unsigned long vco_freq;
126
127	if (rate < HB_PLL_MIN_FREQ)
128	rate = HB_PLL_MIN_FREQ;
129	if (rate > HB_PLL_MAX_FREQ)
130	rate = HB_PLL_MAX_FREQ;
131
132	for (divq = 1; divq <= 6; divq++) {
133	if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
134	break;
135	}
136
137	vco_freq = rate * (1 << divq);
138	divf = (vco_freq + (ref_freq / 2)) / ref_freq;
139	divf--;
140
141	*pdivq = divq;
142	*pdivf = divf;
143	}
144
145	static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
146	unsigned long *parent_rate)
147	{
148	u32 divq, divf;
149	unsigned long ref_freq = *parent_rate;
150
151	clk_pll_calc(rate, ref_freq, &divq, &divf);
152
153	return (ref_freq * (divf + 1)) / (1 << divq);
154	}
155
156	static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
157	unsigned long parent_rate)
158	{
159	struct hb_clk *hbclk = to_hb_clk(hwclk);
160	u32 divq, divf;
161	u32 reg;
162
163	clk_pll_calc(rate, parent_rate, &divq, &divf);
164
165	reg = readl(hbclk->reg);
166	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
167	/* Need to re-lock PLL, so put it into bypass mode */
168	reg \|= HB_PLL_EXT_BYPASS;
169	writel(reg \| HB_PLL_EXT_BYPASS, hbclk->reg);
170
171	writel(reg \| HB_PLL_RESET, hbclk->reg);
172	reg &= ~(HB_PLL_DIVF_MASK \| HB_PLL_DIVQ_MASK);
173	reg \|= (divf << HB_PLL_DIVF_SHIFT) \| (divq << HB_PLL_DIVQ_SHIFT);
174	writel(reg \| HB_PLL_RESET, hbclk->reg);
175	writel(reg, hbclk->reg);
176
177	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
178	;
179	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
180	;
181	reg \|= HB_PLL_EXT_ENA;
182	reg &= ~HB_PLL_EXT_BYPASS;
183	} else {
b5964708	184	writel(reg \| HB_PLL_EXT_BYPASS, hbclk->reg);
8d4d9f52 RH	185	reg &= ~HB_PLL_DIVQ_MASK;
8d4d9f52 RH	186	reg \|= divq << HB_PLL_DIVQ_SHIFT;
b5964708	187	writel(reg \| HB_PLL_EXT_BYPASS, hbclk->reg);
8d4d9f52 RH	188	}
	189	writel(reg, hbclk->reg);
	190
	191	return 0;
	192	}
	193
	194	static const struct clk_ops clk_pll_ops = {
	195	.prepare = clk_pll_prepare,
	196	.unprepare = clk_pll_unprepare,
	197	.enable = clk_pll_enable,
	198	.disable = clk_pll_disable,
	199	.recalc_rate = clk_pll_recalc_rate,
	200	.round_rate = clk_pll_round_rate,
	201	.set_rate = clk_pll_set_rate,
	202	};
	203
	204	static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
	205	unsigned long parent_rate)
	206	{
	207	struct hb_clk *hbclk = to_hb_clk(hwclk);
	208	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
	209	return parent_rate / div;
	210	}
	211
	212	static const struct clk_ops a9periphclk_ops = {
	213	.recalc_rate = clk_cpu_periphclk_recalc_rate,
	214	};
	215
	216	static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
	217	unsigned long parent_rate)
	218	{
	219	struct hb_clk *hbclk = to_hb_clk(hwclk);
	220	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
	221
	222	return parent_rate / (div + 2);
	223	}
	224
	225	static const struct clk_ops a9bclk_ops = {
	226	.recalc_rate = clk_cpu_a9bclk_recalc_rate,
	227	};
	228
	229	static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
	230	unsigned long parent_rate)
	231	{
	232	struct hb_clk *hbclk = to_hb_clk(hwclk);
	233	u32 div;
	234
	235	div = readl(hbclk->reg) & 0x1f;
	236	div++;
	237	div *= 2;
	238
	239	return parent_rate / div;
	240	}
	241
	242	static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
	243	unsigned long *parent_rate)
	244	{
	245	u32 div;
	246
	247	div = *parent_rate / rate;
	248	div++;
	249	div &= ~0x1;
	250
	251	return *parent_rate / div;
252	}
253
254	static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
255	unsigned long parent_rate)
256	{
257	struct hb_clk *hbclk = to_hb_clk(hwclk);
258	u32 div;
259
260	div = parent_rate / rate;
261	if (div & 0x1)
262	return -EINVAL;
263
264	writel(div >> 1, hbclk->reg);
265	return 0;
266	}
267
268	static const struct clk_ops periclk_ops = {
269	.recalc_rate = clk_periclk_recalc_rate,
270	.round_rate = clk_periclk_round_rate,
271	.set_rate = clk_periclk_set_rate,
272	};
273
274	static __init struct clk hb_clk_init(struct device_node node, const struct clk_ops *ops)
275	{
276	u32 reg;
277	struct clk *clk;
278	struct hb_clk *hb_clk;
279	const char *clk_name = node->name;
280	const char *parent_name;
281	struct clk_init_data init;
26cae166	282	struct device_node *srnp;
8d4d9f52 RH	283	int rc;
	284
	285	rc = of_property_read_u32(node, "reg", &reg);
	286	if (WARN_ON(rc))
	287	return NULL;
	288
	289	hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
	290	if (WARN_ON(!hb_clk))
	291	return NULL;
	292
26cae166 SH	293	/* Map system registers */
	294	srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
	295	hb_clk->reg = of_iomap(srnp, 0);
	296	BUG_ON(!hb_clk->reg);
	297	hb_clk->reg += reg;
8d4d9f52 RH	298
	299	of_property_read_string(node, "clock-output-names", &clk_name);
	300
	301	init.name = clk_name;
	302	init.ops = ops;
	303	init.flags = 0;
	304	parent_name = of_clk_get_parent_name(node, 0);
	305	init.parent_names = &parent_name;
	306	init.num_parents = 1;
	307
	308	hb_clk->hw.init = &init;
	309
	310	clk = clk_register(NULL, &hb_clk->hw);
	311	if (WARN_ON(IS_ERR(clk))) {
	312	kfree(hb_clk);
	313	return NULL;
	314	}
	315	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	316	return clk;
	317	}
	318
	319	static void __init hb_pll_init(struct device_node *node)
	320	{
	321	hb_clk_init(node, &clk_pll_ops);
	322	}
d34bcdeb	323	CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
8d4d9f52 RH	324
	325	static void __init hb_a9periph_init(struct device_node *node)
	326	{
	327	hb_clk_init(node, &a9periphclk_ops);
	328	}
d34bcdeb	329	CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
8d4d9f52 RH	330
	331	static void __init hb_a9bus_init(struct device_node *node)
	332	{
	333	struct clk *clk = hb_clk_init(node, &a9bclk_ops);
	334	clk_prepare_enable(clk);
	335	}
d34bcdeb	336	CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
8d4d9f52 RH	337
	338	static void __init hb_emmc_init(struct device_node *node)
	339	{
	340	hb_clk_init(node, &periclk_ops);
	341	}
d34bcdeb	342	CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);