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e1bd55e5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c873d14d JS |
2 | /* |
3 | * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - http://www.ti.com | |
80eeb1f0 SS |
4 | * |
5 | * Authors: | |
6 | * Jyri Sarha <jsarha@ti.com> | |
7 | * Sergej Sawazki <ce3a@gmx.de> | |
c873d14d | 8 | * |
80eeb1f0 | 9 | * Gpio controlled clock implementation |
c873d14d JS |
10 | */ |
11 | ||
12 | #include <linux/clk-provider.h> | |
e21b08e2 | 13 | #include <linux/export.h> |
c873d14d | 14 | #include <linux/slab.h> |
44b4aa97 | 15 | #include <linux/gpio/consumer.h> |
c873d14d JS |
16 | #include <linux/err.h> |
17 | #include <linux/device.h> | |
14b04f28 SB |
18 | #include <linux/platform_device.h> |
19 | #include <linux/of_device.h> | |
c873d14d JS |
20 | |
21 | /** | |
22 | * DOC: basic gpio gated clock which can be enabled and disabled | |
23 | * with gpio output | |
24 | * Traits of this clock: | |
25 | * prepare - clk_(un)prepare only ensures parent is (un)prepared | |
26 | * enable - clk_enable and clk_disable are functional & control gpio | |
27 | * rate - inherits rate from parent. No clk_set_rate support | |
28 | * parent - fixed parent. No clk_set_parent support | |
29 | */ | |
30 | ||
c873d14d JS |
31 | static int clk_gpio_gate_enable(struct clk_hw *hw) |
32 | { | |
33 | struct clk_gpio *clk = to_clk_gpio(hw); | |
34 | ||
35 | gpiod_set_value(clk->gpiod, 1); | |
36 | ||
37 | return 0; | |
38 | } | |
39 | ||
40 | static void clk_gpio_gate_disable(struct clk_hw *hw) | |
41 | { | |
42 | struct clk_gpio *clk = to_clk_gpio(hw); | |
43 | ||
44 | gpiod_set_value(clk->gpiod, 0); | |
45 | } | |
46 | ||
47 | static int clk_gpio_gate_is_enabled(struct clk_hw *hw) | |
48 | { | |
49 | struct clk_gpio *clk = to_clk_gpio(hw); | |
50 | ||
51 | return gpiod_get_value(clk->gpiod); | |
52 | } | |
53 | ||
54 | const struct clk_ops clk_gpio_gate_ops = { | |
55 | .enable = clk_gpio_gate_enable, | |
56 | .disable = clk_gpio_gate_disable, | |
57 | .is_enabled = clk_gpio_gate_is_enabled, | |
58 | }; | |
59 | EXPORT_SYMBOL_GPL(clk_gpio_gate_ops); | |
60 | ||
c0189fee TP |
61 | static int clk_sleeping_gpio_gate_prepare(struct clk_hw *hw) |
62 | { | |
63 | struct clk_gpio *clk = to_clk_gpio(hw); | |
64 | ||
65 | gpiod_set_value_cansleep(clk->gpiod, 1); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | static void clk_sleeping_gpio_gate_unprepare(struct clk_hw *hw) | |
71 | { | |
72 | struct clk_gpio *clk = to_clk_gpio(hw); | |
73 | ||
74 | gpiod_set_value_cansleep(clk->gpiod, 0); | |
75 | } | |
76 | ||
77 | static int clk_sleeping_gpio_gate_is_prepared(struct clk_hw *hw) | |
78 | { | |
79 | struct clk_gpio *clk = to_clk_gpio(hw); | |
80 | ||
81 | return gpiod_get_value_cansleep(clk->gpiod); | |
82 | } | |
83 | ||
84 | static const struct clk_ops clk_sleeping_gpio_gate_ops = { | |
85 | .prepare = clk_sleeping_gpio_gate_prepare, | |
86 | .unprepare = clk_sleeping_gpio_gate_unprepare, | |
87 | .is_prepared = clk_sleeping_gpio_gate_is_prepared, | |
88 | }; | |
89 | ||
c873d14d | 90 | /** |
80eeb1f0 SS |
91 | * DOC: basic clock multiplexer which can be controlled with a gpio output |
92 | * Traits of this clock: | |
93 | * prepare - clk_prepare only ensures that parents are prepared | |
94 | * rate - rate is only affected by parent switching. No clk_set_rate support | |
95 | * parent - parent is adjustable through clk_set_parent | |
c873d14d | 96 | */ |
80eeb1f0 SS |
97 | |
98 | static u8 clk_gpio_mux_get_parent(struct clk_hw *hw) | |
c873d14d | 99 | { |
80eeb1f0 SS |
100 | struct clk_gpio *clk = to_clk_gpio(hw); |
101 | ||
2e838e7f | 102 | return gpiod_get_value_cansleep(clk->gpiod); |
80eeb1f0 SS |
103 | } |
104 | ||
105 | static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index) | |
106 | { | |
107 | struct clk_gpio *clk = to_clk_gpio(hw); | |
108 | ||
2e838e7f | 109 | gpiod_set_value_cansleep(clk->gpiod, index); |
80eeb1f0 SS |
110 | |
111 | return 0; | |
112 | } | |
113 | ||
114 | const struct clk_ops clk_gpio_mux_ops = { | |
115 | .get_parent = clk_gpio_mux_get_parent, | |
116 | .set_parent = clk_gpio_mux_set_parent, | |
117 | .determine_rate = __clk_mux_determine_rate, | |
118 | }; | |
119 | EXPORT_SYMBOL_GPL(clk_gpio_mux_ops); | |
120 | ||
b120743a | 121 | static struct clk_hw *clk_register_gpio(struct device *dev, const char *name, |
908a543a LW |
122 | const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, |
123 | unsigned long flags, const struct clk_ops *clk_gpio_ops) | |
80eeb1f0 SS |
124 | { |
125 | struct clk_gpio *clk_gpio; | |
b120743a | 126 | struct clk_hw *hw; |
80eeb1f0 | 127 | struct clk_init_data init = {}; |
c873d14d JS |
128 | int err; |
129 | ||
80eeb1f0 SS |
130 | if (dev) |
131 | clk_gpio = devm_kzalloc(dev, sizeof(*clk_gpio), GFP_KERNEL); | |
132 | else | |
133 | clk_gpio = kzalloc(sizeof(*clk_gpio), GFP_KERNEL); | |
134 | ||
135 | if (!clk_gpio) | |
136 | return ERR_PTR(-ENOMEM); | |
137 | ||
c873d14d | 138 | init.name = name; |
80eeb1f0 | 139 | init.ops = clk_gpio_ops; |
c873d14d | 140 | init.flags = flags | CLK_IS_BASIC; |
80eeb1f0 SS |
141 | init.parent_names = parent_names; |
142 | init.num_parents = num_parents; | |
c873d14d | 143 | |
908a543a | 144 | clk_gpio->gpiod = gpiod; |
c873d14d JS |
145 | clk_gpio->hw.init = &init; |
146 | ||
b120743a | 147 | hw = &clk_gpio->hw; |
80eeb1f0 | 148 | if (dev) |
b120743a | 149 | err = devm_clk_hw_register(dev, hw); |
80eeb1f0 | 150 | else |
b120743a | 151 | err = clk_hw_register(NULL, hw); |
c873d14d | 152 | |
b120743a SB |
153 | if (!err) |
154 | return hw; | |
c873d14d | 155 | |
80eeb1f0 | 156 | if (!dev) { |
c873d14d | 157 | kfree(clk_gpio); |
80eeb1f0 | 158 | } |
c873d14d | 159 | |
b120743a | 160 | return ERR_PTR(err); |
c873d14d | 161 | } |
80eeb1f0 SS |
162 | |
163 | /** | |
b120743a SB |
164 | * clk_hw_register_gpio_gate - register a gpio clock gate with the clock |
165 | * framework | |
80eeb1f0 SS |
166 | * @dev: device that is registering this clock |
167 | * @name: name of this clock | |
168 | * @parent_name: name of this clock's parent | |
908a543a | 169 | * @gpiod: gpio descriptor to gate this clock |
80eeb1f0 SS |
170 | * @flags: clock flags |
171 | */ | |
b120743a | 172 | struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, |
908a543a | 173 | const char *parent_name, struct gpio_desc *gpiod, |
80eeb1f0 SS |
174 | unsigned long flags) |
175 | { | |
c0189fee TP |
176 | const struct clk_ops *ops; |
177 | ||
178 | if (gpiod_cansleep(gpiod)) | |
179 | ops = &clk_sleeping_gpio_gate_ops; | |
180 | else | |
181 | ops = &clk_gpio_gate_ops; | |
182 | ||
80eeb1f0 SS |
183 | return clk_register_gpio(dev, name, |
184 | (parent_name ? &parent_name : NULL), | |
c0189fee | 185 | (parent_name ? 1 : 0), gpiod, flags, ops); |
80eeb1f0 | 186 | } |
b120743a SB |
187 | EXPORT_SYMBOL_GPL(clk_hw_register_gpio_gate); |
188 | ||
189 | struct clk *clk_register_gpio_gate(struct device *dev, const char *name, | |
908a543a | 190 | const char *parent_name, struct gpio_desc *gpiod, |
b120743a SB |
191 | unsigned long flags) |
192 | { | |
193 | struct clk_hw *hw; | |
194 | ||
908a543a | 195 | hw = clk_hw_register_gpio_gate(dev, name, parent_name, gpiod, flags); |
b120743a SB |
196 | if (IS_ERR(hw)) |
197 | return ERR_CAST(hw); | |
198 | return hw->clk; | |
199 | } | |
c873d14d JS |
200 | EXPORT_SYMBOL_GPL(clk_register_gpio_gate); |
201 | ||
80eeb1f0 | 202 | /** |
b120743a | 203 | * clk_hw_register_gpio_mux - register a gpio clock mux with the clock framework |
80eeb1f0 SS |
204 | * @dev: device that is registering this clock |
205 | * @name: name of this clock | |
206 | * @parent_names: names of this clock's parents | |
207 | * @num_parents: number of parents listed in @parent_names | |
908a543a | 208 | * @gpiod: gpio descriptor to gate this clock |
80eeb1f0 SS |
209 | * @flags: clock flags |
210 | */ | |
b120743a | 211 | struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, |
908a543a LW |
212 | const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, |
213 | unsigned long flags) | |
80eeb1f0 SS |
214 | { |
215 | if (num_parents != 2) { | |
216 | pr_err("mux-clock %s must have 2 parents\n", name); | |
217 | return ERR_PTR(-EINVAL); | |
218 | } | |
219 | ||
220 | return clk_register_gpio(dev, name, parent_names, num_parents, | |
908a543a | 221 | gpiod, flags, &clk_gpio_mux_ops); |
80eeb1f0 | 222 | } |
b120743a SB |
223 | EXPORT_SYMBOL_GPL(clk_hw_register_gpio_mux); |
224 | ||
225 | struct clk *clk_register_gpio_mux(struct device *dev, const char *name, | |
908a543a LW |
226 | const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, |
227 | unsigned long flags) | |
b120743a SB |
228 | { |
229 | struct clk_hw *hw; | |
230 | ||
231 | hw = clk_hw_register_gpio_mux(dev, name, parent_names, num_parents, | |
908a543a | 232 | gpiod, flags); |
b120743a SB |
233 | if (IS_ERR(hw)) |
234 | return ERR_CAST(hw); | |
235 | return hw->clk; | |
236 | } | |
80eeb1f0 SS |
237 | EXPORT_SYMBOL_GPL(clk_register_gpio_mux); |
238 | ||
14b04f28 | 239 | static int gpio_clk_driver_probe(struct platform_device *pdev) |
c873d14d | 240 | { |
14b04f28 SB |
241 | struct device_node *node = pdev->dev.of_node; |
242 | const char **parent_names, *gpio_name; | |
0985df89 | 243 | unsigned int num_parents; |
908a543a | 244 | struct gpio_desc *gpiod; |
14b04f28 | 245 | struct clk *clk; |
908a543a LW |
246 | bool is_mux; |
247 | int ret; | |
14b04f28 SB |
248 | |
249 | num_parents = of_clk_get_parent_count(node); | |
14b04f28 SB |
250 | if (num_parents) { |
251 | parent_names = devm_kcalloc(&pdev->dev, num_parents, | |
252 | sizeof(char *), GFP_KERNEL); | |
253 | if (!parent_names) | |
254 | return -ENOMEM; | |
c873d14d | 255 | |
14b04f28 SB |
256 | of_clk_parent_fill(node, parent_names, num_parents); |
257 | } else { | |
258 | parent_names = NULL; | |
c873d14d JS |
259 | } |
260 | ||
14b04f28 SB |
261 | is_mux = of_device_is_compatible(node, "gpio-mux-clock"); |
262 | ||
908a543a | 263 | gpio_name = is_mux ? "select" : "enable"; |
1b5d1a58 | 264 | gpiod = devm_gpiod_get(&pdev->dev, gpio_name, GPIOD_OUT_LOW); |
908a543a LW |
265 | if (IS_ERR(gpiod)) { |
266 | ret = PTR_ERR(gpiod); | |
267 | if (ret == -EPROBE_DEFER) | |
e665f029 RH |
268 | pr_debug("%pOFn: %s: GPIOs not yet available, retry later\n", |
269 | node, __func__); | |
80eeb1f0 | 270 | else |
e665f029 RH |
271 | pr_err("%pOFn: %s: Can't get '%s' named GPIO property\n", |
272 | node, __func__, | |
14b04f28 | 273 | gpio_name); |
908a543a | 274 | return ret; |
c873d14d | 275 | } |
c873d14d | 276 | |
14b04f28 SB |
277 | if (is_mux) |
278 | clk = clk_register_gpio_mux(&pdev->dev, node->name, | |
908a543a | 279 | parent_names, num_parents, gpiod, 0); |
14b04f28 SB |
280 | else |
281 | clk = clk_register_gpio_gate(&pdev->dev, node->name, | |
908a543a LW |
282 | parent_names ? parent_names[0] : NULL, gpiod, |
283 | 0); | |
14b04f28 SB |
284 | if (IS_ERR(clk)) |
285 | return PTR_ERR(clk); | |
c873d14d | 286 | |
14b04f28 | 287 | return of_clk_add_provider(node, of_clk_src_simple_get, clk); |
80eeb1f0 SS |
288 | } |
289 | ||
14b04f28 SB |
290 | static const struct of_device_id gpio_clk_match_table[] = { |
291 | { .compatible = "gpio-mux-clock" }, | |
292 | { .compatible = "gpio-gate-clock" }, | |
293 | { } | |
294 | }; | |
80eeb1f0 | 295 | |
14b04f28 SB |
296 | static struct platform_driver gpio_clk_driver = { |
297 | .probe = gpio_clk_driver_probe, | |
298 | .driver = { | |
299 | .name = "gpio-clk", | |
300 | .of_match_table = gpio_clk_match_table, | |
301 | }, | |
302 | }; | |
303 | builtin_platform_driver(gpio_clk_driver); |