[linux-2.6-block.git] / drivers / clk / clk-gate.c

/*
 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Gated clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>

/**
 * DOC: basic gatable clock which can gate and ungate it's ouput
 *
 * Traits of this clock:
 * prepare - clk_(un)prepare only ensures parent is (un)prepared
 * enable - clk_enable and clk_disable are functional & control gating
 * rate - inherits rate from parent.  No clk_set_rate support
 * parent - fixed parent.  No clk_set_parent support
 */

#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)

static void clk_gate_set_bit(struct clk_gate *gate)
{
	u32 reg;
	unsigned long flags = 0;

	if (gate->lock)
		spin_lock_irqsave(gate->lock, flags);

	reg = readl(gate->reg);
	reg |= BIT(gate->bit_idx);
	writel(reg, gate->reg);

	if (gate->lock)
		spin_unlock_irqrestore(gate->lock, flags);
}

static void clk_gate_clear_bit(struct clk_gate *gate)
{
	u32 reg;
	unsigned long flags = 0;

	if (gate->lock)
		spin_lock_irqsave(gate->lock, flags);

	reg = readl(gate->reg);
	reg &= ~BIT(gate->bit_idx);
	writel(reg, gate->reg);

	if (gate->lock)
		spin_unlock_irqrestore(gate->lock, flags);
}

static int clk_gate_enable(struct clk_hw *hw)
{
	struct clk_gate *gate = to_clk_gate(hw);

	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
		clk_gate_clear_bit(gate);
	else
		clk_gate_set_bit(gate);

	return 0;
}

static void clk_gate_disable(struct clk_hw *hw)
{
	struct clk_gate *gate = to_clk_gate(hw);

	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
		clk_gate_set_bit(gate);
	else
		clk_gate_clear_bit(gate);
}

static int clk_gate_is_enabled(struct clk_hw *hw)
{
	u32 reg;
	struct clk_gate *gate = to_clk_gate(hw);

	reg = readl(gate->reg);

	/* if a set bit disables this clk, flip it before masking */
	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
		reg ^= BIT(gate->bit_idx);

	reg &= BIT(gate->bit_idx);

	return reg ? 1 : 0;
}

const struct clk_ops clk_gate_ops = {
	.enable = clk_gate_enable,
	.disable = clk_gate_disable,
	.is_enabled = clk_gate_is_enabled,
};
EXPORT_SYMBOL_GPL(clk_gate_ops);

/**
 * clk_register_gate - register a gate clock with the clock framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_name: name of this clock's parent
 * @flags: framework-specific flags for this clock
 * @reg: register address to control gating of this clock
 * @bit_idx: which bit in the register controls gating of this clock
 * @clk_gate_flags: gate-specific flags for this clock
 * @lock: shared register lock for this clock
 */
struct clk *clk_register_gate(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 bit_idx,
		u8 clk_gate_flags, spinlock_t *lock)
{
	struct clk_gate *gate;
	struct clk *clk;

	/* allocate the gate */
	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
	if (!gate) {
		pr_err("%s: could not allocate gated clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	/* struct clk_gate assignments */
	gate->reg = reg;
	gate->bit_idx = bit_idx;
	gate->flags = clk_gate_flags;
	gate->lock = lock;

	/* register the clock */
	clk = clk_register(dev, name,
			&clk_gate_ops, &gate->hw,
			(parent_name ? &parent_name : NULL),
			(parent_name ? 1 : 0),
			flags);

	if (IS_ERR(clk))
		kfree(gate);

	return clk;
}
Commit	Line	Data
9d9f78ed MT	1	/*
	2	* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
	3	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* Gated clock implementation
	10	*/
	11
	12	#include <linux/clk-provider.h>
	13	#include <linux/module.h>
	14	#include <linux/slab.h>
	15	#include <linux/io.h>
	16	#include <linux/err.h>
	17	#include <linux/string.h>
	18
	19	/**
	20	* DOC: basic gatable clock which can gate and ungate it's ouput
	21	*
	22	* Traits of this clock:
	23	* prepare - clk_(un)prepare only ensures parent is (un)prepared
	24	* enable - clk_enable and clk_disable are functional & control gating
	25	* rate - inherits rate from parent. No clk_set_rate support
	26	* parent - fixed parent. No clk_set_parent support
	27	*/
	28
	29	#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
	30
	31	static void clk_gate_set_bit(struct clk_gate *gate)
	32	{
	33	u32 reg;
	34	unsigned long flags = 0;
	35
	36	if (gate->lock)
	37	spin_lock_irqsave(gate->lock, flags);
	38
	39	reg = readl(gate->reg);
	40	reg \|= BIT(gate->bit_idx);
	41	writel(reg, gate->reg);
	42
	43	if (gate->lock)
	44	spin_unlock_irqrestore(gate->lock, flags);
	45	}
	46
	47	static void clk_gate_clear_bit(struct clk_gate *gate)
	48	{
	49	u32 reg;
	50	unsigned long flags = 0;
	51
	52	if (gate->lock)
	53	spin_lock_irqsave(gate->lock, flags);
	54
	55	reg = readl(gate->reg);
	56	reg &= ~BIT(gate->bit_idx);
	57	writel(reg, gate->reg);
	58
	59	if (gate->lock)
	60	spin_unlock_irqrestore(gate->lock, flags);
	61	}
	62
	63	static int clk_gate_enable(struct clk_hw *hw)
	64	{
65	struct clk_gate *gate = to_clk_gate(hw);
66
67	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
68	clk_gate_clear_bit(gate);
69	else
70	clk_gate_set_bit(gate);
71
72	return 0;
73	}
9d9f78ed MT	74
	75	static void clk_gate_disable(struct clk_hw *hw)
	76	{
	77	struct clk_gate *gate = to_clk_gate(hw);
	78
	79	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
	80	clk_gate_set_bit(gate);
	81	else
	82	clk_gate_clear_bit(gate);
	83	}
9d9f78ed MT	84
	85	static int clk_gate_is_enabled(struct clk_hw *hw)
	86	{
	87	u32 reg;
	88	struct clk_gate *gate = to_clk_gate(hw);
	89
	90	reg = readl(gate->reg);
	91
	92	/* if a set bit disables this clk, flip it before masking */
	93	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
	94	reg ^= BIT(gate->bit_idx);
	95
	96	reg &= BIT(gate->bit_idx);
	97
	98	return reg ? 1 : 0;
	99	}
9d9f78ed	100
822c250e	101	const struct clk_ops clk_gate_ops = {
9d9f78ed MT	102	.enable = clk_gate_enable,
	103	.disable = clk_gate_disable,
	104	.is_enabled = clk_gate_is_enabled,
	105	};
	106	EXPORT_SYMBOL_GPL(clk_gate_ops);
	107
27d54591 MT	108	/**
	109	* clk_register_gate - register a gate clock with the clock framework
	110	* @dev: device that is registering this clock
	111	* @name: name of this clock
	112	* @parent_name: name of this clock's parent
	113	* @flags: framework-specific flags for this clock
	114	* @reg: register address to control gating of this clock
	115	* @bit_idx: which bit in the register controls gating of this clock
	116	* @clk_gate_flags: gate-specific flags for this clock
	117	* @lock: shared register lock for this clock
	118	*/
9d9f78ed MT	119	struct clk clk_register_gate(struct device dev, const char *name,
	120	const char *parent_name, unsigned long flags,
	121	void __iomem *reg, u8 bit_idx,
	122	u8 clk_gate_flags, spinlock_t *lock)
	123	{
	124	struct clk_gate *gate;
	125	struct clk *clk;
	126
27d54591	127	/* allocate the gate */
9d9f78ed	128	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
9d9f78ed MT	129	if (!gate) {
9d9f78ed MT	130	pr_err("%s: could not allocate gated clk\n", __func__);
27d54591	131	return ERR_PTR(-ENOMEM);
9d9f78ed MT	132	}
	133
	134	/* struct clk_gate assignments */
	135	gate->reg = reg;
	136	gate->bit_idx = bit_idx;
	137	gate->flags = clk_gate_flags;
	138	gate->lock = lock;
	139
27d54591	140	/* register the clock */
9d9f78ed MT	141	clk = clk_register(dev, name,
9d9f78ed MT	142	&clk_gate_ops, &gate->hw,
27d54591	143	(parent_name ? &parent_name : NULL),
9d9f78ed MT	144	(parent_name ? 1 : 0),
9d9f78ed MT	145	flags);
9d9f78ed	146
27d54591 MT	147	if (IS_ERR(clk))
	148	kfree(gate);
	149
	150	return clk;
9d9f78ed	151	}