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e1bd55e5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9d9f78ed MT |
2 | /* |
3 | * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> | |
4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
5 | * | |
9d9f78ed MT |
6 | * Fixed rate clock implementation |
7 | */ | |
8 | ||
9 | #include <linux/clk-provider.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/err.h> | |
015ba402 | 14 | #include <linux/of.h> |
435779fe | 15 | #include <linux/platform_device.h> |
9d9f78ed MT |
16 | |
17 | /* | |
18 | * DOC: basic fixed-rate clock that cannot gate | |
19 | * | |
20 | * Traits of this clock: | |
21 | * prepare - clk_(un)prepare only ensures parents are prepared | |
22 | * enable - clk_enable only ensures parents are enabled | |
23 | * rate - rate is always a fixed value. No clk_set_rate support | |
24 | * parent - fixed parent. No clk_set_parent support | |
25 | */ | |
26 | ||
38d1e380 SB |
27 | #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) |
28 | ||
9d9f78ed MT |
29 | static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw, |
30 | unsigned long parent_rate) | |
31 | { | |
32 | return to_clk_fixed_rate(hw)->fixed_rate; | |
33 | } | |
9d9f78ed | 34 | |
0903ea60 BB |
35 | static unsigned long clk_fixed_rate_recalc_accuracy(struct clk_hw *hw, |
36 | unsigned long parent_accuracy) | |
37 | { | |
58f0c4ba SB |
38 | struct clk_fixed_rate *fixed = to_clk_fixed_rate(hw); |
39 | ||
40 | if (fixed->flags & CLK_FIXED_RATE_PARENT_ACCURACY) | |
41 | return parent_accuracy; | |
42 | ||
43 | return fixed->fixed_accuracy; | |
0903ea60 BB |
44 | } |
45 | ||
822c250e | 46 | const struct clk_ops clk_fixed_rate_ops = { |
9d9f78ed | 47 | .recalc_rate = clk_fixed_rate_recalc_rate, |
0903ea60 | 48 | .recalc_accuracy = clk_fixed_rate_recalc_accuracy, |
9d9f78ed MT |
49 | }; |
50 | EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); | |
51 | ||
1d7d2065 DB |
52 | static void devm_clk_hw_register_fixed_rate_release(struct device *dev, void *res) |
53 | { | |
54 | struct clk_fixed_rate *fix = res; | |
55 | ||
56 | /* | |
57 | * We can not use clk_hw_unregister_fixed_rate, since it will kfree() | |
58 | * the hw, resulting in double free. Just unregister the hw and let | |
59 | * devres code kfree() it. | |
60 | */ | |
61 | clk_hw_unregister(&fix->hw); | |
62 | } | |
63 | ||
2d34f09e SB |
64 | struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, |
65 | struct device_node *np, const char *name, | |
66 | const char *parent_name, const struct clk_hw *parent_hw, | |
67 | const struct clk_parent_data *parent_data, unsigned long flags, | |
68 | unsigned long fixed_rate, unsigned long fixed_accuracy, | |
1d7d2065 | 69 | unsigned long clk_fixed_flags, bool devm) |
9d9f78ed MT |
70 | { |
71 | struct clk_fixed_rate *fixed; | |
26ef56be | 72 | struct clk_hw *hw; |
cc819cf8 | 73 | struct clk_init_data init = {}; |
2d34f09e | 74 | int ret = -EINVAL; |
9d9f78ed | 75 | |
27d54591 | 76 | /* allocate fixed-rate clock */ |
1d7d2065 DB |
77 | if (devm) |
78 | fixed = devres_alloc(devm_clk_hw_register_fixed_rate_release, | |
79 | sizeof(*fixed), GFP_KERNEL); | |
80 | else | |
81 | fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); | |
d122db7e | 82 | if (!fixed) |
9d9f78ed | 83 | return ERR_PTR(-ENOMEM); |
9d9f78ed | 84 | |
0197b3ea SK |
85 | init.name = name; |
86 | init.ops = &clk_fixed_rate_ops; | |
90b6c5c7 | 87 | init.flags = flags; |
2d34f09e SB |
88 | init.parent_names = parent_name ? &parent_name : NULL; |
89 | init.parent_hws = parent_hw ? &parent_hw : NULL; | |
90 | init.parent_data = parent_data; | |
91 | if (parent_name || parent_hw || parent_data) | |
92 | init.num_parents = 1; | |
93 | else | |
94 | init.num_parents = 0; | |
0197b3ea | 95 | |
9d9f78ed | 96 | /* struct clk_fixed_rate assignments */ |
2d34f09e | 97 | fixed->flags = clk_fixed_flags; |
9d9f78ed | 98 | fixed->fixed_rate = fixed_rate; |
0903ea60 | 99 | fixed->fixed_accuracy = fixed_accuracy; |
0197b3ea | 100 | fixed->hw.init = &init; |
9d9f78ed | 101 | |
27d54591 | 102 | /* register the clock */ |
26ef56be | 103 | hw = &fixed->hw; |
2d34f09e SB |
104 | if (dev || !np) |
105 | ret = clk_hw_register(dev, hw); | |
b69b0adc | 106 | else |
2d34f09e | 107 | ret = of_clk_hw_register(np, hw); |
26ef56be | 108 | if (ret) { |
1d7d2065 DB |
109 | if (devm) |
110 | devres_free(fixed); | |
111 | else | |
112 | kfree(fixed); | |
26ef56be | 113 | hw = ERR_PTR(ret); |
1d7d2065 DB |
114 | } else if (devm) |
115 | devres_add(dev, fixed); | |
27d54591 | 116 | |
26ef56be SB |
117 | return hw; |
118 | } | |
2d34f09e | 119 | EXPORT_SYMBOL_GPL(__clk_hw_register_fixed_rate); |
26ef56be | 120 | |
0903ea60 BB |
121 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
122 | const char *parent_name, unsigned long flags, | |
123 | unsigned long fixed_rate) | |
124 | { | |
576859df SB |
125 | struct clk_hw *hw; |
126 | ||
127 | hw = clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, | |
128 | flags, fixed_rate, 0); | |
129 | if (IS_ERR(hw)) | |
130 | return ERR_CAST(hw); | |
131 | return hw->clk; | |
0903ea60 | 132 | } |
389ae05f | 133 | EXPORT_SYMBOL_GPL(clk_register_fixed_rate); |
015ba402 | 134 | |
0b225e41 MY |
135 | void clk_unregister_fixed_rate(struct clk *clk) |
136 | { | |
137 | struct clk_hw *hw; | |
138 | ||
139 | hw = __clk_get_hw(clk); | |
140 | if (!hw) | |
141 | return; | |
142 | ||
143 | clk_unregister(clk); | |
144 | kfree(to_clk_fixed_rate(hw)); | |
145 | } | |
146 | EXPORT_SYMBOL_GPL(clk_unregister_fixed_rate); | |
147 | ||
52445637 MY |
148 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw) |
149 | { | |
150 | struct clk_fixed_rate *fixed; | |
151 | ||
152 | fixed = to_clk_fixed_rate(hw); | |
153 | ||
154 | clk_hw_unregister(hw); | |
155 | kfree(fixed); | |
156 | } | |
157 | EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_rate); | |
158 | ||
015ba402 | 159 | #ifdef CONFIG_OF |
34e01833 | 160 | static struct clk_hw *_of_fixed_clk_setup(struct device_node *node) |
015ba402 | 161 | { |
34e01833 | 162 | struct clk_hw *hw; |
015ba402 GL |
163 | const char *clk_name = node->name; |
164 | u32 rate; | |
0903ea60 | 165 | u32 accuracy = 0; |
435779fe | 166 | int ret; |
015ba402 GL |
167 | |
168 | if (of_property_read_u32(node, "clock-frequency", &rate)) | |
435779fe | 169 | return ERR_PTR(-EIO); |
015ba402 | 170 | |
0903ea60 BB |
171 | of_property_read_u32(node, "clock-accuracy", &accuracy); |
172 | ||
015ba402 GL |
173 | of_property_read_string(node, "clock-output-names", &clk_name); |
174 | ||
34e01833 | 175 | hw = clk_hw_register_fixed_rate_with_accuracy(NULL, clk_name, NULL, |
d3781a74 | 176 | 0, rate, accuracy); |
34e01833 SB |
177 | if (IS_ERR(hw)) |
178 | return hw; | |
435779fe | 179 | |
34e01833 | 180 | ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); |
435779fe | 181 | if (ret) { |
34e01833 | 182 | clk_hw_unregister_fixed_rate(hw); |
435779fe RRD |
183 | return ERR_PTR(ret); |
184 | } | |
185 | ||
34e01833 | 186 | return hw; |
435779fe RRD |
187 | } |
188 | ||
189 | /** | |
190 | * of_fixed_clk_setup() - Setup function for simple fixed rate clock | |
52ba4fa4 | 191 | * @node: device node for the clock |
435779fe | 192 | */ |
d336e9a7 | 193 | void __init of_fixed_clk_setup(struct device_node *node) |
435779fe RRD |
194 | { |
195 | _of_fixed_clk_setup(node); | |
015ba402 | 196 | } |
f2f6c255 | 197 | CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup); |
435779fe | 198 | |
57e20d68 | 199 | static void of_fixed_clk_remove(struct platform_device *pdev) |
435779fe | 200 | { |
34e01833 | 201 | struct clk_hw *hw = platform_get_drvdata(pdev); |
435779fe | 202 | |
52091c25 | 203 | of_clk_del_provider(pdev->dev.of_node); |
34e01833 | 204 | clk_hw_unregister_fixed_rate(hw); |
435779fe RRD |
205 | } |
206 | ||
207 | static int of_fixed_clk_probe(struct platform_device *pdev) | |
208 | { | |
34e01833 | 209 | struct clk_hw *hw; |
435779fe RRD |
210 | |
211 | /* | |
212 | * This function is not executed when of_fixed_clk_setup | |
213 | * succeeded. | |
214 | */ | |
34e01833 SB |
215 | hw = _of_fixed_clk_setup(pdev->dev.of_node); |
216 | if (IS_ERR(hw)) | |
217 | return PTR_ERR(hw); | |
435779fe | 218 | |
34e01833 | 219 | platform_set_drvdata(pdev, hw); |
435779fe RRD |
220 | |
221 | return 0; | |
222 | } | |
223 | ||
224 | static const struct of_device_id of_fixed_clk_ids[] = { | |
225 | { .compatible = "fixed-clock" }, | |
226 | { } | |
227 | }; | |
435779fe RRD |
228 | |
229 | static struct platform_driver of_fixed_clk_driver = { | |
230 | .driver = { | |
231 | .name = "of_fixed_clk", | |
232 | .of_match_table = of_fixed_clk_ids, | |
233 | }, | |
234 | .probe = of_fixed_clk_probe, | |
57e20d68 | 235 | .remove_new = of_fixed_clk_remove, |
435779fe RRD |
236 | }; |
237 | builtin_platform_driver(of_fixed_clk_driver); | |
015ba402 | 238 | #endif |