Merge tag 'iio-fixes-for-3.19a' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / clk / clk-fixed-rate.c
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1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Fixed rate clock implementation
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/io.h>
16#include <linux/err.h>
015ba402 17#include <linux/of.h>
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18
19/*
20 * DOC: basic fixed-rate clock that cannot gate
21 *
22 * Traits of this clock:
23 * prepare - clk_(un)prepare only ensures parents are prepared
24 * enable - clk_enable only ensures parents are enabled
25 * rate - rate is always a fixed value. No clk_set_rate support
26 * parent - fixed parent. No clk_set_parent support
27 */
28
29#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
30
31static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
32 unsigned long parent_rate)
33{
34 return to_clk_fixed_rate(hw)->fixed_rate;
35}
9d9f78ed 36
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37static unsigned long clk_fixed_rate_recalc_accuracy(struct clk_hw *hw,
38 unsigned long parent_accuracy)
39{
40 return to_clk_fixed_rate(hw)->fixed_accuracy;
41}
42
822c250e 43const struct clk_ops clk_fixed_rate_ops = {
9d9f78ed 44 .recalc_rate = clk_fixed_rate_recalc_rate,
0903ea60 45 .recalc_accuracy = clk_fixed_rate_recalc_accuracy,
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46};
47EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
48
27d54591 49/**
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50 * clk_register_fixed_rate_with_accuracy - register fixed-rate clock with the
51 * clock framework
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52 * @dev: device that is registering this clock
53 * @name: name of this clock
54 * @parent_name: name of clock's parent
55 * @flags: framework-specific flags
56 * @fixed_rate: non-adjustable clock rate
0903ea60 57 * @fixed_accuracy: non-adjustable clock rate
27d54591 58 */
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59struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
60 const char *name, const char *parent_name, unsigned long flags,
61 unsigned long fixed_rate, unsigned long fixed_accuracy)
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62{
63 struct clk_fixed_rate *fixed;
27d54591 64 struct clk *clk;
0197b3ea 65 struct clk_init_data init;
9d9f78ed 66
27d54591 67 /* allocate fixed-rate clock */
9d9f78ed 68 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
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69 if (!fixed) {
70 pr_err("%s: could not allocate fixed clk\n", __func__);
71 return ERR_PTR(-ENOMEM);
72 }
73
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74 init.name = name;
75 init.ops = &clk_fixed_rate_ops;
f7d8caad 76 init.flags = flags | CLK_IS_BASIC;
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77 init.parent_names = (parent_name ? &parent_name: NULL);
78 init.num_parents = (parent_name ? 1 : 0);
79
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80 /* struct clk_fixed_rate assignments */
81 fixed->fixed_rate = fixed_rate;
0903ea60 82 fixed->fixed_accuracy = fixed_accuracy;
0197b3ea 83 fixed->hw.init = &init;
9d9f78ed 84
27d54591 85 /* register the clock */
0197b3ea 86 clk = clk_register(dev, &fixed->hw);
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87 if (IS_ERR(clk))
88 kfree(fixed);
89
90 return clk;
9d9f78ed 91}
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92EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy);
93
94/**
95 * clk_register_fixed_rate - register fixed-rate clock with the clock framework
96 * @dev: device that is registering this clock
97 * @name: name of this clock
98 * @parent_name: name of clock's parent
99 * @flags: framework-specific flags
100 * @fixed_rate: non-adjustable clock rate
101 */
102struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
103 const char *parent_name, unsigned long flags,
104 unsigned long fixed_rate)
105{
106 return clk_register_fixed_rate_with_accuracy(dev, name, parent_name,
107 flags, fixed_rate, 0);
108}
389ae05f 109EXPORT_SYMBOL_GPL(clk_register_fixed_rate);
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110
111#ifdef CONFIG_OF
112/**
113 * of_fixed_clk_setup() - Setup function for simple fixed rate clock
114 */
e4eda8e0 115void of_fixed_clk_setup(struct device_node *node)
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116{
117 struct clk *clk;
118 const char *clk_name = node->name;
119 u32 rate;
0903ea60 120 u32 accuracy = 0;
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121
122 if (of_property_read_u32(node, "clock-frequency", &rate))
123 return;
124
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125 of_property_read_u32(node, "clock-accuracy", &accuracy);
126
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127 of_property_read_string(node, "clock-output-names", &clk_name);
128
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129 clk = clk_register_fixed_rate_with_accuracy(NULL, clk_name, NULL,
130 CLK_IS_ROOT, rate,
131 accuracy);
cdfed3b2 132 if (!IS_ERR(clk))
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133 of_clk_add_provider(node, of_clk_src_simple_get, clk);
134}
135EXPORT_SYMBOL_GPL(of_fixed_clk_setup);
f2f6c255 136CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup);
015ba402 137#endif