clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
[linux-block.git] / drivers / clk / clk-fixed-factor.c
CommitLineData
e1bd55e5 1// SPDX-License-Identifier: GPL-2.0
f0948f59
SH
2/*
3 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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4 */
5#include <linux/module.h>
6#include <linux/clk-provider.h>
7#include <linux/slab.h>
8#include <linux/err.h>
79b16641 9#include <linux/of.h>
971451b3 10#include <linux/platform_device.h>
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11
12/*
13 * DOC: basic fixed multiplier and divider clock that cannot gate
14 *
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
20 */
21
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SH
22static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
23 unsigned long parent_rate)
24{
25 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
bab53301 26 unsigned long long int rate;
f0948f59 27
bab53301
HZ
28 rate = (unsigned long long int)parent_rate * fix->mult;
29 do_div(rate, fix->div);
30 return (unsigned long)rate;
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SH
31}
32
33static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
34 unsigned long *prate)
35{
36 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
37
98d8a60e 38 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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39 unsigned long best_parent;
40
41 best_parent = (rate / fix->mult) * fix->div;
2f508a95 42 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
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SH
43 }
44
45 return (*prate / fix->div) * fix->mult;
46}
47
48static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,
49 unsigned long parent_rate)
50{
3037e9ea
DT
51 /*
52 * We must report success but we can do so unconditionally because
53 * clk_factor_round_rate returns values that ensure this call is a
54 * nop.
55 */
56
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57 return 0;
58}
59
3037e9ea 60const struct clk_ops clk_fixed_factor_ops = {
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61 .round_rate = clk_factor_round_rate,
62 .set_rate = clk_factor_set_rate,
63 .recalc_rate = clk_factor_recalc_rate,
64};
65EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
66
0b9266d2
DP
67static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *res)
68{
50ce6826
DB
69 struct clk_fixed_factor *fix = res;
70
71 /*
72 * We can not use clk_hw_unregister_fixed_factor, since it will kfree()
73 * the hw, resulting in double free. Just unregister the hw and let
74 * devres code kfree() it.
75 */
76 clk_hw_unregister(&fix->hw);
0b9266d2
DP
77}
78
ecbf3f17
SB
79static struct clk_hw *
80__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
81 const char *name, const char *parent_name, int index,
0b9266d2
DP
82 unsigned long flags, unsigned int mult, unsigned int div,
83 bool devm)
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SH
84{
85 struct clk_fixed_factor *fix;
e4818d61 86 struct clk_init_data init = { };
ecbf3f17 87 struct clk_parent_data pdata = { .index = index };
0759ac8a
SB
88 struct clk_hw *hw;
89 int ret;
f0948f59 90
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DP
91 /* You can't use devm without a dev */
92 if (devm && !dev)
93 return ERR_PTR(-EINVAL);
94
95 if (devm)
96 fix = devres_alloc(devm_clk_hw_register_fixed_factor_release,
97 sizeof(*fix), GFP_KERNEL);
98 else
99 fix = kmalloc(sizeof(*fix), GFP_KERNEL);
d122db7e 100 if (!fix)
f0948f59 101 return ERR_PTR(-ENOMEM);
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SH
102
103 /* struct clk_fixed_factor assignments */
104 fix->mult = mult;
105 fix->div = div;
106 fix->hw.init = &init;
107
108 init.name = name;
109 init.ops = &clk_fixed_factor_ops;
90b6c5c7 110 init.flags = flags;
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111 if (parent_name)
112 init.parent_names = &parent_name;
113 else
114 init.parent_data = &pdata;
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115 init.num_parents = 1;
116
0759ac8a 117 hw = &fix->hw;
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118 if (dev)
119 ret = clk_hw_register(dev, hw);
120 else
121 ret = of_clk_hw_register(np, hw);
0759ac8a 122 if (ret) {
0b9266d2
DP
123 if (devm)
124 devres_free(fix);
125 else
126 kfree(fix);
0759ac8a 127 hw = ERR_PTR(ret);
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DP
128 } else if (devm)
129 devres_add(dev, fix);
f0948f59 130
0759ac8a
SB
131 return hw;
132}
ecbf3f17 133
0c125f87
MV
134/**
135 * devm_clk_hw_register_fixed_factor_index - Register a fixed factor clock with
136 * parent from DT index
137 * @dev: device that is registering this clock
138 * @name: name of this clock
139 * @index: index of phandle in @dev 'clocks' property
140 * @flags: fixed factor flags
141 * @mult: multiplier
142 * @div: divider
143 *
144 * Return: Pointer to fixed factor clk_hw structure that was registered or
145 * an error pointer.
146 */
147struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
148 const char *name, unsigned int index, unsigned long flags,
149 unsigned int mult, unsigned int div)
150{
151 return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, index,
152 flags, mult, div, true);
153}
154EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index);
155
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156struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
157 const char *name, const char *parent_name, unsigned long flags,
158 unsigned int mult, unsigned int div)
159{
160 return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
0b9266d2 161 flags, mult, div, false);
ecbf3f17 162}
0759ac8a
SB
163EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
164
165struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
166 const char *parent_name, unsigned long flags,
167 unsigned int mult, unsigned int div)
168{
169 struct clk_hw *hw;
170
171 hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,
172 div);
173 if (IS_ERR(hw))
174 return ERR_CAST(hw);
175 return hw->clk;
f0948f59 176}
5cfe10bb 177EXPORT_SYMBOL_GPL(clk_register_fixed_factor);
cbf9591f
MY
178
179void clk_unregister_fixed_factor(struct clk *clk)
180{
181 struct clk_hw *hw;
182
183 hw = __clk_get_hw(clk);
184 if (!hw)
185 return;
186
187 clk_unregister(clk);
188 kfree(to_clk_fixed_factor(hw));
189}
190EXPORT_SYMBOL_GPL(clk_unregister_fixed_factor);
0759ac8a
SB
191
192void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
193{
194 struct clk_fixed_factor *fix;
195
196 fix = to_clk_fixed_factor(hw);
197
198 clk_hw_unregister(hw);
199 kfree(fix);
200}
201EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
5cfe10bb 202
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DP
203struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
204 const char *name, const char *parent_name, unsigned long flags,
205 unsigned int mult, unsigned int div)
206{
207 return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
208 flags, mult, div, true);
209}
210EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
211
79b16641 212#ifdef CONFIG_OF
ecbf3f17 213static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
79b16641 214{
ecbf3f17 215 struct clk_hw *hw;
79b16641 216 const char *clk_name = node->name;
79b16641 217 u32 div, mult;
971451b3 218 int ret;
79b16641
GC
219
220 if (of_property_read_u32(node, "clock-div", &div)) {
e665f029
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221 pr_err("%s Fixed factor clock <%pOFn> must have a clock-div property\n",
222 __func__, node);
971451b3 223 return ERR_PTR(-EIO);
79b16641
GC
224 }
225
226 if (of_property_read_u32(node, "clock-mult", &mult)) {
e665f029
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227 pr_err("%s Fixed factor clock <%pOFn> must have a clock-mult property\n",
228 __func__, node);
971451b3 229 return ERR_PTR(-EIO);
79b16641
GC
230 }
231
232 of_property_read_string(node, "clock-output-names", &clk_name);
79b16641 233
ecbf3f17 234 hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
c33ed612 235 0, mult, div, false);
ecbf3f17 236 if (IS_ERR(hw)) {
f6dab423 237 /*
f6dab423
RV
238 * Clear OF_POPULATED flag so that clock registration can be
239 * attempted again from probe function.
240 */
241 of_node_clear_flag(node, OF_POPULATED);
ecbf3f17 242 return ERR_CAST(hw);
f6dab423 243 }
971451b3 244
ecbf3f17 245 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
971451b3 246 if (ret) {
ecbf3f17 247 clk_hw_unregister_fixed_factor(hw);
971451b3
RRD
248 return ERR_PTR(ret);
249 }
250
ecbf3f17 251 return hw;
971451b3
RRD
252}
253
254/**
255 * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
52ba4fa4 256 * @node: device node for the clock
971451b3
RRD
257 */
258void __init of_fixed_factor_clk_setup(struct device_node *node)
259{
260 _of_fixed_factor_clk_setup(node);
79b16641 261}
79b16641
GC
262CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock",
263 of_fixed_factor_clk_setup);
971451b3
RRD
264
265static int of_fixed_factor_clk_remove(struct platform_device *pdev)
266{
ecbf3f17 267 struct clk_hw *clk = platform_get_drvdata(pdev);
971451b3 268
f98e8a57 269 of_clk_del_provider(pdev->dev.of_node);
ecbf3f17 270 clk_hw_unregister_fixed_factor(clk);
971451b3
RRD
271
272 return 0;
273}
274
275static int of_fixed_factor_clk_probe(struct platform_device *pdev)
276{
ecbf3f17 277 struct clk_hw *clk;
971451b3
RRD
278
279 /*
280 * This function is not executed when of_fixed_factor_clk_setup
281 * succeeded.
282 */
283 clk = _of_fixed_factor_clk_setup(pdev->dev.of_node);
284 if (IS_ERR(clk))
285 return PTR_ERR(clk);
286
287 platform_set_drvdata(pdev, clk);
288
289 return 0;
290}
291
292static const struct of_device_id of_fixed_factor_clk_ids[] = {
293 { .compatible = "fixed-factor-clock" },
294 { }
295};
296MODULE_DEVICE_TABLE(of, of_fixed_factor_clk_ids);
297
298static struct platform_driver of_fixed_factor_clk_driver = {
299 .driver = {
300 .name = "of_fixed_factor_clk",
301 .of_match_table = of_fixed_factor_clk_ids,
302 },
303 .probe = of_fixed_factor_clk_probe,
304 .remove = of_fixed_factor_clk_remove,
305};
306builtin_platform_driver(of_fixed_factor_clk_driver);
79b16641 307#endif