[linux-2.6-block.git] / drivers / clk / clk-divider.c

/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Adjustable divider clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/log2.h>

/*
 * DOC: basic adjustable divider clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is adjustable.  clk->rate = DIV_ROUND_UP(parent->rate / divisor)
 * parent - fixed parent.  No clk_set_parent support
 */

#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)

#define div_mask(d)	((1 << ((d)->width)) - 1)

static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
{
	unsigned int maxdiv = 0;
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div > maxdiv)
			maxdiv = clkt->div;
	return maxdiv;
}

static unsigned int _get_maxdiv(struct clk_divider *divider)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return div_mask(divider);
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return 1 << div_mask(divider);
	if (divider->table)
		return _get_table_maxdiv(divider->table);
	return div_mask(divider) + 1;
}

static unsigned int _get_table_div(const struct clk_div_table *table,
							unsigned int val)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->val == val)
			return clkt->div;
	return 0;
}

static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return val;
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return 1 << val;
	if (divider->table)
		return _get_table_div(divider->table, val);
	return val + 1;
}

static unsigned int _get_table_val(const struct clk_div_table *table,
							unsigned int div)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div == div)
			return clkt->val;
	return 0;
}

static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return div;
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return __ffs(div);
	if (divider->table)
		return  _get_table_val(divider->table, div);
	return div - 1;
}

static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	unsigned int div, val;

	val = clk_readl(divider->reg) >> divider->shift;
	val &= div_mask(divider);

	div = _get_div(divider, val);
	if (!div) {
		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
			"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
			__clk_get_name(hw->clk));
		return parent_rate;
	}

	return DIV_ROUND_UP(parent_rate, div);
}

/*
 * The reverse of DIV_ROUND_UP: The maximum number which
 * divided by m is r
 */
#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)

static bool _is_valid_table_div(const struct clk_div_table *table,
							 unsigned int div)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div == div)
			return true;
	return false;
}

static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
{
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return is_power_of_2(div);
	if (divider->table)
		return _is_valid_table_div(divider->table, div);
	return true;
}

static int _round_up_table(const struct clk_div_table *table, int div)
{
	const struct clk_div_table *clkt;
	int up = _get_table_maxdiv(table);

	for (clkt = table; clkt->div; clkt++) {
		if (clkt->div == div)
			return clkt->div;
		else if (clkt->div < div)
			continue;

		if ((clkt->div - div) < (up - div))
			up = clkt->div;
	}

	return up;
}

static int _div_round_up(struct clk_divider *divider,
		unsigned long parent_rate, unsigned long rate)
{
	int div = DIV_ROUND_UP(parent_rate, rate);

	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		div = __roundup_pow_of_two(div);
	if (divider->table)
		div = _round_up_table(divider->table, div);

	return div;
}

static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
		unsigned long *best_parent_rate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	int i, bestdiv = 0;
	unsigned long parent_rate, best = 0, now, maxdiv;
	unsigned long parent_rate_saved = *best_parent_rate;

	if (!rate)
		rate = 1;

	maxdiv = _get_maxdiv(divider);

	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
		parent_rate = *best_parent_rate;
		bestdiv = _div_round_up(divider, parent_rate, rate);
		bestdiv = bestdiv == 0 ? 1 : bestdiv;
		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
		return bestdiv;
	}

	/*
	 * The maximum divider we can use without overflowing
	 * unsigned long in rate * i below
	 */
	maxdiv = min(ULONG_MAX / rate, maxdiv);

	for (i = 1; i <= maxdiv; i++) {
		if (!_is_valid_div(divider, i))
			continue;
		if (rate * i == parent_rate_saved) {
			/*
			 * It's the most ideal case if the requested rate can be
			 * divided from parent clock without needing to change
			 * parent rate, so return the divider immediately.
			 */
			*best_parent_rate = parent_rate_saved;
			return i;
		}
		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
				MULT_ROUND_UP(rate, i));
		now = DIV_ROUND_UP(parent_rate, i);
		if (now <= rate && now > best) {
			bestdiv = i;
			best = now;
			*best_parent_rate = parent_rate;
		}
	}

	if (!bestdiv) {
		bestdiv = _get_maxdiv(divider);
		*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
	}

	return bestdiv;
}

static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{
	int div;
	div = clk_divider_bestdiv(hw, rate, prate);

	return DIV_ROUND_UP(*prate, div);
}

static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	unsigned int div, value;
	unsigned long flags = 0;
	u32 val;

	div = DIV_ROUND_UP(parent_rate, rate);

	if (!_is_valid_div(divider, div))
		return -EINVAL;

	value = _get_val(divider, div);

	if (value > div_mask(divider))
		value = div_mask(divider);

	if (divider->lock)
		spin_lock_irqsave(divider->lock, flags);

	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
		val = div_mask(divider) << (divider->shift + 16);
	} else {
		val = clk_readl(divider->reg);
		val &= ~(div_mask(divider) << divider->shift);
	}
	val |= value << divider->shift;
	clk_writel(val, divider->reg);

	if (divider->lock)
		spin_unlock_irqrestore(divider->lock, flags);

	return 0;
}

const struct clk_ops clk_divider_ops = {
	.recalc_rate = clk_divider_recalc_rate,
	.round_rate = clk_divider_round_rate,
	.set_rate = clk_divider_set_rate,
};
EXPORT_SYMBOL_GPL(clk_divider_ops);

static struct clk *_register_divider(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock)
{
	struct clk_divider *div;
	struct clk *clk;
	struct clk_init_data init;

	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
		if (width + shift > 16) {
			pr_warn("divider value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the divider */
	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
	if (!div) {
		pr_err("%s: could not allocate divider clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	init.ops = &clk_divider_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = (parent_name ? &parent_name: NULL);
	init.num_parents = (parent_name ? 1 : 0);

	/* struct clk_divider assignments */
	div->reg = reg;
	div->shift = shift;
	div->width = width;
	div->flags = clk_divider_flags;
	div->lock = lock;
	div->hw.init = &init;
	div->table = table;

	/* register the clock */
	clk = clk_register(dev, &div->hw);

	if (IS_ERR(clk))
		kfree(div);

	return clk;
}

/**
 * clk_register_divider - register a divider clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
struct clk *clk_register_divider(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, spinlock_t *lock)
{
	return _register_divider(dev, name, parent_name, flags, reg, shift,
			width, clk_divider_flags, NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_divider);

/**
 * clk_register_divider_table - register a table based divider clock with
 * the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
struct clk *clk_register_divider_table(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock)
{
	return _register_divider(dev, name, parent_name, flags, reg, shift,
			width, clk_divider_flags, table, lock);
}
EXPORT_SYMBOL_GPL(clk_register_divider_table);
Commit	Line	Data
9d9f78ed MT	1	/*
	2	* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	3	* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
	4	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Adjustable divider clock implementation
	11	*/
	12
	13	#include <linux/clk-provider.h>
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18	#include <linux/string.h>
1a3cd184	19	#include <linux/log2.h>
9d9f78ed MT	20
	21	/*
	22	* DOC: basic adjustable divider clock that cannot gate
	23	*
	24	* Traits of this clock:
	25	* prepare - clk_prepare only ensures that parents are prepared
	26	* enable - clk_enable only ensures that parents are enabled
b11d282d	27	* rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor)
9d9f78ed MT	28	* parent - fixed parent. No clk_set_parent support
	29	*/
	30
	31	#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
	32
1a3cd184	33	#define div_mask(d) ((1 << ((d)->width)) - 1)
6d9252bd	34
357c3f0a RN	35	static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
	36	{
	37	unsigned int maxdiv = 0;
	38	const struct clk_div_table *clkt;
	39
	40	for (clkt = table; clkt->div; clkt++)
	41	if (clkt->div > maxdiv)
	42	maxdiv = clkt->div;
	43	return maxdiv;
	44	}
	45
6d9252bd RN	46	static unsigned int _get_maxdiv(struct clk_divider *divider)
	47	{
	48	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	49	return div_mask(divider);
	50	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	51	return 1 << div_mask(divider);
357c3f0a RN	52	if (divider->table)
357c3f0a RN	53	return _get_table_maxdiv(divider->table);
6d9252bd RN	54	return div_mask(divider) + 1;
	55	}
	56
357c3f0a RN	57	static unsigned int _get_table_div(const struct clk_div_table *table,
	58	unsigned int val)
	59	{
	60	const struct clk_div_table *clkt;
	61
	62	for (clkt = table; clkt->div; clkt++)
	63	if (clkt->val == val)
	64	return clkt->div;
	65	return 0;
	66	}
	67
6d9252bd RN	68	static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
	69	{
	70	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	71	return val;
	72	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	73	return 1 << val;
357c3f0a RN	74	if (divider->table)
357c3f0a RN	75	return _get_table_div(divider->table, val);
6d9252bd RN	76	return val + 1;
	77	}
	78
357c3f0a RN	79	static unsigned int _get_table_val(const struct clk_div_table *table,
	80	unsigned int div)
	81	{
	82	const struct clk_div_table *clkt;
	83
	84	for (clkt = table; clkt->div; clkt++)
	85	if (clkt->div == div)
	86	return clkt->val;
	87	return 0;
	88	}
	89
778037e1	90	static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
6d9252bd RN	91	{
	92	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	93	return div;
	94	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	95	return __ffs(div);
357c3f0a RN	96	if (divider->table)
357c3f0a RN	97	return _get_table_val(divider->table, div);
6d9252bd RN	98	return div - 1;
6d9252bd RN	99	}
9d9f78ed MT	100
	101	static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
	102	unsigned long parent_rate)
	103	{
	104	struct clk_divider *divider = to_clk_divider(hw);
6d9252bd	105	unsigned int div, val;
9d9f78ed	106
aa514ce3	107	val = clk_readl(divider->reg) >> divider->shift;
6d9252bd	108	val &= div_mask(divider);
9d9f78ed	109
6d9252bd RN	110	div = _get_div(divider, val);
6d9252bd RN	111	if (!div) {
056b2053 SB	112	WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
	113	"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
	114	__clk_get_name(hw->clk));
6d9252bd RN	115	return parent_rate;
6d9252bd RN	116	}
9d9f78ed	117
b11d282d	118	return DIV_ROUND_UP(parent_rate, div);
9d9f78ed	119	}
9d9f78ed MT	120
	121	/*
	122	* The reverse of DIV_ROUND_UP: The maximum number which
	123	* divided by m is r
	124	*/
	125	#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
	126
357c3f0a RN	127	static bool _is_valid_table_div(const struct clk_div_table *table,
	128	unsigned int div)
	129	{
	130	const struct clk_div_table *clkt;
	131
	132	for (clkt = table; clkt->div; clkt++)
	133	if (clkt->div == div)
	134	return true;
	135	return false;
	136	}
	137
	138	static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
	139	{
	140	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
1a3cd184	141	return is_power_of_2(div);
357c3f0a RN	142	if (divider->table)
	143	return _is_valid_table_div(divider->table, div);
	144	return true;
	145	}
	146
dd23c2cd MC	147	static int _round_up_table(const struct clk_div_table *table, int div)
	148	{
	149	const struct clk_div_table *clkt;
	150	int up = _get_table_maxdiv(table);
	151
	152	for (clkt = table; clkt->div; clkt++) {
	153	if (clkt->div == div)
	154	return clkt->div;
	155	else if (clkt->div < div)
	156	continue;
	157
	158	if ((clkt->div - div) < (up - div))
	159	up = clkt->div;
	160	}
	161
	162	return up;
	163	}
	164
	165	static int _div_round_up(struct clk_divider *divider,
	166	unsigned long parent_rate, unsigned long rate)
	167	{
	168	int div = DIV_ROUND_UP(parent_rate, rate);
	169
	170	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	171	div = __roundup_pow_of_two(div);
	172	if (divider->table)
	173	div = _round_up_table(divider->table, div);
	174
	175	return div;
	176	}
	177
9d9f78ed MT	178	static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
	179	unsigned long *best_parent_rate)
	180	{
	181	struct clk_divider *divider = to_clk_divider(hw);
	182	int i, bestdiv = 0;
	183	unsigned long parent_rate, best = 0, now, maxdiv;
081c9025	184	unsigned long parent_rate_saved = *best_parent_rate;
9d9f78ed MT	185
	186	if (!rate)
	187	rate = 1;
	188
6d9252bd	189	maxdiv = _get_maxdiv(divider);
9d9f78ed	190
81536e07 SG	191	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
81536e07 SG	192	parent_rate = *best_parent_rate;
dd23c2cd	193	bestdiv = _div_round_up(divider, parent_rate, rate);
9d9f78ed MT	194	bestdiv = bestdiv == 0 ? 1 : bestdiv;
	195	bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
	196	return bestdiv;
	197	}
	198
	199	/*
	200	* The maximum divider we can use without overflowing
	201	* unsigned long in rate * i below
	202	*/
	203	maxdiv = min(ULONG_MAX / rate, maxdiv);
	204
	205	for (i = 1; i <= maxdiv; i++) {
357c3f0a	206	if (!_is_valid_div(divider, i))
6d9252bd	207	continue;
081c9025 SG	208	if (rate * i == parent_rate_saved) {
	209	/*
	210	* It's the most ideal case if the requested rate can be
	211	* divided from parent clock without needing to change
	212	* parent rate, so return the divider immediately.
	213	*/
	214	*best_parent_rate = parent_rate_saved;
	215	return i;
	216	}
9d9f78ed MT	217	parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
9d9f78ed MT	218	MULT_ROUND_UP(rate, i));
b11d282d	219	now = DIV_ROUND_UP(parent_rate, i);
9d9f78ed MT	220	if (now <= rate && now > best) {
	221	bestdiv = i;
	222	best = now;
	223	*best_parent_rate = parent_rate;
	224	}
	225	}
	226
	227	if (!bestdiv) {
6d9252bd	228	bestdiv = _get_maxdiv(divider);
9d9f78ed MT	229	*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
	230	}
	231
	232	return bestdiv;
	233	}
	234
	235	static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
	236	unsigned long *prate)
	237	{
	238	int div;
	239	div = clk_divider_bestdiv(hw, rate, prate);
	240
b11d282d	241	return DIV_ROUND_UP(*prate, div);
9d9f78ed	242	}
9d9f78ed	243
1c0035d7 SG	244	static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
1c0035d7 SG	245	unsigned long parent_rate)
9d9f78ed MT	246	{
9d9f78ed MT	247	struct clk_divider *divider = to_clk_divider(hw);
6d9252bd	248	unsigned int div, value;
9d9f78ed MT	249	unsigned long flags = 0;
	250	u32 val;
	251
b11d282d	252	div = DIV_ROUND_UP(parent_rate, rate);
dd23c2cd MC	253
	254	if (!_is_valid_div(divider, div))
	255	return -EINVAL;
	256
6d9252bd	257	value = _get_val(divider, div);
9d9f78ed	258
6d9252bd RN	259	if (value > div_mask(divider))
6d9252bd RN	260	value = div_mask(divider);
9d9f78ed MT	261
	262	if (divider->lock)
	263	spin_lock_irqsave(divider->lock, flags);
	264
d57dfe75 HZ	265	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
	266	val = div_mask(divider) << (divider->shift + 16);
	267	} else {
aa514ce3	268	val = clk_readl(divider->reg);
d57dfe75 HZ	269	val &= ~(div_mask(divider) << divider->shift);
d57dfe75 HZ	270	}
6d9252bd	271	val \|= value << divider->shift;
aa514ce3	272	clk_writel(val, divider->reg);
9d9f78ed MT	273
	274	if (divider->lock)
	275	spin_unlock_irqrestore(divider->lock, flags);
	276
	277	return 0;
	278	}
9d9f78ed	279
822c250e	280	const struct clk_ops clk_divider_ops = {
9d9f78ed MT	281	.recalc_rate = clk_divider_recalc_rate,
	282	.round_rate = clk_divider_round_rate,
	283	.set_rate = clk_divider_set_rate,
	284	};
	285	EXPORT_SYMBOL_GPL(clk_divider_ops);
	286
357c3f0a	287	static struct clk _register_divider(struct device dev, const char *name,
9d9f78ed MT	288	const char *parent_name, unsigned long flags,
9d9f78ed MT	289	void __iomem *reg, u8 shift, u8 width,
357c3f0a RN	290	u8 clk_divider_flags, const struct clk_div_table *table,
357c3f0a RN	291	spinlock_t *lock)
9d9f78ed MT	292	{
	293	struct clk_divider *div;
	294	struct clk *clk;
0197b3ea	295	struct clk_init_data init;
9d9f78ed	296
d57dfe75 HZ	297	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
	298	if (width + shift > 16) {
	299	pr_warn("divider value exceeds LOWORD field\n");
	300	return ERR_PTR(-EINVAL);
	301	}
	302	}
	303
27d54591	304	/* allocate the divider */
9d9f78ed	305	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
9d9f78ed MT	306	if (!div) {
9d9f78ed MT	307	pr_err("%s: could not allocate divider clk\n", __func__);
27d54591	308	return ERR_PTR(-ENOMEM);
9d9f78ed MT	309	}
9d9f78ed MT	310
0197b3ea SK	311	init.name = name;
0197b3ea SK	312	init.ops = &clk_divider_ops;
f7d8caad	313	init.flags = flags \| CLK_IS_BASIC;
0197b3ea SK	314	init.parent_names = (parent_name ? &parent_name: NULL);
	315	init.num_parents = (parent_name ? 1 : 0);
	316
9d9f78ed MT	317	/* struct clk_divider assignments */
	318	div->reg = reg;
	319	div->shift = shift;
	320	div->width = width;
	321	div->flags = clk_divider_flags;
	322	div->lock = lock;
0197b3ea	323	div->hw.init = &init;
357c3f0a	324	div->table = table;
9d9f78ed	325
27d54591	326	/* register the clock */
0197b3ea	327	clk = clk_register(dev, &div->hw);
9d9f78ed	328
27d54591 MT	329	if (IS_ERR(clk))
27d54591 MT	330	kfree(div);
9d9f78ed	331
27d54591	332	return clk;
9d9f78ed	333	}
357c3f0a RN	334
	335	/**
	336	* clk_register_divider - register a divider clock with the clock framework
	337	* @dev: device registering this clock
	338	* @name: name of this clock
	339	* @parent_name: name of clock's parent
	340	* @flags: framework-specific flags
	341	* @reg: register address to adjust divider
	342	* @shift: number of bits to shift the bitfield
	343	* @width: width of the bitfield
	344	* @clk_divider_flags: divider-specific flags for this clock
	345	* @lock: shared register lock for this clock
	346	*/
	347	struct clk clk_register_divider(struct device dev, const char *name,
	348	const char *parent_name, unsigned long flags,
	349	void __iomem *reg, u8 shift, u8 width,
	350	u8 clk_divider_flags, spinlock_t *lock)
	351	{
	352	return _register_divider(dev, name, parent_name, flags, reg, shift,
	353	width, clk_divider_flags, NULL, lock);
	354	}
4c5eeea9	355	EXPORT_SYMBOL_GPL(clk_register_divider);
357c3f0a RN	356
	357	/**
	358	* clk_register_divider_table - register a table based divider clock with
	359	* the clock framework
	360	* @dev: device registering this clock
	361	* @name: name of this clock
	362	* @parent_name: name of clock's parent
	363	* @flags: framework-specific flags
	364	* @reg: register address to adjust divider
	365	* @shift: number of bits to shift the bitfield
	366	* @width: width of the bitfield
	367	* @clk_divider_flags: divider-specific flags for this clock
	368	* @table: array of divider/value pairs ending with a div set to 0
	369	* @lock: shared register lock for this clock
	370	*/
	371	struct clk clk_register_divider_table(struct device dev, const char *name,
	372	const char *parent_name, unsigned long flags,
	373	void __iomem *reg, u8 shift, u8 width,
	374	u8 clk_divider_flags, const struct clk_div_table *table,
	375	spinlock_t *lock)
	376	{
	377	return _register_divider(dev, name, parent_name, flags, reg, shift,
	378	width, clk_divider_flags, table, lock);
	379	}
4c5eeea9	380	EXPORT_SYMBOL_GPL(clk_register_divider_table);