[linux-block.git] / drivers / clk / clk-cs2000-cp.c

// SPDX-License-Identifier: GPL-2.0
/*
 * CS2000  --  CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 */
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/regmap.h>

#define CH_MAX 4
#define RATIO_REG_SIZE 4

#define DEVICE_ID	0x1
#define DEVICE_CTRL	0x2
#define DEVICE_CFG1	0x3
#define DEVICE_CFG2	0x4
#define GLOBAL_CFG	0x5
#define Ratio_Add(x, nth)	(6 + (x * 4) + (nth))
#define Ratio_Val(x, nth)	((x >> (24 - (8 * nth))) & 0xFF)
#define Val_Ratio(x, nth)	((x & 0xFF) << (24 - (8 * nth)))
#define FUNC_CFG1	0x16
#define FUNC_CFG2	0x17

/* DEVICE_ID */
#define REVISION_MASK	(0x7)
#define REVISION_B2_B3	(0x4)
#define REVISION_C1	(0x6)

/* DEVICE_CTRL */
#define PLL_UNLOCK	(1 << 7)
#define AUXOUTDIS	(1 << 1)
#define CLKOUTDIS	(1 << 0)

/* DEVICE_CFG1 */
#define RSEL(x)		(((x) & 0x3) << 3)
#define RSEL_MASK	RSEL(0x3)
#define AUXOUTSRC(x)	(((x) & 0x3) << 1)
#define AUXOUTSRC_MASK	AUXOUTSRC(0x3)
#define ENDEV1		(0x1)

/* DEVICE_CFG2 */
#define AUTORMOD	(1 << 3)
#define LOCKCLK(x)	(((x) & 0x3) << 1)
#define LOCKCLK_MASK	LOCKCLK(0x3)
#define FRACNSRC_MASK	(1 << 0)
#define FRACNSRC_STATIC		(0 << 0)
#define FRACNSRC_DYNAMIC	(1 << 0)

/* GLOBAL_CFG */
#define FREEZE		(1 << 7)
#define ENDEV2		(0x1)

/* FUNC_CFG1 */
#define CLKSKIPEN	(1 << 7)
#define REFCLKDIV(x)	(((x) & 0x3) << 3)
#define REFCLKDIV_MASK	REFCLKDIV(0x3)

/* FUNC_CFG2 */
#define LFRATIO_MASK	(1 << 3)
#define LFRATIO_20_12	(0 << 3)
#define LFRATIO_12_20	(1 << 3)

#define CH_SIZE_ERR(ch)		((ch < 0) || (ch >= CH_MAX))
#define hw_to_priv(_hw)		container_of(_hw, struct cs2000_priv, hw)
#define priv_to_client(priv)	(priv->client)
#define priv_to_dev(priv)	(&(priv_to_client(priv)->dev))

#define CLK_IN	0
#define REF_CLK	1
#define CLK_MAX 2

static bool cs2000_readable_reg(struct device *dev, unsigned int reg)
{
	return reg > 0;
}

static bool cs2000_writeable_reg(struct device *dev, unsigned int reg)
{
	return reg != DEVICE_ID;
}

static bool cs2000_volatile_reg(struct device *dev, unsigned int reg)
{
	return reg == DEVICE_CTRL;
}

static const struct regmap_config cs2000_regmap_config = {
	.reg_bits	= 8,
	.val_bits	= 8,
	.max_register	= FUNC_CFG2,
	.readable_reg	= cs2000_readable_reg,
	.writeable_reg	= cs2000_writeable_reg,
	.volatile_reg	= cs2000_volatile_reg,
};

struct cs2000_priv {
	struct clk_hw hw;
	struct i2c_client *client;
	struct clk *clk_in;
	struct clk *ref_clk;
	struct regmap *regmap;

	bool dynamic_mode;
	bool lf_ratio;
	bool clk_skip;

	/* suspend/resume */
	unsigned long saved_rate;
	unsigned long saved_parent_rate;
};

static const struct of_device_id cs2000_of_match[] = {
	{ .compatible = "cirrus,cs2000-cp", },
	{},
};
MODULE_DEVICE_TABLE(of, cs2000_of_match);

static const struct i2c_device_id cs2000_id[] = {
	{ "cs2000-cp", },
	{}
};
MODULE_DEVICE_TABLE(i2c, cs2000_id);

static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable)
{
	int ret;

	ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, ENDEV1,
				 enable ? ENDEV1 : 0);
	if (ret < 0)
		return ret;

	ret = regmap_update_bits(priv->regmap, GLOBAL_CFG,  ENDEV2,
				 enable ? ENDEV2 : 0);
	if (ret < 0)
		return ret;

	ret = regmap_update_bits(priv->regmap, FUNC_CFG1, CLKSKIPEN,
				 (enable && priv->clk_skip) ? CLKSKIPEN : 0);
	if (ret < 0)
		return ret;

	return 0;
}

static int cs2000_ref_clk_bound_rate(struct cs2000_priv *priv,
				     u32 rate_in)
{
	u32 val;

	if (rate_in >= 32000000 && rate_in < 56000000)
		val = 0x0;
	else if (rate_in >= 16000000 && rate_in < 28000000)
		val = 0x1;
	else if (rate_in >= 8000000 && rate_in < 14000000)
		val = 0x2;
	else
		return -EINVAL;

	return regmap_update_bits(priv->regmap, FUNC_CFG1,
				  REFCLKDIV_MASK,
				  REFCLKDIV(val));
}

static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
{
	struct device *dev = priv_to_dev(priv);
	unsigned int i, val;
	int ret;

	for (i = 0; i < 256; i++) {
		ret = regmap_read(priv->regmap, DEVICE_CTRL, &val);
		if (ret < 0)
			return ret;
		if (!(val & PLL_UNLOCK))
			return 0;
		udelay(1);
	}

	dev_err(dev, "pll lock failed\n");

	return -ETIMEDOUT;
}

static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable)
{
	/* enable both AUX_OUT, CLK_OUT */
	return regmap_update_bits(priv->regmap, DEVICE_CTRL,
				  (AUXOUTDIS | CLKOUTDIS),
				  enable ? 0 :
				  (AUXOUTDIS | CLKOUTDIS));
}

static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out, bool lf_ratio)
{
	u64 ratio;
	u32 multiplier = lf_ratio ? 12 : 20;

	/*
	 * ratio = rate_out / rate_in * 2^multiplier
	 *
	 * To avoid over flow, rate_out is u64.
	 * The result should be u32.
	 */
	ratio = (u64)rate_out << multiplier;
	do_div(ratio, rate_in);

	return ratio;
}

static unsigned long cs2000_ratio_to_rate(u32 ratio, u32 rate_in, bool lf_ratio)
{
	u64 rate_out;
	u32 multiplier = lf_ratio ? 12 : 20;

	/*
	 * ratio = rate_out / rate_in * 2^multiplier
	 *
	 * To avoid over flow, rate_out is u64.
	 * The result should be u32 or unsigned long.
	 */

	rate_out = (u64)ratio * rate_in;
	return rate_out >> multiplier;
}

static int cs2000_ratio_set(struct cs2000_priv *priv,
			    int ch, u32 rate_in, u32 rate_out)
{
	u32 val;
	unsigned int i;
	int ret;

	if (CH_SIZE_ERR(ch))
		return -EINVAL;

	val = cs2000_rate_to_ratio(rate_in, rate_out, priv->lf_ratio);
	for (i = 0; i < RATIO_REG_SIZE; i++) {
		ret = regmap_write(priv->regmap,
				   Ratio_Add(ch, i),
				   Ratio_Val(val, i));
		if (ret < 0)
			return ret;
	}

	return 0;
}

static u32 cs2000_ratio_get(struct cs2000_priv *priv, int ch)
{
	unsigned int tmp, i;
	u32 val;
	int ret;

	val = 0;
	for (i = 0; i < RATIO_REG_SIZE; i++) {
		ret = regmap_read(priv->regmap, Ratio_Add(ch, i), &tmp);
		if (ret < 0)
			return 0;

		val |= Val_Ratio(tmp, i);
	}

	return val;
}

static int cs2000_ratio_select(struct cs2000_priv *priv, int ch)
{
	int ret;
	u8 fracnsrc;

	if (CH_SIZE_ERR(ch))
		return -EINVAL;

	ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, RSEL_MASK, RSEL(ch));
	if (ret < 0)
		return ret;

	fracnsrc = priv->dynamic_mode ? FRACNSRC_DYNAMIC : FRACNSRC_STATIC;

	ret = regmap_update_bits(priv->regmap, DEVICE_CFG2,
				 AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK,
				 LOCKCLK(ch) | fracnsrc);
	if (ret < 0)
		return ret;

	return 0;
}

static unsigned long cs2000_recalc_rate(struct clk_hw *hw,
					unsigned long parent_rate)
{
	struct cs2000_priv *priv = hw_to_priv(hw);
	int ch = 0; /* it uses ch0 only at this point */
	u32 ratio;

	ratio = cs2000_ratio_get(priv, ch);

	return cs2000_ratio_to_rate(ratio, parent_rate, priv->lf_ratio);
}

static long cs2000_round_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long *parent_rate)
{
	struct cs2000_priv *priv = hw_to_priv(hw);
	u32 ratio;

	ratio = cs2000_rate_to_ratio(*parent_rate, rate, priv->lf_ratio);

	return cs2000_ratio_to_rate(ratio, *parent_rate, priv->lf_ratio);
}

static int cs2000_select_ratio_mode(struct cs2000_priv *priv,
				    unsigned long rate,
				    unsigned long parent_rate)
{
	/*
	 * From the datasheet:
	 *
	 * | It is recommended that the 12.20 High-Resolution format be
	 * | utilized whenever the desired ratio is less than 4096 since
	 * | the output frequency accuracy of the PLL is directly proportional
	 * | to the accuracy of the timing reference clock and the resolution
	 * | of the R_UD.
	 *
	 * This mode is only available in dynamic mode.
	 */
	priv->lf_ratio = priv->dynamic_mode && ((rate / parent_rate) > 4096);

	return regmap_update_bits(priv->regmap, FUNC_CFG2, LFRATIO_MASK,
				  priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20);
}

static int __cs2000_set_rate(struct cs2000_priv *priv, int ch,
			     unsigned long rate, unsigned long parent_rate)

{
	int ret;

	ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, FREEZE);
	if (ret < 0)
		return ret;

	ret = cs2000_select_ratio_mode(priv, rate, parent_rate);
	if (ret < 0)
		return ret;

	ret = cs2000_ratio_set(priv, ch, parent_rate, rate);
	if (ret < 0)
		return ret;

	ret = cs2000_ratio_select(priv, ch);
	if (ret < 0)
		return ret;

	ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, 0);
	if (ret < 0)
		return ret;

	priv->saved_rate	= rate;
	priv->saved_parent_rate	= parent_rate;

	return 0;
}

static int cs2000_set_rate(struct clk_hw *hw,
			   unsigned long rate, unsigned long parent_rate)
{
	struct cs2000_priv *priv = hw_to_priv(hw);
	int ch = 0; /* it uses ch0 only at this point */

	return __cs2000_set_rate(priv, ch, rate, parent_rate);
}

static int cs2000_set_saved_rate(struct cs2000_priv *priv)
{
	int ch = 0; /* it uses ch0 only at this point */

	return __cs2000_set_rate(priv, ch,
				 priv->saved_rate,
				 priv->saved_parent_rate);
}

static int cs2000_enable(struct clk_hw *hw)
{
	struct cs2000_priv *priv = hw_to_priv(hw);
	int ret;

	ret = cs2000_enable_dev_config(priv, true);
	if (ret < 0)
		return ret;

	ret = cs2000_clk_out_enable(priv, true);
	if (ret < 0)
		return ret;

	ret = cs2000_wait_pll_lock(priv);
	if (ret < 0)
		return ret;

	return ret;
}

static void cs2000_disable(struct clk_hw *hw)
{
	struct cs2000_priv *priv = hw_to_priv(hw);

	cs2000_enable_dev_config(priv, false);

	cs2000_clk_out_enable(priv, false);
}

static u8 cs2000_get_parent(struct clk_hw *hw)
{
	struct cs2000_priv *priv = hw_to_priv(hw);

	/*
	 * In dynamic mode, output rates are derived from CLK_IN.
	 * In static mode, CLK_IN is ignored, so we return REF_CLK instead.
	 */
	return priv->dynamic_mode ? CLK_IN : REF_CLK;
}

static const struct clk_ops cs2000_ops = {
	.get_parent	= cs2000_get_parent,
	.recalc_rate	= cs2000_recalc_rate,
	.round_rate	= cs2000_round_rate,
	.set_rate	= cs2000_set_rate,
	.prepare	= cs2000_enable,
	.unprepare	= cs2000_disable,
};

static int cs2000_clk_get(struct cs2000_priv *priv)
{
	struct device *dev = priv_to_dev(priv);
	struct clk *clk_in, *ref_clk;

	clk_in = devm_clk_get(dev, "clk_in");
	/* not yet provided */
	if (IS_ERR(clk_in))
		return -EPROBE_DEFER;

	ref_clk = devm_clk_get(dev, "ref_clk");
	/* not yet provided */
	if (IS_ERR(ref_clk))
		return -EPROBE_DEFER;

	priv->clk_in	= clk_in;
	priv->ref_clk	= ref_clk;

	return 0;
}

static int cs2000_clk_register(struct cs2000_priv *priv)
{
	struct device *dev = priv_to_dev(priv);
	struct device_node *np = dev->of_node;
	struct clk_init_data init;
	const char *name = np->name;
	static const char *parent_names[CLK_MAX];
	u32 aux_out = 0;
	int ref_clk_rate;
	int ch = 0; /* it uses ch0 only at this point */
	int ret;

	of_property_read_string(np, "clock-output-names", &name);

	priv->dynamic_mode = of_property_read_bool(np, "cirrus,dynamic-mode");
	dev_info(dev, "operating in %s mode\n",
		 priv->dynamic_mode ? "dynamic" : "static");

	of_property_read_u32(np, "cirrus,aux-output-source", &aux_out);
	ret = regmap_update_bits(priv->regmap, DEVICE_CFG1,
				 AUXOUTSRC_MASK, AUXOUTSRC(aux_out));
	if (ret < 0)
		return ret;

	priv->clk_skip = of_property_read_bool(np, "cirrus,clock-skip");

	ref_clk_rate = clk_get_rate(priv->ref_clk);
	ret = cs2000_ref_clk_bound_rate(priv, ref_clk_rate);
	if (ret < 0)
		return ret;

	if (priv->dynamic_mode) {
		/* Default to low-frequency mode to allow for large ratios */
		priv->lf_ratio = true;
	} else {
		/*
		 * set default rate as 1/1.
		 * otherwise .set_rate which setup ratio
		 * is never called if user requests 1/1 rate
		 */
		ret = __cs2000_set_rate(priv, ch, ref_clk_rate, ref_clk_rate);
		if (ret < 0)
			return ret;
	}

	parent_names[CLK_IN]	= __clk_get_name(priv->clk_in);
	parent_names[REF_CLK]	= __clk_get_name(priv->ref_clk);

	init.name		= name;
	init.ops		= &cs2000_ops;
	init.flags		= CLK_SET_RATE_GATE;
	init.parent_names	= parent_names;
	init.num_parents	= ARRAY_SIZE(parent_names);

	priv->hw.init = &init;

	ret = clk_hw_register(dev, &priv->hw);
	if (ret)
		return ret;

	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
	if (ret < 0) {
		clk_hw_unregister(&priv->hw);
		return ret;
	}

	return 0;
}

static int cs2000_version_print(struct cs2000_priv *priv)
{
	struct device *dev = priv_to_dev(priv);
	const char *revision;
	unsigned int val;
	int ret;

	ret = regmap_read(priv->regmap, DEVICE_ID, &val);
	if (ret < 0)
		return ret;

	/* CS2000 should be 0x0 */
	if (val >> 3)
		return -EIO;

	switch (val & REVISION_MASK) {
	case REVISION_B2_B3:
		revision = "B2 / B3";
		break;
	case REVISION_C1:
		revision = "C1";
		break;
	default:
		return -EIO;
	}

	dev_info(dev, "revision - %s\n", revision);

	return 0;
}

static void cs2000_remove(struct i2c_client *client)
{
	struct cs2000_priv *priv = i2c_get_clientdata(client);
	struct device *dev = priv_to_dev(priv);
	struct device_node *np = dev->of_node;

	of_clk_del_provider(np);

	clk_hw_unregister(&priv->hw);
}

static int cs2000_probe(struct i2c_client *client)
{
	struct cs2000_priv *priv;
	struct device *dev = &client->dev;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->client = client;
	i2c_set_clientdata(client, priv);

	priv->regmap = devm_regmap_init_i2c(client, &cs2000_regmap_config);
	if (IS_ERR(priv->regmap))
		return PTR_ERR(priv->regmap);

	ret = cs2000_clk_get(priv);
	if (ret < 0)
		return ret;

	ret = cs2000_clk_register(priv);
	if (ret < 0)
		return ret;

	ret = cs2000_version_print(priv);
	if (ret < 0)
		goto probe_err;

	return 0;

probe_err:
	cs2000_remove(client);

	return ret;
}

static int __maybe_unused cs2000_resume(struct device *dev)
{
	struct cs2000_priv *priv = dev_get_drvdata(dev);

	return cs2000_set_saved_rate(priv);
}

static const struct dev_pm_ops cs2000_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, cs2000_resume)
};

static struct i2c_driver cs2000_driver = {
	.driver = {
		.name = "cs2000-cp",
		.pm	= &cs2000_pm_ops,
		.of_match_table = cs2000_of_match,
	},
	.probe_new	= cs2000_probe,
	.remove		= cs2000_remove,
	.id_table	= cs2000_id,
};

module_i2c_driver(cs2000_driver);

MODULE_DESCRIPTION("CS2000-CP driver");
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
67075b3c	1	// SPDX-License-Identifier: GPL-2.0
64dfbe24 KM	2	/*
	3	* CS2000 -- CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
	4	*
	5	* Copyright (C) 2015 Renesas Electronics Corporation
	6	* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
64dfbe24 KM	7	*/
	8	#include <linux/clk-provider.h>
	9	#include <linux/delay.h>
	10	#include <linux/clk.h>
	11	#include <linux/i2c.h>
	12	#include <linux/of_device.h>
	13	#include <linux/module.h>
5edffb98	14	#include <linux/regmap.h>
64dfbe24 KM	15
	16	#define CH_MAX 4
	17	#define RATIO_REG_SIZE 4
	18
	19	#define DEVICE_ID 0x1
	20	#define DEVICE_CTRL 0x2
	21	#define DEVICE_CFG1 0x3
	22	#define DEVICE_CFG2 0x4
	23	#define GLOBAL_CFG 0x5
	24	#define Ratio_Add(x, nth) (6 + (x * 4) + (nth))
	25	#define Ratio_Val(x, nth) ((x >> (24 - (8 * nth))) & 0xFF)
	26	#define Val_Ratio(x, nth) ((x & 0xFF) << (24 - (8 * nth)))
	27	#define FUNC_CFG1 0x16
	28	#define FUNC_CFG2 0x17
	29
	30	/* DEVICE_ID */
	31	#define REVISION_MASK (0x7)
	32	#define REVISION_B2_B3 (0x4)
	33	#define REVISION_C1 (0x6)
	34
	35	/* DEVICE_CTRL */
	36	#define PLL_UNLOCK (1 << 7)
1f9dfd7a KM	37	#define AUXOUTDIS (1 << 1)
1f9dfd7a KM	38	#define CLKOUTDIS (1 << 0)
64dfbe24 KM	39
	40	/* DEVICE_CFG1 */
	41	#define RSEL(x) (((x) & 0x3) << 3)
	42	#define RSEL_MASK RSEL(0x3)
a6e11bb2 DM	43	#define AUXOUTSRC(x) (((x) & 0x3) << 1)
a6e11bb2 DM	44	#define AUXOUTSRC_MASK AUXOUTSRC(0x3)
64dfbe24 KM	45	#define ENDEV1 (0x1)
64dfbe24 KM	46
1f9dfd7a KM	47	/* DEVICE_CFG2 */
	48	#define AUTORMOD (1 << 3)
	49	#define LOCKCLK(x) (((x) & 0x3) << 1)
	50	#define LOCKCLK_MASK LOCKCLK(0x3)
b295a015 KM	51	#define FRACNSRC_MASK (1 << 0)
b295a015 KM	52	#define FRACNSRC_STATIC (0 << 0)
da1eb4e8	53	#define FRACNSRC_DYNAMIC (1 << 0)
1f9dfd7a	54
64dfbe24	55	/* GLOBAL_CFG */
2f3d32fe	56	#define FREEZE (1 << 7)
64dfbe24 KM	57	#define ENDEV2 (0x1)
64dfbe24 KM	58
1f9dfd7a	59	/* FUNC_CFG1 */
d127967a	60	#define CLKSKIPEN (1 << 7)
1f9dfd7a KM	61	#define REFCLKDIV(x) (((x) & 0x3) << 3)
	62	#define REFCLKDIV_MASK REFCLKDIV(0x3)
	63
b3da896e KM	64	/* FUNC_CFG2 */
	65	#define LFRATIO_MASK (1 << 3)
	66	#define LFRATIO_20_12 (0 << 3)
	67	#define LFRATIO_12_20 (1 << 3)
	68
64dfbe24 KM	69	#define CH_SIZE_ERR(ch) ((ch < 0) \|\| (ch >= CH_MAX))
	70	#define hw_to_priv(_hw) container_of(_hw, struct cs2000_priv, hw)
	71	#define priv_to_client(priv) (priv->client)
	72	#define priv_to_dev(priv) (&(priv_to_client(priv)->dev))
	73
	74	#define CLK_IN 0
	75	#define REF_CLK 1
	76	#define CLK_MAX 2
	77
5edffb98 DM	78	static bool cs2000_readable_reg(struct device *dev, unsigned int reg)
	79	{
	80	return reg > 0;
	81	}
	82
	83	static bool cs2000_writeable_reg(struct device *dev, unsigned int reg)
	84	{
	85	return reg != DEVICE_ID;
	86	}
	87
	88	static bool cs2000_volatile_reg(struct device *dev, unsigned int reg)
	89	{
	90	return reg == DEVICE_CTRL;
	91	}
	92
	93	static const struct regmap_config cs2000_regmap_config = {
	94	.reg_bits = 8,
	95	.val_bits = 8,
	96	.max_register = FUNC_CFG2,
	97	.readable_reg = cs2000_readable_reg,
	98	.writeable_reg = cs2000_writeable_reg,
	99	.volatile_reg = cs2000_volatile_reg,
	100	};
	101
64dfbe24 KM	102	struct cs2000_priv {
	103	struct clk_hw hw;
	104	struct i2c_client *client;
	105	struct clk *clk_in;
	106	struct clk *ref_clk;
5edffb98	107	struct regmap *regmap;
c567fb37	108
da1eb4e8 DM	109	bool dynamic_mode;
da1eb4e8 DM	110	bool lf_ratio;
b8368825	111	bool clk_skip;
da1eb4e8	112
c567fb37 KN	113	/* suspend/resume */
	114	unsigned long saved_rate;
	115	unsigned long saved_parent_rate;
64dfbe24 KM	116	};
	117
	118	static const struct of_device_id cs2000_of_match[] = {
	119	{ .compatible = "cirrus,cs2000-cp", },
	120	{},
	121	};
	122	MODULE_DEVICE_TABLE(of, cs2000_of_match);
	123
	124	static const struct i2c_device_id cs2000_id[] = {
	125	{ "cs2000-cp", },
	126	{}
	127	};
	128	MODULE_DEVICE_TABLE(i2c, cs2000_id);
	129
64dfbe24 KM	130	static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable)
	131	{
	132	int ret;
	133
5edffb98 DM	134	ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, ENDEV1,
5edffb98 DM	135	enable ? ENDEV1 : 0);
64dfbe24 KM	136	if (ret < 0)
	137	return ret;
	138
5edffb98 DM	139	ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, ENDEV2,
5edffb98 DM	140	enable ? ENDEV2 : 0);
64dfbe24 KM	141	if (ret < 0)
	142	return ret;
	143
5edffb98 DM	144	ret = regmap_update_bits(priv->regmap, FUNC_CFG1, CLKSKIPEN,
5edffb98 DM	145	(enable && priv->clk_skip) ? CLKSKIPEN : 0);
d127967a KM	146	if (ret < 0)
	147	return ret;
	148
64dfbe24 KM	149	return 0;
	150	}
	151
da1eb4e8 DM	152	static int cs2000_ref_clk_bound_rate(struct cs2000_priv *priv,
da1eb4e8 DM	153	u32 rate_in)
64dfbe24 KM	154	{
	155	u32 val;
	156
	157	if (rate_in >= 32000000 && rate_in < 56000000)
	158	val = 0x0;
	159	else if (rate_in >= 16000000 && rate_in < 28000000)
	160	val = 0x1;
	161	else if (rate_in >= 8000000 && rate_in < 14000000)
	162	val = 0x2;
	163	else
	164	return -EINVAL;
	165
5edffb98 DM	166	return regmap_update_bits(priv->regmap, FUNC_CFG1,
	167	REFCLKDIV_MASK,
	168	REFCLKDIV(val));
64dfbe24 KM	169	}
	170
	171	static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
	172	{
	173	struct device *dev = priv_to_dev(priv);
5edffb98 DM	174	unsigned int i, val;
5edffb98 DM	175	int ret;
64dfbe24 KM	176
64dfbe24 KM	177	for (i = 0; i < 256; i++) {
5edffb98 DM	178	ret = regmap_read(priv->regmap, DEVICE_CTRL, &val);
	179	if (ret < 0)
	180	return ret;
64dfbe24 KM	181	if (!(val & PLL_UNLOCK))
	182	return 0;
	183	udelay(1);
	184	}
	185
	186	dev_err(dev, "pll lock failed\n");
	187
	188	return -ETIMEDOUT;
	189	}
	190
	191	static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable)
	192	{
	193	/* enable both AUX_OUT, CLK_OUT */
5edffb98 DM	194	return regmap_update_bits(priv->regmap, DEVICE_CTRL,
	195	(AUXOUTDIS \| CLKOUTDIS),
	196	enable ? 0 :
	197	(AUXOUTDIS \| CLKOUTDIS));
64dfbe24 KM	198	}
64dfbe24 KM	199
da1eb4e8	200	static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out, bool lf_ratio)
64dfbe24 KM	201	{
64dfbe24 KM	202	u64 ratio;
da1eb4e8	203	u32 multiplier = lf_ratio ? 12 : 20;
64dfbe24 KM	204
64dfbe24 KM	205	/*
da1eb4e8	206	* ratio = rate_out / rate_in * 2^multiplier
64dfbe24 KM	207	*
	208	* To avoid over flow, rate_out is u64.
	209	* The result should be u32.
	210	*/
da1eb4e8	211	ratio = (u64)rate_out << multiplier;
64dfbe24 KM	212	do_div(ratio, rate_in);
	213
	214	return ratio;
	215	}
	216
da1eb4e8	217	static unsigned long cs2000_ratio_to_rate(u32 ratio, u32 rate_in, bool lf_ratio)
64dfbe24 KM	218	{
64dfbe24 KM	219	u64 rate_out;
da1eb4e8	220	u32 multiplier = lf_ratio ? 12 : 20;
64dfbe24 KM	221
64dfbe24 KM	222	/*
da1eb4e8	223	* ratio = rate_out / rate_in * 2^multiplier
64dfbe24 KM	224	*
	225	* To avoid over flow, rate_out is u64.
	226	* The result should be u32 or unsigned long.
	227	*/
	228
	229	rate_out = (u64)ratio * rate_in;
da1eb4e8	230	return rate_out >> multiplier;
64dfbe24 KM	231	}
	232
	233	static int cs2000_ratio_set(struct cs2000_priv *priv,
	234	int ch, u32 rate_in, u32 rate_out)
	235	{
	236	u32 val;
	237	unsigned int i;
	238	int ret;
	239
	240	if (CH_SIZE_ERR(ch))
	241	return -EINVAL;
	242
da1eb4e8	243	val = cs2000_rate_to_ratio(rate_in, rate_out, priv->lf_ratio);
64dfbe24	244	for (i = 0; i < RATIO_REG_SIZE; i++) {
5edffb98	245	ret = regmap_write(priv->regmap,
64dfbe24 KM	246	Ratio_Add(ch, i),
	247	Ratio_Val(val, i));
	248	if (ret < 0)
	249	return ret;
	250	}
	251
	252	return 0;
	253	}
	254
	255	static u32 cs2000_ratio_get(struct cs2000_priv *priv, int ch)
	256	{
5edffb98	257	unsigned int tmp, i;
64dfbe24	258	u32 val;
5edffb98	259	int ret;
64dfbe24 KM	260
	261	val = 0;
	262	for (i = 0; i < RATIO_REG_SIZE; i++) {
5edffb98 DM	263	ret = regmap_read(priv->regmap, Ratio_Add(ch, i), &tmp);
5edffb98 DM	264	if (ret < 0)
64dfbe24 KM	265	return 0;
	266
	267	val \|= Val_Ratio(tmp, i);
	268	}
	269
	270	return val;
	271	}
	272
	273	static int cs2000_ratio_select(struct cs2000_priv *priv, int ch)
	274	{
	275	int ret;
da1eb4e8	276	u8 fracnsrc;
64dfbe24 KM	277
	278	if (CH_SIZE_ERR(ch))
	279	return -EINVAL;
	280
5edffb98	281	ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, RSEL_MASK, RSEL(ch));
64dfbe24 KM	282	if (ret < 0)
	283	return ret;
	284
da1eb4e8 DM	285	fracnsrc = priv->dynamic_mode ? FRACNSRC_DYNAMIC : FRACNSRC_STATIC;
da1eb4e8 DM	286
5edffb98 DM	287	ret = regmap_update_bits(priv->regmap, DEVICE_CFG2,
	288	AUTORMOD \| LOCKCLK_MASK \| FRACNSRC_MASK,
	289	LOCKCLK(ch) \| fracnsrc);
64dfbe24 KM	290	if (ret < 0)
	291	return ret;
	292
	293	return 0;
	294	}
	295
	296	static unsigned long cs2000_recalc_rate(struct clk_hw *hw,
	297	unsigned long parent_rate)
	298	{
	299	struct cs2000_priv *priv = hw_to_priv(hw);
	300	int ch = 0; /* it uses ch0 only at this point */
	301	u32 ratio;
	302
	303	ratio = cs2000_ratio_get(priv, ch);
	304
da1eb4e8	305	return cs2000_ratio_to_rate(ratio, parent_rate, priv->lf_ratio);
64dfbe24 KM	306	}
	307
	308	static long cs2000_round_rate(struct clk_hw *hw, unsigned long rate,
	309	unsigned long *parent_rate)
	310	{
da1eb4e8	311	struct cs2000_priv *priv = hw_to_priv(hw);
64dfbe24 KM	312	u32 ratio;
64dfbe24 KM	313
da1eb4e8 DM	314	ratio = cs2000_rate_to_ratio(*parent_rate, rate, priv->lf_ratio);
	315
	316	return cs2000_ratio_to_rate(ratio, *parent_rate, priv->lf_ratio);
	317	}
	318
	319	static int cs2000_select_ratio_mode(struct cs2000_priv *priv,
	320	unsigned long rate,
	321	unsigned long parent_rate)
	322	{
	323	/*
	324	* From the datasheet:
	325	*
	326	* \| It is recommended that the 12.20 High-Resolution format be
	327	* \| utilized whenever the desired ratio is less than 4096 since
	328	* \| the output frequency accuracy of the PLL is directly proportional
	329	* \| to the accuracy of the timing reference clock and the resolution
	330	* \| of the R_UD.
	331	*
	332	* This mode is only available in dynamic mode.
	333	*/
	334	priv->lf_ratio = priv->dynamic_mode && ((rate / parent_rate) > 4096);
64dfbe24	335
5edffb98 DM	336	return regmap_update_bits(priv->regmap, FUNC_CFG2, LFRATIO_MASK,
5edffb98 DM	337	priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20);
64dfbe24 KM	338	}
	339
	340	static int __cs2000_set_rate(struct cs2000_priv *priv, int ch,
	341	unsigned long rate, unsigned long parent_rate)
	342
	343	{
	344	int ret;
	345
5edffb98	346	ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, FREEZE);
2f3d32fe DM	347	if (ret < 0)
	348	return ret;
	349
da1eb4e8	350	ret = cs2000_select_ratio_mode(priv, rate, parent_rate);
64dfbe24 KM	351	if (ret < 0)
	352	return ret;
	353
	354	ret = cs2000_ratio_set(priv, ch, parent_rate, rate);
	355	if (ret < 0)
	356	return ret;
	357
	358	ret = cs2000_ratio_select(priv, ch);
	359	if (ret < 0)
	360	return ret;
	361
5edffb98	362	ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, 0);
2f3d32fe DM	363	if (ret < 0)
	364	return ret;
	365
c567fb37 KN	366	priv->saved_rate = rate;
	367	priv->saved_parent_rate = parent_rate;
	368
64dfbe24 KM	369	return 0;
	370	}
	371
	372	static int cs2000_set_rate(struct clk_hw *hw,
	373	unsigned long rate, unsigned long parent_rate)
	374	{
	375	struct cs2000_priv *priv = hw_to_priv(hw);
	376	int ch = 0; /* it uses ch0 only at this point */
	377
	378	return __cs2000_set_rate(priv, ch, rate, parent_rate);
	379	}
	380
e001525c GI	381	static int cs2000_set_saved_rate(struct cs2000_priv *priv)
	382	{
	383	int ch = 0; /* it uses ch0 only at this point */
	384
	385	return __cs2000_set_rate(priv, ch,
	386	priv->saved_rate,
	387	priv->saved_parent_rate);
	388	}
	389
64dfbe24 KM	390	static int cs2000_enable(struct clk_hw *hw)
	391	{
	392	struct cs2000_priv *priv = hw_to_priv(hw);
	393	int ret;
	394
	395	ret = cs2000_enable_dev_config(priv, true);
	396	if (ret < 0)
	397	return ret;
	398
	399	ret = cs2000_clk_out_enable(priv, true);
	400	if (ret < 0)
	401	return ret;
	402
	403	ret = cs2000_wait_pll_lock(priv);
	404	if (ret < 0)
	405	return ret;
	406
	407	return ret;
	408	}
	409
	410	static void cs2000_disable(struct clk_hw *hw)
	411	{
	412	struct cs2000_priv *priv = hw_to_priv(hw);
	413
	414	cs2000_enable_dev_config(priv, false);
	415
	416	cs2000_clk_out_enable(priv, false);
	417	}
	418
	419	static u8 cs2000_get_parent(struct clk_hw *hw)
	420	{
da1eb4e8 DM	421	struct cs2000_priv *priv = hw_to_priv(hw);
	422
	423	/*
	424	* In dynamic mode, output rates are derived from CLK_IN.
	425	* In static mode, CLK_IN is ignored, so we return REF_CLK instead.
	426	*/
	427	return priv->dynamic_mode ? CLK_IN : REF_CLK;
64dfbe24 KM	428	}
	429
	430	static const struct clk_ops cs2000_ops = {
	431	.get_parent = cs2000_get_parent,
	432	.recalc_rate = cs2000_recalc_rate,
	433	.round_rate = cs2000_round_rate,
	434	.set_rate = cs2000_set_rate,
	435	.prepare = cs2000_enable,
	436	.unprepare = cs2000_disable,
	437	};
	438
	439	static int cs2000_clk_get(struct cs2000_priv *priv)
	440	{
83dd720d	441	struct device *dev = priv_to_dev(priv);
64dfbe24 KM	442	struct clk clk_in, ref_clk;
	443
	444	clk_in = devm_clk_get(dev, "clk_in");
	445	/* not yet provided */
	446	if (IS_ERR(clk_in))
	447	return -EPROBE_DEFER;
	448
	449	ref_clk = devm_clk_get(dev, "ref_clk");
	450	/* not yet provided */
	451	if (IS_ERR(ref_clk))
	452	return -EPROBE_DEFER;
	453
	454	priv->clk_in = clk_in;
	455	priv->ref_clk = ref_clk;
	456
	457	return 0;
	458	}
	459
	460	static int cs2000_clk_register(struct cs2000_priv *priv)
	461	{
	462	struct device *dev = priv_to_dev(priv);
	463	struct device_node *np = dev->of_node;
	464	struct clk_init_data init;
	465	const char *name = np->name;
64dfbe24	466	static const char *parent_names[CLK_MAX];
a6e11bb2	467	u32 aux_out = 0;
da1eb4e8	468	int ref_clk_rate;
64dfbe24	469	int ch = 0; /* it uses ch0 only at this point */
64dfbe24 KM	470	int ret;
	471
	472	of_property_read_string(np, "clock-output-names", &name);
	473
da1eb4e8 DM	474	priv->dynamic_mode = of_property_read_bool(np, "cirrus,dynamic-mode");
	475	dev_info(dev, "operating in %s mode\n",
	476	priv->dynamic_mode ? "dynamic" : "static");
	477
a6e11bb2	478	of_property_read_u32(np, "cirrus,aux-output-source", &aux_out);
5edffb98 DM	479	ret = regmap_update_bits(priv->regmap, DEVICE_CFG1,
5edffb98 DM	480	AUXOUTSRC_MASK, AUXOUTSRC(aux_out));
a6e11bb2 DM	481	if (ret < 0)
	482	return ret;
	483
b8368825 DM	484	priv->clk_skip = of_property_read_bool(np, "cirrus,clock-skip");
b8368825 DM	485
da1eb4e8 DM	486	ref_clk_rate = clk_get_rate(priv->ref_clk);
da1eb4e8 DM	487	ret = cs2000_ref_clk_bound_rate(priv, ref_clk_rate);
64dfbe24 KM	488	if (ret < 0)
	489	return ret;
	490
da1eb4e8 DM	491	if (priv->dynamic_mode) {
	492	/* Default to low-frequency mode to allow for large ratios */
	493	priv->lf_ratio = true;
	494	} else {
	495	/*
	496	* set default rate as 1/1.
	497	* otherwise .set_rate which setup ratio
	498	* is never called if user requests 1/1 rate
	499	*/
	500	ret = __cs2000_set_rate(priv, ch, ref_clk_rate, ref_clk_rate);
	501	if (ret < 0)
	502	return ret;
	503	}
	504
64dfbe24 KM	505	parent_names[CLK_IN] = __clk_get_name(priv->clk_in);
	506	parent_names[REF_CLK] = __clk_get_name(priv->ref_clk);
	507
	508	init.name = name;
	509	init.ops = &cs2000_ops;
	510	init.flags = CLK_SET_RATE_GATE;
	511	init.parent_names = parent_names;
	512	init.num_parents = ARRAY_SIZE(parent_names);
	513
	514	priv->hw.init = &init;
	515
2ceb3c7a SB	516	ret = clk_hw_register(dev, &priv->hw);
	517	if (ret)
	518	return ret;
64dfbe24	519
2ceb3c7a	520	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
64dfbe24	521	if (ret < 0) {
2ceb3c7a	522	clk_hw_unregister(&priv->hw);
64dfbe24 KM	523	return ret;
	524	}
	525
64dfbe24 KM	526	return 0;
	527	}
	528
	529	static int cs2000_version_print(struct cs2000_priv *priv)
	530	{
83dd720d	531	struct device *dev = priv_to_dev(priv);
64dfbe24	532	const char *revision;
5edffb98 DM	533	unsigned int val;
5edffb98 DM	534	int ret;
64dfbe24	535
5edffb98 DM	536	ret = regmap_read(priv->regmap, DEVICE_ID, &val);
	537	if (ret < 0)
	538	return ret;
64dfbe24 KM	539
	540	/* CS2000 should be 0x0 */
	541	if (val >> 3)
	542	return -EIO;
	543
	544	switch (val & REVISION_MASK) {
	545	case REVISION_B2_B3:
	546	revision = "B2 / B3";
	547	break;
	548	case REVISION_C1:
	549	revision = "C1";
	550	break;
	551	default:
	552	return -EIO;
	553	}
	554
	555	dev_info(dev, "revision - %s\n", revision);
	556
	557	return 0;
	558	}
	559
ed5c2f5f	560	static void cs2000_remove(struct i2c_client *client)
64dfbe24 KM	561	{
64dfbe24 KM	562	struct cs2000_priv *priv = i2c_get_clientdata(client);
83dd720d	563	struct device *dev = priv_to_dev(priv);
64dfbe24 KM	564	struct device_node *np = dev->of_node;
	565
	566	of_clk_del_provider(np);
	567
2ceb3c7a	568	clk_hw_unregister(&priv->hw);
64dfbe24 KM	569	}
64dfbe24 KM	570
eb5f909a	571	static int cs2000_probe(struct i2c_client *client)
64dfbe24 KM	572	{
	573	struct cs2000_priv *priv;
	574	struct device *dev = &client->dev;
	575	int ret;
	576
	577	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	578	if (!priv)
	579	return -ENOMEM;
	580
	581	priv->client = client;
	582	i2c_set_clientdata(client, priv);
	583
5edffb98 DM	584	priv->regmap = devm_regmap_init_i2c(client, &cs2000_regmap_config);
	585	if (IS_ERR(priv->regmap))
	586	return PTR_ERR(priv->regmap);
	587
64dfbe24 KM	588	ret = cs2000_clk_get(priv);
	589	if (ret < 0)
	590	return ret;
	591
	592	ret = cs2000_clk_register(priv);
	593	if (ret < 0)
	594	return ret;
	595
	596	ret = cs2000_version_print(priv);
	597	if (ret < 0)
	598	goto probe_err;
	599
	600	return 0;
	601
	602	probe_err:
	603	cs2000_remove(client);
	604
	605	return ret;
	606	}
	607
a21b8594	608	static int __maybe_unused cs2000_resume(struct device *dev)
c567fb37 KN	609	{
c567fb37 KN	610	struct cs2000_priv *priv = dev_get_drvdata(dev);
c567fb37	611
e001525c	612	return cs2000_set_saved_rate(priv);
c567fb37 KN	613	}
	614
	615	static const struct dev_pm_ops cs2000_pm_ops = {
eade4ccd	616	SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, cs2000_resume)
c567fb37 KN	617	};
c567fb37 KN	618
64dfbe24 KM	619	static struct i2c_driver cs2000_driver = {
	620	.driver = {
	621	.name = "cs2000-cp",
c567fb37	622	.pm = &cs2000_pm_ops,
64dfbe24 KM	623	.of_match_table = cs2000_of_match,
64dfbe24 KM	624	},
eb5f909a	625	.probe_new = cs2000_probe,
64dfbe24 KM	626	.remove = cs2000_remove,
	627	.id_table = cs2000_id,
	628	};
	629
	630	module_i2c_driver(cs2000_driver);
	631
	632	MODULE_DESCRIPTION("CS2000-CP driver");
	633	MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
	634	MODULE_LICENSE("GPL v2");