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ebafb63d | 1 | // SPDX-License-Identifier: GPL-2.0 |
86be408b SN |
2 | /* |
3 | * Copyright (C) 2014 Samsung Electronics Co., Ltd. | |
4 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
86be408b SN |
5 | */ |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/clk-provider.h> | |
9 | #include <linux/clk/clk-conf.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/printk.h> | |
86be408b SN |
13 | |
14 | static int __set_clk_parents(struct device_node *node, bool clk_supplier) | |
15 | { | |
16 | struct of_phandle_args clkspec; | |
17 | int index, rc, num_parents; | |
18 | struct clk *clk, *pclk; | |
19 | ||
20 | num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", | |
21 | "#clock-cells"); | |
22 | if (num_parents == -EINVAL) | |
16673931 RH |
23 | pr_err("clk: invalid value of clock-parents property at %pOF\n", |
24 | node); | |
86be408b SN |
25 | |
26 | for (index = 0; index < num_parents; index++) { | |
27 | rc = of_parse_phandle_with_args(node, "assigned-clock-parents", | |
28 | "#clock-cells", index, &clkspec); | |
29 | if (rc < 0) { | |
30 | /* skip empty (null) phandles */ | |
31 | if (rc == -ENOENT) | |
32 | continue; | |
33 | else | |
34 | return rc; | |
35 | } | |
27a6e1b0 CL |
36 | if (clkspec.np == node && !clk_supplier) { |
37 | of_node_put(clkspec.np); | |
86be408b | 38 | return 0; |
27a6e1b0 | 39 | } |
306c342f | 40 | pclk = of_clk_get_from_provider(&clkspec); |
27a6e1b0 | 41 | of_node_put(clkspec.np); |
86be408b | 42 | if (IS_ERR(pclk)) { |
e2d79333 | 43 | if (PTR_ERR(pclk) != -EPROBE_DEFER) |
16673931 RH |
44 | pr_warn("clk: couldn't get parent clock %d for %pOF\n", |
45 | index, node); | |
86be408b SN |
46 | return PTR_ERR(pclk); |
47 | } | |
48 | ||
49 | rc = of_parse_phandle_with_args(node, "assigned-clocks", | |
50 | "#clock-cells", index, &clkspec); | |
51 | if (rc < 0) | |
52 | goto err; | |
53 | if (clkspec.np == node && !clk_supplier) { | |
27a6e1b0 | 54 | of_node_put(clkspec.np); |
86be408b SN |
55 | rc = 0; |
56 | goto err; | |
57 | } | |
306c342f | 58 | clk = of_clk_get_from_provider(&clkspec); |
27a6e1b0 | 59 | of_node_put(clkspec.np); |
6ba19bf0 | 60 | if (IS_ERR(clk)) { |
e2d79333 | 61 | if (PTR_ERR(clk) != -EPROBE_DEFER) |
16673931 RH |
62 | pr_warn("clk: couldn't get assigned clock %d for %pOF\n", |
63 | index, node); | |
6ba19bf0 | 64 | rc = PTR_ERR(clk); |
86be408b SN |
65 | goto err; |
66 | } | |
67 | ||
68 | rc = clk_set_parent(clk, pclk); | |
69 | if (rc < 0) | |
70 | pr_err("clk: failed to reparent %s to %s: %d\n", | |
71 | __clk_get_name(clk), __clk_get_name(pclk), rc); | |
72 | clk_put(clk); | |
73 | clk_put(pclk); | |
74 | } | |
75 | return 0; | |
76 | err: | |
77 | clk_put(pclk); | |
78 | return rc; | |
79 | } | |
80 | ||
81 | static int __set_clk_rates(struct device_node *node, bool clk_supplier) | |
82 | { | |
83 | struct of_phandle_args clkspec; | |
84 | struct property *prop; | |
85 | const __be32 *cur; | |
86 | int rc, index = 0; | |
87 | struct clk *clk; | |
88 | u32 rate; | |
89 | ||
90 | of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) { | |
91 | if (rate) { | |
92 | rc = of_parse_phandle_with_args(node, "assigned-clocks", | |
93 | "#clock-cells", index, &clkspec); | |
94 | if (rc < 0) { | |
95 | /* skip empty (null) phandles */ | |
96 | if (rc == -ENOENT) | |
97 | continue; | |
98 | else | |
99 | return rc; | |
100 | } | |
27a6e1b0 CL |
101 | if (clkspec.np == node && !clk_supplier) { |
102 | of_node_put(clkspec.np); | |
86be408b | 103 | return 0; |
27a6e1b0 | 104 | } |
86be408b | 105 | |
306c342f | 106 | clk = of_clk_get_from_provider(&clkspec); |
27a6e1b0 | 107 | of_node_put(clkspec.np); |
86be408b | 108 | if (IS_ERR(clk)) { |
e2d79333 | 109 | if (PTR_ERR(clk) != -EPROBE_DEFER) |
16673931 RH |
110 | pr_warn("clk: couldn't get clock %d for %pOF\n", |
111 | index, node); | |
86be408b SN |
112 | return PTR_ERR(clk); |
113 | } | |
114 | ||
115 | rc = clk_set_rate(clk, rate); | |
116 | if (rc < 0) | |
ee177c5d | 117 | pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n", |
2885c3b2 CC |
118 | __clk_get_name(clk), rate, rc, |
119 | clk_get_rate(clk)); | |
86be408b SN |
120 | clk_put(clk); |
121 | } | |
122 | index++; | |
123 | } | |
124 | return 0; | |
125 | } | |
126 | ||
127 | /** | |
128 | * of_clk_set_defaults() - parse and set assigned clocks configuration | |
129 | * @node: device node to apply clock settings for | |
130 | * @clk_supplier: true if clocks supplied by @node should also be considered | |
131 | * | |
132 | * This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties | |
133 | * and sets any specified clock parents and rates. The @clk_supplier argument | |
134 | * should be set to true if @node may be also a clock supplier of any clock | |
135 | * listed in its 'assigned-clocks' or 'assigned-clock-parents' properties. | |
004cbb47 | 136 | * If @clk_supplier is false the function exits returning 0 as soon as it |
86be408b SN |
137 | * determines the @node is also a supplier of any of the clocks. |
138 | */ | |
139 | int of_clk_set_defaults(struct device_node *node, bool clk_supplier) | |
140 | { | |
141 | int rc; | |
142 | ||
143 | if (!node) | |
144 | return 0; | |
145 | ||
146 | rc = __set_clk_parents(node, clk_supplier); | |
147 | if (rc < 0) | |
148 | return rc; | |
149 | ||
150 | return __set_clk_rates(node, clk_supplier); | |
151 | } | |
b11a6fac | 152 | EXPORT_SYMBOL_GPL(of_clk_set_defaults); |