[linux-2.6-block.git] / drivers / clk / clk-composite.c

/*
 * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/slab.h>

static u8 clk_composite_get_parent(struct clk_hw *hw)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *mux_ops = composite->mux_ops;
	struct clk_hw *mux_hw = composite->mux_hw;

	__clk_hw_set_clk(mux_hw, hw);

	return mux_ops->get_parent(mux_hw);
}

static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *mux_ops = composite->mux_ops;
	struct clk_hw *mux_hw = composite->mux_hw;

	__clk_hw_set_clk(mux_hw, hw);

	return mux_ops->set_parent(mux_hw, index);
}

static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
					    unsigned long parent_rate)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	struct clk_hw *rate_hw = composite->rate_hw;

	__clk_hw_set_clk(rate_hw, hw);

	return rate_ops->recalc_rate(rate_hw, parent_rate);
}

static int clk_composite_determine_rate(struct clk_hw *hw,
					struct clk_rate_request *req)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	const struct clk_ops *mux_ops = composite->mux_ops;
	struct clk_hw *rate_hw = composite->rate_hw;
	struct clk_hw *mux_hw = composite->mux_hw;
	struct clk_hw *parent;
	unsigned long parent_rate;
	long tmp_rate, best_rate = 0;
	unsigned long rate_diff;
	unsigned long best_rate_diff = ULONG_MAX;
	long rate;
	int i;

	if (rate_hw && rate_ops && rate_ops->determine_rate) {
		__clk_hw_set_clk(rate_hw, hw);
		return rate_ops->determine_rate(rate_hw, req);
	} else if (rate_hw && rate_ops && rate_ops->round_rate &&
		   mux_hw && mux_ops && mux_ops->set_parent) {
		req->best_parent_hw = NULL;

		if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
			parent = clk_hw_get_parent(mux_hw);
			req->best_parent_hw = parent;
			req->best_parent_rate = clk_hw_get_rate(parent);

			rate = rate_ops->round_rate(rate_hw, req->rate,
						    &req->best_parent_rate);
			if (rate < 0)
				return rate;

			req->rate = rate;
			return 0;
		}

		for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
			parent = clk_hw_get_parent_by_index(mux_hw, i);
			if (!parent)
				continue;

			parent_rate = clk_hw_get_rate(parent);

			tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
							&parent_rate);
			if (tmp_rate < 0)
				continue;

			rate_diff = abs(req->rate - tmp_rate);

			if (!rate_diff || !req->best_parent_hw
				       || best_rate_diff > rate_diff) {
				req->best_parent_hw = parent;
				req->best_parent_rate = parent_rate;
				best_rate_diff = rate_diff;
				best_rate = tmp_rate;
			}

			if (!rate_diff)
				return 0;
		}

		req->rate = best_rate;
		return 0;
	} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
		__clk_hw_set_clk(mux_hw, hw);
		return mux_ops->determine_rate(mux_hw, req);
	} else {
		pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
		return -EINVAL;
	}
}

static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
				  unsigned long *prate)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	struct clk_hw *rate_hw = composite->rate_hw;

	__clk_hw_set_clk(rate_hw, hw);

	return rate_ops->round_rate(rate_hw, rate, prate);
}

static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
			       unsigned long parent_rate)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	struct clk_hw *rate_hw = composite->rate_hw;

	__clk_hw_set_clk(rate_hw, hw);

	return rate_ops->set_rate(rate_hw, rate, parent_rate);
}

static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
					     unsigned long rate,
					     unsigned long parent_rate,
					     u8 index)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	const struct clk_ops *mux_ops = composite->mux_ops;
	struct clk_hw *rate_hw = composite->rate_hw;
	struct clk_hw *mux_hw = composite->mux_hw;
	unsigned long temp_rate;

	__clk_hw_set_clk(rate_hw, hw);
	__clk_hw_set_clk(mux_hw, hw);

	temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
	if (temp_rate > rate) {
		rate_ops->set_rate(rate_hw, rate, parent_rate);
		mux_ops->set_parent(mux_hw, index);
	} else {
		mux_ops->set_parent(mux_hw, index);
		rate_ops->set_rate(rate_hw, rate, parent_rate);
	}

	return 0;
}

static int clk_composite_is_enabled(struct clk_hw *hw)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *gate_ops = composite->gate_ops;
	struct clk_hw *gate_hw = composite->gate_hw;

	__clk_hw_set_clk(gate_hw, hw);

	return gate_ops->is_enabled(gate_hw);
}

static int clk_composite_enable(struct clk_hw *hw)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *gate_ops = composite->gate_ops;
	struct clk_hw *gate_hw = composite->gate_hw;

	__clk_hw_set_clk(gate_hw, hw);

	return gate_ops->enable(gate_hw);
}

static void clk_composite_disable(struct clk_hw *hw)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *gate_ops = composite->gate_ops;
	struct clk_hw *gate_hw = composite->gate_hw;

	__clk_hw_set_clk(gate_hw, hw);

	gate_ops->disable(gate_hw);
}

struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
			const char * const *parent_names, int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	struct clk_hw *hw;
	struct clk_init_data init;
	struct clk_composite *composite;
	struct clk_ops *clk_composite_ops;
	int ret;

	composite = kzalloc(sizeof(*composite), GFP_KERNEL);
	if (!composite)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = parent_names;
	init.num_parents = num_parents;
	hw = &composite->hw;

	clk_composite_ops = &composite->ops;

	if (mux_hw && mux_ops) {
		if (!mux_ops->get_parent) {
			hw = ERR_PTR(-EINVAL);
			goto err;
		}

		composite->mux_hw = mux_hw;
		composite->mux_ops = mux_ops;
		clk_composite_ops->get_parent = clk_composite_get_parent;
		if (mux_ops->set_parent)
			clk_composite_ops->set_parent = clk_composite_set_parent;
		if (mux_ops->determine_rate)
			clk_composite_ops->determine_rate = clk_composite_determine_rate;
	}

	if (rate_hw && rate_ops) {
		if (!rate_ops->recalc_rate) {
			hw = ERR_PTR(-EINVAL);
			goto err;
		}
		clk_composite_ops->recalc_rate = clk_composite_recalc_rate;

		if (rate_ops->determine_rate)
			clk_composite_ops->determine_rate =
				clk_composite_determine_rate;
		else if (rate_ops->round_rate)
			clk_composite_ops->round_rate =
				clk_composite_round_rate;

		/* .set_rate requires either .round_rate or .determine_rate */
		if (rate_ops->set_rate) {
			if (rate_ops->determine_rate || rate_ops->round_rate)
				clk_composite_ops->set_rate =
						clk_composite_set_rate;
			else
				WARN(1, "%s: missing round_rate op is required\n",
						__func__);
		}

		composite->rate_hw = rate_hw;
		composite->rate_ops = rate_ops;
	}

	if (mux_hw && mux_ops && rate_hw && rate_ops) {
		if (mux_ops->set_parent && rate_ops->set_rate)
			clk_composite_ops->set_rate_and_parent =
			clk_composite_set_rate_and_parent;
	}

	if (gate_hw && gate_ops) {
		if (!gate_ops->is_enabled || !gate_ops->enable ||
		    !gate_ops->disable) {
			hw = ERR_PTR(-EINVAL);
			goto err;
		}

		composite->gate_hw = gate_hw;
		composite->gate_ops = gate_ops;
		clk_composite_ops->is_enabled = clk_composite_is_enabled;
		clk_composite_ops->enable = clk_composite_enable;
		clk_composite_ops->disable = clk_composite_disable;
	}

	init.ops = clk_composite_ops;
	composite->hw.init = &init;

	ret = clk_hw_register(dev, hw);
	if (ret) {
		hw = ERR_PTR(ret);
		goto err;
	}

	if (composite->mux_hw)
		composite->mux_hw->clk = hw->clk;

	if (composite->rate_hw)
		composite->rate_hw->clk = hw->clk;

	if (composite->gate_hw)
		composite->gate_hw->clk = hw->clk;

	return hw;

err:
	kfree(composite);
	return hw;
}

struct clk *clk_register_composite(struct device *dev, const char *name,
			const char * const *parent_names, int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	struct clk_hw *hw;

	hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
			mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
			flags);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}

void clk_unregister_composite(struct clk *clk)
{
	struct clk_composite *composite;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	composite = to_clk_composite(hw);

	clk_unregister(clk);
	kfree(composite);
}
Commit	Line	Data
ece70094 PG	1	/*
	2	* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/clk-provider.h>
	19	#include <linux/err.h>
	20	#include <linux/slab.h>
	21
ece70094 PG	22	static u8 clk_composite_get_parent(struct clk_hw *hw)
	23	{
	24	struct clk_composite *composite = to_clk_composite(hw);
	25	const struct clk_ops *mux_ops = composite->mux_ops;
	26	struct clk_hw *mux_hw = composite->mux_hw;
	27
4e907ef6	28	__clk_hw_set_clk(mux_hw, hw);
ece70094 PG	29
	30	return mux_ops->get_parent(mux_hw);
	31	}
	32
	33	static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
	34	{
	35	struct clk_composite *composite = to_clk_composite(hw);
	36	const struct clk_ops *mux_ops = composite->mux_ops;
	37	struct clk_hw *mux_hw = composite->mux_hw;
	38
4e907ef6	39	__clk_hw_set_clk(mux_hw, hw);
ece70094 PG	40
	41	return mux_ops->set_parent(mux_hw, index);
	42	}
	43
	44	static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
	45	unsigned long parent_rate)
	46	{
	47	struct clk_composite *composite = to_clk_composite(hw);
d3a1c7be MT	48	const struct clk_ops *rate_ops = composite->rate_ops;
d3a1c7be MT	49	struct clk_hw *rate_hw = composite->rate_hw;
ece70094	50
4e907ef6	51	__clk_hw_set_clk(rate_hw, hw);
ece70094	52
d3a1c7be	53	return rate_ops->recalc_rate(rate_hw, parent_rate);
ece70094 PG	54	}
ece70094 PG	55
0817b62c BB	56	static int clk_composite_determine_rate(struct clk_hw *hw,
0817b62c BB	57	struct clk_rate_request *req)
107f3198 EL	58	{
	59	struct clk_composite *composite = to_clk_composite(hw);
	60	const struct clk_ops *rate_ops = composite->rate_ops;
	61	const struct clk_ops *mux_ops = composite->mux_ops;
	62	struct clk_hw *rate_hw = composite->rate_hw;
	63	struct clk_hw *mux_hw = composite->mux_hw;
2f508a95	64	struct clk_hw *parent;
3eb635f1 BB	65	unsigned long parent_rate;
	66	long tmp_rate, best_rate = 0;
	67	unsigned long rate_diff;
	68	unsigned long best_rate_diff = ULONG_MAX;
0817b62c	69	long rate;
3eb635f1	70	int i;
107f3198 EL	71
107f3198 EL	72	if (rate_hw && rate_ops && rate_ops->determine_rate) {
4e907ef6	73	__clk_hw_set_clk(rate_hw, hw);
0817b62c	74	return rate_ops->determine_rate(rate_hw, req);
3eb635f1 BB	75	} else if (rate_hw && rate_ops && rate_ops->round_rate &&
3eb635f1 BB	76	mux_hw && mux_ops && mux_ops->set_parent) {
0817b62c	77	req->best_parent_hw = NULL;
3eb635f1	78
98d8a60e	79	if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
2f508a95 SB	80	parent = clk_hw_get_parent(mux_hw);
	81	req->best_parent_hw = parent;
	82	req->best_parent_rate = clk_hw_get_rate(parent);
3eb635f1	83
0817b62c BB	84	rate = rate_ops->round_rate(rate_hw, req->rate,
	85	&req->best_parent_rate);
	86	if (rate < 0)
	87	return rate;
	88
	89	req->rate = rate;
	90	return 0;
3eb635f1 BB	91	}
3eb635f1 BB	92
497295af	93	for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
2f508a95	94	parent = clk_hw_get_parent_by_index(mux_hw, i);
3eb635f1 BB	95	if (!parent)
	96	continue;
	97
2f508a95	98	parent_rate = clk_hw_get_rate(parent);
3eb635f1	99
0817b62c	100	tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
3eb635f1 BB	101	&parent_rate);
	102	if (tmp_rate < 0)
	103	continue;
	104
0817b62c	105	rate_diff = abs(req->rate - tmp_rate);
3eb635f1	106
0817b62c	107	if (!rate_diff \|\| !req->best_parent_hw
3eb635f1	108	\|\| best_rate_diff > rate_diff) {
2f508a95	109	req->best_parent_hw = parent;
0817b62c	110	req->best_parent_rate = parent_rate;
3eb635f1 BB	111	best_rate_diff = rate_diff;
	112	best_rate = tmp_rate;
	113	}
	114
	115	if (!rate_diff)
0817b62c	116	return 0;
3eb635f1 BB	117	}
3eb635f1 BB	118
0817b62c BB	119	req->rate = best_rate;
0817b62c BB	120	return 0;
107f3198	121	} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
4e907ef6	122	__clk_hw_set_clk(mux_hw, hw);
0817b62c	123	return mux_ops->determine_rate(mux_hw, req);
107f3198 EL	124	} else {
107f3198 EL	125	pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
57d866e6	126	return -EINVAL;
107f3198 EL	127	}
	128	}
	129
ece70094 PG	130	static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
	131	unsigned long *prate)
	132	{
	133	struct clk_composite *composite = to_clk_composite(hw);
d3a1c7be MT	134	const struct clk_ops *rate_ops = composite->rate_ops;
d3a1c7be MT	135	struct clk_hw *rate_hw = composite->rate_hw;
ece70094	136
4e907ef6	137	__clk_hw_set_clk(rate_hw, hw);
ece70094	138
d3a1c7be	139	return rate_ops->round_rate(rate_hw, rate, prate);
ece70094 PG	140	}
	141
	142	static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
	143	unsigned long parent_rate)
	144	{
	145	struct clk_composite *composite = to_clk_composite(hw);
d3a1c7be MT	146	const struct clk_ops *rate_ops = composite->rate_ops;
d3a1c7be MT	147	struct clk_hw *rate_hw = composite->rate_hw;
ece70094	148
4e907ef6	149	__clk_hw_set_clk(rate_hw, hw);
ece70094	150
d3a1c7be	151	return rate_ops->set_rate(rate_hw, rate, parent_rate);
ece70094 PG	152	}
ece70094 PG	153
9e52cec0 FX	154	static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
	155	unsigned long rate,
	156	unsigned long parent_rate,
	157	u8 index)
	158	{
	159	struct clk_composite *composite = to_clk_composite(hw);
	160	const struct clk_ops *rate_ops = composite->rate_ops;
	161	const struct clk_ops *mux_ops = composite->mux_ops;
	162	struct clk_hw *rate_hw = composite->rate_hw;
	163	struct clk_hw *mux_hw = composite->mux_hw;
	164	unsigned long temp_rate;
	165
	166	__clk_hw_set_clk(rate_hw, hw);
	167	__clk_hw_set_clk(mux_hw, hw);
	168
	169	temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
	170	if (temp_rate > rate) {
	171	rate_ops->set_rate(rate_hw, rate, parent_rate);
	172	mux_ops->set_parent(mux_hw, index);
	173	} else {
	174	mux_ops->set_parent(mux_hw, index);
	175	rate_ops->set_rate(rate_hw, rate, parent_rate);
	176	}
	177
	178	return 0;
	179	}
	180
ece70094 PG	181	static int clk_composite_is_enabled(struct clk_hw *hw)
	182	{
	183	struct clk_composite *composite = to_clk_composite(hw);
	184	const struct clk_ops *gate_ops = composite->gate_ops;
	185	struct clk_hw *gate_hw = composite->gate_hw;
	186
4e907ef6	187	__clk_hw_set_clk(gate_hw, hw);
ece70094 PG	188
	189	return gate_ops->is_enabled(gate_hw);
	190	}
	191
	192	static int clk_composite_enable(struct clk_hw *hw)
	193	{
	194	struct clk_composite *composite = to_clk_composite(hw);
	195	const struct clk_ops *gate_ops = composite->gate_ops;
	196	struct clk_hw *gate_hw = composite->gate_hw;
	197
4e907ef6	198	__clk_hw_set_clk(gate_hw, hw);
ece70094 PG	199
	200	return gate_ops->enable(gate_hw);
	201	}
	202
	203	static void clk_composite_disable(struct clk_hw *hw)
	204	{
	205	struct clk_composite *composite = to_clk_composite(hw);
	206	const struct clk_ops *gate_ops = composite->gate_ops;
	207	struct clk_hw *gate_hw = composite->gate_hw;
	208
4e907ef6	209	__clk_hw_set_clk(gate_hw, hw);
ece70094 PG	210
	211	gate_ops->disable(gate_hw);
	212	}
	213
49cb392d	214	struct clk_hw clk_hw_register_composite(struct device dev, const char *name,
2893c379	215	const char * const *parent_names, int num_parents,
ece70094	216	struct clk_hw mux_hw, const struct clk_ops mux_ops,
d3a1c7be	217	struct clk_hw rate_hw, const struct clk_ops rate_ops,
ece70094 PG	218	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	219	unsigned long flags)
	220	{
49cb392d	221	struct clk_hw *hw;
ece70094 PG	222	struct clk_init_data init;
	223	struct clk_composite *composite;
	224	struct clk_ops *clk_composite_ops;
49cb392d	225	int ret;
ece70094 PG	226
ece70094 PG	227	composite = kzalloc(sizeof(*composite), GFP_KERNEL);
d122db7e	228	if (!composite)
ece70094	229	return ERR_PTR(-ENOMEM);
ece70094 PG	230
	231	init.name = name;
	232	init.flags = flags \| CLK_IS_BASIC;
	233	init.parent_names = parent_names;
	234	init.num_parents = num_parents;
49cb392d	235	hw = &composite->hw;
ece70094 PG	236
	237	clk_composite_ops = &composite->ops;
	238
	239	if (mux_hw && mux_ops) {
0c02cf2f	240	if (!mux_ops->get_parent) {
49cb392d	241	hw = ERR_PTR(-EINVAL);
ece70094 PG	242	goto err;
	243	}
	244
	245	composite->mux_hw = mux_hw;
	246	composite->mux_ops = mux_ops;
	247	clk_composite_ops->get_parent = clk_composite_get_parent;
0c02cf2f HS	248	if (mux_ops->set_parent)
0c02cf2f HS	249	clk_composite_ops->set_parent = clk_composite_set_parent;
107f3198 EL	250	if (mux_ops->determine_rate)
107f3198 EL	251	clk_composite_ops->determine_rate = clk_composite_determine_rate;
ece70094 PG	252	}
ece70094 PG	253
d3a1c7be	254	if (rate_hw && rate_ops) {
f363e215	255	if (!rate_ops->recalc_rate) {
49cb392d	256	hw = ERR_PTR(-EINVAL);
ece70094 PG	257	goto err;
ece70094 PG	258	}
5a994e15	259	clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
ece70094	260
5a994e15 MT	261	if (rate_ops->determine_rate)
	262	clk_composite_ops->determine_rate =
	263	clk_composite_determine_rate;
	264	else if (rate_ops->round_rate)
	265	clk_composite_ops->round_rate =
	266	clk_composite_round_rate;
	267
	268	/* .set_rate requires either .round_rate or .determine_rate */
	269	if (rate_ops->set_rate) {
	270	if (rate_ops->determine_rate \|\| rate_ops->round_rate)
	271	clk_composite_ops->set_rate =
	272	clk_composite_set_rate;
	273	else
	274	WARN(1, "%s: missing round_rate op is required\n",
	275	__func__);
f363e215 MT	276	}
f363e215 MT	277
d3a1c7be MT	278	composite->rate_hw = rate_hw;
d3a1c7be MT	279	composite->rate_ops = rate_ops;
ece70094 PG	280	}
ece70094 PG	281
9e52cec0 FX	282	if (mux_hw && mux_ops && rate_hw && rate_ops) {
	283	if (mux_ops->set_parent && rate_ops->set_rate)
	284	clk_composite_ops->set_rate_and_parent =
	285	clk_composite_set_rate_and_parent;
	286	}
	287
ece70094 PG	288	if (gate_hw && gate_ops) {
	289	if (!gate_ops->is_enabled \|\| !gate_ops->enable \|\|
	290	!gate_ops->disable) {
49cb392d	291	hw = ERR_PTR(-EINVAL);
ece70094 PG	292	goto err;
	293	}
	294
	295	composite->gate_hw = gate_hw;
	296	composite->gate_ops = gate_ops;
	297	clk_composite_ops->is_enabled = clk_composite_is_enabled;
	298	clk_composite_ops->enable = clk_composite_enable;
	299	clk_composite_ops->disable = clk_composite_disable;
	300	}
	301
	302	init.ops = clk_composite_ops;
	303	composite->hw.init = &init;
	304
49cb392d SB	305	ret = clk_hw_register(dev, hw);
	306	if (ret) {
	307	hw = ERR_PTR(ret);
ece70094	308	goto err;
49cb392d	309	}
ece70094 PG	310
ece70094 PG	311	if (composite->mux_hw)
49cb392d	312	composite->mux_hw->clk = hw->clk;
ece70094	313
d3a1c7be	314	if (composite->rate_hw)
49cb392d	315	composite->rate_hw->clk = hw->clk;
ece70094 PG	316
ece70094 PG	317	if (composite->gate_hw)
49cb392d	318	composite->gate_hw->clk = hw->clk;
ece70094	319
49cb392d	320	return hw;
ece70094 PG	321
	322	err:
	323	kfree(composite);
49cb392d SB	324	return hw;
	325	}
	326
	327	struct clk clk_register_composite(struct device dev, const char *name,
	328	const char * const *parent_names, int num_parents,
	329	struct clk_hw mux_hw, const struct clk_ops mux_ops,
	330	struct clk_hw rate_hw, const struct clk_ops rate_ops,
	331	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	332	unsigned long flags)
	333	{
	334	struct clk_hw *hw;
	335
	336	hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
	337	mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
	338	flags);
	339	if (IS_ERR(hw))
	340	return ERR_CAST(hw);
	341	return hw->clk;
ece70094	342	}
92a39d90 MR	343
	344	void clk_unregister_composite(struct clk *clk)
	345	{
	346	struct clk_composite *composite;
	347	struct clk_hw *hw;
	348
	349	hw = __clk_get_hw(clk);
	350	if (!hw)
	351	return;
	352
	353	composite = to_clk_composite(hw);
	354
	355	clk_unregister(clk);
	356	kfree(composite);
	357	}