[linux-block.git] / drivers / clk / clk-bd718x7.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2018 ROHM Semiconductors

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mfd/rohm-generic.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/regmap.h>

/* clk control registers */
/* BD71815 */
#define BD71815_REG_OUT32K	0x1d
/* BD71828 */
#define BD71828_REG_OUT32K	0x4B
/* BD71837 and BD71847 */
#define BD718XX_REG_OUT32K	0x2E

/*
 * BD71837, BD71847, and BD71828 all use bit [0] to clk output control
 */
#define CLK_OUT_EN_MASK		BIT(0)


struct bd718xx_clk {
	struct clk_hw hw;
	u8 reg;
	u8 mask;
	struct platform_device *pdev;
	struct regmap *regmap;
};

static int bd71837_clk_set(struct bd718xx_clk *c, unsigned int status)
{
	return regmap_update_bits(c->regmap, c->reg, c->mask, status);
}

static void bd71837_clk_disable(struct clk_hw *hw)
{
	int rv;
	struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);

	rv = bd71837_clk_set(c, 0);
	if (rv)
		dev_dbg(&c->pdev->dev, "Failed to disable 32K clk (%d)\n", rv);
}

static int bd71837_clk_enable(struct clk_hw *hw)
{
	struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);

	return bd71837_clk_set(c, 0xffffffff);
}

static int bd71837_clk_is_enabled(struct clk_hw *hw)
{
	int enabled;
	int rval;
	struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);

	rval = regmap_read(c->regmap, c->reg, &enabled);

	if (rval)
		return rval;

	return enabled & c->mask;
}

static const struct clk_ops bd71837_clk_ops = {
	.prepare = &bd71837_clk_enable,
	.unprepare = &bd71837_clk_disable,
	.is_prepared = &bd71837_clk_is_enabled,
};

static int bd71837_clk_probe(struct platform_device *pdev)
{
	struct bd718xx_clk *c;
	int rval = -ENOMEM;
	const char *parent_clk;
	struct device *parent = pdev->dev.parent;
	struct clk_init_data init = {
		.name = "bd718xx-32k-out",
		.ops = &bd71837_clk_ops,
	};
	enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data;

	c = devm_kzalloc(&pdev->dev, sizeof(*c), GFP_KERNEL);
	if (!c)
		return -ENOMEM;

	c->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	if (!c->regmap)
		return -ENODEV;

	init.num_parents = 1;
	parent_clk = of_clk_get_parent_name(parent->of_node, 0);

	init.parent_names = &parent_clk;
	if (!parent_clk) {
		dev_err(&pdev->dev, "No parent clk found\n");
		return -EINVAL;
	}
	switch (chip) {
	case ROHM_CHIP_TYPE_BD71837:
	case ROHM_CHIP_TYPE_BD71847:
		c->reg = BD718XX_REG_OUT32K;
		c->mask = CLK_OUT_EN_MASK;
		break;
	case ROHM_CHIP_TYPE_BD71828:
		c->reg = BD71828_REG_OUT32K;
		c->mask = CLK_OUT_EN_MASK;
		break;
	case ROHM_CHIP_TYPE_BD71815:
		c->reg = BD71815_REG_OUT32K;
		c->mask = CLK_OUT_EN_MASK;
		break;
	default:
		dev_err(&pdev->dev, "Unknown clk chip\n");
		return -EINVAL;
	}
	c->pdev = pdev;
	c->hw.init = &init;

	of_property_read_string_index(parent->of_node,
				      "clock-output-names", 0, &init.name);

	rval = devm_clk_hw_register(&pdev->dev, &c->hw);
	if (rval) {
		dev_err(&pdev->dev, "failed to register 32K clk");
		return rval;
	}
	rval = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
					   &c->hw);
	if (rval)
		dev_err(&pdev->dev, "adding clk provider failed\n");

	return rval;
}

static const struct platform_device_id bd718x7_clk_id[] = {
	{ "bd71837-clk", ROHM_CHIP_TYPE_BD71837 },
	{ "bd71847-clk", ROHM_CHIP_TYPE_BD71847 },
	{ "bd71828-clk", ROHM_CHIP_TYPE_BD71828 },
	{ "bd71815-clk", ROHM_CHIP_TYPE_BD71815 },
	{ },
};
MODULE_DEVICE_TABLE(platform, bd718x7_clk_id);

static struct platform_driver bd71837_clk = {
	.driver = {
		.name = "bd718xx-clk",
	},
	.probe = bd71837_clk_probe,
	.id_table = bd718x7_clk_id,
};

module_platform_driver(bd71837_clk);

MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and chip clk driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bd718xx-clk");
Commit	Line	Data
2e62246b MV	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (C) 2018 ROHM Semiconductors
	3
	4	#include <linux/kernel.h>
	5	#include <linux/module.h>
	6	#include <linux/init.h>
	7	#include <linux/err.h>
	8	#include <linux/platform_device.h>
	9	#include <linux/slab.h>
ae866dec	10	#include <linux/mfd/rohm-generic.h>
2e62246b MV	11	#include <linux/clk-provider.h>
	12	#include <linux/clkdev.h>
	13	#include <linux/regmap.h>
	14
ae866dec	15	/* clk control registers */
42391f7e MV	16	/* BD71815 */
42391f7e MV	17	#define BD71815_REG_OUT32K 0x1d
ae866dec MV	18	/* BD71828 */
	19	#define BD71828_REG_OUT32K 0x4B
	20	/* BD71837 and BD71847 */
	21	#define BD718XX_REG_OUT32K 0x2E
	22
	23	/*
fa5b6541	24	* BD71837, BD71847, and BD71828 all use bit [0] to clk output control
ae866dec MV	25	*/
	26	#define CLK_OUT_EN_MASK BIT(0)
	27
	28
2e62246b MV	29	struct bd718xx_clk {
	30	struct clk_hw hw;
	31	u8 reg;
	32	u8 mask;
	33	struct platform_device *pdev;
ddddfafd	34	struct regmap *regmap;
2e62246b MV	35	};
2e62246b MV	36
ae866dec	37	static int bd71837_clk_set(struct bd718xx_clk *c, unsigned int status)
2e62246b	38	{
ddddfafd	39	return regmap_update_bits(c->regmap, c->reg, c->mask, status);
2e62246b MV	40	}
	41
	42	static void bd71837_clk_disable(struct clk_hw *hw)
	43	{
	44	int rv;
	45	struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
	46
ae866dec	47	rv = bd71837_clk_set(c, 0);
2e62246b MV	48	if (rv)
	49	dev_dbg(&c->pdev->dev, "Failed to disable 32K clk (%d)\n", rv);
	50	}
	51
	52	static int bd71837_clk_enable(struct clk_hw *hw)
	53	{
ae866dec MV	54	struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
	55
	56	return bd71837_clk_set(c, 0xffffffff);
2e62246b MV	57	}
	58
	59	static int bd71837_clk_is_enabled(struct clk_hw *hw)
	60	{
	61	int enabled;
	62	int rval;
	63	struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
	64
ddddfafd	65	rval = regmap_read(c->regmap, c->reg, &enabled);
2e62246b MV	66
	67	if (rval)
	68	return rval;
	69
	70	return enabled & c->mask;
	71	}
	72
	73	static const struct clk_ops bd71837_clk_ops = {
	74	.prepare = &bd71837_clk_enable,
	75	.unprepare = &bd71837_clk_disable,
	76	.is_prepared = &bd71837_clk_is_enabled,
	77	};
	78
	79	static int bd71837_clk_probe(struct platform_device *pdev)
	80	{
	81	struct bd718xx_clk *c;
	82	int rval = -ENOMEM;
	83	const char *parent_clk;
	84	struct device *parent = pdev->dev.parent;
2e62246b MV	85	struct clk_init_data init = {
	86	.name = "bd718xx-32k-out",
	87	.ops = &bd71837_clk_ops,
	88	};
1b1c26b2	89	enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data;
2e62246b MV	90
	91	c = devm_kzalloc(&pdev->dev, sizeof(*c), GFP_KERNEL);
	92	if (!c)
	93	return -ENOMEM;
	94
ddddfafd MV	95	c->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	96	if (!c->regmap)
	97	return -ENODEV;
	98
2e62246b MV	99	init.num_parents = 1;
	100	parent_clk = of_clk_get_parent_name(parent->of_node, 0);
	101
	102	init.parent_names = &parent_clk;
	103	if (!parent_clk) {
	104	dev_err(&pdev->dev, "No parent clk found\n");
	105	return -EINVAL;
	106	}
1b1c26b2	107	switch (chip) {
0dae7f58 MV	108	case ROHM_CHIP_TYPE_BD71837:
	109	case ROHM_CHIP_TYPE_BD71847:
	110	c->reg = BD718XX_REG_OUT32K;
ae866dec MV	111	c->mask = CLK_OUT_EN_MASK;
	112	break;
	113	case ROHM_CHIP_TYPE_BD71828:
	114	c->reg = BD71828_REG_OUT32K;
	115	c->mask = CLK_OUT_EN_MASK;
0dae7f58	116	break;
42391f7e MV	117	case ROHM_CHIP_TYPE_BD71815:
	118	c->reg = BD71815_REG_OUT32K;
	119	c->mask = CLK_OUT_EN_MASK;
	120	break;
0dae7f58 MV	121	default:
	122	dev_err(&pdev->dev, "Unknown clk chip\n");
	123	return -EINVAL;
	124	}
2e62246b MV	125	c->pdev = pdev;
	126	c->hw.init = &init;
	127
	128	of_property_read_string_index(parent->of_node,
	129	"clock-output-names", 0, &init.name);
	130
	131	rval = devm_clk_hw_register(&pdev->dev, &c->hw);
	132	if (rval) {
	133	dev_err(&pdev->dev, "failed to register 32K clk");
	134	return rval;
	135	}
	136	rval = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
	137	&c->hw);
	138	if (rval)
	139	dev_err(&pdev->dev, "adding clk provider failed\n");
	140
	141	return rval;
	142	}
	143
1b1c26b2 MV	144	static const struct platform_device_id bd718x7_clk_id[] = {
	145	{ "bd71837-clk", ROHM_CHIP_TYPE_BD71837 },
	146	{ "bd71847-clk", ROHM_CHIP_TYPE_BD71847 },
ae866dec	147	{ "bd71828-clk", ROHM_CHIP_TYPE_BD71828 },
42391f7e	148	{ "bd71815-clk", ROHM_CHIP_TYPE_BD71815 },
1b1c26b2 MV	149	{ },
	150	};
	151	MODULE_DEVICE_TABLE(platform, bd718x7_clk_id);
	152
2e62246b MV	153	static struct platform_driver bd71837_clk = {
	154	.driver = {
	155	.name = "bd718xx-clk",
	156	},
	157	.probe = bd71837_clk_probe,
1b1c26b2	158	.id_table = bd718x7_clk_id,
2e62246b MV	159	};
	160
	161	module_platform_driver(bd71837_clk);
	162
	163	MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
fa5b6541	164	MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and chip clk driver");
2e62246b	165	MODULE_LICENSE("GPL");
8ad1193e	166	MODULE_ALIAS("platform:bd718xx-clk");