[linux-block.git] / drivers / clk / clk-axi-clkgen.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * AXI clkgen driver
 *
 * Copyright 2012-2013 Analog Devices Inc.
 *  Author: Lars-Peter Clausen <lars@metafoo.de>
 */

#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/err.h>

#define AXI_CLKGEN_V2_REG_RESET		0x40
#define AXI_CLKGEN_V2_REG_CLKSEL	0x44
#define AXI_CLKGEN_V2_REG_DRP_CNTRL	0x70
#define AXI_CLKGEN_V2_REG_DRP_STATUS	0x74

#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE	BIT(1)
#define AXI_CLKGEN_V2_RESET_ENABLE	BIT(0)

#define AXI_CLKGEN_V2_DRP_CNTRL_SEL	BIT(29)
#define AXI_CLKGEN_V2_DRP_CNTRL_READ	BIT(28)

#define AXI_CLKGEN_V2_DRP_STATUS_BUSY	BIT(16)

#define MMCM_REG_CLKOUT5_2	0x07
#define MMCM_REG_CLKOUT0_1	0x08
#define MMCM_REG_CLKOUT0_2	0x09
#define MMCM_REG_CLKOUT6_2	0x13
#define MMCM_REG_CLK_FB1	0x14
#define MMCM_REG_CLK_FB2	0x15
#define MMCM_REG_CLK_DIV	0x16
#define MMCM_REG_LOCK1		0x18
#define MMCM_REG_LOCK2		0x19
#define MMCM_REG_LOCK3		0x1a
#define MMCM_REG_POWER		0x28
#define MMCM_REG_FILTER1	0x4e
#define MMCM_REG_FILTER2	0x4f

#define MMCM_CLKOUT_NOCOUNT	BIT(6)

#define MMCM_CLK_DIV_DIVIDE	BIT(11)
#define MMCM_CLK_DIV_NOCOUNT	BIT(12)

struct axi_clkgen_limits {
	unsigned int fpfd_min;
	unsigned int fpfd_max;
	unsigned int fvco_min;
	unsigned int fvco_max;
};

struct axi_clkgen {
	void __iomem *base;
	struct clk_hw clk_hw;
	struct axi_clkgen_limits limits;
};

static uint32_t axi_clkgen_lookup_filter(unsigned int m)
{
	switch (m) {
	case 0:
		return 0x01001990;
	case 1:
		return 0x01001190;
	case 2:
		return 0x01009890;
	case 3:
		return 0x01001890;
	case 4:
		return 0x01008890;
	case 5 ... 8:
		return 0x01009090;
	case 9 ... 11:
		return 0x01000890;
	case 12:
		return 0x08009090;
	case 13 ... 22:
		return 0x01001090;
	case 23 ... 36:
		return 0x01008090;
	case 37 ... 46:
		return 0x08001090;
	default:
		return 0x08008090;
	}
}

static const uint32_t axi_clkgen_lock_table[] = {
	0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
	0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
	0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
	0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
	0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
	0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
	0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
	0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
	0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
};

static uint32_t axi_clkgen_lookup_lock(unsigned int m)
{
	if (m < ARRAY_SIZE(axi_clkgen_lock_table))
		return axi_clkgen_lock_table[m];
	return 0x1f1f00fa;
}

static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
	.fpfd_min = 10000,
	.fpfd_max = 450000,
	.fvco_min = 800000,
	.fvco_max = 1600000,
};

static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
	.fpfd_min = 10000,
	.fpfd_max = 300000,
	.fvco_min = 600000,
	.fvco_max = 1200000,
};

static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
	unsigned long fin, unsigned long fout,
	unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
{
	unsigned long d, d_min, d_max, _d_min, _d_max;
	unsigned long m, m_min, m_max;
	unsigned long f, dout, best_f, fvco;
	unsigned long fract_shift = 0;
	unsigned long fvco_min_fract, fvco_max_fract;

	fin /= 1000;
	fout /= 1000;

	best_f = ULONG_MAX;
	*best_d = 0;
	*best_m = 0;
	*best_dout = 0;

	d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1);
	d_max = min_t(unsigned long, fin / limits->fpfd_min, 80);

again:
	fvco_min_fract = limits->fvco_min << fract_shift;
	fvco_max_fract = limits->fvco_max << fract_shift;

	m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
	m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);

	for (m = m_min; m <= m_max; m++) {
		_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
		_d_max = min(d_max, fin * m / fvco_min_fract);

		for (d = _d_min; d <= _d_max; d++) {
			fvco = fin * m / d;

			dout = DIV_ROUND_CLOSEST(fvco, fout);
			dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
			f = fvco / dout;
			if (abs(f - fout) < abs(best_f - fout)) {
				best_f = f;
				*best_d = d;
				*best_m = m << (3 - fract_shift);
				*best_dout = dout << (3 - fract_shift);
				if (best_f == fout)
					return;
			}
		}
	}

	/* Lets see if we find a better setting in fractional mode */
	if (fract_shift == 0) {
		fract_shift = 3;
		goto again;
	}
}

struct axi_clkgen_div_params {
	unsigned int low;
	unsigned int high;
	unsigned int edge;
	unsigned int nocount;
	unsigned int frac_en;
	unsigned int frac;
	unsigned int frac_wf_f;
	unsigned int frac_wf_r;
	unsigned int frac_phase;
};

static void axi_clkgen_calc_clk_params(unsigned int divider,
	unsigned int frac_divider, struct axi_clkgen_div_params *params)
{

	memset(params, 0x0, sizeof(*params));

	if (divider == 1) {
		params->nocount = 1;
		return;
	}

	if (frac_divider == 0) {
		params->high = divider / 2;
		params->edge = divider % 2;
		params->low = divider - params->high;
	} else {
		params->frac_en = 1;
		params->frac = frac_divider;

		params->high = divider / 2;
		params->edge = divider % 2;
		params->low = params->high;

		if (params->edge == 0) {
			params->high--;
			params->frac_wf_r = 1;
		}

		if (params->edge == 0 || frac_divider == 1)
			params->low--;
		if (((params->edge == 0) ^ (frac_divider == 1)) ||
			(divider == 2 && frac_divider == 1))
			params->frac_wf_f = 1;

		params->frac_phase = params->edge * 4 + frac_divider / 2;
	}
}

static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int val)
{
	writel(val, axi_clkgen->base + reg);
}

static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int *val)
{
	*val = readl(axi_clkgen->base + reg);
}

static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
{
	unsigned int timeout = 10000;
	unsigned int val;

	do {
		axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);

	if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
		return -EIO;

	return val & 0xffff;
}

static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int *val)
{
	unsigned int reg_val;
	int ret;

	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	if (ret < 0)
		return ret;

	reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
	reg_val |= (reg << 16);

	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);

	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	if (ret < 0)
		return ret;

	*val = ret;

	return 0;
}

static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int val, unsigned int mask)
{
	unsigned int reg_val = 0;
	int ret;

	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	if (ret < 0)
		return ret;

	if (mask != 0xffff) {
		axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
		reg_val &= ~mask;
	}

	reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);

	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);

	return 0;
}

static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
	bool enable)
{
	unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;

	if (enable)
		val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;

	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
}

static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
{
	return container_of(clk_hw, struct axi_clkgen, clk_hw);
}

static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
	unsigned int reg1, unsigned int reg2, unsigned int reg3,
	struct axi_clkgen_div_params *params)
{
	axi_clkgen_mmcm_write(axi_clkgen, reg1,
		(params->high << 6) | params->low, 0xefff);
	axi_clkgen_mmcm_write(axi_clkgen, reg2,
		(params->frac << 12) | (params->frac_en << 11) |
		(params->frac_wf_r << 10) | (params->edge << 7) |
		(params->nocount << 6), 0x7fff);
	if (reg3 != 0) {
		axi_clkgen_mmcm_write(axi_clkgen, reg3,
			(params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
	}
}

static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
	unsigned long rate, unsigned long parent_rate)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
	unsigned int d, m, dout;
	struct axi_clkgen_div_params params;
	uint32_t power = 0;
	uint32_t filter;
	uint32_t lock;

	if (parent_rate == 0 || rate == 0)
		return -EINVAL;

	axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);

	if (d == 0 || dout == 0 || m == 0)
		return -EINVAL;

	if ((dout & 0x7) != 0 || (m & 0x7) != 0)
		power |= 0x9800;

	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);

	filter = axi_clkgen_lookup_filter(m - 1);
	lock = axi_clkgen_lookup_lock(m - 1);

	axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
	axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
		MMCM_REG_CLKOUT5_2, &params);

	axi_clkgen_calc_clk_params(d, 0, &params);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
		(params.edge << 13) | (params.nocount << 12) |
		(params.high << 6) | params.low, 0x3fff);

	axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
	axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
		MMCM_REG_CLKOUT6_2, &params);

	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
		(((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
		(((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);

	return 0;
}

static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
	unsigned long *parent_rate)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw);
	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
	unsigned int d, m, dout;
	unsigned long long tmp;

	axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout);

	if (d == 0 || dout == 0 || m == 0)
		return -EINVAL;

	tmp = (unsigned long long)*parent_rate * m;
	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);

	return min_t(unsigned long long, tmp, LONG_MAX);
}

static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
	unsigned int reg1, unsigned int reg2)
{
	unsigned int val1, val2;
	unsigned int div;

	axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
	if (val2 & MMCM_CLKOUT_NOCOUNT)
		return 8;

	axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);

	div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
	div <<= 3;

	if (val2 & MMCM_CLK_DIV_DIVIDE) {
		if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
			div += 8;
		else
			div += 16;

		div += (val2 >> 12) & 0x7;
	}

	return div;
}

static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
	unsigned long parent_rate)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	unsigned int d, m, dout;
	unsigned long long tmp;
	unsigned int val;

	dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
		MMCM_REG_CLKOUT0_2);
	m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
		MMCM_REG_CLK_FB2);

	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
	if (val & MMCM_CLK_DIV_NOCOUNT)
		d = 1;
	else
		d = (val & 0x3f) + ((val >> 6) & 0x3f);

	if (d == 0 || dout == 0)
		return 0;

	tmp = (unsigned long long)parent_rate * m;
	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);

	return min_t(unsigned long long, tmp, ULONG_MAX);
}

static int axi_clkgen_enable(struct clk_hw *clk_hw)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);

	axi_clkgen_mmcm_enable(axi_clkgen, true);

	return 0;
}

static void axi_clkgen_disable(struct clk_hw *clk_hw)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);

	axi_clkgen_mmcm_enable(axi_clkgen, false);
}

static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);

	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);

	return 0;
}

static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	unsigned int parent;

	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);

	return parent;
}

static const struct clk_ops axi_clkgen_ops = {
	.recalc_rate = axi_clkgen_recalc_rate,
	.round_rate = axi_clkgen_round_rate,
	.set_rate = axi_clkgen_set_rate,
	.enable = axi_clkgen_enable,
	.disable = axi_clkgen_disable,
	.set_parent = axi_clkgen_set_parent,
	.get_parent = axi_clkgen_get_parent,
};

static int axi_clkgen_probe(struct platform_device *pdev)
{
	const struct axi_clkgen_limits *dflt_limits;
	struct axi_clkgen *axi_clkgen;
	struct clk_init_data init;
	const char *parent_names[2];
	const char *clk_name;
	unsigned int i;
	int ret;

	dflt_limits = device_get_match_data(&pdev->dev);
	if (!dflt_limits)
		return -ENODEV;

	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
	if (!axi_clkgen)
		return -ENOMEM;

	axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(axi_clkgen->base))
		return PTR_ERR(axi_clkgen->base);

	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
	if (init.num_parents < 1 || init.num_parents > 2)
		return -EINVAL;

	for (i = 0; i < init.num_parents; i++) {
		parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
		if (!parent_names[i])
			return -EINVAL;
	}

	memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits));

	clk_name = pdev->dev.of_node->name;
	of_property_read_string(pdev->dev.of_node, "clock-output-names",
		&clk_name);

	init.name = clk_name;
	init.ops = &axi_clkgen_ops;
	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
	init.parent_names = parent_names;

	axi_clkgen_mmcm_enable(axi_clkgen, false);

	axi_clkgen->clk_hw.init = &init;
	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
	if (ret)
		return ret;

	return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
				      &axi_clkgen->clk_hw);
}

static int axi_clkgen_remove(struct platform_device *pdev)
{
	of_clk_del_provider(pdev->dev.of_node);

	return 0;
}

static const struct of_device_id axi_clkgen_ids[] = {
	{
		.compatible = "adi,zynqmp-axi-clkgen-2.00.a",
		.data = &axi_clkgen_zynqmp_default_limits,
	},
	{
		.compatible = "adi,axi-clkgen-2.00.a",
		.data = &axi_clkgen_zynq_default_limits,
	},
	{ }
};
MODULE_DEVICE_TABLE(of, axi_clkgen_ids);

static struct platform_driver axi_clkgen_driver = {
	.driver = {
		.name = "adi-axi-clkgen",
		.of_match_table = axi_clkgen_ids,
	},
	.probe = axi_clkgen_probe,
	.remove = axi_clkgen_remove,
};
module_platform_driver(axi_clkgen_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
Commit	Line	Data
fda8d26e	1	// SPDX-License-Identifier: GPL-2.0-only
0e646c52 LPC	2	/*
	3	* AXI clkgen driver
	4	*
	5	* Copyright 2012-2013 Analog Devices Inc.
	6	* Author: Lars-Peter Clausen <lars@metafoo.de>
0e646c52 LPC	7	*/
	8
	9	#include <linux/platform_device.h>
	10	#include <linux/clk-provider.h>
0e646c52 LPC	11	#include <linux/slab.h>
	12	#include <linux/io.h>
	13	#include <linux/of.h>
	14	#include <linux/module.h>
	15	#include <linux/err.h>
	16
1887c3a6	17	#define AXI_CLKGEN_V2_REG_RESET 0x40
62d1e782	18	#define AXI_CLKGEN_V2_REG_CLKSEL 0x44
1887c3a6 LPC	19	#define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
	20	#define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
	21
	22	#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
	23	#define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
	24
	25	#define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
	26	#define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
	27
	28	#define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
	29
86378cf6	30	#define MMCM_REG_CLKOUT5_2 0x07
1887c3a6 LPC	31	#define MMCM_REG_CLKOUT0_1 0x08
1887c3a6 LPC	32	#define MMCM_REG_CLKOUT0_2 0x09
86378cf6	33	#define MMCM_REG_CLKOUT6_2 0x13
1887c3a6 LPC	34	#define MMCM_REG_CLK_FB1 0x14
	35	#define MMCM_REG_CLK_FB2 0x15
	36	#define MMCM_REG_CLK_DIV 0x16
	37	#define MMCM_REG_LOCK1 0x18
	38	#define MMCM_REG_LOCK2 0x19
	39	#define MMCM_REG_LOCK3 0x1a
a3947209	40	#define MMCM_REG_POWER 0x28
1887c3a6 LPC	41	#define MMCM_REG_FILTER1 0x4e
	42	#define MMCM_REG_FILTER2 0x4f
	43
063578dc LPC	44	#define MMCM_CLKOUT_NOCOUNT BIT(6)
063578dc LPC	45
86378cf6	46	#define MMCM_CLK_DIV_DIVIDE BIT(11)
063578dc LPC	47	#define MMCM_CLK_DIV_NOCOUNT BIT(12)
063578dc LPC	48
ac1ee86a AA	49	struct axi_clkgen_limits {
	50	unsigned int fpfd_min;
	51	unsigned int fpfd_max;
	52	unsigned int fvco_min;
	53	unsigned int fvco_max;
	54	};
	55
0e646c52 LPC	56	struct axi_clkgen {
	57	void __iomem *base;
	58	struct clk_hw clk_hw;
ac1ee86a	59	struct axi_clkgen_limits limits;
0e646c52 LPC	60	};
	61
	62	static uint32_t axi_clkgen_lookup_filter(unsigned int m)
	63	{
	64	switch (m) {
	65	case 0:
	66	return 0x01001990;
	67	case 1:
	68	return 0x01001190;
	69	case 2:
	70	return 0x01009890;
	71	case 3:
	72	return 0x01001890;
	73	case 4:
	74	return 0x01008890;
	75	case 5 ... 8:
	76	return 0x01009090;
	77	case 9 ... 11:
	78	return 0x01000890;
	79	case 12:
	80	return 0x08009090;
	81	case 13 ... 22:
	82	return 0x01001090;
	83	case 23 ... 36:
	84	return 0x01008090;
	85	case 37 ... 46:
	86	return 0x08001090;
	87	default:
	88	return 0x08008090;
	89	}
	90	}
	91
	92	static const uint32_t axi_clkgen_lock_table[] = {
	93	0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
	94	0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
	95	0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
	96	0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
	97	0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
	98	0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
	99	0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
	100	0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
	101	0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
	102	};
	103
	104	static uint32_t axi_clkgen_lookup_lock(unsigned int m)
	105	{
	106	if (m < ARRAY_SIZE(axi_clkgen_lock_table))
	107	return axi_clkgen_lock_table[m];
	108	return 0x1f1f00fa;
	109	}
	110
da68c309 AA	111	static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
	112	.fpfd_min = 10000,
	113	.fpfd_max = 450000,
	114	.fvco_min = 800000,
	115	.fvco_max = 1600000,
	116	};
	117
ac1ee86a AA	118	static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
	119	.fpfd_min = 10000,
	120	.fpfd_max = 300000,
	121	.fvco_min = 600000,
	122	.fvco_max = 1200000,
	123	};
0e646c52	124
ac1ee86a AA	125	static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
ac1ee86a AA	126	unsigned long fin, unsigned long fout,
0e646c52 LPC	127	unsigned int best_d, unsigned int best_m, unsigned int *best_dout)
	128	{
	129	unsigned long d, d_min, d_max, _d_min, _d_max;
	130	unsigned long m, m_min, m_max;
	131	unsigned long f, dout, best_f, fvco;
86378cf6 LPC	132	unsigned long fract_shift = 0;
86378cf6 LPC	133	unsigned long fvco_min_fract, fvco_max_fract;
0e646c52 LPC	134
	135	fin /= 1000;
	136	fout /= 1000;
	137
	138	best_f = ULONG_MAX;
	139	*best_d = 0;
	140	*best_m = 0;
	141	*best_dout = 0;
	142
ac1ee86a AA	143	d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1);
ac1ee86a AA	144	d_max = min_t(unsigned long, fin / limits->fpfd_min, 80);
0e646c52	145
86378cf6	146	again:
ac1ee86a AA	147	fvco_min_fract = limits->fvco_min << fract_shift;
ac1ee86a AA	148	fvco_max_fract = limits->fvco_max << fract_shift;
86378cf6 LPC	149
	150	m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
	151	m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
0e646c52 LPC	152
0e646c52 LPC	153	for (m = m_min; m <= m_max; m++) {
86378cf6 LPC	154	_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
86378cf6 LPC	155	_d_max = min(d_max, fin * m / fvco_min_fract);
0e646c52 LPC	156
	157	for (d = _d_min; d <= _d_max; d++) {
	158	fvco = fin * m / d;
	159
	160	dout = DIV_ROUND_CLOSEST(fvco, fout);
86378cf6	161	dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
0e646c52 LPC	162	f = fvco / dout;
	163	if (abs(f - fout) < abs(best_f - fout)) {
	164	best_f = f;
	165	*best_d = d;
86378cf6 LPC	166	*best_m = m << (3 - fract_shift);
86378cf6 LPC	167	*best_dout = dout << (3 - fract_shift);
0e646c52 LPC	168	if (best_f == fout)
	169	return;
	170	}
	171	}
	172	}
86378cf6 LPC	173
	174	/* Lets see if we find a better setting in fractional mode */
	175	if (fract_shift == 0) {
	176	fract_shift = 3;
	177	goto again;
	178	}
0e646c52 LPC	179	}
0e646c52 LPC	180
86378cf6 LPC	181	struct axi_clkgen_div_params {
	182	unsigned int low;
	183	unsigned int high;
	184	unsigned int edge;
	185	unsigned int nocount;
	186	unsigned int frac_en;
	187	unsigned int frac;
	188	unsigned int frac_wf_f;
	189	unsigned int frac_wf_r;
	190	unsigned int frac_phase;
	191	};
	192
	193	static void axi_clkgen_calc_clk_params(unsigned int divider,
	194	unsigned int frac_divider, struct axi_clkgen_div_params *params)
0e646c52	195	{
0e646c52	196
86378cf6 LPC	197	memset(params, 0x0, sizeof(*params));
	198
	199	if (divider == 1) {
	200	params->nocount = 1;
	201	return;
	202	}
	203
	204	if (frac_divider == 0) {
	205	params->high = divider / 2;
	206	params->edge = divider % 2;
	207	params->low = divider - params->high;
	208	} else {
	209	params->frac_en = 1;
	210	params->frac = frac_divider;
	211
	212	params->high = divider / 2;
	213	params->edge = divider % 2;
	214	params->low = params->high;
	215
	216	if (params->edge == 0) {
	217	params->high--;
	218	params->frac_wf_r = 1;
	219	}
	220
	221	if (params->edge == 0 \|\| frac_divider == 1)
	222	params->low--;
	223	if (((params->edge == 0) ^ (frac_divider == 1)) \|\|
	224	(divider == 2 && frac_divider == 1))
	225	params->frac_wf_f = 1;
	226
	227	params->frac_phase = params->edge * 4 + frac_divider / 2;
	228	}
0e646c52 LPC	229	}
	230
	231	static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
	232	unsigned int reg, unsigned int val)
	233	{
	234	writel(val, axi_clkgen->base + reg);
	235	}
	236
	237	static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
	238	unsigned int reg, unsigned int *val)
	239	{
	240	*val = readl(axi_clkgen->base + reg);
	241	}
	242
1887c3a6 LPC	243	static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
	244	{
	245	unsigned int timeout = 10000;
	246	unsigned int val;
	247
	248	do {
	249	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
	250	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
	251
	252	if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
	253	return -EIO;
	254
	255	return val & 0xffff;
	256	}
	257
d95b599c	258	static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
1887c3a6 LPC	259	unsigned int reg, unsigned int *val)
	260	{
	261	unsigned int reg_val;
	262	int ret;
	263
	264	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	265	if (ret < 0)
	266	return ret;
	267
	268	reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL \| AXI_CLKGEN_V2_DRP_CNTRL_READ;
	269	reg_val \|= (reg << 16);
	270
	271	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
	272
	273	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	274	if (ret < 0)
	275	return ret;
	276
	277	*val = ret;
	278
	279	return 0;
	280	}
	281
d95b599c	282	static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
1887c3a6 LPC	283	unsigned int reg, unsigned int val, unsigned int mask)
	284	{
	285	unsigned int reg_val = 0;
	286	int ret;
	287
	288	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	289	if (ret < 0)
	290	return ret;
	291
	292	if (mask != 0xffff) {
d95b599c	293	axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
1887c3a6 LPC	294	reg_val &= ~mask;
	295	}
	296
	297	reg_val \|= AXI_CLKGEN_V2_DRP_CNTRL_SEL \| (reg << 16) \| (val & mask);
	298
	299	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
	300
	301	return 0;
	302	}
	303
d95b599c	304	static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
1887c3a6 LPC	305	bool enable)
	306	{
	307	unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
	308
	309	if (enable)
	310	val \|= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
	311
	312	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
	313	}
	314
0e646c52 LPC	315	static struct axi_clkgen clk_hw_to_axi_clkgen(struct clk_hw clk_hw)
	316	{
	317	return container_of(clk_hw, struct axi_clkgen, clk_hw);
	318	}
	319
86378cf6 LPC	320	static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
	321	unsigned int reg1, unsigned int reg2, unsigned int reg3,
	322	struct axi_clkgen_div_params *params)
	323	{
	324	axi_clkgen_mmcm_write(axi_clkgen, reg1,
	325	(params->high << 6) \| params->low, 0xefff);
	326	axi_clkgen_mmcm_write(axi_clkgen, reg2,
	327	(params->frac << 12) \| (params->frac_en << 11) \|
	328	(params->frac_wf_r << 10) \| (params->edge << 7) \|
	329	(params->nocount << 6), 0x7fff);
	330	if (reg3 != 0) {
	331	axi_clkgen_mmcm_write(axi_clkgen, reg3,
	332	(params->frac_phase << 11) \| (params->frac_wf_f << 10), 0x3c00);
	333	}
	334	}
	335
0e646c52 LPC	336	static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
	337	unsigned long rate, unsigned long parent_rate)
	338	{
	339	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
ac1ee86a	340	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
0e646c52	341	unsigned int d, m, dout;
86378cf6	342	struct axi_clkgen_div_params params;
a3947209	343	uint32_t power = 0;
0e646c52 LPC	344	uint32_t filter;
	345	uint32_t lock;
	346
	347	if (parent_rate == 0 \|\| rate == 0)
	348	return -EINVAL;
	349
ac1ee86a	350	axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);
0e646c52 LPC	351
	352	if (d == 0 \|\| dout == 0 \|\| m == 0)
	353	return -EINVAL;
	354
a3947209 LPC	355	if ((dout & 0x7) != 0 \|\| (m & 0x7) != 0)
	356	power \|= 0x9800;
	357
	358	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
	359
0e646c52 LPC	360	filter = axi_clkgen_lookup_filter(m - 1);
	361	lock = axi_clkgen_lookup_lock(m - 1);
	362
86378cf6 LPC	363	axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
	364	axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
	365	MMCM_REG_CLKOUT5_2, &params);
0e646c52	366
86378cf6	367	axi_clkgen_calc_clk_params(d, 0, &params);
1887c3a6	368	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
86378cf6 LPC	369	(params.edge << 13) \| (params.nocount << 12) \|
86378cf6 LPC	370	(params.high << 6) \| params.low, 0x3fff);
0e646c52	371
86378cf6 LPC	372	axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
	373	axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
	374	MMCM_REG_CLKOUT6_2, &params);
1887c3a6 LPC	375
	376	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
	377	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
	378	(((lock >> 16) & 0x1f) << 10) \| 0x1, 0x7fff);
	379	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
	380	(((lock >> 24) & 0x1f) << 10) \| 0x3e9, 0x7fff);
	381	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
	382	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
0e646c52 LPC	383
	384	return 0;
	385	}
	386
	387	static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
	388	unsigned long *parent_rate)
	389	{
ac1ee86a AA	390	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw);
ac1ee86a AA	391	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
0e646c52	392	unsigned int d, m, dout;
448c3c05	393	unsigned long long tmp;
0e646c52	394
ac1ee86a	395	axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout);
0e646c52 LPC	396
	397	if (d == 0 \|\| dout == 0 \|\| m == 0)
	398	return -EINVAL;
	399
448c3c05 LPC	400	tmp = (unsigned long long)parent_rate m;
	401	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
	402
	403	return min_t(unsigned long long, tmp, LONG_MAX);
0e646c52 LPC	404	}
0e646c52 LPC	405
86378cf6 LPC	406	static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
	407	unsigned int reg1, unsigned int reg2)
	408	{
	409	unsigned int val1, val2;
	410	unsigned int div;
	411
	412	axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
	413	if (val2 & MMCM_CLKOUT_NOCOUNT)
	414	return 8;
	415
	416	axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
	417
	418	div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
	419	div <<= 3;
	420
	421	if (val2 & MMCM_CLK_DIV_DIVIDE) {
	422	if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
	423	div += 8;
	424	else
	425	div += 16;
	426
	427	div += (val2 >> 12) & 0x7;
	428	}
	429
	430	return div;
	431	}
	432
0e646c52 LPC	433	static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
	434	unsigned long parent_rate)
	435	{
	436	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	437	unsigned int d, m, dout;
0e646c52	438	unsigned long long tmp;
86378cf6	439	unsigned int val;
0e646c52	440
86378cf6 LPC	441	dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
	442	MMCM_REG_CLKOUT0_2);
	443	m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
	444	MMCM_REG_CLK_FB2);
063578dc	445
86378cf6 LPC	446	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
86378cf6 LPC	447	if (val & MMCM_CLK_DIV_NOCOUNT)
063578dc LPC	448	d = 1;
063578dc LPC	449	else
86378cf6	450	d = (val & 0x3f) + ((val >> 6) & 0x3f);
0e646c52 LPC	451
	452	if (d == 0 \|\| dout == 0)
	453	return 0;
	454
448c3c05 LPC	455	tmp = (unsigned long long)parent_rate * m;
448c3c05 LPC	456	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
0e646c52	457
3d6f1c72	458	return min_t(unsigned long long, tmp, ULONG_MAX);
0e646c52 LPC	459	}
0e646c52 LPC	460
1887c3a6 LPC	461	static int axi_clkgen_enable(struct clk_hw *clk_hw)
	462	{
	463	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	464
	465	axi_clkgen_mmcm_enable(axi_clkgen, true);
	466
	467	return 0;
	468	}
	469
	470	static void axi_clkgen_disable(struct clk_hw *clk_hw)
	471	{
	472	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	473
	474	axi_clkgen_mmcm_enable(axi_clkgen, false);
	475	}
	476
62d1e782 LPC	477	static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
	478	{
	479	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	480
	481	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
	482
	483	return 0;
	484	}
	485
	486	static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
	487	{
	488	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	489	unsigned int parent;
	490
	491	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
	492
	493	return parent;
	494	}
	495
0e646c52 LPC	496	static const struct clk_ops axi_clkgen_ops = {
	497	.recalc_rate = axi_clkgen_recalc_rate,
	498	.round_rate = axi_clkgen_round_rate,
	499	.set_rate = axi_clkgen_set_rate,
1887c3a6 LPC	500	.enable = axi_clkgen_enable,
1887c3a6 LPC	501	.disable = axi_clkgen_disable,
62d1e782 LPC	502	.set_parent = axi_clkgen_set_parent,
62d1e782 LPC	503	.get_parent = axi_clkgen_get_parent,
0e646c52 LPC	504	};
	505
	506	static int axi_clkgen_probe(struct platform_device *pdev)
	507	{
ac1ee86a	508	const struct axi_clkgen_limits *dflt_limits;
0e646c52 LPC	509	struct axi_clkgen *axi_clkgen;
0e646c52 LPC	510	struct clk_init_data init;
62d1e782	511	const char *parent_names[2];
0e646c52	512	const char *clk_name;
62d1e782	513	unsigned int i;
e0d30bb9	514	int ret;
0e646c52	515
ac1ee86a AA	516	dflt_limits = device_get_match_data(&pdev->dev);
ac1ee86a AA	517	if (!dflt_limits)
1887c3a6 LPC	518	return -ENODEV;
1887c3a6 LPC	519
0e646c52 LPC	520	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
	521	if (!axi_clkgen)
	522	return -ENOMEM;
	523
6ba7ea76	524	axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);
0e646c52 LPC	525	if (IS_ERR(axi_clkgen->base))
	526	return PTR_ERR(axi_clkgen->base);
	527
62d1e782 LPC	528	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
62d1e782 LPC	529	if (init.num_parents < 1 \|\| init.num_parents > 2)
0e646c52 LPC	530	return -EINVAL;
0e646c52 LPC	531
62d1e782 LPC	532	for (i = 0; i < init.num_parents; i++) {
	533	parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
	534	if (!parent_names[i])
	535	return -EINVAL;
	536	}
	537
ac1ee86a AA	538	memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits));
ac1ee86a AA	539
0e646c52 LPC	540	clk_name = pdev->dev.of_node->name;
	541	of_property_read_string(pdev->dev.of_node, "clock-output-names",
	542	&clk_name);
	543
	544	init.name = clk_name;
	545	init.ops = &axi_clkgen_ops;
62d1e782 LPC	546	init.flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE;
62d1e782 LPC	547	init.parent_names = parent_names;
0e646c52	548
1887c3a6 LPC	549	axi_clkgen_mmcm_enable(axi_clkgen, false);
1887c3a6 LPC	550
0e646c52	551	axi_clkgen->clk_hw.init = &init;
e0d30bb9 SB	552	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
	553	if (ret)
	554	return ret;
0e646c52	555
e0d30bb9 SB	556	return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
e0d30bb9 SB	557	&axi_clkgen->clk_hw);
0e646c52 LPC	558	}
	559
	560	static int axi_clkgen_remove(struct platform_device *pdev)
	561	{
	562	of_clk_del_provider(pdev->dev.of_node);
	563
	564	return 0;
	565	}
	566
16214f97	567	static const struct of_device_id axi_clkgen_ids[] = {
da68c309 AA	568	{
	569	.compatible = "adi,zynqmp-axi-clkgen-2.00.a",
	570	.data = &axi_clkgen_zynqmp_default_limits,
	571	},
16214f97 AA	572	{
	573	.compatible = "adi,axi-clkgen-2.00.a",
	574	.data = &axi_clkgen_zynq_default_limits,
	575	},
	576	{ }
	577	};
	578	MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
	579
0e646c52 LPC	580	static struct platform_driver axi_clkgen_driver = {
	581	.driver = {
	582	.name = "adi-axi-clkgen",
0e646c52 LPC	583	.of_match_table = axi_clkgen_ids,
	584	},
	585	.probe = axi_clkgen_probe,
	586	.remove = axi_clkgen_remove,
	587	};
	588	module_platform_driver(axi_clkgen_driver);
	589
	590	MODULE_LICENSE("GPL v2");
	591	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
	592	MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");