[linux-2.6-block.git] / drivers / clk / clk-aspeed.c

// SPDX-License-Identifier: GPL-2.0+

#define pr_fmt(fmt) "clk-aspeed: " fmt

#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <dt-bindings/clock/aspeed-clock.h>

#define ASPEED_NUM_CLKS		35

#define ASPEED_RESET_CTRL	0x04
#define ASPEED_CLK_SELECTION	0x08
#define ASPEED_CLK_STOP_CTRL	0x0c
#define ASPEED_MPLL_PARAM	0x20
#define ASPEED_HPLL_PARAM	0x24
#define  AST2500_HPLL_BYPASS_EN	BIT(20)
#define  AST2400_HPLL_STRAPPED	BIT(18)
#define  AST2400_HPLL_BYPASS_EN	BIT(17)
#define ASPEED_MISC_CTRL	0x2c
#define  UART_DIV13_EN		BIT(12)
#define ASPEED_STRAP		0x70
#define  CLKIN_25MHZ_EN		BIT(23)
#define  AST2400_CLK_SOURCE_SEL	BIT(18)
#define ASPEED_CLK_SELECTION_2	0xd8

/* Globally visible clocks */
static DEFINE_SPINLOCK(aspeed_clk_lock);

/* Keeps track of all clocks */
static struct clk_hw_onecell_data *aspeed_clk_data;

static void __iomem *scu_base;

/**
 * struct aspeed_gate_data - Aspeed gated clocks
 * @clock_idx: bit used to gate this clock in the clock register
 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
 *             reset is required when enabling the clock
 * @name: the clock name
 * @parent_name: the name of the parent clock
 * @flags: standard clock framework flags
 */
struct aspeed_gate_data {
	u8		clock_idx;
	s8		reset_idx;
	const char	*name;
	const char	*parent_name;
	unsigned long	flags;
};

/**
 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
 * @hw:		handle between common and hardware-specific interfaces
 * @reg:	register controlling gate
 * @clock_idx:	bit used to gate this clock in the clock register
 * @reset_idx:	bit used to reset this IP in the reset register. -1 if no
 *		reset is required when enabling the clock
 * @flags:	hardware-specific flags
 * @lock:	register lock
 *
 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
 * This modified version of clk_gate allows an optional reset bit to be
 * specified.
 */
struct aspeed_clk_gate {
	struct clk_hw	hw;
	struct regmap	*map;
	u8		clock_idx;
	s8		reset_idx;
	u8		flags;
	spinlock_t	*lock;
};

#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)

/* TODO: ask Aspeed about the actual parent data */
static const struct aspeed_gate_data aspeed_gates[] = {
	/*				 clk rst   name			parent	flags */
	[ASPEED_CLK_GATE_ECLK] =	{  0, -1, "eclk-gate",		"eclk",	0 }, /* Video Engine */
	[ASPEED_CLK_GATE_GCLK] =	{  1,  7, "gclk-gate",		NULL,	0 }, /* 2D engine */
	[ASPEED_CLK_GATE_MCLK] =	{  2, -1, "mclk-gate",		"mpll",	CLK_IS_CRITICAL }, /* SDRAM */
	[ASPEED_CLK_GATE_VCLK] =	{  3,  6, "vclk-gate",		NULL,	0 }, /* Video Capture */
	[ASPEED_CLK_GATE_BCLK] =	{  4, 10, "bclk-gate",		"bclk",	0 }, /* PCIe/PCI */
	[ASPEED_CLK_GATE_DCLK] =	{  5, -1, "dclk-gate",		NULL,	0 }, /* DAC */
	[ASPEED_CLK_GATE_REFCLK] =	{  6, -1, "refclk-gate",	"clkin", CLK_IS_CRITICAL },
	[ASPEED_CLK_GATE_USBPORT2CLK] =	{  7,  3, "usb-port2-gate",	NULL,	0 }, /* USB2.0 Host port 2 */
	[ASPEED_CLK_GATE_LCLK] =	{  8,  5, "lclk-gate",		NULL,	0 }, /* LPC */
	[ASPEED_CLK_GATE_USBUHCICLK] =	{  9, 15, "usb-uhci-gate",	NULL,	0 }, /* USB1.1 (requires port 2 enabled) */
	[ASPEED_CLK_GATE_D1CLK] =	{ 10, 13, "d1clk-gate",		NULL,	0 }, /* GFX CRT */
	[ASPEED_CLK_GATE_YCLK] =	{ 13,  4, "yclk-gate",		NULL,	0 }, /* HAC */
	[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate",	NULL,	0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
	[ASPEED_CLK_GATE_UART1CLK] =	{ 15, -1, "uart1clk-gate",	"uart",	0 }, /* UART1 */
	[ASPEED_CLK_GATE_UART2CLK] =	{ 16, -1, "uart2clk-gate",	"uart",	0 }, /* UART2 */
	[ASPEED_CLK_GATE_UART5CLK] =	{ 17, -1, "uart5clk-gate",	"uart",	0 }, /* UART5 */
	[ASPEED_CLK_GATE_ESPICLK] =	{ 19, -1, "espiclk-gate",	NULL,	0 }, /* eSPI */
	[ASPEED_CLK_GATE_MAC1CLK] =	{ 20, 11, "mac1clk-gate",	"mac",	0 }, /* MAC1 */
	[ASPEED_CLK_GATE_MAC2CLK] =	{ 21, 12, "mac2clk-gate",	"mac",	0 }, /* MAC2 */
	[ASPEED_CLK_GATE_RSACLK] =	{ 24, -1, "rsaclk-gate",	NULL,	0 }, /* RSA */
	[ASPEED_CLK_GATE_UART3CLK] =	{ 25, -1, "uart3clk-gate",	"uart",	0 }, /* UART3 */
	[ASPEED_CLK_GATE_UART4CLK] =	{ 26, -1, "uart4clk-gate",	"uart",	0 }, /* UART4 */
	[ASPEED_CLK_GATE_SDCLKCLK] =	{ 27, 16, "sdclk-gate",		NULL,	0 }, /* SDIO/SD */
	[ASPEED_CLK_GATE_LHCCLK] =	{ 28, -1, "lhclk-gate",		"lhclk", 0 }, /* LPC master/LPC+ */
};

static const struct clk_div_table ast2500_mac_div_table[] = {
	{ 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
	{ 0x1, 4 },
	{ 0x2, 6 },
	{ 0x3, 8 },
	{ 0x4, 10 },
	{ 0x5, 12 },
	{ 0x6, 14 },
	{ 0x7, 16 },
	{ 0 }
};

static const struct clk_div_table ast2400_div_table[] = {
	{ 0x0, 2 },
	{ 0x1, 4 },
	{ 0x2, 6 },
	{ 0x3, 8 },
	{ 0x4, 10 },
	{ 0x5, 12 },
	{ 0x6, 14 },
	{ 0x7, 16 },
	{ 0 }
};

static const struct clk_div_table ast2500_div_table[] = {
	{ 0x0, 4 },
	{ 0x1, 8 },
	{ 0x2, 12 },
	{ 0x3, 16 },
	{ 0x4, 20 },
	{ 0x5, 24 },
	{ 0x6, 28 },
	{ 0x7, 32 },
	{ 0 }
};

static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
{
	unsigned int mult, div;

	if (val & AST2400_HPLL_BYPASS_EN) {
		/* Pass through mode */
		mult = div = 1;
	} else {
		/* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
		u32 n = (val >> 5) & 0x3f;
		u32 od = (val >> 4) & 0x1;
		u32 d = val & 0xf;

		mult = (2 - od) * (n + 2);
		div = d + 1;
	}
	return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
			mult, div);
};

static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
{
	unsigned int mult, div;

	if (val & AST2500_HPLL_BYPASS_EN) {
		/* Pass through mode */
		mult = div = 1;
	} else {
		/* F = clkin * [(M+1) / (N+1)] / (P + 1) */
		u32 p = (val >> 13) & 0x3f;
		u32 m = (val >> 5) & 0xff;
		u32 n = val & 0x1f;

		mult = (m + 1) / (n + 1);
		div = p + 1;
	}

	return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
			mult, div);
}

struct aspeed_clk_soc_data {
	const struct clk_div_table *div_table;
	const struct clk_div_table *mac_div_table;
	struct clk_hw *(*calc_pll)(const char *name, u32 val);
};

static const struct aspeed_clk_soc_data ast2500_data = {
	.div_table = ast2500_div_table,
	.mac_div_table = ast2500_mac_div_table,
	.calc_pll = aspeed_ast2500_calc_pll,
};

static const struct aspeed_clk_soc_data ast2400_data = {
	.div_table = ast2400_div_table,
	.mac_div_table = ast2400_div_table,
	.calc_pll = aspeed_ast2400_calc_pll,
};

static int aspeed_clk_probe(struct platform_device *pdev)
{
	const struct aspeed_clk_soc_data *soc_data;
	struct device *dev = &pdev->dev;
	struct regmap *map;
	struct clk_hw *hw;
	u32 val, rate;

	map = syscon_node_to_regmap(dev->of_node);
	if (IS_ERR(map)) {
		dev_err(dev, "no syscon regmap\n");
		return PTR_ERR(map);
	}

	/* SoC generations share common layouts but have different divisors */
	soc_data = of_device_get_match_data(dev);
	if (!soc_data) {
		dev_err(dev, "no match data for platform\n");
		return -EINVAL;
	}

	/* UART clock div13 setting */
	regmap_read(map, ASPEED_MISC_CTRL, &val);
	if (val & UART_DIV13_EN)
		rate = 24000000 / 13;
	else
		rate = 24000000;
	/* TODO: Find the parent data for the uart clock */
	hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
	if (IS_ERR(hw))
		return PTR_ERR(hw);
	aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;

	/*
	 * Memory controller (M-PLL) PLL. This clock is configured by the
	 * bootloader, and is exposed to Linux as a read-only clock rate.
	 */
	regmap_read(map, ASPEED_MPLL_PARAM, &val);
	hw = soc_data->calc_pll("mpll", val);
	if (IS_ERR(hw))
		return PTR_ERR(hw);
	aspeed_clk_data->hws[ASPEED_CLK_MPLL] =	hw;

	/* SD/SDIO clock divider (TODO: There's a gate too) */
	hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0,
			scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
			soc_data->div_table,
			&aspeed_clk_lock);
	if (IS_ERR(hw))
		return PTR_ERR(hw);
	aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;

	/* MAC AHB bus clock divider */
	hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
			scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
			soc_data->mac_div_table,
			&aspeed_clk_lock);
	if (IS_ERR(hw))
		return PTR_ERR(hw);
	aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;

	/* LPC Host (LHCLK) clock divider */
	hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
			scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
			soc_data->div_table,
			&aspeed_clk_lock);
	if (IS_ERR(hw))
		return PTR_ERR(hw);
	aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;

	/* P-Bus (BCLK) clock divider */
	hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
			scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
			soc_data->div_table,
			&aspeed_clk_lock);
	if (IS_ERR(hw))
		return PTR_ERR(hw);
	aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;

	return 0;
};

static const struct of_device_id aspeed_clk_dt_ids[] = {
	{ .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
	{ .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
	{ }
};

static struct platform_driver aspeed_clk_driver = {
	.probe  = aspeed_clk_probe,
	.driver = {
		.name = "aspeed-clk",
		.of_match_table = aspeed_clk_dt_ids,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(aspeed_clk_driver);

static void __init aspeed_ast2400_cc(struct regmap *map)
{
	struct clk_hw *hw;
	u32 val, freq, div;

	/*
	 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
	 * strapping
	 */
	regmap_read(map, ASPEED_STRAP, &val);
	if (val & CLKIN_25MHZ_EN)
		freq = 25000000;
	else if (val & AST2400_CLK_SOURCE_SEL)
		freq = 48000000;
	else
		freq = 24000000;
	hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
	pr_debug("clkin @%u MHz\n", freq / 1000000);

	/*
	 * High-speed PLL clock derived from the crystal. This the CPU clock,
	 * and we assume that it is enabled
	 */
	regmap_read(map, ASPEED_HPLL_PARAM, &val);
	WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured");
	aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val);

	/*
	 * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
	 *   00: Select CPU:AHB = 1:1
	 *   01: Select CPU:AHB = 2:1
	 *   10: Select CPU:AHB = 4:1
	 *   11: Select CPU:AHB = 3:1
	 */
	regmap_read(map, ASPEED_STRAP, &val);
	val = (val >> 10) & 0x3;
	div = val + 1;
	if (div == 3)
		div = 4;
	else if (div == 4)
		div = 3;
	hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
	aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;

	/* APB clock clock selection register SCU08 (aka PCLK) */
	hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
			scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
			ast2400_div_table,
			&aspeed_clk_lock);
	aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
}

static void __init aspeed_ast2500_cc(struct regmap *map)
{
	struct clk_hw *hw;
	u32 val, freq, div;

	/* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
	regmap_read(map, ASPEED_STRAP, &val);
	if (val & CLKIN_25MHZ_EN)
		freq = 25000000;
	else
		freq = 24000000;
	hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
	pr_debug("clkin @%u MHz\n", freq / 1000000);

	/*
	 * High-speed PLL clock derived from the crystal. This the CPU clock,
	 * and we assume that it is enabled
	 */
	regmap_read(map, ASPEED_HPLL_PARAM, &val);
	aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);

	/* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
	regmap_read(map, ASPEED_STRAP, &val);
	val = (val >> 9) & 0x7;
	WARN(val == 0, "strapping is zero: cannot determine ahb clock");
	div = 2 * (val + 1);
	hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
	aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;

	/* APB clock clock selection register SCU08 (aka PCLK) */
	regmap_read(map, ASPEED_CLK_SELECTION, &val);
	val = (val >> 23) & 0x7;
	div = 4 * (val + 1);
	hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
	aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
};

static void __init aspeed_cc_init(struct device_node *np)
{
	struct regmap *map;
	u32 val;
	int ret;
	int i;

	scu_base = of_iomap(np, 0);
	if (IS_ERR(scu_base))
		return;

	aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) +
			sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS,
			GFP_KERNEL);
	if (!aspeed_clk_data)
		return;

	/*
	 * This way all clocks fetched before the platform device probes,
	 * except those we assign here for early use, will be deferred.
	 */
	for (i = 0; i < ASPEED_NUM_CLKS; i++)
		aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);

	map = syscon_node_to_regmap(np);
	if (IS_ERR(map)) {
		pr_err("no syscon regmap\n");
		return;
	}
	/*
	 * We check that the regmap works on this very first access,
	 * but as this is an MMIO-backed regmap, subsequent regmap
	 * access is not going to fail and we skip error checks from
	 * this point.
	 */
	ret = regmap_read(map, ASPEED_STRAP, &val);
	if (ret) {
		pr_err("failed to read strapping register\n");
		return;
	}

	if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
		aspeed_ast2400_cc(map);
	else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
		aspeed_ast2500_cc(map);
	else
		pr_err("unknown platform, failed to add clocks\n");

	aspeed_clk_data->num = ASPEED_NUM_CLKS;
	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
	if (ret)
		pr_err("failed to add DT provider: %d\n", ret);
};
CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
Commit	Line	Data
5eda5d79 JS	1	// SPDX-License-Identifier: GPL-2.0+
	2
	3	#define pr_fmt(fmt) "clk-aspeed: " fmt
	4
	5	#include <linux/clk-provider.h>
	6	#include <linux/mfd/syscon.h>
	7	#include <linux/of_address.h>
98f3118d JS	8	#include <linux/of_device.h>
98f3118d JS	9	#include <linux/platform_device.h>
5eda5d79 JS	10	#include <linux/regmap.h>
	11	#include <linux/slab.h>
	12	#include <linux/spinlock.h>
	13
	14	#include <dt-bindings/clock/aspeed-clock.h>
	15
	16	#define ASPEED_NUM_CLKS 35
	17
99d01e0e JS	18	#define ASPEED_RESET_CTRL 0x04
	19	#define ASPEED_CLK_SELECTION 0x08
	20	#define ASPEED_CLK_STOP_CTRL 0x0c
	21	#define ASPEED_MPLL_PARAM 0x20
	22	#define ASPEED_HPLL_PARAM 0x24
	23	#define AST2500_HPLL_BYPASS_EN BIT(20)
	24	#define AST2400_HPLL_STRAPPED BIT(18)
	25	#define AST2400_HPLL_BYPASS_EN BIT(17)
	26	#define ASPEED_MISC_CTRL 0x2c
	27	#define UART_DIV13_EN BIT(12)
5eda5d79	28	#define ASPEED_STRAP 0x70
99d01e0e JS	29	#define CLKIN_25MHZ_EN BIT(23)
	30	#define AST2400_CLK_SOURCE_SEL BIT(18)
	31	#define ASPEED_CLK_SELECTION_2 0xd8
	32
	33	/* Globally visible clocks */
	34	static DEFINE_SPINLOCK(aspeed_clk_lock);
5eda5d79 JS	35
	36	/* Keeps track of all clocks */
	37	static struct clk_hw_onecell_data *aspeed_clk_data;
	38
	39	static void __iomem *scu_base;
	40
	41	/**
	42	* struct aspeed_gate_data - Aspeed gated clocks
	43	* @clock_idx: bit used to gate this clock in the clock register
	44	* @reset_idx: bit used to reset this IP in the reset register. -1 if no
	45	* reset is required when enabling the clock
	46	* @name: the clock name
	47	* @parent_name: the name of the parent clock
	48	* @flags: standard clock framework flags
	49	*/
	50	struct aspeed_gate_data {
	51	u8 clock_idx;
	52	s8 reset_idx;
	53	const char *name;
	54	const char *parent_name;
	55	unsigned long flags;
	56	};
	57
	58	/**
	59	* struct aspeed_clk_gate - Aspeed specific clk_gate structure
	60	* @hw: handle between common and hardware-specific interfaces
	61	* @reg: register controlling gate
	62	* @clock_idx: bit used to gate this clock in the clock register
	63	* @reset_idx: bit used to reset this IP in the reset register. -1 if no
	64	* reset is required when enabling the clock
	65	* @flags: hardware-specific flags
	66	* @lock: register lock
	67	*
	68	* Some of the clocks in the Aspeed SoC must be put in reset before enabling.
	69	* This modified version of clk_gate allows an optional reset bit to be
	70	* specified.
	71	*/
	72	struct aspeed_clk_gate {
	73	struct clk_hw hw;
	74	struct regmap *map;
	75	u8 clock_idx;
	76	s8 reset_idx;
	77	u8 flags;
	78	spinlock_t *lock;
	79	};
	80
	81	#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
	82
	83	/* TODO: ask Aspeed about the actual parent data */
	84	static const struct aspeed_gate_data aspeed_gates[] = {
	85	/* clk rst name parent flags */
	86	[ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
	87	[ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
	88	[ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
	89	[ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
	90	[ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
	91	[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */
	92	[ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
	93	[ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
	94	[ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
	95	[ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
	96	[ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
	97	[ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
	98	[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
99	[ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
100	[ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
101	[ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
102	[ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
103	[ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
104	[ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
105	[ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
106	[ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
107	[ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
108	[ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
109	[ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
110	};
111
98f3118d JS	112	static const struct clk_div_table ast2500_mac_div_table[] = {
	113	{ 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
	114	{ 0x1, 4 },
	115	{ 0x2, 6 },
	116	{ 0x3, 8 },
	117	{ 0x4, 10 },
	118	{ 0x5, 12 },
	119	{ 0x6, 14 },
	120	{ 0x7, 16 },
	121	{ 0 }
	122	};
	123
99d01e0e JS	124	static const struct clk_div_table ast2400_div_table[] = {
	125	{ 0x0, 2 },
	126	{ 0x1, 4 },
	127	{ 0x2, 6 },
	128	{ 0x3, 8 },
	129	{ 0x4, 10 },
	130	{ 0x5, 12 },
	131	{ 0x6, 14 },
	132	{ 0x7, 16 },
	133	{ 0 }
	134	};
	135
	136	static const struct clk_div_table ast2500_div_table[] = {
	137	{ 0x0, 4 },
	138	{ 0x1, 8 },
	139	{ 0x2, 12 },
	140	{ 0x3, 16 },
	141	{ 0x4, 20 },
	142	{ 0x5, 24 },
	143	{ 0x6, 28 },
	144	{ 0x7, 32 },
	145	{ 0 }
	146	};
	147
	148	static struct clk_hw aspeed_ast2400_calc_pll(const char name, u32 val)
	149	{
	150	unsigned int mult, div;
	151
	152	if (val & AST2400_HPLL_BYPASS_EN) {
	153	/* Pass through mode */
	154	mult = div = 1;
	155	} else {
	156	/* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
	157	u32 n = (val >> 5) & 0x3f;
	158	u32 od = (val >> 4) & 0x1;
	159	u32 d = val & 0xf;
	160
	161	mult = (2 - od) * (n + 2);
	162	div = d + 1;
	163	}
	164	return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
	165	mult, div);
	166	};
	167
	168	static struct clk_hw aspeed_ast2500_calc_pll(const char name, u32 val)
	169	{
	170	unsigned int mult, div;
	171
	172	if (val & AST2500_HPLL_BYPASS_EN) {
	173	/* Pass through mode */
	174	mult = div = 1;
	175	} else {
	176	/* F = clkin * [(M+1) / (N+1)] / (P + 1) */
	177	u32 p = (val >> 13) & 0x3f;
	178	u32 m = (val >> 5) & 0xff;
	179	u32 n = val & 0x1f;
	180
	181	mult = (m + 1) / (n + 1);
	182	div = p + 1;
	183	}
	184
	185	return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
	186	mult, div);
	187	}
188
98f3118d JS	189	struct aspeed_clk_soc_data {
	190	const struct clk_div_table *div_table;
	191	const struct clk_div_table *mac_div_table;
	192	struct clk_hw (calc_pll)(const char *name, u32 val);
	193	};
	194
	195	static const struct aspeed_clk_soc_data ast2500_data = {
	196	.div_table = ast2500_div_table,
	197	.mac_div_table = ast2500_mac_div_table,
	198	.calc_pll = aspeed_ast2500_calc_pll,
	199	};
	200
	201	static const struct aspeed_clk_soc_data ast2400_data = {
	202	.div_table = ast2400_div_table,
	203	.mac_div_table = ast2400_div_table,
	204	.calc_pll = aspeed_ast2400_calc_pll,
	205	};
	206
	207	static int aspeed_clk_probe(struct platform_device *pdev)
	208	{
	209	const struct aspeed_clk_soc_data *soc_data;
	210	struct device *dev = &pdev->dev;
	211	struct regmap *map;
	212	struct clk_hw *hw;
	213	u32 val, rate;
	214
	215	map = syscon_node_to_regmap(dev->of_node);
	216	if (IS_ERR(map)) {
	217	dev_err(dev, "no syscon regmap\n");
	218	return PTR_ERR(map);
	219	}
	220
	221	/* SoC generations share common layouts but have different divisors */
	222	soc_data = of_device_get_match_data(dev);
	223	if (!soc_data) {
	224	dev_err(dev, "no match data for platform\n");
	225	return -EINVAL;
	226	}
	227
	228	/* UART clock div13 setting */
	229	regmap_read(map, ASPEED_MISC_CTRL, &val);
	230	if (val & UART_DIV13_EN)
	231	rate = 24000000 / 13;
	232	else
	233	rate = 24000000;
	234	/* TODO: Find the parent data for the uart clock */
	235	hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
	236	if (IS_ERR(hw))
	237	return PTR_ERR(hw);
	238	aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;
	239
	240	/*
	241	* Memory controller (M-PLL) PLL. This clock is configured by the
	242	* bootloader, and is exposed to Linux as a read-only clock rate.
	243	*/
	244	regmap_read(map, ASPEED_MPLL_PARAM, &val);
	245	hw = soc_data->calc_pll("mpll", val);
	246	if (IS_ERR(hw))
	247	return PTR_ERR(hw);
	248	aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
	249
	250	/* SD/SDIO clock divider (TODO: There's a gate too) */
	251	hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0,
	252	scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
253	soc_data->div_table,
254	&aspeed_clk_lock);
255	if (IS_ERR(hw))
256	return PTR_ERR(hw);
257	aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;
258
259	/* MAC AHB bus clock divider */
260	hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
261	scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
262	soc_data->mac_div_table,
263	&aspeed_clk_lock);
264	if (IS_ERR(hw))
265	return PTR_ERR(hw);
266	aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
267
268	/* LPC Host (LHCLK) clock divider */
269	hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
270	scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
271	soc_data->div_table,
272	&aspeed_clk_lock);
273	if (IS_ERR(hw))
274	return PTR_ERR(hw);
275	aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
276
277	/* P-Bus (BCLK) clock divider */
278	hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
279	scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
280	soc_data->div_table,
281	&aspeed_clk_lock);
282	if (IS_ERR(hw))
283	return PTR_ERR(hw);
284	aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
285
286	return 0;
287	};
288
289	static const struct of_device_id aspeed_clk_dt_ids[] = {
290	{ .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
291	{ .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
292	{ }
293	};
294
295	static struct platform_driver aspeed_clk_driver = {
296	.probe = aspeed_clk_probe,
297	.driver = {
298	.name = "aspeed-clk",
299	.of_match_table = aspeed_clk_dt_ids,
300	.suppress_bind_attrs = true,
301	},
302	};
303	builtin_platform_driver(aspeed_clk_driver);
304
99d01e0e JS	305	static void __init aspeed_ast2400_cc(struct regmap *map)
	306	{
	307	struct clk_hw *hw;
	308	u32 val, freq, div;
	309
	310	/*
	311	* CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
	312	* strapping
	313	*/
	314	regmap_read(map, ASPEED_STRAP, &val);
	315	if (val & CLKIN_25MHZ_EN)
	316	freq = 25000000;
	317	else if (val & AST2400_CLK_SOURCE_SEL)
	318	freq = 48000000;
	319	else
	320	freq = 24000000;
	321	hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
	322	pr_debug("clkin @%u MHz\n", freq / 1000000);
	323
	324	/*
	325	* High-speed PLL clock derived from the crystal. This the CPU clock,
	326	* and we assume that it is enabled
	327	*/
	328	regmap_read(map, ASPEED_HPLL_PARAM, &val);
	329	WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured");
	330	aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val);
	331
	332	/*
	333	* Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
	334	* 00: Select CPU:AHB = 1:1
	335	* 01: Select CPU:AHB = 2:1
	336	* 10: Select CPU:AHB = 4:1
	337	* 11: Select CPU:AHB = 3:1
	338	*/
	339	regmap_read(map, ASPEED_STRAP, &val);
	340	val = (val >> 10) & 0x3;
	341	div = val + 1;
	342	if (div == 3)
	343	div = 4;
	344	else if (div == 4)
	345	div = 3;
	346	hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
	347	aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
	348
	349	/* APB clock clock selection register SCU08 (aka PCLK) */
	350	hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
	351	scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
	352	ast2400_div_table,
	353	&aspeed_clk_lock);
	354	aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
	355	}
	356
	357	static void __init aspeed_ast2500_cc(struct regmap *map)
	358	{
	359	struct clk_hw *hw;
	360	u32 val, freq, div;
	361
	362	/* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
	363	regmap_read(map, ASPEED_STRAP, &val);
	364	if (val & CLKIN_25MHZ_EN)
	365	freq = 25000000;
	366	else
	367	freq = 24000000;
	368	hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
369	pr_debug("clkin @%u MHz\n", freq / 1000000);
370
371	/*
372	* High-speed PLL clock derived from the crystal. This the CPU clock,
373	* and we assume that it is enabled
374	*/
375	regmap_read(map, ASPEED_HPLL_PARAM, &val);
376	aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);
377
378	/* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
379	regmap_read(map, ASPEED_STRAP, &val);
380	val = (val >> 9) & 0x7;
381	WARN(val == 0, "strapping is zero: cannot determine ahb clock");
382	div = 2 * (val + 1);
383	hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
384	aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
385
386	/* APB clock clock selection register SCU08 (aka PCLK) */
387	regmap_read(map, ASPEED_CLK_SELECTION, &val);
388	val = (val >> 23) & 0x7;
389	div = 4 * (val + 1);
390	hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
391	aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
392	};
393
5eda5d79 JS	394	static void __init aspeed_cc_init(struct device_node *np)
	395	{
	396	struct regmap *map;
	397	u32 val;
	398	int ret;
	399	int i;
	400
	401	scu_base = of_iomap(np, 0);
	402	if (IS_ERR(scu_base))
	403	return;
	404
	405	aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) +
	406	sizeof(aspeed_clk_data->hws) ASPEED_NUM_CLKS,
	407	GFP_KERNEL);
	408	if (!aspeed_clk_data)
	409	return;
	410
	411	/*
	412	* This way all clocks fetched before the platform device probes,
	413	* except those we assign here for early use, will be deferred.
	414	*/
	415	for (i = 0; i < ASPEED_NUM_CLKS; i++)
	416	aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
	417
	418	map = syscon_node_to_regmap(np);
	419	if (IS_ERR(map)) {
	420	pr_err("no syscon regmap\n");
	421	return;
	422	}
	423	/*
	424	* We check that the regmap works on this very first access,
	425	* but as this is an MMIO-backed regmap, subsequent regmap
	426	* access is not going to fail and we skip error checks from
	427	* this point.
	428	*/
	429	ret = regmap_read(map, ASPEED_STRAP, &val);
	430	if (ret) {
	431	pr_err("failed to read strapping register\n");
	432	return;
	433	}
	434
99d01e0e JS	435	if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
	436	aspeed_ast2400_cc(map);
	437	else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
	438	aspeed_ast2500_cc(map);
	439	else
	440	pr_err("unknown platform, failed to add clocks\n");
	441
5eda5d79 JS	442	aspeed_clk_data->num = ASPEED_NUM_CLKS;
	443	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
	444	if (ret)
	445	pr_err("failed to add DT provider: %d\n", ret);
	446	};
	447	CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
	448	CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);