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5eda5d79 JS |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | ||
3 | #define pr_fmt(fmt) "clk-aspeed: " fmt | |
4 | ||
5 | #include <linux/clk-provider.h> | |
6 | #include <linux/mfd/syscon.h> | |
7 | #include <linux/of_address.h> | |
98f3118d JS |
8 | #include <linux/of_device.h> |
9 | #include <linux/platform_device.h> | |
5eda5d79 | 10 | #include <linux/regmap.h> |
f7989839 | 11 | #include <linux/reset-controller.h> |
5eda5d79 JS |
12 | #include <linux/slab.h> |
13 | #include <linux/spinlock.h> | |
14 | ||
15 | #include <dt-bindings/clock/aspeed-clock.h> | |
16 | ||
17 | #define ASPEED_NUM_CLKS 35 | |
18 | ||
99d01e0e JS |
19 | #define ASPEED_RESET_CTRL 0x04 |
20 | #define ASPEED_CLK_SELECTION 0x08 | |
21 | #define ASPEED_CLK_STOP_CTRL 0x0c | |
22 | #define ASPEED_MPLL_PARAM 0x20 | |
23 | #define ASPEED_HPLL_PARAM 0x24 | |
24 | #define AST2500_HPLL_BYPASS_EN BIT(20) | |
25 | #define AST2400_HPLL_STRAPPED BIT(18) | |
26 | #define AST2400_HPLL_BYPASS_EN BIT(17) | |
27 | #define ASPEED_MISC_CTRL 0x2c | |
28 | #define UART_DIV13_EN BIT(12) | |
5eda5d79 | 29 | #define ASPEED_STRAP 0x70 |
99d01e0e JS |
30 | #define CLKIN_25MHZ_EN BIT(23) |
31 | #define AST2400_CLK_SOURCE_SEL BIT(18) | |
32 | #define ASPEED_CLK_SELECTION_2 0xd8 | |
33 | ||
34 | /* Globally visible clocks */ | |
35 | static DEFINE_SPINLOCK(aspeed_clk_lock); | |
5eda5d79 JS |
36 | |
37 | /* Keeps track of all clocks */ | |
38 | static struct clk_hw_onecell_data *aspeed_clk_data; | |
39 | ||
40 | static void __iomem *scu_base; | |
41 | ||
42 | /** | |
43 | * struct aspeed_gate_data - Aspeed gated clocks | |
44 | * @clock_idx: bit used to gate this clock in the clock register | |
45 | * @reset_idx: bit used to reset this IP in the reset register. -1 if no | |
46 | * reset is required when enabling the clock | |
47 | * @name: the clock name | |
48 | * @parent_name: the name of the parent clock | |
49 | * @flags: standard clock framework flags | |
50 | */ | |
51 | struct aspeed_gate_data { | |
52 | u8 clock_idx; | |
53 | s8 reset_idx; | |
54 | const char *name; | |
55 | const char *parent_name; | |
56 | unsigned long flags; | |
57 | }; | |
58 | ||
59 | /** | |
60 | * struct aspeed_clk_gate - Aspeed specific clk_gate structure | |
61 | * @hw: handle between common and hardware-specific interfaces | |
62 | * @reg: register controlling gate | |
63 | * @clock_idx: bit used to gate this clock in the clock register | |
64 | * @reset_idx: bit used to reset this IP in the reset register. -1 if no | |
65 | * reset is required when enabling the clock | |
66 | * @flags: hardware-specific flags | |
67 | * @lock: register lock | |
68 | * | |
69 | * Some of the clocks in the Aspeed SoC must be put in reset before enabling. | |
70 | * This modified version of clk_gate allows an optional reset bit to be | |
71 | * specified. | |
72 | */ | |
73 | struct aspeed_clk_gate { | |
74 | struct clk_hw hw; | |
75 | struct regmap *map; | |
76 | u8 clock_idx; | |
77 | s8 reset_idx; | |
78 | u8 flags; | |
79 | spinlock_t *lock; | |
80 | }; | |
81 | ||
82 | #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) | |
83 | ||
84 | /* TODO: ask Aspeed about the actual parent data */ | |
85 | static const struct aspeed_gate_data aspeed_gates[] = { | |
86 | /* clk rst name parent flags */ | |
87 | [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ | |
88 | [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ | |
89 | [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ | |
90 | [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ | |
91 | [ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ | |
92 | [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */ | |
93 | [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, | |
94 | [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ | |
95 | [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */ | |
96 | [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ | |
97 | [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */ | |
98 | [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ | |
99 | [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ | |
100 | [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ | |
101 | [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ | |
102 | [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ | |
103 | [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ | |
104 | [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */ | |
105 | [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */ | |
106 | [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */ | |
107 | [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ | |
108 | [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ | |
109 | [ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ | |
110 | [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ | |
111 | }; | |
112 | ||
98f3118d JS |
113 | static const struct clk_div_table ast2500_mac_div_table[] = { |
114 | { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ | |
115 | { 0x1, 4 }, | |
116 | { 0x2, 6 }, | |
117 | { 0x3, 8 }, | |
118 | { 0x4, 10 }, | |
119 | { 0x5, 12 }, | |
120 | { 0x6, 14 }, | |
121 | { 0x7, 16 }, | |
122 | { 0 } | |
123 | }; | |
124 | ||
99d01e0e JS |
125 | static const struct clk_div_table ast2400_div_table[] = { |
126 | { 0x0, 2 }, | |
127 | { 0x1, 4 }, | |
128 | { 0x2, 6 }, | |
129 | { 0x3, 8 }, | |
130 | { 0x4, 10 }, | |
131 | { 0x5, 12 }, | |
132 | { 0x6, 14 }, | |
133 | { 0x7, 16 }, | |
134 | { 0 } | |
135 | }; | |
136 | ||
137 | static const struct clk_div_table ast2500_div_table[] = { | |
138 | { 0x0, 4 }, | |
139 | { 0x1, 8 }, | |
140 | { 0x2, 12 }, | |
141 | { 0x3, 16 }, | |
142 | { 0x4, 20 }, | |
143 | { 0x5, 24 }, | |
144 | { 0x6, 28 }, | |
145 | { 0x7, 32 }, | |
146 | { 0 } | |
147 | }; | |
148 | ||
149 | static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val) | |
150 | { | |
151 | unsigned int mult, div; | |
152 | ||
153 | if (val & AST2400_HPLL_BYPASS_EN) { | |
154 | /* Pass through mode */ | |
155 | mult = div = 1; | |
156 | } else { | |
157 | /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ | |
158 | u32 n = (val >> 5) & 0x3f; | |
159 | u32 od = (val >> 4) & 0x1; | |
160 | u32 d = val & 0xf; | |
161 | ||
162 | mult = (2 - od) * (n + 2); | |
163 | div = d + 1; | |
164 | } | |
165 | return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, | |
166 | mult, div); | |
167 | }; | |
168 | ||
169 | static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) | |
170 | { | |
171 | unsigned int mult, div; | |
172 | ||
173 | if (val & AST2500_HPLL_BYPASS_EN) { | |
174 | /* Pass through mode */ | |
175 | mult = div = 1; | |
176 | } else { | |
177 | /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ | |
178 | u32 p = (val >> 13) & 0x3f; | |
179 | u32 m = (val >> 5) & 0xff; | |
180 | u32 n = val & 0x1f; | |
181 | ||
182 | mult = (m + 1) / (n + 1); | |
183 | div = p + 1; | |
184 | } | |
185 | ||
186 | return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, | |
187 | mult, div); | |
188 | } | |
189 | ||
98f3118d JS |
190 | struct aspeed_clk_soc_data { |
191 | const struct clk_div_table *div_table; | |
192 | const struct clk_div_table *mac_div_table; | |
193 | struct clk_hw *(*calc_pll)(const char *name, u32 val); | |
194 | }; | |
195 | ||
196 | static const struct aspeed_clk_soc_data ast2500_data = { | |
197 | .div_table = ast2500_div_table, | |
198 | .mac_div_table = ast2500_mac_div_table, | |
199 | .calc_pll = aspeed_ast2500_calc_pll, | |
200 | }; | |
201 | ||
202 | static const struct aspeed_clk_soc_data ast2400_data = { | |
203 | .div_table = ast2400_div_table, | |
204 | .mac_div_table = ast2400_div_table, | |
205 | .calc_pll = aspeed_ast2400_calc_pll, | |
206 | }; | |
207 | ||
8a53fc51 EJ |
208 | static int aspeed_clk_is_enabled(struct clk_hw *hw) |
209 | { | |
210 | struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); | |
211 | u32 clk = BIT(gate->clock_idx); | |
212 | u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; | |
213 | u32 reg; | |
214 | ||
215 | regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); | |
216 | ||
217 | return ((reg & clk) == enval) ? 1 : 0; | |
218 | } | |
219 | ||
15ed8ce5 JS |
220 | static int aspeed_clk_enable(struct clk_hw *hw) |
221 | { | |
222 | struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); | |
223 | unsigned long flags; | |
224 | u32 clk = BIT(gate->clock_idx); | |
225 | u32 rst = BIT(gate->reset_idx); | |
6671507f | 226 | u32 enval; |
15ed8ce5 JS |
227 | |
228 | spin_lock_irqsave(gate->lock, flags); | |
229 | ||
8a53fc51 EJ |
230 | if (aspeed_clk_is_enabled(hw)) { |
231 | spin_unlock_irqrestore(gate->lock, flags); | |
232 | return 0; | |
233 | } | |
234 | ||
15ed8ce5 JS |
235 | if (gate->reset_idx >= 0) { |
236 | /* Put IP in reset */ | |
237 | regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); | |
238 | ||
239 | /* Delay 100us */ | |
240 | udelay(100); | |
241 | } | |
242 | ||
243 | /* Enable clock */ | |
6671507f BH |
244 | enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; |
245 | regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); | |
15ed8ce5 JS |
246 | |
247 | if (gate->reset_idx >= 0) { | |
248 | /* A delay of 10ms is specified by the ASPEED docs */ | |
249 | mdelay(10); | |
250 | ||
251 | /* Take IP out of reset */ | |
252 | regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); | |
253 | } | |
254 | ||
255 | spin_unlock_irqrestore(gate->lock, flags); | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | static void aspeed_clk_disable(struct clk_hw *hw) | |
261 | { | |
262 | struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); | |
263 | unsigned long flags; | |
264 | u32 clk = BIT(gate->clock_idx); | |
6671507f | 265 | u32 enval; |
15ed8ce5 JS |
266 | |
267 | spin_lock_irqsave(gate->lock, flags); | |
268 | ||
6671507f BH |
269 | enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0; |
270 | regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); | |
15ed8ce5 JS |
271 | |
272 | spin_unlock_irqrestore(gate->lock, flags); | |
273 | } | |
274 | ||
15ed8ce5 JS |
275 | static const struct clk_ops aspeed_clk_gate_ops = { |
276 | .enable = aspeed_clk_enable, | |
277 | .disable = aspeed_clk_disable, | |
278 | .is_enabled = aspeed_clk_is_enabled, | |
279 | }; | |
280 | ||
f7989839 JS |
281 | /** |
282 | * struct aspeed_reset - Aspeed reset controller | |
283 | * @map: regmap to access the containing system controller | |
284 | * @rcdev: reset controller device | |
285 | */ | |
286 | struct aspeed_reset { | |
287 | struct regmap *map; | |
288 | struct reset_controller_dev rcdev; | |
289 | }; | |
290 | ||
291 | #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) | |
292 | ||
293 | static const u8 aspeed_resets[] = { | |
294 | [ASPEED_RESET_XDMA] = 25, | |
295 | [ASPEED_RESET_MCTP] = 24, | |
296 | [ASPEED_RESET_ADC] = 23, | |
297 | [ASPEED_RESET_JTAG_MASTER] = 22, | |
298 | [ASPEED_RESET_MIC] = 18, | |
299 | [ASPEED_RESET_PWM] = 9, | |
300 | [ASPEED_RESET_PCIVGA] = 8, | |
301 | [ASPEED_RESET_I2C] = 2, | |
302 | [ASPEED_RESET_AHB] = 1, | |
303 | }; | |
304 | ||
305 | static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, | |
306 | unsigned long id) | |
307 | { | |
308 | struct aspeed_reset *ar = to_aspeed_reset(rcdev); | |
309 | u32 rst = BIT(aspeed_resets[id]); | |
310 | ||
311 | return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); | |
312 | } | |
313 | ||
314 | static int aspeed_reset_assert(struct reset_controller_dev *rcdev, | |
315 | unsigned long id) | |
316 | { | |
317 | struct aspeed_reset *ar = to_aspeed_reset(rcdev); | |
318 | u32 rst = BIT(aspeed_resets[id]); | |
319 | ||
320 | return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); | |
321 | } | |
322 | ||
323 | static int aspeed_reset_status(struct reset_controller_dev *rcdev, | |
324 | unsigned long id) | |
325 | { | |
326 | struct aspeed_reset *ar = to_aspeed_reset(rcdev); | |
327 | u32 val, rst = BIT(aspeed_resets[id]); | |
328 | int ret; | |
329 | ||
330 | ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); | |
331 | if (ret) | |
332 | return ret; | |
333 | ||
334 | return !!(val & rst); | |
335 | } | |
336 | ||
337 | static const struct reset_control_ops aspeed_reset_ops = { | |
338 | .assert = aspeed_reset_assert, | |
339 | .deassert = aspeed_reset_deassert, | |
340 | .status = aspeed_reset_status, | |
341 | }; | |
342 | ||
15ed8ce5 JS |
343 | static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, |
344 | const char *name, const char *parent_name, unsigned long flags, | |
345 | struct regmap *map, u8 clock_idx, u8 reset_idx, | |
346 | u8 clk_gate_flags, spinlock_t *lock) | |
347 | { | |
348 | struct aspeed_clk_gate *gate; | |
349 | struct clk_init_data init; | |
350 | struct clk_hw *hw; | |
351 | int ret; | |
352 | ||
353 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
354 | if (!gate) | |
355 | return ERR_PTR(-ENOMEM); | |
356 | ||
357 | init.name = name; | |
358 | init.ops = &aspeed_clk_gate_ops; | |
359 | init.flags = flags; | |
360 | init.parent_names = parent_name ? &parent_name : NULL; | |
361 | init.num_parents = parent_name ? 1 : 0; | |
362 | ||
363 | gate->map = map; | |
364 | gate->clock_idx = clock_idx; | |
365 | gate->reset_idx = reset_idx; | |
366 | gate->flags = clk_gate_flags; | |
367 | gate->lock = lock; | |
368 | gate->hw.init = &init; | |
369 | ||
370 | hw = &gate->hw; | |
371 | ret = clk_hw_register(dev, hw); | |
372 | if (ret) { | |
373 | kfree(gate); | |
374 | hw = ERR_PTR(ret); | |
375 | } | |
376 | ||
377 | return hw; | |
378 | } | |
379 | ||
98f3118d JS |
380 | static int aspeed_clk_probe(struct platform_device *pdev) |
381 | { | |
382 | const struct aspeed_clk_soc_data *soc_data; | |
383 | struct device *dev = &pdev->dev; | |
f7989839 | 384 | struct aspeed_reset *ar; |
98f3118d JS |
385 | struct regmap *map; |
386 | struct clk_hw *hw; | |
387 | u32 val, rate; | |
f7989839 | 388 | int i, ret; |
98f3118d JS |
389 | |
390 | map = syscon_node_to_regmap(dev->of_node); | |
391 | if (IS_ERR(map)) { | |
392 | dev_err(dev, "no syscon regmap\n"); | |
393 | return PTR_ERR(map); | |
394 | } | |
395 | ||
f7989839 JS |
396 | ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); |
397 | if (!ar) | |
398 | return -ENOMEM; | |
399 | ||
400 | ar->map = map; | |
401 | ar->rcdev.owner = THIS_MODULE; | |
402 | ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); | |
403 | ar->rcdev.ops = &aspeed_reset_ops; | |
404 | ar->rcdev.of_node = dev->of_node; | |
405 | ||
406 | ret = devm_reset_controller_register(dev, &ar->rcdev); | |
407 | if (ret) { | |
408 | dev_err(dev, "could not register reset controller\n"); | |
409 | return ret; | |
410 | } | |
411 | ||
98f3118d JS |
412 | /* SoC generations share common layouts but have different divisors */ |
413 | soc_data = of_device_get_match_data(dev); | |
414 | if (!soc_data) { | |
415 | dev_err(dev, "no match data for platform\n"); | |
416 | return -EINVAL; | |
417 | } | |
418 | ||
419 | /* UART clock div13 setting */ | |
420 | regmap_read(map, ASPEED_MISC_CTRL, &val); | |
421 | if (val & UART_DIV13_EN) | |
422 | rate = 24000000 / 13; | |
423 | else | |
424 | rate = 24000000; | |
425 | /* TODO: Find the parent data for the uart clock */ | |
426 | hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); | |
427 | if (IS_ERR(hw)) | |
428 | return PTR_ERR(hw); | |
429 | aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; | |
430 | ||
431 | /* | |
432 | * Memory controller (M-PLL) PLL. This clock is configured by the | |
433 | * bootloader, and is exposed to Linux as a read-only clock rate. | |
434 | */ | |
435 | regmap_read(map, ASPEED_MPLL_PARAM, &val); | |
436 | hw = soc_data->calc_pll("mpll", val); | |
437 | if (IS_ERR(hw)) | |
438 | return PTR_ERR(hw); | |
439 | aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; | |
440 | ||
441 | /* SD/SDIO clock divider (TODO: There's a gate too) */ | |
442 | hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, | |
443 | scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, | |
444 | soc_data->div_table, | |
445 | &aspeed_clk_lock); | |
446 | if (IS_ERR(hw)) | |
447 | return PTR_ERR(hw); | |
448 | aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; | |
449 | ||
450 | /* MAC AHB bus clock divider */ | |
451 | hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, | |
452 | scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, | |
453 | soc_data->mac_div_table, | |
454 | &aspeed_clk_lock); | |
455 | if (IS_ERR(hw)) | |
456 | return PTR_ERR(hw); | |
457 | aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; | |
458 | ||
459 | /* LPC Host (LHCLK) clock divider */ | |
460 | hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, | |
461 | scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, | |
462 | soc_data->div_table, | |
463 | &aspeed_clk_lock); | |
464 | if (IS_ERR(hw)) | |
465 | return PTR_ERR(hw); | |
466 | aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; | |
467 | ||
468 | /* P-Bus (BCLK) clock divider */ | |
469 | hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, | |
470 | scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, | |
471 | soc_data->div_table, | |
472 | &aspeed_clk_lock); | |
473 | if (IS_ERR(hw)) | |
474 | return PTR_ERR(hw); | |
475 | aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; | |
476 | ||
15ed8ce5 JS |
477 | /* |
478 | * TODO: There are a number of clocks that not included in this driver | |
479 | * as more information is required: | |
480 | * D2-PLL | |
481 | * D-PLL | |
482 | * YCLK | |
483 | * RGMII | |
484 | * RMII | |
485 | * UART[1..5] clock source mux | |
486 | * Video Engine (ECLK) mux and clock divider | |
487 | */ | |
488 | ||
489 | for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { | |
490 | const struct aspeed_gate_data *gd = &aspeed_gates[i]; | |
6671507f | 491 | u32 gate_flags; |
15ed8ce5 | 492 | |
6671507f BH |
493 | /* Special case: the USB port 1 clock (bit 14) is always |
494 | * working the opposite way from the other ones. | |
495 | */ | |
496 | gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; | |
15ed8ce5 JS |
497 | hw = aspeed_clk_hw_register_gate(dev, |
498 | gd->name, | |
499 | gd->parent_name, | |
500 | gd->flags, | |
501 | map, | |
502 | gd->clock_idx, | |
503 | gd->reset_idx, | |
6671507f | 504 | gate_flags, |
15ed8ce5 JS |
505 | &aspeed_clk_lock); |
506 | if (IS_ERR(hw)) | |
507 | return PTR_ERR(hw); | |
508 | aspeed_clk_data->hws[i] = hw; | |
509 | } | |
510 | ||
98f3118d JS |
511 | return 0; |
512 | }; | |
513 | ||
514 | static const struct of_device_id aspeed_clk_dt_ids[] = { | |
515 | { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, | |
516 | { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, | |
517 | { } | |
518 | }; | |
519 | ||
520 | static struct platform_driver aspeed_clk_driver = { | |
521 | .probe = aspeed_clk_probe, | |
522 | .driver = { | |
523 | .name = "aspeed-clk", | |
524 | .of_match_table = aspeed_clk_dt_ids, | |
525 | .suppress_bind_attrs = true, | |
526 | }, | |
527 | }; | |
528 | builtin_platform_driver(aspeed_clk_driver); | |
529 | ||
99d01e0e JS |
530 | static void __init aspeed_ast2400_cc(struct regmap *map) |
531 | { | |
532 | struct clk_hw *hw; | |
533 | u32 val, freq, div; | |
534 | ||
535 | /* | |
536 | * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by | |
537 | * strapping | |
538 | */ | |
539 | regmap_read(map, ASPEED_STRAP, &val); | |
540 | if (val & CLKIN_25MHZ_EN) | |
541 | freq = 25000000; | |
542 | else if (val & AST2400_CLK_SOURCE_SEL) | |
543 | freq = 48000000; | |
544 | else | |
545 | freq = 24000000; | |
546 | hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); | |
547 | pr_debug("clkin @%u MHz\n", freq / 1000000); | |
548 | ||
549 | /* | |
550 | * High-speed PLL clock derived from the crystal. This the CPU clock, | |
551 | * and we assume that it is enabled | |
552 | */ | |
553 | regmap_read(map, ASPEED_HPLL_PARAM, &val); | |
554 | WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured"); | |
555 | aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val); | |
556 | ||
557 | /* | |
558 | * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) | |
559 | * 00: Select CPU:AHB = 1:1 | |
560 | * 01: Select CPU:AHB = 2:1 | |
561 | * 10: Select CPU:AHB = 4:1 | |
562 | * 11: Select CPU:AHB = 3:1 | |
563 | */ | |
564 | regmap_read(map, ASPEED_STRAP, &val); | |
565 | val = (val >> 10) & 0x3; | |
566 | div = val + 1; | |
567 | if (div == 3) | |
568 | div = 4; | |
569 | else if (div == 4) | |
570 | div = 3; | |
571 | hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); | |
572 | aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; | |
573 | ||
574 | /* APB clock clock selection register SCU08 (aka PCLK) */ | |
575 | hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0, | |
576 | scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, | |
577 | ast2400_div_table, | |
578 | &aspeed_clk_lock); | |
579 | aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; | |
580 | } | |
581 | ||
582 | static void __init aspeed_ast2500_cc(struct regmap *map) | |
583 | { | |
584 | struct clk_hw *hw; | |
585 | u32 val, freq, div; | |
586 | ||
587 | /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ | |
588 | regmap_read(map, ASPEED_STRAP, &val); | |
589 | if (val & CLKIN_25MHZ_EN) | |
590 | freq = 25000000; | |
591 | else | |
592 | freq = 24000000; | |
593 | hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); | |
594 | pr_debug("clkin @%u MHz\n", freq / 1000000); | |
595 | ||
596 | /* | |
597 | * High-speed PLL clock derived from the crystal. This the CPU clock, | |
598 | * and we assume that it is enabled | |
599 | */ | |
600 | regmap_read(map, ASPEED_HPLL_PARAM, &val); | |
601 | aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); | |
602 | ||
603 | /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ | |
604 | regmap_read(map, ASPEED_STRAP, &val); | |
605 | val = (val >> 9) & 0x7; | |
606 | WARN(val == 0, "strapping is zero: cannot determine ahb clock"); | |
607 | div = 2 * (val + 1); | |
608 | hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); | |
609 | aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; | |
610 | ||
611 | /* APB clock clock selection register SCU08 (aka PCLK) */ | |
612 | regmap_read(map, ASPEED_CLK_SELECTION, &val); | |
613 | val = (val >> 23) & 0x7; | |
614 | div = 4 * (val + 1); | |
615 | hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); | |
616 | aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; | |
617 | }; | |
618 | ||
5eda5d79 JS |
619 | static void __init aspeed_cc_init(struct device_node *np) |
620 | { | |
621 | struct regmap *map; | |
622 | u32 val; | |
623 | int ret; | |
624 | int i; | |
625 | ||
626 | scu_base = of_iomap(np, 0); | |
accf475a | 627 | if (!scu_base) |
5eda5d79 JS |
628 | return; |
629 | ||
630 | aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) + | |
631 | sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS, | |
632 | GFP_KERNEL); | |
633 | if (!aspeed_clk_data) | |
634 | return; | |
635 | ||
636 | /* | |
637 | * This way all clocks fetched before the platform device probes, | |
638 | * except those we assign here for early use, will be deferred. | |
639 | */ | |
640 | for (i = 0; i < ASPEED_NUM_CLKS; i++) | |
641 | aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); | |
642 | ||
643 | map = syscon_node_to_regmap(np); | |
644 | if (IS_ERR(map)) { | |
645 | pr_err("no syscon regmap\n"); | |
646 | return; | |
647 | } | |
648 | /* | |
649 | * We check that the regmap works on this very first access, | |
650 | * but as this is an MMIO-backed regmap, subsequent regmap | |
651 | * access is not going to fail and we skip error checks from | |
652 | * this point. | |
653 | */ | |
654 | ret = regmap_read(map, ASPEED_STRAP, &val); | |
655 | if (ret) { | |
656 | pr_err("failed to read strapping register\n"); | |
657 | return; | |
658 | } | |
659 | ||
99d01e0e JS |
660 | if (of_device_is_compatible(np, "aspeed,ast2400-scu")) |
661 | aspeed_ast2400_cc(map); | |
662 | else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) | |
663 | aspeed_ast2500_cc(map); | |
664 | else | |
665 | pr_err("unknown platform, failed to add clocks\n"); | |
666 | ||
5eda5d79 JS |
667 | aspeed_clk_data->num = ASPEED_NUM_CLKS; |
668 | ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); | |
669 | if (ret) | |
670 | pr_err("failed to add DT provider: %d\n", ret); | |
671 | }; | |
672 | CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init); | |
673 | CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init); |