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beca8ccc SH |
1 | /* |
2 | * Copyright (c) 2014 Marvell Technology Group Ltd. | |
3 | * | |
4 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
5 | * Alexandre Belloni <alexandre.belloni@free-electrons.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <linux/clk-provider.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/slab.h> | |
25 | ||
26 | #include "berlin2-avpll.h" | |
27 | ||
28 | /* | |
29 | * Berlin2 SoCs comprise up to two PLLs called AVPLL built upon a | |
30 | * VCO with 8 channels each, channel 8 is the odd-one-out and does | |
31 | * not provide mul/div. | |
32 | * | |
33 | * Unfortunately, its registers are not named but just numbered. To | |
34 | * get in at least some kind of structure, we split each AVPLL into | |
35 | * the VCOs and each channel into separate clock drivers. | |
36 | * | |
37 | * Also, here and there the VCO registers are a bit different with | |
38 | * respect to bit shifts. Make sure to add a comment for those. | |
39 | */ | |
40 | #define NUM_CHANNELS 8 | |
41 | ||
42 | #define AVPLL_CTRL(x) ((x) * 0x4) | |
43 | ||
44 | #define VCO_CTRL0 AVPLL_CTRL(0) | |
45 | /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */ | |
46 | #define VCO_RESET BIT(0) | |
47 | #define VCO_POWERUP BIT(1) | |
48 | #define VCO_INTERPOL_SHIFT 2 | |
49 | #define VCO_INTERPOL_MASK (0xf << VCO_INTERPOL_SHIFT) | |
50 | #define VCO_REG1V45_SEL_SHIFT 6 | |
51 | #define VCO_REG1V45_SEL(x) ((x) << VCO_REG1V45_SEL_SHIFT) | |
52 | #define VCO_REG1V45_SEL_1V40 VCO_REG1V45_SEL(0) | |
53 | #define VCO_REG1V45_SEL_1V45 VCO_REG1V45_SEL(1) | |
54 | #define VCO_REG1V45_SEL_1V50 VCO_REG1V45_SEL(2) | |
55 | #define VCO_REG1V45_SEL_1V55 VCO_REG1V45_SEL(3) | |
56 | #define VCO_REG1V45_SEL_MASK VCO_REG1V45_SEL(3) | |
57 | #define VCO_REG0V9_SEL_SHIFT 8 | |
58 | #define VCO_REG0V9_SEL_MASK (0xf << VCO_REG0V9_SEL_SHIFT) | |
59 | #define VCO_VTHCAL_SHIFT 12 | |
60 | #define VCO_VTHCAL(x) ((x) << VCO_VTHCAL_SHIFT) | |
61 | #define VCO_VTHCAL_0V90 VCO_VTHCAL(0) | |
62 | #define VCO_VTHCAL_0V95 VCO_VTHCAL(1) | |
63 | #define VCO_VTHCAL_1V00 VCO_VTHCAL(2) | |
64 | #define VCO_VTHCAL_1V05 VCO_VTHCAL(3) | |
65 | #define VCO_VTHCAL_MASK VCO_VTHCAL(3) | |
66 | #define VCO_KVCOEXT_SHIFT 14 | |
67 | #define VCO_KVCOEXT_MASK (0x3 << VCO_KVCOEXT_SHIFT) | |
68 | #define VCO_KVCOEXT_ENABLE BIT(17) | |
69 | #define VCO_V2IEXT_SHIFT 18 | |
70 | #define VCO_V2IEXT_MASK (0xf << VCO_V2IEXT_SHIFT) | |
71 | #define VCO_V2IEXT_ENABLE BIT(22) | |
72 | #define VCO_SPEED_SHIFT 23 | |
73 | #define VCO_SPEED(x) ((x) << VCO_SPEED_SHIFT) | |
74 | #define VCO_SPEED_1G08_1G21 VCO_SPEED(0) | |
75 | #define VCO_SPEED_1G21_1G40 VCO_SPEED(1) | |
76 | #define VCO_SPEED_1G40_1G61 VCO_SPEED(2) | |
77 | #define VCO_SPEED_1G61_1G86 VCO_SPEED(3) | |
78 | #define VCO_SPEED_1G86_2G00 VCO_SPEED(4) | |
79 | #define VCO_SPEED_2G00_2G22 VCO_SPEED(5) | |
80 | #define VCO_SPEED_2G22 VCO_SPEED(6) | |
81 | #define VCO_SPEED_MASK VCO_SPEED(0x7) | |
82 | #define VCO_CLKDET_ENABLE BIT(26) | |
83 | #define VCO_CTRL1 AVPLL_CTRL(1) | |
84 | #define VCO_REFDIV_SHIFT 0 | |
85 | #define VCO_REFDIV(x) ((x) << VCO_REFDIV_SHIFT) | |
86 | #define VCO_REFDIV_1 VCO_REFDIV(0) | |
87 | #define VCO_REFDIV_2 VCO_REFDIV(1) | |
88 | #define VCO_REFDIV_4 VCO_REFDIV(2) | |
89 | #define VCO_REFDIV_3 VCO_REFDIV(3) | |
90 | #define VCO_REFDIV_MASK VCO_REFDIV(0x3f) | |
91 | #define VCO_FBDIV_SHIFT 6 | |
92 | #define VCO_FBDIV(x) ((x) << VCO_FBDIV_SHIFT) | |
93 | #define VCO_FBDIV_MASK VCO_FBDIV(0xff) | |
94 | #define VCO_ICP_SHIFT 14 | |
95 | /* PLL Charge Pump Current = 10uA * (x + 1) */ | |
96 | #define VCO_ICP(x) ((x) << VCO_ICP_SHIFT) | |
97 | #define VCO_ICP_MASK VCO_ICP(0xf) | |
98 | #define VCO_LOAD_CAP BIT(18) | |
99 | #define VCO_CALIBRATION_START BIT(19) | |
100 | #define VCO_FREQOFFSETn(x) AVPLL_CTRL(3 + (x)) | |
101 | #define VCO_FREQOFFSET_MASK 0x7ffff | |
102 | #define VCO_CTRL10 AVPLL_CTRL(10) | |
103 | #define VCO_POWERUP_CH1 BIT(20) | |
104 | #define VCO_CTRL11 AVPLL_CTRL(11) | |
105 | #define VCO_CTRL12 AVPLL_CTRL(12) | |
106 | #define VCO_CTRL13 AVPLL_CTRL(13) | |
107 | #define VCO_CTRL14 AVPLL_CTRL(14) | |
108 | #define VCO_CTRL15 AVPLL_CTRL(15) | |
109 | #define VCO_SYNC1n(x) AVPLL_CTRL(15 + (x)) | |
110 | #define VCO_SYNC1_MASK 0x1ffff | |
111 | #define VCO_SYNC2n(x) AVPLL_CTRL(23 + (x)) | |
112 | #define VCO_SYNC2_MASK 0x1ffff | |
113 | #define VCO_CTRL30 AVPLL_CTRL(30) | |
114 | #define VCO_DPLL_CH1_ENABLE BIT(17) | |
115 | ||
116 | struct berlin2_avpll_vco { | |
117 | struct clk_hw hw; | |
118 | void __iomem *base; | |
119 | u8 flags; | |
120 | }; | |
121 | ||
122 | #define to_avpll_vco(hw) container_of(hw, struct berlin2_avpll_vco, hw) | |
123 | ||
124 | static int berlin2_avpll_vco_is_enabled(struct clk_hw *hw) | |
125 | { | |
126 | struct berlin2_avpll_vco *vco = to_avpll_vco(hw); | |
127 | u32 reg; | |
128 | ||
129 | reg = readl_relaxed(vco->base + VCO_CTRL0); | |
130 | if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) | |
131 | reg >>= 4; | |
132 | ||
133 | return !!(reg & VCO_POWERUP); | |
134 | } | |
135 | ||
136 | static int berlin2_avpll_vco_enable(struct clk_hw *hw) | |
137 | { | |
138 | struct berlin2_avpll_vco *vco = to_avpll_vco(hw); | |
139 | u32 reg; | |
140 | ||
141 | reg = readl_relaxed(vco->base + VCO_CTRL0); | |
142 | if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) | |
143 | reg |= VCO_POWERUP << 4; | |
144 | else | |
145 | reg |= VCO_POWERUP; | |
146 | writel_relaxed(reg, vco->base + VCO_CTRL0); | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static void berlin2_avpll_vco_disable(struct clk_hw *hw) | |
152 | { | |
153 | struct berlin2_avpll_vco *vco = to_avpll_vco(hw); | |
154 | u32 reg; | |
155 | ||
156 | reg = readl_relaxed(vco->base + VCO_CTRL0); | |
157 | if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) | |
158 | reg &= ~(VCO_POWERUP << 4); | |
159 | else | |
160 | reg &= ~VCO_POWERUP; | |
161 | writel_relaxed(reg, vco->base + VCO_CTRL0); | |
162 | } | |
163 | ||
164 | static u8 vco_refdiv[] = { 1, 2, 4, 3 }; | |
165 | ||
166 | static unsigned long | |
167 | berlin2_avpll_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) | |
168 | { | |
169 | struct berlin2_avpll_vco *vco = to_avpll_vco(hw); | |
170 | u32 reg, refdiv, fbdiv; | |
171 | u64 freq = parent_rate; | |
172 | ||
173 | /* AVPLL VCO frequency: Fvco = (Fref / refdiv) * fbdiv */ | |
174 | reg = readl_relaxed(vco->base + VCO_CTRL1); | |
175 | refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; | |
176 | refdiv = vco_refdiv[refdiv]; | |
177 | fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; | |
178 | freq *= fbdiv; | |
179 | do_div(freq, refdiv); | |
180 | ||
181 | return (unsigned long)freq; | |
182 | } | |
183 | ||
184 | static const struct clk_ops berlin2_avpll_vco_ops = { | |
185 | .is_enabled = berlin2_avpll_vco_is_enabled, | |
186 | .enable = berlin2_avpll_vco_enable, | |
187 | .disable = berlin2_avpll_vco_disable, | |
188 | .recalc_rate = berlin2_avpll_vco_recalc_rate, | |
189 | }; | |
190 | ||
f6475e29 | 191 | int __init berlin2_avpll_vco_register(void __iomem *base, |
beca8ccc SH |
192 | const char *name, const char *parent_name, |
193 | u8 vco_flags, unsigned long flags) | |
194 | { | |
195 | struct berlin2_avpll_vco *vco; | |
196 | struct clk_init_data init; | |
197 | ||
198 | vco = kzalloc(sizeof(*vco), GFP_KERNEL); | |
199 | if (!vco) | |
f6475e29 | 200 | return -ENOMEM; |
beca8ccc SH |
201 | |
202 | vco->base = base; | |
203 | vco->flags = vco_flags; | |
204 | vco->hw.init = &init; | |
205 | init.name = name; | |
206 | init.ops = &berlin2_avpll_vco_ops; | |
207 | init.parent_names = &parent_name; | |
208 | init.num_parents = 1; | |
209 | init.flags = flags; | |
210 | ||
f6475e29 | 211 | return clk_hw_register(NULL, &vco->hw); |
beca8ccc SH |
212 | } |
213 | ||
214 | struct berlin2_avpll_channel { | |
215 | struct clk_hw hw; | |
216 | void __iomem *base; | |
217 | u8 flags; | |
218 | u8 index; | |
219 | }; | |
220 | ||
221 | #define to_avpll_channel(hw) container_of(hw, struct berlin2_avpll_channel, hw) | |
222 | ||
223 | static int berlin2_avpll_channel_is_enabled(struct clk_hw *hw) | |
224 | { | |
225 | struct berlin2_avpll_channel *ch = to_avpll_channel(hw); | |
226 | u32 reg; | |
227 | ||
228 | if (ch->index == 7) | |
229 | return 1; | |
230 | ||
231 | reg = readl_relaxed(ch->base + VCO_CTRL10); | |
232 | reg &= VCO_POWERUP_CH1 << ch->index; | |
233 | ||
234 | return !!reg; | |
235 | } | |
236 | ||
237 | static int berlin2_avpll_channel_enable(struct clk_hw *hw) | |
238 | { | |
239 | struct berlin2_avpll_channel *ch = to_avpll_channel(hw); | |
240 | u32 reg; | |
241 | ||
242 | reg = readl_relaxed(ch->base + VCO_CTRL10); | |
243 | reg |= VCO_POWERUP_CH1 << ch->index; | |
244 | writel_relaxed(reg, ch->base + VCO_CTRL10); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | static void berlin2_avpll_channel_disable(struct clk_hw *hw) | |
250 | { | |
251 | struct berlin2_avpll_channel *ch = to_avpll_channel(hw); | |
252 | u32 reg; | |
253 | ||
254 | reg = readl_relaxed(ch->base + VCO_CTRL10); | |
255 | reg &= ~(VCO_POWERUP_CH1 << ch->index); | |
256 | writel_relaxed(reg, ch->base + VCO_CTRL10); | |
257 | } | |
258 | ||
259 | static const u8 div_hdmi[] = { 1, 2, 4, 6 }; | |
260 | static const u8 div_av1[] = { 1, 2, 5, 5 }; | |
261 | ||
262 | static unsigned long | |
263 | berlin2_avpll_channel_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) | |
264 | { | |
265 | struct berlin2_avpll_channel *ch = to_avpll_channel(hw); | |
266 | u32 reg, div_av2, div_av3, divider = 1; | |
267 | u64 freq = parent_rate; | |
268 | ||
269 | reg = readl_relaxed(ch->base + VCO_CTRL30); | |
270 | if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0) | |
271 | goto skip_div; | |
272 | ||
273 | /* | |
274 | * Fch = (Fref * sync2) / | |
275 | * (sync1 * div_hdmi * div_av1 * div_av2 * div_av3) | |
276 | */ | |
277 | ||
278 | reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); | |
279 | /* BG2/BG2CDs SYNC1 reg on AVPLL_B channel 1 is shifted by 4 */ | |
280 | if (ch->flags & BERLIN2_AVPLL_BIT_QUIRK && ch->index == 0) | |
281 | reg >>= 4; | |
282 | divider = reg & VCO_SYNC1_MASK; | |
283 | ||
284 | reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); | |
285 | freq *= reg & VCO_SYNC2_MASK; | |
286 | ||
287 | /* Channel 8 has no dividers */ | |
288 | if (ch->index == 7) | |
289 | goto skip_div; | |
290 | ||
291 | /* | |
292 | * HDMI divider start at VCO_CTRL11, bit 7; MSB is enable, lower 2 bit | |
293 | * determine divider. | |
294 | */ | |
295 | reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7; | |
296 | reg = (reg >> (ch->index * 3)); | |
297 | if (reg & BIT(2)) | |
298 | divider *= div_hdmi[reg & 0x3]; | |
299 | ||
300 | /* | |
301 | * AV1 divider start at VCO_CTRL11, bit 28; MSB is enable, lower 2 bit | |
302 | * determine divider. | |
303 | */ | |
304 | if (ch->index == 0) { | |
305 | reg = readl_relaxed(ch->base + VCO_CTRL11); | |
306 | reg >>= 28; | |
307 | } else { | |
308 | reg = readl_relaxed(ch->base + VCO_CTRL12); | |
309 | reg >>= (ch->index-1) * 3; | |
310 | } | |
311 | if (reg & BIT(2)) | |
312 | divider *= div_av1[reg & 0x3]; | |
313 | ||
314 | /* | |
315 | * AV2 divider start at VCO_CTRL12, bit 18; each 7 bits wide, | |
316 | * zero is not a valid value. | |
317 | */ | |
318 | if (ch->index < 2) { | |
319 | reg = readl_relaxed(ch->base + VCO_CTRL12); | |
320 | reg >>= 18 + (ch->index * 7); | |
321 | } else if (ch->index < 7) { | |
322 | reg = readl_relaxed(ch->base + VCO_CTRL13); | |
323 | reg >>= (ch->index - 2) * 7; | |
324 | } else { | |
325 | reg = readl_relaxed(ch->base + VCO_CTRL14); | |
326 | } | |
327 | div_av2 = reg & 0x7f; | |
328 | if (div_av2) | |
329 | divider *= div_av2; | |
330 | ||
331 | /* | |
332 | * AV3 divider start at VCO_CTRL14, bit 7; each 4 bits wide. | |
333 | * AV2/AV3 form a fractional divider, where only specfic values for AV3 | |
334 | * are allowed. AV3 != 0 divides by AV2/2, AV3=0 is bypass. | |
335 | */ | |
336 | if (ch->index < 6) { | |
337 | reg = readl_relaxed(ch->base + VCO_CTRL14); | |
338 | reg >>= 7 + (ch->index * 4); | |
339 | } else { | |
340 | reg = readl_relaxed(ch->base + VCO_CTRL15); | |
341 | } | |
342 | div_av3 = reg & 0xf; | |
343 | if (div_av2 && div_av3) | |
344 | freq *= 2; | |
345 | ||
346 | skip_div: | |
347 | do_div(freq, divider); | |
348 | return (unsigned long)freq; | |
349 | } | |
350 | ||
351 | static const struct clk_ops berlin2_avpll_channel_ops = { | |
352 | .is_enabled = berlin2_avpll_channel_is_enabled, | |
353 | .enable = berlin2_avpll_channel_enable, | |
354 | .disable = berlin2_avpll_channel_disable, | |
355 | .recalc_rate = berlin2_avpll_channel_recalc_rate, | |
356 | }; | |
357 | ||
358 | /* | |
359 | * Another nice quirk: | |
360 | * On some production SoCs, AVPLL channels are scrambled with respect | |
361 | * to the channel numbering in the registers but still referenced by | |
362 | * their original channel numbers. We deal with it by having a flag | |
363 | * and a translation table for the index. | |
364 | */ | |
365 | static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 }; | |
366 | ||
f6475e29 | 367 | int __init berlin2_avpll_channel_register(void __iomem *base, |
beca8ccc SH |
368 | const char *name, u8 index, const char *parent_name, |
369 | u8 ch_flags, unsigned long flags) | |
370 | { | |
371 | struct berlin2_avpll_channel *ch; | |
372 | struct clk_init_data init; | |
373 | ||
374 | ch = kzalloc(sizeof(*ch), GFP_KERNEL); | |
375 | if (!ch) | |
f6475e29 | 376 | return -ENOMEM; |
beca8ccc SH |
377 | |
378 | ch->base = base; | |
379 | if (ch_flags & BERLIN2_AVPLL_SCRAMBLE_QUIRK) | |
380 | ch->index = quirk_index[index]; | |
381 | else | |
382 | ch->index = index; | |
383 | ||
384 | ch->flags = ch_flags; | |
385 | ch->hw.init = &init; | |
386 | init.name = name; | |
387 | init.ops = &berlin2_avpll_channel_ops; | |
388 | init.parent_names = &parent_name; | |
389 | init.num_parents = 1; | |
390 | init.flags = flags; | |
391 | ||
f6475e29 | 392 | return clk_hw_register(NULL, &ch->hw); |
beca8ccc | 393 | } |