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e1098e59 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
75fabc3f | 2 | /* |
41691b88 | 3 | * Copyright (C) 2010,2015 Broadcom |
75fabc3f | 4 | * Copyright (C) 2012 Stephen Warren |
75fabc3f SA |
5 | */ |
6 | ||
41691b88 EA |
7 | /** |
8 | * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) | |
9 | * | |
10 | * The clock tree on the 2835 has several levels. There's a root | |
11 | * oscillator running at 19.2Mhz. After the oscillator there are 5 | |
12 | * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", | |
13 | * and "HDMI displays". Those 5 PLLs each can divide their output to | |
14 | * produce up to 4 channels. Finally, there is the level of clocks to | |
15 | * be consumed by other hardware components (like "H264" or "HDMI | |
16 | * state machine"), which divide off of some subset of the PLL | |
17 | * channels. | |
18 | * | |
19 | * All of the clocks in the tree are exposed in the DT, because the DT | |
20 | * may want to make assignments of the final layer of clocks to the | |
21 | * PLL channels, and some components of the hardware will actually | |
22 | * skip layers of the tree (for example, the pixel clock comes | |
23 | * directly from the PLLH PIX channel without using a CM_*CTL clock | |
24 | * generator). | |
25 | */ | |
26 | ||
75fabc3f SA |
27 | #include <linux/clk-provider.h> |
28 | #include <linux/clkdev.h> | |
9e400c5c | 29 | #include <linux/clk.h> |
96bf9c69 | 30 | #include <linux/debugfs.h> |
3f919581 | 31 | #include <linux/delay.h> |
62e59c4e | 32 | #include <linux/io.h> |
41691b88 | 33 | #include <linux/module.h> |
ee0a5a90 | 34 | #include <linux/of_device.h> |
41691b88 EA |
35 | #include <linux/platform_device.h> |
36 | #include <linux/slab.h> | |
37 | #include <dt-bindings/clock/bcm2835.h> | |
38 | ||
39 | #define CM_PASSWORD 0x5a000000 | |
40 | ||
41 | #define CM_GNRICCTL 0x000 | |
42 | #define CM_GNRICDIV 0x004 | |
43 | # define CM_DIV_FRAC_BITS 12 | |
959ca92a | 44 | # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) |
41691b88 EA |
45 | |
46 | #define CM_VPUCTL 0x008 | |
47 | #define CM_VPUDIV 0x00c | |
48 | #define CM_SYSCTL 0x010 | |
49 | #define CM_SYSDIV 0x014 | |
50 | #define CM_PERIACTL 0x018 | |
51 | #define CM_PERIADIV 0x01c | |
52 | #define CM_PERIICTL 0x020 | |
53 | #define CM_PERIIDIV 0x024 | |
54 | #define CM_H264CTL 0x028 | |
55 | #define CM_H264DIV 0x02c | |
56 | #define CM_ISPCTL 0x030 | |
57 | #define CM_ISPDIV 0x034 | |
58 | #define CM_V3DCTL 0x038 | |
59 | #define CM_V3DDIV 0x03c | |
60 | #define CM_CAM0CTL 0x040 | |
61 | #define CM_CAM0DIV 0x044 | |
62 | #define CM_CAM1CTL 0x048 | |
63 | #define CM_CAM1DIV 0x04c | |
64 | #define CM_CCP2CTL 0x050 | |
65 | #define CM_CCP2DIV 0x054 | |
66 | #define CM_DSI0ECTL 0x058 | |
67 | #define CM_DSI0EDIV 0x05c | |
68 | #define CM_DSI0PCTL 0x060 | |
69 | #define CM_DSI0PDIV 0x064 | |
70 | #define CM_DPICTL 0x068 | |
71 | #define CM_DPIDIV 0x06c | |
72 | #define CM_GP0CTL 0x070 | |
73 | #define CM_GP0DIV 0x074 | |
74 | #define CM_GP1CTL 0x078 | |
75 | #define CM_GP1DIV 0x07c | |
76 | #define CM_GP2CTL 0x080 | |
77 | #define CM_GP2DIV 0x084 | |
78 | #define CM_HSMCTL 0x088 | |
79 | #define CM_HSMDIV 0x08c | |
80 | #define CM_OTPCTL 0x090 | |
81 | #define CM_OTPDIV 0x094 | |
2103a215 MS |
82 | #define CM_PCMCTL 0x098 |
83 | #define CM_PCMDIV 0x09c | |
41691b88 EA |
84 | #define CM_PWMCTL 0x0a0 |
85 | #define CM_PWMDIV 0x0a4 | |
2103a215 MS |
86 | #define CM_SLIMCTL 0x0a8 |
87 | #define CM_SLIMDIV 0x0ac | |
41691b88 EA |
88 | #define CM_SMICTL 0x0b0 |
89 | #define CM_SMIDIV 0x0b4 | |
2103a215 MS |
90 | /* no definition for 0x0b8 and 0x0bc */ |
91 | #define CM_TCNTCTL 0x0c0 | |
3f919581 EA |
92 | # define CM_TCNT_SRC1_SHIFT 12 |
93 | #define CM_TCNTCNT 0x0c4 | |
2103a215 MS |
94 | #define CM_TECCTL 0x0c8 |
95 | #define CM_TECDIV 0x0cc | |
96 | #define CM_TD0CTL 0x0d0 | |
97 | #define CM_TD0DIV 0x0d4 | |
98 | #define CM_TD1CTL 0x0d8 | |
99 | #define CM_TD1DIV 0x0dc | |
41691b88 EA |
100 | #define CM_TSENSCTL 0x0e0 |
101 | #define CM_TSENSDIV 0x0e4 | |
102 | #define CM_TIMERCTL 0x0e8 | |
103 | #define CM_TIMERDIV 0x0ec | |
104 | #define CM_UARTCTL 0x0f0 | |
105 | #define CM_UARTDIV 0x0f4 | |
106 | #define CM_VECCTL 0x0f8 | |
107 | #define CM_VECDIV 0x0fc | |
108 | #define CM_PULSECTL 0x190 | |
109 | #define CM_PULSEDIV 0x194 | |
110 | #define CM_SDCCTL 0x1a8 | |
111 | #define CM_SDCDIV 0x1ac | |
112 | #define CM_ARMCTL 0x1b0 | |
d3d6f15f MS |
113 | #define CM_AVEOCTL 0x1b8 |
114 | #define CM_AVEODIV 0x1bc | |
41691b88 EA |
115 | #define CM_EMMCCTL 0x1c0 |
116 | #define CM_EMMCDIV 0x1c4 | |
42de9ad4 SW |
117 | #define CM_EMMC2CTL 0x1d0 |
118 | #define CM_EMMC2DIV 0x1d4 | |
41691b88 EA |
119 | |
120 | /* General bits for the CM_*CTL regs */ | |
121 | # define CM_ENABLE BIT(4) | |
122 | # define CM_KILL BIT(5) | |
123 | # define CM_GATE_BIT 6 | |
124 | # define CM_GATE BIT(CM_GATE_BIT) | |
125 | # define CM_BUSY BIT(7) | |
126 | # define CM_BUSYD BIT(8) | |
959ca92a | 127 | # define CM_FRAC BIT(9) |
41691b88 EA |
128 | # define CM_SRC_SHIFT 0 |
129 | # define CM_SRC_BITS 4 | |
130 | # define CM_SRC_MASK 0xf | |
131 | # define CM_SRC_GND 0 | |
132 | # define CM_SRC_OSC 1 | |
133 | # define CM_SRC_TESTDEBUG0 2 | |
134 | # define CM_SRC_TESTDEBUG1 3 | |
135 | # define CM_SRC_PLLA_CORE 4 | |
136 | # define CM_SRC_PLLA_PER 4 | |
137 | # define CM_SRC_PLLC_CORE0 5 | |
138 | # define CM_SRC_PLLC_PER 5 | |
139 | # define CM_SRC_PLLC_CORE1 8 | |
140 | # define CM_SRC_PLLD_CORE 6 | |
141 | # define CM_SRC_PLLD_PER 6 | |
142 | # define CM_SRC_PLLH_AUX 7 | |
143 | # define CM_SRC_PLLC_CORE1 8 | |
144 | # define CM_SRC_PLLC_CORE2 9 | |
145 | ||
146 | #define CM_OSCCOUNT 0x100 | |
147 | ||
148 | #define CM_PLLA 0x104 | |
149 | # define CM_PLL_ANARST BIT(8) | |
150 | # define CM_PLLA_HOLDPER BIT(7) | |
151 | # define CM_PLLA_LOADPER BIT(6) | |
152 | # define CM_PLLA_HOLDCORE BIT(5) | |
153 | # define CM_PLLA_LOADCORE BIT(4) | |
154 | # define CM_PLLA_HOLDCCP2 BIT(3) | |
155 | # define CM_PLLA_LOADCCP2 BIT(2) | |
156 | # define CM_PLLA_HOLDDSI0 BIT(1) | |
157 | # define CM_PLLA_LOADDSI0 BIT(0) | |
158 | ||
159 | #define CM_PLLC 0x108 | |
160 | # define CM_PLLC_HOLDPER BIT(7) | |
161 | # define CM_PLLC_LOADPER BIT(6) | |
162 | # define CM_PLLC_HOLDCORE2 BIT(5) | |
163 | # define CM_PLLC_LOADCORE2 BIT(4) | |
164 | # define CM_PLLC_HOLDCORE1 BIT(3) | |
165 | # define CM_PLLC_LOADCORE1 BIT(2) | |
166 | # define CM_PLLC_HOLDCORE0 BIT(1) | |
167 | # define CM_PLLC_LOADCORE0 BIT(0) | |
168 | ||
169 | #define CM_PLLD 0x10c | |
170 | # define CM_PLLD_HOLDPER BIT(7) | |
171 | # define CM_PLLD_LOADPER BIT(6) | |
172 | # define CM_PLLD_HOLDCORE BIT(5) | |
173 | # define CM_PLLD_LOADCORE BIT(4) | |
174 | # define CM_PLLD_HOLDDSI1 BIT(3) | |
175 | # define CM_PLLD_LOADDSI1 BIT(2) | |
176 | # define CM_PLLD_HOLDDSI0 BIT(1) | |
177 | # define CM_PLLD_LOADDSI0 BIT(0) | |
178 | ||
179 | #define CM_PLLH 0x110 | |
180 | # define CM_PLLH_LOADRCAL BIT(2) | |
181 | # define CM_PLLH_LOADAUX BIT(1) | |
182 | # define CM_PLLH_LOADPIX BIT(0) | |
183 | ||
184 | #define CM_LOCK 0x114 | |
185 | # define CM_LOCK_FLOCKH BIT(12) | |
186 | # define CM_LOCK_FLOCKD BIT(11) | |
187 | # define CM_LOCK_FLOCKC BIT(10) | |
188 | # define CM_LOCK_FLOCKB BIT(9) | |
189 | # define CM_LOCK_FLOCKA BIT(8) | |
190 | ||
191 | #define CM_EVENT 0x118 | |
192 | #define CM_DSI1ECTL 0x158 | |
193 | #define CM_DSI1EDIV 0x15c | |
194 | #define CM_DSI1PCTL 0x160 | |
195 | #define CM_DSI1PDIV 0x164 | |
196 | #define CM_DFTCTL 0x168 | |
197 | #define CM_DFTDIV 0x16c | |
198 | ||
199 | #define CM_PLLB 0x170 | |
200 | # define CM_PLLB_HOLDARM BIT(1) | |
201 | # define CM_PLLB_LOADARM BIT(0) | |
202 | ||
203 | #define A2W_PLLA_CTRL 0x1100 | |
204 | #define A2W_PLLC_CTRL 0x1120 | |
205 | #define A2W_PLLD_CTRL 0x1140 | |
206 | #define A2W_PLLH_CTRL 0x1160 | |
207 | #define A2W_PLLB_CTRL 0x11e0 | |
208 | # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) | |
209 | # define A2W_PLL_CTRL_PWRDN BIT(16) | |
210 | # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 | |
211 | # define A2W_PLL_CTRL_PDIV_SHIFT 12 | |
212 | # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff | |
213 | # define A2W_PLL_CTRL_NDIV_SHIFT 0 | |
214 | ||
215 | #define A2W_PLLA_ANA0 0x1010 | |
216 | #define A2W_PLLC_ANA0 0x1030 | |
217 | #define A2W_PLLD_ANA0 0x1050 | |
218 | #define A2W_PLLH_ANA0 0x1070 | |
219 | #define A2W_PLLB_ANA0 0x10f0 | |
220 | ||
221 | #define A2W_PLL_KA_SHIFT 7 | |
222 | #define A2W_PLL_KA_MASK GENMASK(9, 7) | |
223 | #define A2W_PLL_KI_SHIFT 19 | |
224 | #define A2W_PLL_KI_MASK GENMASK(21, 19) | |
225 | #define A2W_PLL_KP_SHIFT 15 | |
226 | #define A2W_PLL_KP_MASK GENMASK(18, 15) | |
227 | ||
228 | #define A2W_PLLH_KA_SHIFT 19 | |
229 | #define A2W_PLLH_KA_MASK GENMASK(21, 19) | |
230 | #define A2W_PLLH_KI_LOW_SHIFT 22 | |
231 | #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) | |
232 | #define A2W_PLLH_KI_HIGH_SHIFT 0 | |
233 | #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) | |
234 | #define A2W_PLLH_KP_SHIFT 1 | |
235 | #define A2W_PLLH_KP_MASK GENMASK(4, 1) | |
236 | ||
237 | #define A2W_XOSC_CTRL 0x1190 | |
238 | # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) | |
239 | # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) | |
240 | # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) | |
241 | # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) | |
242 | # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) | |
243 | # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) | |
244 | # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) | |
245 | # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) | |
246 | ||
247 | #define A2W_PLLA_FRAC 0x1200 | |
248 | #define A2W_PLLC_FRAC 0x1220 | |
249 | #define A2W_PLLD_FRAC 0x1240 | |
250 | #define A2W_PLLH_FRAC 0x1260 | |
251 | #define A2W_PLLB_FRAC 0x12e0 | |
252 | # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) | |
253 | # define A2W_PLL_FRAC_BITS 20 | |
254 | ||
255 | #define A2W_PLL_CHANNEL_DISABLE BIT(8) | |
256 | #define A2W_PLL_DIV_BITS 8 | |
257 | #define A2W_PLL_DIV_SHIFT 0 | |
258 | ||
259 | #define A2W_PLLA_DSI0 0x1300 | |
260 | #define A2W_PLLA_CORE 0x1400 | |
261 | #define A2W_PLLA_PER 0x1500 | |
262 | #define A2W_PLLA_CCP2 0x1600 | |
263 | ||
264 | #define A2W_PLLC_CORE2 0x1320 | |
265 | #define A2W_PLLC_CORE1 0x1420 | |
266 | #define A2W_PLLC_PER 0x1520 | |
267 | #define A2W_PLLC_CORE0 0x1620 | |
268 | ||
269 | #define A2W_PLLD_DSI0 0x1340 | |
270 | #define A2W_PLLD_CORE 0x1440 | |
271 | #define A2W_PLLD_PER 0x1540 | |
272 | #define A2W_PLLD_DSI1 0x1640 | |
273 | ||
274 | #define A2W_PLLH_AUX 0x1360 | |
275 | #define A2W_PLLH_RCAL 0x1460 | |
276 | #define A2W_PLLH_PIX 0x1560 | |
277 | #define A2W_PLLH_STS 0x1660 | |
278 | ||
279 | #define A2W_PLLH_CTRLR 0x1960 | |
280 | #define A2W_PLLH_FRACR 0x1a60 | |
281 | #define A2W_PLLH_AUXR 0x1b60 | |
282 | #define A2W_PLLH_RCALR 0x1c60 | |
283 | #define A2W_PLLH_PIXR 0x1d60 | |
284 | #define A2W_PLLH_STSR 0x1e60 | |
285 | ||
286 | #define A2W_PLLB_ARM 0x13e0 | |
287 | #define A2W_PLLB_SP0 0x14e0 | |
288 | #define A2W_PLLB_SP1 0x15e0 | |
289 | #define A2W_PLLB_SP2 0x16e0 | |
290 | ||
291 | #define LOCK_TIMEOUT_NS 100000000 | |
292 | #define BCM2835_MAX_FB_RATE 1750000000u | |
293 | ||
ee0a5a90 | 294 | #define SOC_BCM2835 BIT(0) |
42de9ad4 SW |
295 | #define SOC_BCM2711 BIT(1) |
296 | #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711) | |
ee0a5a90 | 297 | |
8a39e9fa EA |
298 | /* |
299 | * Names of clocks used within the driver that need to be replaced | |
300 | * with an external parent's name. This array is in the order that | |
301 | * the clocks node in the DT references external clocks. | |
302 | */ | |
303 | static const char *const cprman_parent_names[] = { | |
304 | "xosc", | |
305 | "dsi0_byte", | |
306 | "dsi0_ddr2", | |
307 | "dsi0_ddr", | |
308 | "dsi1_byte", | |
309 | "dsi1_ddr2", | |
310 | "dsi1_ddr", | |
311 | }; | |
312 | ||
41691b88 EA |
313 | struct bcm2835_cprman { |
314 | struct device *dev; | |
315 | void __iomem *regs; | |
6e1e60da | 316 | spinlock_t regs_lock; /* spinlock for all clocks */ |
f34e4651 | 317 | unsigned int soc; |
8a39e9fa EA |
318 | |
319 | /* | |
320 | * Real names of cprman clock parents looked up through | |
321 | * of_clk_get_parent_name(), which will be used in the | |
322 | * parent_names[] arrays for clock registration. | |
323 | */ | |
324 | const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)]; | |
41691b88 | 325 | |
b19f009d SB |
326 | /* Must be last */ |
327 | struct clk_hw_onecell_data onecell; | |
41691b88 EA |
328 | }; |
329 | ||
ee0a5a90 SW |
330 | struct cprman_plat_data { |
331 | unsigned int soc; | |
332 | }; | |
333 | ||
41691b88 EA |
334 | static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) |
335 | { | |
336 | writel(CM_PASSWORD | val, cprman->regs + reg); | |
337 | } | |
338 | ||
339 | static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) | |
340 | { | |
341 | return readl(cprman->regs + reg); | |
342 | } | |
526d239c | 343 | |
3f919581 EA |
344 | /* Does a cycle of measuring a clock through the TCNT clock, which may |
345 | * source from many other clocks in the system. | |
346 | */ | |
347 | static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman, | |
348 | u32 tcnt_mux) | |
349 | { | |
350 | u32 osccount = 19200; /* 1ms */ | |
351 | u32 count; | |
352 | ktime_t timeout; | |
353 | ||
354 | spin_lock(&cprman->regs_lock); | |
355 | ||
356 | cprman_write(cprman, CM_TCNTCTL, CM_KILL); | |
357 | ||
358 | cprman_write(cprman, CM_TCNTCTL, | |
359 | (tcnt_mux & CM_SRC_MASK) | | |
360 | (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT); | |
361 | ||
362 | cprman_write(cprman, CM_OSCCOUNT, osccount); | |
363 | ||
364 | /* do a kind delay at the start */ | |
365 | mdelay(1); | |
366 | ||
367 | /* Finish off whatever is left of OSCCOUNT */ | |
368 | timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
369 | while (cprman_read(cprman, CM_OSCCOUNT)) { | |
370 | if (ktime_after(ktime_get(), timeout)) { | |
371 | dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); | |
372 | count = 0; | |
373 | goto out; | |
374 | } | |
375 | cpu_relax(); | |
376 | } | |
377 | ||
378 | /* Wait for BUSY to clear. */ | |
379 | timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
380 | while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) { | |
381 | if (ktime_after(ktime_get(), timeout)) { | |
382 | dev_err(cprman->dev, "timeout waiting for !BUSY\n"); | |
383 | count = 0; | |
384 | goto out; | |
385 | } | |
386 | cpu_relax(); | |
387 | } | |
388 | ||
389 | count = cprman_read(cprman, CM_TCNTCNT); | |
390 | ||
391 | cprman_write(cprman, CM_TCNTCTL, 0); | |
392 | ||
393 | out: | |
394 | spin_unlock(&cprman->regs_lock); | |
395 | ||
396 | return count * 1000; | |
397 | } | |
398 | ||
d75d50c0 | 399 | static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, |
dc543267 RF |
400 | const struct debugfs_reg32 *regs, |
401 | size_t nregs, struct dentry *dentry) | |
96bf9c69 | 402 | { |
96bf9c69 MS |
403 | struct debugfs_regset32 *regset; |
404 | ||
405 | regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); | |
406 | if (!regset) | |
d75d50c0 | 407 | return; |
96bf9c69 MS |
408 | |
409 | regset->regs = regs; | |
410 | regset->nregs = nregs; | |
411 | regset->base = cprman->regs + base; | |
412 | ||
c0526a11 | 413 | debugfs_create_regset32("regdump", S_IRUGO, dentry, regset); |
96bf9c69 MS |
414 | } |
415 | ||
41691b88 EA |
416 | struct bcm2835_pll_data { |
417 | const char *name; | |
418 | u32 cm_ctrl_reg; | |
419 | u32 a2w_ctrl_reg; | |
420 | u32 frac_reg; | |
421 | u32 ana_reg_base; | |
422 | u32 reference_enable_mask; | |
423 | /* Bit in CM_LOCK to indicate when the PLL has locked. */ | |
424 | u32 lock_mask; | |
b2683d06 | 425 | u32 flags; |
41691b88 EA |
426 | |
427 | const struct bcm2835_pll_ana_bits *ana; | |
428 | ||
429 | unsigned long min_rate; | |
430 | unsigned long max_rate; | |
431 | /* | |
432 | * Highest rate for the VCO before we have to use the | |
433 | * pre-divide-by-2. | |
434 | */ | |
435 | unsigned long max_fb_rate; | |
436 | }; | |
437 | ||
438 | struct bcm2835_pll_ana_bits { | |
439 | u32 mask0; | |
440 | u32 set0; | |
441 | u32 mask1; | |
442 | u32 set1; | |
443 | u32 mask3; | |
444 | u32 set3; | |
445 | u32 fb_prediv_mask; | |
446 | }; | |
447 | ||
448 | static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { | |
449 | .mask0 = 0, | |
450 | .set0 = 0, | |
49012d1b | 451 | .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK, |
41691b88 | 452 | .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), |
49012d1b | 453 | .mask3 = A2W_PLL_KA_MASK, |
41691b88 EA |
454 | .set3 = (2 << A2W_PLL_KA_SHIFT), |
455 | .fb_prediv_mask = BIT(14), | |
456 | }; | |
457 | ||
458 | static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { | |
49012d1b | 459 | .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK, |
41691b88 | 460 | .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), |
49012d1b | 461 | .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK, |
41691b88 EA |
462 | .set1 = (6 << A2W_PLLH_KP_SHIFT), |
463 | .mask3 = 0, | |
464 | .set3 = 0, | |
465 | .fb_prediv_mask = BIT(11), | |
466 | }; | |
467 | ||
41691b88 EA |
468 | struct bcm2835_pll_divider_data { |
469 | const char *name; | |
3b15afef MS |
470 | const char *source_pll; |
471 | ||
41691b88 EA |
472 | u32 cm_reg; |
473 | u32 a2w_reg; | |
474 | ||
475 | u32 load_mask; | |
476 | u32 hold_mask; | |
477 | u32 fixed_divider; | |
55486091 | 478 | u32 flags; |
41691b88 EA |
479 | }; |
480 | ||
41691b88 EA |
481 | struct bcm2835_clock_data { |
482 | const char *name; | |
483 | ||
484 | const char *const *parents; | |
485 | int num_mux_parents; | |
486 | ||
155e8b3b BB |
487 | /* Bitmap encoding which parents accept rate change propagation. */ |
488 | unsigned int set_rate_parent; | |
489 | ||
41691b88 EA |
490 | u32 ctl_reg; |
491 | u32 div_reg; | |
492 | ||
493 | /* Number of integer bits in the divider */ | |
494 | u32 int_bits; | |
495 | /* Number of fractional bits in the divider */ | |
496 | u32 frac_bits; | |
497 | ||
e69fdcca EA |
498 | u32 flags; |
499 | ||
41691b88 | 500 | bool is_vpu_clock; |
959ca92a | 501 | bool is_mash_clock; |
3542976d | 502 | bool low_jitter; |
3f919581 EA |
503 | |
504 | u32 tcnt_mux; | |
41691b88 EA |
505 | }; |
506 | ||
56eb3a2e MS |
507 | struct bcm2835_gate_data { |
508 | const char *name; | |
509 | const char *parent; | |
510 | ||
511 | u32 ctl_reg; | |
512 | }; | |
513 | ||
41691b88 EA |
514 | struct bcm2835_pll { |
515 | struct clk_hw hw; | |
516 | struct bcm2835_cprman *cprman; | |
517 | const struct bcm2835_pll_data *data; | |
518 | }; | |
519 | ||
520 | static int bcm2835_pll_is_on(struct clk_hw *hw) | |
521 | { | |
522 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
523 | struct bcm2835_cprman *cprman = pll->cprman; | |
524 | const struct bcm2835_pll_data *data = pll->data; | |
525 | ||
526 | return cprman_read(cprman, data->a2w_ctrl_reg) & | |
527 | A2W_PLL_CTRL_PRST_DISABLE; | |
528 | } | |
529 | ||
f34e4651 NSJ |
530 | static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman, |
531 | const struct bcm2835_pll_data *data) | |
532 | { | |
533 | /* | |
534 | * On BCM2711 there isn't a pre-divisor available in the PLL feedback | |
535 | * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed | |
536 | * for to for VCO RANGE bits. | |
537 | */ | |
538 | if (cprman->soc & SOC_BCM2711) | |
539 | return 0; | |
540 | ||
541 | return data->ana->fb_prediv_mask; | |
542 | } | |
543 | ||
41691b88 EA |
544 | static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, |
545 | unsigned long parent_rate, | |
546 | u32 *ndiv, u32 *fdiv) | |
547 | { | |
548 | u64 div; | |
549 | ||
550 | div = (u64)rate << A2W_PLL_FRAC_BITS; | |
551 | do_div(div, parent_rate); | |
552 | ||
553 | *ndiv = div >> A2W_PLL_FRAC_BITS; | |
554 | *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); | |
555 | } | |
556 | ||
557 | static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, | |
558 | u32 ndiv, u32 fdiv, u32 pdiv) | |
559 | { | |
560 | u64 rate; | |
561 | ||
562 | if (pdiv == 0) | |
563 | return 0; | |
564 | ||
565 | rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); | |
566 | do_div(rate, pdiv); | |
567 | return rate >> A2W_PLL_FRAC_BITS; | |
568 | } | |
569 | ||
570 | static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
571 | unsigned long *parent_rate) | |
572 | { | |
c4e634ce EA |
573 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); |
574 | const struct bcm2835_pll_data *data = pll->data; | |
41691b88 EA |
575 | u32 ndiv, fdiv; |
576 | ||
c4e634ce EA |
577 | rate = clamp(rate, data->min_rate, data->max_rate); |
578 | ||
41691b88 EA |
579 | bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); |
580 | ||
581 | return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); | |
582 | } | |
583 | ||
584 | static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, | |
585 | unsigned long parent_rate) | |
586 | { | |
587 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
588 | struct bcm2835_cprman *cprman = pll->cprman; | |
589 | const struct bcm2835_pll_data *data = pll->data; | |
590 | u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); | |
591 | u32 ndiv, pdiv, fdiv; | |
592 | bool using_prediv; | |
593 | ||
594 | if (parent_rate == 0) | |
595 | return 0; | |
596 | ||
597 | fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; | |
598 | ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; | |
599 | pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; | |
600 | using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & | |
f34e4651 | 601 | bcm2835_pll_get_prediv_mask(cprman, data); |
41691b88 | 602 | |
e45098d7 | 603 | if (using_prediv) { |
41691b88 | 604 | ndiv *= 2; |
e45098d7 PE |
605 | fdiv *= 2; |
606 | } | |
41691b88 EA |
607 | |
608 | return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); | |
609 | } | |
610 | ||
611 | static void bcm2835_pll_off(struct clk_hw *hw) | |
612 | { | |
613 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
614 | struct bcm2835_cprman *cprman = pll->cprman; | |
615 | const struct bcm2835_pll_data *data = pll->data; | |
616 | ||
6727f086 | 617 | spin_lock(&cprman->regs_lock); |
75387237 | 618 | cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); |
6727f086 MS |
619 | cprman_write(cprman, data->a2w_ctrl_reg, |
620 | cprman_read(cprman, data->a2w_ctrl_reg) | | |
621 | A2W_PLL_CTRL_PWRDN); | |
622 | spin_unlock(&cprman->regs_lock); | |
41691b88 EA |
623 | } |
624 | ||
625 | static int bcm2835_pll_on(struct clk_hw *hw) | |
626 | { | |
627 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
628 | struct bcm2835_cprman *cprman = pll->cprman; | |
629 | const struct bcm2835_pll_data *data = pll->data; | |
630 | ktime_t timeout; | |
631 | ||
e708b383 EA |
632 | cprman_write(cprman, data->a2w_ctrl_reg, |
633 | cprman_read(cprman, data->a2w_ctrl_reg) & | |
634 | ~A2W_PLL_CTRL_PWRDN); | |
635 | ||
41691b88 | 636 | /* Take the PLL out of reset. */ |
7997f3b2 | 637 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
638 | cprman_write(cprman, data->cm_ctrl_reg, |
639 | cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); | |
7997f3b2 | 640 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
641 | |
642 | /* Wait for the PLL to lock. */ | |
643 | timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
644 | while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { | |
645 | if (ktime_after(ktime_get(), timeout)) { | |
646 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
647 | clk_hw_get_name(hw)); | |
648 | return -ETIMEDOUT; | |
649 | } | |
650 | ||
651 | cpu_relax(); | |
652 | } | |
653 | ||
75387237 BB |
654 | cprman_write(cprman, data->a2w_ctrl_reg, |
655 | cprman_read(cprman, data->a2w_ctrl_reg) | | |
656 | A2W_PLL_CTRL_PRST_DISABLE); | |
657 | ||
41691b88 EA |
658 | return 0; |
659 | } | |
660 | ||
661 | static void | |
662 | bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) | |
663 | { | |
664 | int i; | |
665 | ||
666 | /* | |
667 | * ANA register setup is done as a series of writes to | |
668 | * ANA3-ANA0, in that order. This lets us write all 4 | |
669 | * registers as a single cycle of the serdes interface (taking | |
670 | * 100 xosc clocks), whereas if we were to update ana0, 1, and | |
671 | * 3 individually through their partial-write registers, each | |
672 | * would be their own serdes cycle. | |
673 | */ | |
674 | for (i = 3; i >= 0; i--) | |
675 | cprman_write(cprman, ana_reg_base + i * 4, ana[i]); | |
676 | } | |
677 | ||
678 | static int bcm2835_pll_set_rate(struct clk_hw *hw, | |
679 | unsigned long rate, unsigned long parent_rate) | |
680 | { | |
681 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
682 | struct bcm2835_cprman *cprman = pll->cprman; | |
683 | const struct bcm2835_pll_data *data = pll->data; | |
f34e4651 | 684 | u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data); |
41691b88 EA |
685 | bool was_using_prediv, use_fb_prediv, do_ana_setup_first; |
686 | u32 ndiv, fdiv, a2w_ctl; | |
687 | u32 ana[4]; | |
688 | int i; | |
689 | ||
41691b88 EA |
690 | if (rate > data->max_fb_rate) { |
691 | use_fb_prediv = true; | |
692 | rate /= 2; | |
693 | } else { | |
694 | use_fb_prediv = false; | |
695 | } | |
696 | ||
697 | bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); | |
698 | ||
699 | for (i = 3; i >= 0; i--) | |
700 | ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); | |
701 | ||
f34e4651 | 702 | was_using_prediv = ana[1] & prediv_mask; |
41691b88 EA |
703 | |
704 | ana[0] &= ~data->ana->mask0; | |
705 | ana[0] |= data->ana->set0; | |
706 | ana[1] &= ~data->ana->mask1; | |
707 | ana[1] |= data->ana->set1; | |
708 | ana[3] &= ~data->ana->mask3; | |
709 | ana[3] |= data->ana->set3; | |
710 | ||
711 | if (was_using_prediv && !use_fb_prediv) { | |
f34e4651 | 712 | ana[1] &= ~prediv_mask; |
41691b88 EA |
713 | do_ana_setup_first = true; |
714 | } else if (!was_using_prediv && use_fb_prediv) { | |
f34e4651 | 715 | ana[1] |= prediv_mask; |
41691b88 EA |
716 | do_ana_setup_first = false; |
717 | } else { | |
718 | do_ana_setup_first = true; | |
719 | } | |
720 | ||
721 | /* Unmask the reference clock from the oscillator. */ | |
7997f3b2 | 722 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
723 | cprman_write(cprman, A2W_XOSC_CTRL, |
724 | cprman_read(cprman, A2W_XOSC_CTRL) | | |
725 | data->reference_enable_mask); | |
7997f3b2 | 726 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
727 | |
728 | if (do_ana_setup_first) | |
729 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
730 | ||
731 | /* Set the PLL multiplier from the oscillator. */ | |
732 | cprman_write(cprman, data->frac_reg, fdiv); | |
733 | ||
734 | a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); | |
735 | a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; | |
736 | a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; | |
737 | a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; | |
738 | a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; | |
739 | cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); | |
740 | ||
741 | if (!do_ana_setup_first) | |
742 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
d75d50c0 | 747 | static void bcm2835_pll_debug_init(struct clk_hw *hw, |
96bf9c69 MS |
748 | struct dentry *dentry) |
749 | { | |
750 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
751 | struct bcm2835_cprman *cprman = pll->cprman; | |
752 | const struct bcm2835_pll_data *data = pll->data; | |
753 | struct debugfs_reg32 *regs; | |
754 | ||
a86854d0 | 755 | regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); |
96bf9c69 | 756 | if (!regs) |
d75d50c0 | 757 | return; |
96bf9c69 MS |
758 | |
759 | regs[0].name = "cm_ctrl"; | |
760 | regs[0].offset = data->cm_ctrl_reg; | |
761 | regs[1].name = "a2w_ctrl"; | |
762 | regs[1].offset = data->a2w_ctrl_reg; | |
763 | regs[2].name = "frac"; | |
764 | regs[2].offset = data->frac_reg; | |
765 | regs[3].name = "ana0"; | |
766 | regs[3].offset = data->ana_reg_base + 0 * 4; | |
767 | regs[4].name = "ana1"; | |
768 | regs[4].offset = data->ana_reg_base + 1 * 4; | |
769 | regs[5].name = "ana2"; | |
770 | regs[5].offset = data->ana_reg_base + 2 * 4; | |
771 | regs[6].name = "ana3"; | |
772 | regs[6].offset = data->ana_reg_base + 3 * 4; | |
773 | ||
d75d50c0 | 774 | bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); |
96bf9c69 MS |
775 | } |
776 | ||
41691b88 EA |
777 | static const struct clk_ops bcm2835_pll_clk_ops = { |
778 | .is_prepared = bcm2835_pll_is_on, | |
779 | .prepare = bcm2835_pll_on, | |
780 | .unprepare = bcm2835_pll_off, | |
781 | .recalc_rate = bcm2835_pll_get_rate, | |
782 | .set_rate = bcm2835_pll_set_rate, | |
783 | .round_rate = bcm2835_pll_round_rate, | |
96bf9c69 | 784 | .debug_init = bcm2835_pll_debug_init, |
41691b88 EA |
785 | }; |
786 | ||
787 | struct bcm2835_pll_divider { | |
788 | struct clk_divider div; | |
789 | struct bcm2835_cprman *cprman; | |
790 | const struct bcm2835_pll_divider_data *data; | |
791 | }; | |
792 | ||
793 | static struct bcm2835_pll_divider * | |
794 | bcm2835_pll_divider_from_hw(struct clk_hw *hw) | |
795 | { | |
796 | return container_of(hw, struct bcm2835_pll_divider, div.hw); | |
797 | } | |
798 | ||
799 | static int bcm2835_pll_divider_is_on(struct clk_hw *hw) | |
800 | { | |
801 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
802 | struct bcm2835_cprman *cprman = divider->cprman; | |
803 | const struct bcm2835_pll_divider_data *data = divider->data; | |
804 | ||
805 | return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); | |
806 | } | |
807 | ||
699470f3 MB |
808 | static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw, |
809 | struct clk_rate_request *req) | |
41691b88 | 810 | { |
699470f3 | 811 | return clk_divider_ops.determine_rate(hw, req); |
41691b88 EA |
812 | } |
813 | ||
814 | static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, | |
815 | unsigned long parent_rate) | |
816 | { | |
79c1e2fc | 817 | return clk_divider_ops.recalc_rate(hw, parent_rate); |
41691b88 EA |
818 | } |
819 | ||
820 | static void bcm2835_pll_divider_off(struct clk_hw *hw) | |
821 | { | |
822 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
823 | struct bcm2835_cprman *cprman = divider->cprman; | |
824 | const struct bcm2835_pll_divider_data *data = divider->data; | |
825 | ||
ec36a5c6 | 826 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
827 | cprman_write(cprman, data->cm_reg, |
828 | (cprman_read(cprman, data->cm_reg) & | |
829 | ~data->load_mask) | data->hold_mask); | |
68af4fa8 BB |
830 | cprman_write(cprman, data->a2w_reg, |
831 | cprman_read(cprman, data->a2w_reg) | | |
832 | A2W_PLL_CHANNEL_DISABLE); | |
ec36a5c6 | 833 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
834 | } |
835 | ||
836 | static int bcm2835_pll_divider_on(struct clk_hw *hw) | |
837 | { | |
838 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
839 | struct bcm2835_cprman *cprman = divider->cprman; | |
840 | const struct bcm2835_pll_divider_data *data = divider->data; | |
841 | ||
ec36a5c6 | 842 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
843 | cprman_write(cprman, data->a2w_reg, |
844 | cprman_read(cprman, data->a2w_reg) & | |
845 | ~A2W_PLL_CHANNEL_DISABLE); | |
846 | ||
847 | cprman_write(cprman, data->cm_reg, | |
848 | cprman_read(cprman, data->cm_reg) & ~data->hold_mask); | |
ec36a5c6 | 849 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
850 | |
851 | return 0; | |
852 | } | |
853 | ||
854 | static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, | |
855 | unsigned long rate, | |
856 | unsigned long parent_rate) | |
857 | { | |
858 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
859 | struct bcm2835_cprman *cprman = divider->cprman; | |
860 | const struct bcm2835_pll_divider_data *data = divider->data; | |
773b3966 | 861 | u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; |
41691b88 | 862 | |
773b3966 EA |
863 | div = DIV_ROUND_UP_ULL(parent_rate, rate); |
864 | ||
865 | div = min(div, max_div); | |
866 | if (div == max_div) | |
867 | div = 0; | |
41691b88 | 868 | |
773b3966 | 869 | cprman_write(cprman, data->a2w_reg, div); |
41691b88 EA |
870 | cm = cprman_read(cprman, data->cm_reg); |
871 | cprman_write(cprman, data->cm_reg, cm | data->load_mask); | |
872 | cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
d75d50c0 SB |
877 | static void bcm2835_pll_divider_debug_init(struct clk_hw *hw, |
878 | struct dentry *dentry) | |
96bf9c69 MS |
879 | { |
880 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
881 | struct bcm2835_cprman *cprman = divider->cprman; | |
882 | const struct bcm2835_pll_divider_data *data = divider->data; | |
883 | struct debugfs_reg32 *regs; | |
884 | ||
a86854d0 | 885 | regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); |
96bf9c69 | 886 | if (!regs) |
d75d50c0 | 887 | return; |
96bf9c69 MS |
888 | |
889 | regs[0].name = "cm"; | |
890 | regs[0].offset = data->cm_reg; | |
891 | regs[1].name = "a2w"; | |
892 | regs[1].offset = data->a2w_reg; | |
893 | ||
d75d50c0 | 894 | bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); |
96bf9c69 MS |
895 | } |
896 | ||
41691b88 EA |
897 | static const struct clk_ops bcm2835_pll_divider_clk_ops = { |
898 | .is_prepared = bcm2835_pll_divider_is_on, | |
899 | .prepare = bcm2835_pll_divider_on, | |
900 | .unprepare = bcm2835_pll_divider_off, | |
901 | .recalc_rate = bcm2835_pll_divider_get_rate, | |
902 | .set_rate = bcm2835_pll_divider_set_rate, | |
699470f3 | 903 | .determine_rate = bcm2835_pll_divider_determine_rate, |
96bf9c69 | 904 | .debug_init = bcm2835_pll_divider_debug_init, |
41691b88 EA |
905 | }; |
906 | ||
907 | /* | |
908 | * The CM dividers do fixed-point division, so we can't use the | |
909 | * generic integer divider code like the PLL dividers do (and we can't | |
910 | * fake it by having some fixed shifts preceding it in the clock tree, | |
911 | * because we'd run out of bits in a 32-bit unsigned long). | |
912 | */ | |
913 | struct bcm2835_clock { | |
914 | struct clk_hw hw; | |
915 | struct bcm2835_cprman *cprman; | |
916 | const struct bcm2835_clock_data *data; | |
917 | }; | |
918 | ||
919 | static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) | |
920 | { | |
921 | return container_of(hw, struct bcm2835_clock, hw); | |
922 | } | |
923 | ||
924 | static int bcm2835_clock_is_on(struct clk_hw *hw) | |
925 | { | |
926 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
927 | struct bcm2835_cprman *cprman = clock->cprman; | |
928 | const struct bcm2835_clock_data *data = clock->data; | |
929 | ||
930 | return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; | |
931 | } | |
932 | ||
933 | static u32 bcm2835_clock_choose_div(struct clk_hw *hw, | |
934 | unsigned long rate, | |
8ca011ef | 935 | unsigned long parent_rate) |
41691b88 EA |
936 | { |
937 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
938 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c RP |
939 | u32 unused_frac_mask = |
940 | GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; | |
41691b88 | 941 | u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; |
9c95b32c | 942 | u64 rem; |
959ca92a | 943 | u32 div, mindiv, maxdiv; |
41691b88 | 944 | |
9c95b32c | 945 | rem = do_div(temp, rate); |
41691b88 | 946 | div = temp; |
9c95b32c | 947 | div &= ~unused_frac_mask; |
41691b88 | 948 | |
959ca92a MS |
949 | /* different clamping limits apply for a mash clock */ |
950 | if (data->is_mash_clock) { | |
951 | /* clamp to min divider of 2 */ | |
952 | mindiv = 2 << CM_DIV_FRAC_BITS; | |
953 | /* clamp to the highest possible integer divider */ | |
954 | maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; | |
955 | } else { | |
956 | /* clamp to min divider of 1 */ | |
957 | mindiv = 1 << CM_DIV_FRAC_BITS; | |
958 | /* clamp to the highest possible fractional divider */ | |
959 | maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, | |
960 | CM_DIV_FRAC_BITS - data->frac_bits); | |
961 | } | |
962 | ||
963 | /* apply the clamping limits */ | |
964 | div = max_t(u32, div, mindiv); | |
965 | div = min_t(u32, div, maxdiv); | |
41691b88 EA |
966 | |
967 | return div; | |
968 | } | |
969 | ||
970 | static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, | |
971 | unsigned long parent_rate, | |
972 | u32 div) | |
973 | { | |
974 | const struct bcm2835_clock_data *data = clock->data; | |
975 | u64 temp; | |
976 | ||
8a39e9fa EA |
977 | if (data->int_bits == 0 && data->frac_bits == 0) |
978 | return parent_rate; | |
979 | ||
41691b88 EA |
980 | /* |
981 | * The divisor is a 12.12 fixed point field, but only some of | |
982 | * the bits are populated in any given clock. | |
983 | */ | |
984 | div >>= CM_DIV_FRAC_BITS - data->frac_bits; | |
985 | div &= (1 << (data->int_bits + data->frac_bits)) - 1; | |
986 | ||
987 | if (div == 0) | |
988 | return 0; | |
989 | ||
990 | temp = (u64)parent_rate << data->frac_bits; | |
991 | ||
992 | do_div(temp, div); | |
993 | ||
994 | return temp; | |
995 | } | |
996 | ||
41691b88 EA |
997 | static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, |
998 | unsigned long parent_rate) | |
999 | { | |
1000 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1001 | struct bcm2835_cprman *cprman = clock->cprman; | |
1002 | const struct bcm2835_clock_data *data = clock->data; | |
8a39e9fa EA |
1003 | u32 div; |
1004 | ||
1005 | if (data->int_bits == 0 && data->frac_bits == 0) | |
1006 | return parent_rate; | |
1007 | ||
1008 | div = cprman_read(cprman, data->div_reg); | |
41691b88 EA |
1009 | |
1010 | return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); | |
1011 | } | |
1012 | ||
1013 | static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) | |
1014 | { | |
1015 | struct bcm2835_cprman *cprman = clock->cprman; | |
1016 | const struct bcm2835_clock_data *data = clock->data; | |
1017 | ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
1018 | ||
1019 | while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { | |
1020 | if (ktime_after(ktime_get(), timeout)) { | |
1021 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
1022 | clk_hw_get_name(&clock->hw)); | |
1023 | return; | |
1024 | } | |
1025 | cpu_relax(); | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | static void bcm2835_clock_off(struct clk_hw *hw) | |
1030 | { | |
1031 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1032 | struct bcm2835_cprman *cprman = clock->cprman; | |
1033 | const struct bcm2835_clock_data *data = clock->data; | |
1034 | ||
1035 | spin_lock(&cprman->regs_lock); | |
1036 | cprman_write(cprman, data->ctl_reg, | |
1037 | cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); | |
1038 | spin_unlock(&cprman->regs_lock); | |
1039 | ||
1040 | /* BUSY will remain high until the divider completes its cycle. */ | |
1041 | bcm2835_clock_wait_busy(clock); | |
1042 | } | |
1043 | ||
1044 | static int bcm2835_clock_on(struct clk_hw *hw) | |
1045 | { | |
1046 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1047 | struct bcm2835_cprman *cprman = clock->cprman; | |
1048 | const struct bcm2835_clock_data *data = clock->data; | |
1049 | ||
1050 | spin_lock(&cprman->regs_lock); | |
1051 | cprman_write(cprman, data->ctl_reg, | |
1052 | cprman_read(cprman, data->ctl_reg) | | |
1053 | CM_ENABLE | | |
1054 | CM_GATE); | |
1055 | spin_unlock(&cprman->regs_lock); | |
1056 | ||
3f919581 EA |
1057 | /* Debug code to measure the clock once it's turned on to see |
1058 | * if it's ticking at the rate we expect. | |
1059 | */ | |
1060 | if (data->tcnt_mux && false) { | |
1061 | dev_info(cprman->dev, | |
1062 | "clk %s: rate %ld, measure %ld\n", | |
1063 | data->name, | |
1064 | clk_hw_get_rate(hw), | |
1065 | bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux)); | |
1066 | } | |
1067 | ||
41691b88 EA |
1068 | return 0; |
1069 | } | |
1070 | ||
1071 | static int bcm2835_clock_set_rate(struct clk_hw *hw, | |
1072 | unsigned long rate, unsigned long parent_rate) | |
1073 | { | |
1074 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1075 | struct bcm2835_cprman *cprman = clock->cprman; | |
1076 | const struct bcm2835_clock_data *data = clock->data; | |
8ca011ef | 1077 | u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate); |
959ca92a MS |
1078 | u32 ctl; |
1079 | ||
1080 | spin_lock(&cprman->regs_lock); | |
1081 | ||
1082 | /* | |
1083 | * Setting up frac support | |
1084 | * | |
1085 | * In principle it is recommended to stop/start the clock first, | |
1086 | * but as we set CLK_SET_RATE_GATE during registration of the | |
1087 | * clock this requirement should be take care of by the | |
1088 | * clk-framework. | |
1089 | */ | |
1090 | ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; | |
1091 | ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; | |
1092 | cprman_write(cprman, data->ctl_reg, ctl); | |
41691b88 EA |
1093 | |
1094 | cprman_write(cprman, data->div_reg, div); | |
1095 | ||
959ca92a MS |
1096 | spin_unlock(&cprman->regs_lock); |
1097 | ||
41691b88 EA |
1098 | return 0; |
1099 | } | |
1100 | ||
67615c58 EA |
1101 | static bool |
1102 | bcm2835_clk_is_pllc(struct clk_hw *hw) | |
1103 | { | |
1104 | if (!hw) | |
1105 | return false; | |
1106 | ||
1107 | return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; | |
1108 | } | |
1109 | ||
155e8b3b BB |
1110 | static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, |
1111 | int parent_idx, | |
1112 | unsigned long rate, | |
1113 | u32 *div, | |
3542976d PE |
1114 | unsigned long *prate, |
1115 | unsigned long *avgrate) | |
155e8b3b BB |
1116 | { |
1117 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1118 | struct bcm2835_cprman *cprman = clock->cprman; | |
1119 | const struct bcm2835_clock_data *data = clock->data; | |
2aab7a20 | 1120 | unsigned long best_rate = 0; |
155e8b3b BB |
1121 | u32 curdiv, mindiv, maxdiv; |
1122 | struct clk_hw *parent; | |
1123 | ||
1124 | parent = clk_hw_get_parent_by_index(hw, parent_idx); | |
1125 | ||
1126 | if (!(BIT(parent_idx) & data->set_rate_parent)) { | |
1127 | *prate = clk_hw_get_rate(parent); | |
8ca011ef | 1128 | *div = bcm2835_clock_choose_div(hw, rate, *prate); |
155e8b3b | 1129 | |
3542976d PE |
1130 | *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div); |
1131 | ||
1132 | if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) { | |
1133 | unsigned long high, low; | |
1134 | u32 int_div = *div & ~CM_DIV_FRAC_MASK; | |
1135 | ||
1136 | high = bcm2835_clock_rate_from_divisor(clock, *prate, | |
1137 | int_div); | |
1138 | int_div += CM_DIV_FRAC_MASK + 1; | |
1139 | low = bcm2835_clock_rate_from_divisor(clock, *prate, | |
1140 | int_div); | |
1141 | ||
1142 | /* | |
1143 | * Return a value which is the maximum deviation | |
1144 | * below the ideal rate, for use as a metric. | |
1145 | */ | |
1146 | return *avgrate - max(*avgrate - low, high - *avgrate); | |
1147 | } | |
1148 | return *avgrate; | |
155e8b3b BB |
1149 | } |
1150 | ||
1151 | if (data->frac_bits) | |
1152 | dev_warn(cprman->dev, | |
1153 | "frac bits are not used when propagating rate change"); | |
1154 | ||
1155 | /* clamp to min divider of 2 if we're dealing with a mash clock */ | |
1156 | mindiv = data->is_mash_clock ? 2 : 1; | |
1157 | maxdiv = BIT(data->int_bits) - 1; | |
1158 | ||
1159 | /* TODO: Be smart, and only test a subset of the available divisors. */ | |
1160 | for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) { | |
1161 | unsigned long tmp_rate; | |
1162 | ||
1163 | tmp_rate = clk_hw_round_rate(parent, rate * curdiv); | |
1164 | tmp_rate /= curdiv; | |
1165 | if (curdiv == mindiv || | |
1166 | (tmp_rate > best_rate && tmp_rate <= rate)) | |
1167 | best_rate = tmp_rate; | |
1168 | ||
1169 | if (best_rate == rate) | |
1170 | break; | |
1171 | } | |
1172 | ||
1173 | *div = curdiv << CM_DIV_FRAC_BITS; | |
1174 | *prate = curdiv * best_rate; | |
3542976d | 1175 | *avgrate = best_rate; |
155e8b3b BB |
1176 | |
1177 | return best_rate; | |
1178 | } | |
1179 | ||
6d18b8ad | 1180 | static int bcm2835_clock_determine_rate(struct clk_hw *hw, |
6e1e60da | 1181 | struct clk_rate_request *req) |
6d18b8ad | 1182 | { |
6d18b8ad | 1183 | struct clk_hw *parent, *best_parent = NULL; |
67615c58 | 1184 | bool current_parent_is_pllc; |
6d18b8ad RP |
1185 | unsigned long rate, best_rate = 0; |
1186 | unsigned long prate, best_prate = 0; | |
3542976d | 1187 | unsigned long avgrate, best_avgrate = 0; |
6d18b8ad RP |
1188 | size_t i; |
1189 | u32 div; | |
1190 | ||
67615c58 EA |
1191 | current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); |
1192 | ||
6d18b8ad RP |
1193 | /* |
1194 | * Select parent clock that results in the closest but lower rate | |
1195 | */ | |
1196 | for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { | |
1197 | parent = clk_hw_get_parent_by_index(hw, i); | |
1198 | if (!parent) | |
1199 | continue; | |
67615c58 EA |
1200 | |
1201 | /* | |
1202 | * Don't choose a PLLC-derived clock as our parent | |
1203 | * unless it had been manually set that way. PLLC's | |
1204 | * frequency gets adjusted by the firmware due to | |
1205 | * over-temp or under-voltage conditions, without | |
1206 | * prior notification to our clock consumer. | |
1207 | */ | |
1208 | if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) | |
1209 | continue; | |
1210 | ||
155e8b3b | 1211 | rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, |
3542976d PE |
1212 | &div, &prate, |
1213 | &avgrate); | |
5517357a | 1214 | if (abs(req->rate - rate) < abs(req->rate - best_rate)) { |
6d18b8ad RP |
1215 | best_parent = parent; |
1216 | best_prate = prate; | |
1217 | best_rate = rate; | |
3542976d | 1218 | best_avgrate = avgrate; |
6d18b8ad RP |
1219 | } |
1220 | } | |
1221 | ||
1222 | if (!best_parent) | |
1223 | return -EINVAL; | |
1224 | ||
1225 | req->best_parent_hw = best_parent; | |
1226 | req->best_parent_rate = best_prate; | |
1227 | ||
3542976d | 1228 | req->rate = best_avgrate; |
6d18b8ad RP |
1229 | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) | |
1234 | { | |
1235 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1236 | struct bcm2835_cprman *cprman = clock->cprman; | |
1237 | const struct bcm2835_clock_data *data = clock->data; | |
1238 | u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; | |
1239 | ||
1240 | cprman_write(cprman, data->ctl_reg, src); | |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | static u8 bcm2835_clock_get_parent(struct clk_hw *hw) | |
1245 | { | |
1246 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1247 | struct bcm2835_cprman *cprman = clock->cprman; | |
1248 | const struct bcm2835_clock_data *data = clock->data; | |
1249 | u32 src = cprman_read(cprman, data->ctl_reg); | |
1250 | ||
1251 | return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; | |
1252 | } | |
1253 | ||
dc543267 | 1254 | static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { |
96bf9c69 MS |
1255 | { |
1256 | .name = "ctl", | |
1257 | .offset = 0, | |
1258 | }, | |
1259 | { | |
1260 | .name = "div", | |
1261 | .offset = 4, | |
1262 | }, | |
1263 | }; | |
1264 | ||
d75d50c0 | 1265 | static void bcm2835_clock_debug_init(struct clk_hw *hw, |
96bf9c69 MS |
1266 | struct dentry *dentry) |
1267 | { | |
1268 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1269 | struct bcm2835_cprman *cprman = clock->cprman; | |
1270 | const struct bcm2835_clock_data *data = clock->data; | |
1271 | ||
d75d50c0 | 1272 | bcm2835_debugfs_regset(cprman, data->ctl_reg, |
96bf9c69 MS |
1273 | bcm2835_debugfs_clock_reg32, |
1274 | ARRAY_SIZE(bcm2835_debugfs_clock_reg32), | |
1275 | dentry); | |
1276 | } | |
1277 | ||
41691b88 EA |
1278 | static const struct clk_ops bcm2835_clock_clk_ops = { |
1279 | .is_prepared = bcm2835_clock_is_on, | |
1280 | .prepare = bcm2835_clock_on, | |
1281 | .unprepare = bcm2835_clock_off, | |
1282 | .recalc_rate = bcm2835_clock_get_rate, | |
1283 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1284 | .determine_rate = bcm2835_clock_determine_rate, |
1285 | .set_parent = bcm2835_clock_set_parent, | |
1286 | .get_parent = bcm2835_clock_get_parent, | |
96bf9c69 | 1287 | .debug_init = bcm2835_clock_debug_init, |
41691b88 EA |
1288 | }; |
1289 | ||
1290 | static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) | |
1291 | { | |
1292 | return true; | |
1293 | } | |
1294 | ||
1295 | /* | |
1296 | * The VPU clock can never be disabled (it doesn't have an ENABLE | |
1297 | * bit), so it gets its own set of clock ops. | |
1298 | */ | |
1299 | static const struct clk_ops bcm2835_vpu_clock_clk_ops = { | |
1300 | .is_prepared = bcm2835_vpu_clock_is_on, | |
1301 | .recalc_rate = bcm2835_clock_get_rate, | |
1302 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1303 | .determine_rate = bcm2835_clock_determine_rate, |
1304 | .set_parent = bcm2835_clock_set_parent, | |
1305 | .get_parent = bcm2835_clock_get_parent, | |
96bf9c69 | 1306 | .debug_init = bcm2835_clock_debug_init, |
41691b88 EA |
1307 | }; |
1308 | ||
b19f009d | 1309 | static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, |
99a1ae29 | 1310 | const void *data) |
41691b88 | 1311 | { |
99a1ae29 | 1312 | const struct bcm2835_pll_data *pll_data = data; |
41691b88 EA |
1313 | struct bcm2835_pll *pll; |
1314 | struct clk_init_data init; | |
b19f009d | 1315 | int ret; |
41691b88 EA |
1316 | |
1317 | memset(&init, 0, sizeof(init)); | |
1318 | ||
1319 | /* All of the PLLs derive from the external oscillator. */ | |
8a39e9fa | 1320 | init.parent_names = &cprman->real_parent_names[0]; |
41691b88 | 1321 | init.num_parents = 1; |
99a1ae29 | 1322 | init.name = pll_data->name; |
41691b88 | 1323 | init.ops = &bcm2835_pll_clk_ops; |
b2683d06 | 1324 | init.flags = pll_data->flags | CLK_IGNORE_UNUSED; |
41691b88 EA |
1325 | |
1326 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
1327 | if (!pll) | |
1328 | return NULL; | |
1329 | ||
1330 | pll->cprman = cprman; | |
99a1ae29 | 1331 | pll->data = pll_data; |
41691b88 EA |
1332 | pll->hw.init = &init; |
1333 | ||
b19f009d | 1334 | ret = devm_clk_hw_register(cprman->dev, &pll->hw); |
f6c992ca NE |
1335 | if (ret) { |
1336 | kfree(pll); | |
b19f009d | 1337 | return NULL; |
f6c992ca | 1338 | } |
b19f009d | 1339 | return &pll->hw; |
41691b88 EA |
1340 | } |
1341 | ||
b19f009d | 1342 | static struct clk_hw * |
41691b88 | 1343 | bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, |
99a1ae29 | 1344 | const void *data) |
41691b88 | 1345 | { |
99a1ae29 | 1346 | const struct bcm2835_pll_divider_data *divider_data = data; |
41691b88 EA |
1347 | struct bcm2835_pll_divider *divider; |
1348 | struct clk_init_data init; | |
41691b88 | 1349 | const char *divider_name; |
b19f009d | 1350 | int ret; |
41691b88 | 1351 | |
99a1ae29 | 1352 | if (divider_data->fixed_divider != 1) { |
41691b88 | 1353 | divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, |
99a1ae29 | 1354 | "%s_prediv", divider_data->name); |
41691b88 EA |
1355 | if (!divider_name) |
1356 | return NULL; | |
1357 | } else { | |
99a1ae29 | 1358 | divider_name = divider_data->name; |
41691b88 EA |
1359 | } |
1360 | ||
1361 | memset(&init, 0, sizeof(init)); | |
1362 | ||
99a1ae29 | 1363 | init.parent_names = ÷r_data->source_pll; |
41691b88 EA |
1364 | init.num_parents = 1; |
1365 | init.name = divider_name; | |
1366 | init.ops = &bcm2835_pll_divider_clk_ops; | |
99a1ae29 | 1367 | init.flags = divider_data->flags | CLK_IGNORE_UNUSED; |
41691b88 EA |
1368 | |
1369 | divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); | |
1370 | if (!divider) | |
1371 | return NULL; | |
1372 | ||
99a1ae29 | 1373 | divider->div.reg = cprman->regs + divider_data->a2w_reg; |
41691b88 EA |
1374 | divider->div.shift = A2W_PLL_DIV_SHIFT; |
1375 | divider->div.width = A2W_PLL_DIV_BITS; | |
79c1e2fc | 1376 | divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; |
41691b88 EA |
1377 | divider->div.lock = &cprman->regs_lock; |
1378 | divider->div.hw.init = &init; | |
1379 | divider->div.table = NULL; | |
1380 | ||
1381 | divider->cprman = cprman; | |
99a1ae29 | 1382 | divider->data = divider_data; |
41691b88 | 1383 | |
b19f009d SB |
1384 | ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); |
1385 | if (ret) | |
1386 | return ERR_PTR(ret); | |
41691b88 EA |
1387 | |
1388 | /* | |
1389 | * PLLH's channels have a fixed divide by 10 afterwards, which | |
1390 | * is what our consumers are actually using. | |
1391 | */ | |
99a1ae29 NC |
1392 | if (divider_data->fixed_divider != 1) { |
1393 | return clk_hw_register_fixed_factor(cprman->dev, | |
1394 | divider_data->name, | |
b19f009d SB |
1395 | divider_name, |
1396 | CLK_SET_RATE_PARENT, | |
1397 | 1, | |
99a1ae29 | 1398 | divider_data->fixed_divider); |
41691b88 EA |
1399 | } |
1400 | ||
b19f009d | 1401 | return ÷r->div.hw; |
41691b88 EA |
1402 | } |
1403 | ||
b19f009d | 1404 | static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, |
99a1ae29 | 1405 | const void *data) |
41691b88 | 1406 | { |
99a1ae29 | 1407 | const struct bcm2835_clock_data *clock_data = data; |
41691b88 EA |
1408 | struct bcm2835_clock *clock; |
1409 | struct clk_init_data init; | |
6d18b8ad | 1410 | const char *parents[1 << CM_SRC_BITS]; |
99e71543 | 1411 | size_t i; |
b19f009d | 1412 | int ret; |
41691b88 EA |
1413 | |
1414 | /* | |
8a39e9fa EA |
1415 | * Replace our strings referencing parent clocks with the |
1416 | * actual clock-output-name of the parent. | |
41691b88 | 1417 | */ |
99a1ae29 NC |
1418 | for (i = 0; i < clock_data->num_mux_parents; i++) { |
1419 | parents[i] = clock_data->parents[i]; | |
8a39e9fa | 1420 | |
99e71543 YX |
1421 | ret = match_string(cprman_parent_names, |
1422 | ARRAY_SIZE(cprman_parent_names), | |
1423 | parents[i]); | |
1424 | if (ret >= 0) | |
1425 | parents[i] = cprman->real_parent_names[ret]; | |
41691b88 EA |
1426 | } |
1427 | ||
1428 | memset(&init, 0, sizeof(init)); | |
6d18b8ad | 1429 | init.parent_names = parents; |
99a1ae29 NC |
1430 | init.num_parents = clock_data->num_mux_parents; |
1431 | init.name = clock_data->name; | |
1432 | init.flags = clock_data->flags | CLK_IGNORE_UNUSED; | |
41691b88 | 1433 | |
155e8b3b BB |
1434 | /* |
1435 | * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate | |
1436 | * rate changes on at least of the parents. | |
1437 | */ | |
99a1ae29 | 1438 | if (clock_data->set_rate_parent) |
155e8b3b BB |
1439 | init.flags |= CLK_SET_RATE_PARENT; |
1440 | ||
99a1ae29 | 1441 | if (clock_data->is_vpu_clock) { |
41691b88 EA |
1442 | init.ops = &bcm2835_vpu_clock_clk_ops; |
1443 | } else { | |
1444 | init.ops = &bcm2835_clock_clk_ops; | |
1445 | init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; | |
eddcbe83 EA |
1446 | |
1447 | /* If the clock wasn't actually enabled at boot, it's not | |
1448 | * critical. | |
1449 | */ | |
99a1ae29 | 1450 | if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE)) |
eddcbe83 | 1451 | init.flags &= ~CLK_IS_CRITICAL; |
41691b88 EA |
1452 | } |
1453 | ||
1454 | clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); | |
1455 | if (!clock) | |
1456 | return NULL; | |
1457 | ||
1458 | clock->cprman = cprman; | |
99a1ae29 | 1459 | clock->data = clock_data; |
41691b88 EA |
1460 | clock->hw.init = &init; |
1461 | ||
b19f009d SB |
1462 | ret = devm_clk_hw_register(cprman->dev, &clock->hw); |
1463 | if (ret) | |
1464 | return ERR_PTR(ret); | |
1465 | return &clock->hw; | |
41691b88 EA |
1466 | } |
1467 | ||
f376c43b | 1468 | static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman, |
99a1ae29 | 1469 | const void *data) |
56eb3a2e | 1470 | { |
99a1ae29 NC |
1471 | const struct bcm2835_gate_data *gate_data = data; |
1472 | ||
1473 | return clk_hw_register_gate(cprman->dev, gate_data->name, | |
1474 | gate_data->parent, | |
f376c43b | 1475 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, |
99a1ae29 | 1476 | cprman->regs + gate_data->ctl_reg, |
f376c43b | 1477 | CM_GATE_BIT, 0, &cprman->regs_lock); |
56eb3a2e MS |
1478 | } |
1479 | ||
56eb3a2e | 1480 | struct bcm2835_clk_desc { |
99a1ae29 NC |
1481 | struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman, |
1482 | const void *data); | |
ee0a5a90 | 1483 | unsigned int supported; |
56eb3a2e MS |
1484 | const void *data; |
1485 | }; | |
1486 | ||
3b15afef | 1487 | /* assignment helper macros for different clock types */ |
99a1ae29 | 1488 | #define _REGISTER(f, s, ...) { .clk_register = f, \ |
ee0a5a90 SW |
1489 | .supported = s, \ |
1490 | .data = __VA_ARGS__ } | |
1491 | #define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \ | |
1492 | s, \ | |
3b15afef MS |
1493 | &(struct bcm2835_pll_data) \ |
1494 | {__VA_ARGS__}) | |
ee0a5a90 SW |
1495 | #define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \ |
1496 | s, \ | |
1497 | &(struct bcm2835_pll_divider_data) \ | |
1498 | {__VA_ARGS__}) | |
1499 | #define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \ | |
1500 | s, \ | |
3b15afef MS |
1501 | &(struct bcm2835_clock_data) \ |
1502 | {__VA_ARGS__}) | |
ee0a5a90 SW |
1503 | #define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \ |
1504 | s, \ | |
3b15afef MS |
1505 | &(struct bcm2835_gate_data) \ |
1506 | {__VA_ARGS__}) | |
1507 | ||
1508 | /* parent mux arrays plus helper macros */ | |
1509 | ||
1510 | /* main oscillator parent mux */ | |
1511 | static const char *const bcm2835_clock_osc_parents[] = { | |
1512 | "gnd", | |
1513 | "xosc", | |
1514 | "testdebug0", | |
1515 | "testdebug1" | |
1516 | }; | |
1517 | ||
ee0a5a90 SW |
1518 | #define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \ |
1519 | s, \ | |
3b15afef MS |
1520 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ |
1521 | .parents = bcm2835_clock_osc_parents, \ | |
1522 | __VA_ARGS__) | |
1523 | ||
1524 | /* main peripherial parent mux */ | |
1525 | static const char *const bcm2835_clock_per_parents[] = { | |
1526 | "gnd", | |
1527 | "xosc", | |
1528 | "testdebug0", | |
1529 | "testdebug1", | |
1530 | "plla_per", | |
1531 | "pllc_per", | |
1532 | "plld_per", | |
1533 | "pllh_aux", | |
1534 | }; | |
1535 | ||
ee0a5a90 SW |
1536 | #define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \ |
1537 | s, \ | |
3b15afef MS |
1538 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ |
1539 | .parents = bcm2835_clock_per_parents, \ | |
1540 | __VA_ARGS__) | |
56eb3a2e | 1541 | |
8c0de581 PE |
1542 | /* |
1543 | * Restrict clock sources for the PCM peripheral to the oscillator and | |
1544 | * PLLD_PER because other source may have varying rates or be switched | |
1545 | * off. | |
1546 | * | |
1547 | * Prevent other sources from being selected by replacing their names in | |
1548 | * the list of potential parents with dummy entries (entry index is | |
1549 | * significant). | |
1550 | */ | |
1551 | static const char *const bcm2835_pcm_per_parents[] = { | |
1552 | "-", | |
1553 | "xosc", | |
1554 | "-", | |
1555 | "-", | |
1556 | "-", | |
1557 | "-", | |
1558 | "plld_per", | |
1559 | "-", | |
1560 | }; | |
1561 | ||
ee0a5a90 SW |
1562 | #define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \ |
1563 | s, \ | |
8c0de581 PE |
1564 | .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \ |
1565 | .parents = bcm2835_pcm_per_parents, \ | |
1566 | __VA_ARGS__) | |
1567 | ||
3b15afef MS |
1568 | /* main vpu parent mux */ |
1569 | static const char *const bcm2835_clock_vpu_parents[] = { | |
1570 | "gnd", | |
1571 | "xosc", | |
1572 | "testdebug0", | |
1573 | "testdebug1", | |
1574 | "plla_core", | |
1575 | "pllc_core0", | |
1576 | "plld_core", | |
1577 | "pllh_aux", | |
1578 | "pllc_core1", | |
1579 | "pllc_core2", | |
1580 | }; | |
1581 | ||
ee0a5a90 SW |
1582 | #define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \ |
1583 | s, \ | |
3b15afef MS |
1584 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ |
1585 | .parents = bcm2835_clock_vpu_parents, \ | |
1586 | __VA_ARGS__) | |
1587 | ||
8a39e9fa EA |
1588 | /* |
1589 | * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI | |
1590 | * analog PHY. The _inv variants are generated internally to cprman, | |
1591 | * but we don't use them so they aren't hooked up. | |
1592 | */ | |
1593 | static const char *const bcm2835_clock_dsi0_parents[] = { | |
1594 | "gnd", | |
1595 | "xosc", | |
1596 | "testdebug0", | |
1597 | "testdebug1", | |
1598 | "dsi0_ddr", | |
1599 | "dsi0_ddr_inv", | |
1600 | "dsi0_ddr2", | |
1601 | "dsi0_ddr2_inv", | |
1602 | "dsi0_byte", | |
1603 | "dsi0_byte_inv", | |
1604 | }; | |
1605 | ||
1606 | static const char *const bcm2835_clock_dsi1_parents[] = { | |
1607 | "gnd", | |
1608 | "xosc", | |
1609 | "testdebug0", | |
1610 | "testdebug1", | |
1611 | "dsi1_ddr", | |
1612 | "dsi1_ddr_inv", | |
1613 | "dsi1_ddr2", | |
1614 | "dsi1_ddr2_inv", | |
1615 | "dsi1_byte", | |
1616 | "dsi1_byte_inv", | |
1617 | }; | |
1618 | ||
ee0a5a90 SW |
1619 | #define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \ |
1620 | s, \ | |
8a39e9fa EA |
1621 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ |
1622 | .parents = bcm2835_clock_dsi0_parents, \ | |
1623 | __VA_ARGS__) | |
1624 | ||
ee0a5a90 SW |
1625 | #define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \ |
1626 | s, \ | |
8a39e9fa EA |
1627 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ |
1628 | .parents = bcm2835_clock_dsi1_parents, \ | |
1629 | __VA_ARGS__) | |
1630 | ||
3b15afef MS |
1631 | /* |
1632 | * the real definition of all the pll, pll_dividers and clocks | |
1633 | * these make use of the above REGISTER_* macros | |
1634 | */ | |
56eb3a2e | 1635 | static const struct bcm2835_clk_desc clk_desc_array[] = { |
3b15afef MS |
1636 | /* the PLL + PLL dividers */ |
1637 | ||
1638 | /* | |
1639 | * PLLA is the auxiliary PLL, used to drive the CCP2 | |
1640 | * (Compact Camera Port 2) transmitter clock. | |
1641 | * | |
1642 | * It is in the PX LDO power domain, which is on when the | |
1643 | * AUDIO domain is on. | |
1644 | */ | |
1645 | [BCM2835_PLLA] = REGISTER_PLL( | |
ee0a5a90 | 1646 | SOC_ALL, |
3b15afef MS |
1647 | .name = "plla", |
1648 | .cm_ctrl_reg = CM_PLLA, | |
1649 | .a2w_ctrl_reg = A2W_PLLA_CTRL, | |
1650 | .frac_reg = A2W_PLLA_FRAC, | |
1651 | .ana_reg_base = A2W_PLLA_ANA0, | |
1652 | .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, | |
1653 | .lock_mask = CM_LOCK_FLOCKA, | |
1654 | ||
1655 | .ana = &bcm2835_ana_default, | |
1656 | ||
1657 | .min_rate = 600000000u, | |
1658 | .max_rate = 2400000000u, | |
1659 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1660 | [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( | |
ee0a5a90 | 1661 | SOC_ALL, |
3b15afef MS |
1662 | .name = "plla_core", |
1663 | .source_pll = "plla", | |
1664 | .cm_reg = CM_PLLA, | |
1665 | .a2w_reg = A2W_PLLA_CORE, | |
1666 | .load_mask = CM_PLLA_LOADCORE, | |
1667 | .hold_mask = CM_PLLA_HOLDCORE, | |
55486091 EA |
1668 | .fixed_divider = 1, |
1669 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1670 | [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( |
ee0a5a90 | 1671 | SOC_ALL, |
3b15afef MS |
1672 | .name = "plla_per", |
1673 | .source_pll = "plla", | |
1674 | .cm_reg = CM_PLLA, | |
1675 | .a2w_reg = A2W_PLLA_PER, | |
1676 | .load_mask = CM_PLLA_LOADPER, | |
1677 | .hold_mask = CM_PLLA_HOLDPER, | |
55486091 EA |
1678 | .fixed_divider = 1, |
1679 | .flags = CLK_SET_RATE_PARENT), | |
72843695 | 1680 | [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( |
ee0a5a90 | 1681 | SOC_ALL, |
72843695 MS |
1682 | .name = "plla_dsi0", |
1683 | .source_pll = "plla", | |
1684 | .cm_reg = CM_PLLA, | |
1685 | .a2w_reg = A2W_PLLA_DSI0, | |
1686 | .load_mask = CM_PLLA_LOADDSI0, | |
1687 | .hold_mask = CM_PLLA_HOLDDSI0, | |
1688 | .fixed_divider = 1), | |
1689 | [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( | |
ee0a5a90 | 1690 | SOC_ALL, |
72843695 MS |
1691 | .name = "plla_ccp2", |
1692 | .source_pll = "plla", | |
1693 | .cm_reg = CM_PLLA, | |
1694 | .a2w_reg = A2W_PLLA_CCP2, | |
1695 | .load_mask = CM_PLLA_LOADCCP2, | |
1696 | .hold_mask = CM_PLLA_HOLDCCP2, | |
55486091 EA |
1697 | .fixed_divider = 1, |
1698 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1699 | |
dbe01b44 MR |
1700 | /* PLLB is used for the ARM's clock. */ |
1701 | [BCM2835_PLLB] = REGISTER_PLL( | |
1702 | SOC_ALL, | |
1703 | .name = "pllb", | |
1704 | .cm_ctrl_reg = CM_PLLB, | |
1705 | .a2w_ctrl_reg = A2W_PLLB_CTRL, | |
1706 | .frac_reg = A2W_PLLB_FRAC, | |
1707 | .ana_reg_base = A2W_PLLB_ANA0, | |
1708 | .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, | |
1709 | .lock_mask = CM_LOCK_FLOCKB, | |
1710 | ||
1711 | .ana = &bcm2835_ana_default, | |
1712 | ||
1713 | .min_rate = 600000000u, | |
1714 | .max_rate = 3000000000u, | |
0d46fafc MR |
1715 | .max_fb_rate = BCM2835_MAX_FB_RATE, |
1716 | .flags = CLK_GET_RATE_NOCACHE), | |
dbe01b44 MR |
1717 | [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( |
1718 | SOC_ALL, | |
1719 | .name = "pllb_arm", | |
1720 | .source_pll = "pllb", | |
1721 | .cm_reg = CM_PLLB, | |
1722 | .a2w_reg = A2W_PLLB_ARM, | |
1723 | .load_mask = CM_PLLB_LOADARM, | |
1724 | .hold_mask = CM_PLLB_HOLDARM, | |
1725 | .fixed_divider = 1, | |
0d46fafc | 1726 | .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE), |
3b15afef MS |
1727 | |
1728 | /* | |
1729 | * PLLC is the core PLL, used to drive the core VPU clock. | |
1730 | * | |
1731 | * It is in the PX LDO power domain, which is on when the | |
1732 | * AUDIO domain is on. | |
1733 | */ | |
1734 | [BCM2835_PLLC] = REGISTER_PLL( | |
ee0a5a90 | 1735 | SOC_ALL, |
3b15afef MS |
1736 | .name = "pllc", |
1737 | .cm_ctrl_reg = CM_PLLC, | |
1738 | .a2w_ctrl_reg = A2W_PLLC_CTRL, | |
1739 | .frac_reg = A2W_PLLC_FRAC, | |
1740 | .ana_reg_base = A2W_PLLC_ANA0, | |
1741 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
1742 | .lock_mask = CM_LOCK_FLOCKC, | |
1743 | ||
1744 | .ana = &bcm2835_ana_default, | |
1745 | ||
1746 | .min_rate = 600000000u, | |
1747 | .max_rate = 3000000000u, | |
1748 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1749 | [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( | |
ee0a5a90 | 1750 | SOC_ALL, |
3b15afef MS |
1751 | .name = "pllc_core0", |
1752 | .source_pll = "pllc", | |
1753 | .cm_reg = CM_PLLC, | |
1754 | .a2w_reg = A2W_PLLC_CORE0, | |
1755 | .load_mask = CM_PLLC_LOADCORE0, | |
1756 | .hold_mask = CM_PLLC_HOLDCORE0, | |
55486091 EA |
1757 | .fixed_divider = 1, |
1758 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1759 | [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( |
ee0a5a90 | 1760 | SOC_ALL, |
3b15afef MS |
1761 | .name = "pllc_core1", |
1762 | .source_pll = "pllc", | |
1763 | .cm_reg = CM_PLLC, | |
1764 | .a2w_reg = A2W_PLLC_CORE1, | |
1765 | .load_mask = CM_PLLC_LOADCORE1, | |
1766 | .hold_mask = CM_PLLC_HOLDCORE1, | |
55486091 EA |
1767 | .fixed_divider = 1, |
1768 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1769 | [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( |
ee0a5a90 | 1770 | SOC_ALL, |
3b15afef MS |
1771 | .name = "pllc_core2", |
1772 | .source_pll = "pllc", | |
1773 | .cm_reg = CM_PLLC, | |
1774 | .a2w_reg = A2W_PLLC_CORE2, | |
1775 | .load_mask = CM_PLLC_LOADCORE2, | |
1776 | .hold_mask = CM_PLLC_HOLDCORE2, | |
55486091 EA |
1777 | .fixed_divider = 1, |
1778 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1779 | [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( |
ee0a5a90 | 1780 | SOC_ALL, |
3b15afef MS |
1781 | .name = "pllc_per", |
1782 | .source_pll = "pllc", | |
1783 | .cm_reg = CM_PLLC, | |
1784 | .a2w_reg = A2W_PLLC_PER, | |
1785 | .load_mask = CM_PLLC_LOADPER, | |
1786 | .hold_mask = CM_PLLC_HOLDPER, | |
55486091 EA |
1787 | .fixed_divider = 1, |
1788 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1789 | |
1790 | /* | |
1791 | * PLLD is the display PLL, used to drive DSI display panels. | |
1792 | * | |
1793 | * It is in the PX LDO power domain, which is on when the | |
1794 | * AUDIO domain is on. | |
1795 | */ | |
1796 | [BCM2835_PLLD] = REGISTER_PLL( | |
ee0a5a90 | 1797 | SOC_ALL, |
3b15afef MS |
1798 | .name = "plld", |
1799 | .cm_ctrl_reg = CM_PLLD, | |
1800 | .a2w_ctrl_reg = A2W_PLLD_CTRL, | |
1801 | .frac_reg = A2W_PLLD_FRAC, | |
1802 | .ana_reg_base = A2W_PLLD_ANA0, | |
1803 | .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, | |
1804 | .lock_mask = CM_LOCK_FLOCKD, | |
1805 | ||
1806 | .ana = &bcm2835_ana_default, | |
1807 | ||
1808 | .min_rate = 600000000u, | |
1809 | .max_rate = 2400000000u, | |
1810 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1811 | [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( | |
ee0a5a90 | 1812 | SOC_ALL, |
3b15afef MS |
1813 | .name = "plld_core", |
1814 | .source_pll = "plld", | |
1815 | .cm_reg = CM_PLLD, | |
1816 | .a2w_reg = A2W_PLLD_CORE, | |
1817 | .load_mask = CM_PLLD_LOADCORE, | |
1818 | .hold_mask = CM_PLLD_HOLDCORE, | |
55486091 EA |
1819 | .fixed_divider = 1, |
1820 | .flags = CLK_SET_RATE_PARENT), | |
5c5ba218 SW |
1821 | /* |
1822 | * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core. | |
1823 | * Otherwise this could cause firmware lookups. That's why we mark | |
1824 | * it as critical. | |
1825 | */ | |
3b15afef | 1826 | [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( |
ee0a5a90 | 1827 | SOC_ALL, |
3b15afef MS |
1828 | .name = "plld_per", |
1829 | .source_pll = "plld", | |
1830 | .cm_reg = CM_PLLD, | |
1831 | .a2w_reg = A2W_PLLD_PER, | |
1832 | .load_mask = CM_PLLD_LOADPER, | |
1833 | .hold_mask = CM_PLLD_HOLDPER, | |
55486091 | 1834 | .fixed_divider = 1, |
5c5ba218 | 1835 | .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), |
72843695 | 1836 | [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( |
ee0a5a90 | 1837 | SOC_ALL, |
72843695 MS |
1838 | .name = "plld_dsi0", |
1839 | .source_pll = "plld", | |
1840 | .cm_reg = CM_PLLD, | |
1841 | .a2w_reg = A2W_PLLD_DSI0, | |
1842 | .load_mask = CM_PLLD_LOADDSI0, | |
1843 | .hold_mask = CM_PLLD_HOLDDSI0, | |
1844 | .fixed_divider = 1), | |
1845 | [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( | |
ee0a5a90 | 1846 | SOC_ALL, |
72843695 MS |
1847 | .name = "plld_dsi1", |
1848 | .source_pll = "plld", | |
1849 | .cm_reg = CM_PLLD, | |
1850 | .a2w_reg = A2W_PLLD_DSI1, | |
1851 | .load_mask = CM_PLLD_LOADDSI1, | |
1852 | .hold_mask = CM_PLLD_HOLDDSI1, | |
1853 | .fixed_divider = 1), | |
3b15afef MS |
1854 | |
1855 | /* | |
1856 | * PLLH is used to supply the pixel clock or the AUX clock for the | |
1857 | * TV encoder. | |
1858 | * | |
1859 | * It is in the HDMI power domain. | |
1860 | */ | |
1861 | [BCM2835_PLLH] = REGISTER_PLL( | |
ee0a5a90 | 1862 | SOC_BCM2835, |
3b15afef MS |
1863 | "pllh", |
1864 | .cm_ctrl_reg = CM_PLLH, | |
1865 | .a2w_ctrl_reg = A2W_PLLH_CTRL, | |
1866 | .frac_reg = A2W_PLLH_FRAC, | |
1867 | .ana_reg_base = A2W_PLLH_ANA0, | |
1868 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
1869 | .lock_mask = CM_LOCK_FLOCKH, | |
1870 | ||
1871 | .ana = &bcm2835_ana_pllh, | |
1872 | ||
1873 | .min_rate = 600000000u, | |
1874 | .max_rate = 3000000000u, | |
1875 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1876 | [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( | |
ee0a5a90 | 1877 | SOC_BCM2835, |
3b15afef MS |
1878 | .name = "pllh_rcal", |
1879 | .source_pll = "pllh", | |
1880 | .cm_reg = CM_PLLH, | |
1881 | .a2w_reg = A2W_PLLH_RCAL, | |
1882 | .load_mask = CM_PLLH_LOADRCAL, | |
1883 | .hold_mask = 0, | |
55486091 EA |
1884 | .fixed_divider = 10, |
1885 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1886 | [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( |
ee0a5a90 | 1887 | SOC_BCM2835, |
3b15afef MS |
1888 | .name = "pllh_aux", |
1889 | .source_pll = "pllh", | |
1890 | .cm_reg = CM_PLLH, | |
1891 | .a2w_reg = A2W_PLLH_AUX, | |
1892 | .load_mask = CM_PLLH_LOADAUX, | |
1893 | .hold_mask = 0, | |
55486091 EA |
1894 | .fixed_divider = 1, |
1895 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1896 | [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( |
ee0a5a90 | 1897 | SOC_BCM2835, |
3b15afef MS |
1898 | .name = "pllh_pix", |
1899 | .source_pll = "pllh", | |
1900 | .cm_reg = CM_PLLH, | |
1901 | .a2w_reg = A2W_PLLH_PIX, | |
1902 | .load_mask = CM_PLLH_LOADPIX, | |
1903 | .hold_mask = 0, | |
55486091 EA |
1904 | .fixed_divider = 10, |
1905 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1906 | |
56eb3a2e | 1907 | /* the clocks */ |
3b15afef MS |
1908 | |
1909 | /* clocks with oscillator parent mux */ | |
1910 | ||
1911 | /* One Time Programmable Memory clock. Maximum 10Mhz. */ | |
1912 | [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( | |
ee0a5a90 | 1913 | SOC_ALL, |
3b15afef MS |
1914 | .name = "otp", |
1915 | .ctl_reg = CM_OTPCTL, | |
1916 | .div_reg = CM_OTPDIV, | |
1917 | .int_bits = 4, | |
3f919581 EA |
1918 | .frac_bits = 0, |
1919 | .tcnt_mux = 6), | |
3b15afef MS |
1920 | /* |
1921 | * Used for a 1Mhz clock for the system clocksource, and also used | |
1922 | * bythe watchdog timer and the camera pulse generator. | |
1923 | */ | |
1924 | [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( | |
ee0a5a90 | 1925 | SOC_ALL, |
3b15afef MS |
1926 | .name = "timer", |
1927 | .ctl_reg = CM_TIMERCTL, | |
1928 | .div_reg = CM_TIMERDIV, | |
1929 | .int_bits = 6, | |
1930 | .frac_bits = 12), | |
1931 | /* | |
1932 | * Clock for the temperature sensor. | |
1933 | * Generally run at 2Mhz, max 5Mhz. | |
1934 | */ | |
1935 | [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( | |
ee0a5a90 | 1936 | SOC_ALL, |
3b15afef MS |
1937 | .name = "tsens", |
1938 | .ctl_reg = CM_TSENSCTL, | |
1939 | .div_reg = CM_TSENSDIV, | |
1940 | .int_bits = 5, | |
1941 | .frac_bits = 0), | |
d3d6f15f | 1942 | [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( |
ee0a5a90 | 1943 | SOC_ALL, |
d3d6f15f MS |
1944 | .name = "tec", |
1945 | .ctl_reg = CM_TECCTL, | |
1946 | .div_reg = CM_TECDIV, | |
1947 | .int_bits = 6, | |
1948 | .frac_bits = 0), | |
3b15afef MS |
1949 | |
1950 | /* clocks with vpu parent mux */ | |
1951 | [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( | |
ee0a5a90 | 1952 | SOC_ALL, |
3b15afef MS |
1953 | .name = "h264", |
1954 | .ctl_reg = CM_H264CTL, | |
1955 | .div_reg = CM_H264DIV, | |
1956 | .int_bits = 4, | |
3f919581 EA |
1957 | .frac_bits = 8, |
1958 | .tcnt_mux = 1), | |
3b15afef | 1959 | [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( |
ee0a5a90 | 1960 | SOC_ALL, |
3b15afef MS |
1961 | .name = "isp", |
1962 | .ctl_reg = CM_ISPCTL, | |
1963 | .div_reg = CM_ISPDIV, | |
1964 | .int_bits = 4, | |
3f919581 EA |
1965 | .frac_bits = 8, |
1966 | .tcnt_mux = 2), | |
d3d6f15f | 1967 | |
3b15afef MS |
1968 | /* |
1969 | * Secondary SDRAM clock. Used for low-voltage modes when the PLL | |
1970 | * in the SDRAM controller can't be used. | |
1971 | */ | |
1972 | [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( | |
ee0a5a90 | 1973 | SOC_ALL, |
3b15afef MS |
1974 | .name = "sdram", |
1975 | .ctl_reg = CM_SDCCTL, | |
1976 | .div_reg = CM_SDCDIV, | |
1977 | .int_bits = 6, | |
3f919581 EA |
1978 | .frac_bits = 0, |
1979 | .tcnt_mux = 3), | |
3b15afef | 1980 | [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( |
ee0a5a90 | 1981 | SOC_ALL, |
3b15afef MS |
1982 | .name = "v3d", |
1983 | .ctl_reg = CM_V3DCTL, | |
1984 | .div_reg = CM_V3DDIV, | |
1985 | .int_bits = 4, | |
3f919581 EA |
1986 | .frac_bits = 8, |
1987 | .tcnt_mux = 4), | |
3b15afef MS |
1988 | /* |
1989 | * VPU clock. This doesn't have an enable bit, since it drives | |
1990 | * the bus for everything else, and is special so it doesn't need | |
1991 | * to be gated for rate changes. It is also known as "clk_audio" | |
1992 | * in various hardware documentation. | |
1993 | */ | |
1994 | [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( | |
ee0a5a90 | 1995 | SOC_ALL, |
3b15afef MS |
1996 | .name = "vpu", |
1997 | .ctl_reg = CM_VPUCTL, | |
1998 | .div_reg = CM_VPUDIV, | |
1999 | .int_bits = 12, | |
2000 | .frac_bits = 8, | |
e69fdcca | 2001 | .flags = CLK_IS_CRITICAL, |
3f919581 EA |
2002 | .is_vpu_clock = true, |
2003 | .tcnt_mux = 5), | |
3b15afef MS |
2004 | |
2005 | /* clocks with per parent mux */ | |
d3d6f15f | 2006 | [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( |
ee0a5a90 | 2007 | SOC_ALL, |
d3d6f15f MS |
2008 | .name = "aveo", |
2009 | .ctl_reg = CM_AVEOCTL, | |
2010 | .div_reg = CM_AVEODIV, | |
2011 | .int_bits = 4, | |
3f919581 EA |
2012 | .frac_bits = 0, |
2013 | .tcnt_mux = 38), | |
d3d6f15f | 2014 | [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( |
ee0a5a90 | 2015 | SOC_ALL, |
d3d6f15f MS |
2016 | .name = "cam0", |
2017 | .ctl_reg = CM_CAM0CTL, | |
2018 | .div_reg = CM_CAM0DIV, | |
2019 | .int_bits = 4, | |
3f919581 EA |
2020 | .frac_bits = 8, |
2021 | .tcnt_mux = 14), | |
d3d6f15f | 2022 | [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( |
ee0a5a90 | 2023 | SOC_ALL, |
d3d6f15f MS |
2024 | .name = "cam1", |
2025 | .ctl_reg = CM_CAM1CTL, | |
2026 | .div_reg = CM_CAM1DIV, | |
2027 | .int_bits = 4, | |
3f919581 EA |
2028 | .frac_bits = 8, |
2029 | .tcnt_mux = 15), | |
d3d6f15f | 2030 | [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( |
ee0a5a90 | 2031 | SOC_ALL, |
d3d6f15f MS |
2032 | .name = "dft", |
2033 | .ctl_reg = CM_DFTCTL, | |
2034 | .div_reg = CM_DFTDIV, | |
2035 | .int_bits = 5, | |
2036 | .frac_bits = 0), | |
2037 | [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( | |
ee0a5a90 | 2038 | SOC_ALL, |
d3d6f15f MS |
2039 | .name = "dpi", |
2040 | .ctl_reg = CM_DPICTL, | |
2041 | .div_reg = CM_DPIDIV, | |
2042 | .int_bits = 4, | |
3f919581 EA |
2043 | .frac_bits = 8, |
2044 | .tcnt_mux = 17), | |
3b15afef MS |
2045 | |
2046 | /* Arasan EMMC clock */ | |
2047 | [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( | |
ee0a5a90 | 2048 | SOC_ALL, |
3b15afef MS |
2049 | .name = "emmc", |
2050 | .ctl_reg = CM_EMMCCTL, | |
2051 | .div_reg = CM_EMMCDIV, | |
2052 | .int_bits = 4, | |
3f919581 EA |
2053 | .frac_bits = 8, |
2054 | .tcnt_mux = 39), | |
d3d6f15f | 2055 | |
42de9ad4 SW |
2056 | /* EMMC2 clock (only available for BCM2711) */ |
2057 | [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK( | |
2058 | SOC_BCM2711, | |
2059 | .name = "emmc2", | |
2060 | .ctl_reg = CM_EMMC2CTL, | |
2061 | .div_reg = CM_EMMC2DIV, | |
2062 | .int_bits = 4, | |
2063 | .frac_bits = 8, | |
2064 | .tcnt_mux = 42), | |
2065 | ||
d3d6f15f MS |
2066 | /* General purpose (GPIO) clocks */ |
2067 | [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( | |
ee0a5a90 | 2068 | SOC_ALL, |
d3d6f15f MS |
2069 | .name = "gp0", |
2070 | .ctl_reg = CM_GP0CTL, | |
2071 | .div_reg = CM_GP0DIV, | |
2072 | .int_bits = 12, | |
2073 | .frac_bits = 12, | |
3f919581 EA |
2074 | .is_mash_clock = true, |
2075 | .tcnt_mux = 20), | |
d3d6f15f | 2076 | [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( |
ee0a5a90 | 2077 | SOC_ALL, |
d3d6f15f MS |
2078 | .name = "gp1", |
2079 | .ctl_reg = CM_GP1CTL, | |
2080 | .div_reg = CM_GP1DIV, | |
2081 | .int_bits = 12, | |
2082 | .frac_bits = 12, | |
eddcbe83 | 2083 | .flags = CLK_IS_CRITICAL, |
3f919581 EA |
2084 | .is_mash_clock = true, |
2085 | .tcnt_mux = 21), | |
d3d6f15f | 2086 | [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( |
ee0a5a90 | 2087 | SOC_ALL, |
d3d6f15f MS |
2088 | .name = "gp2", |
2089 | .ctl_reg = CM_GP2CTL, | |
2090 | .div_reg = CM_GP2DIV, | |
2091 | .int_bits = 12, | |
eddcbe83 EA |
2092 | .frac_bits = 12, |
2093 | .flags = CLK_IS_CRITICAL), | |
d3d6f15f | 2094 | |
3b15afef MS |
2095 | /* HDMI state machine */ |
2096 | [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( | |
ee0a5a90 | 2097 | SOC_ALL, |
3b15afef MS |
2098 | .name = "hsm", |
2099 | .ctl_reg = CM_HSMCTL, | |
2100 | .div_reg = CM_HSMDIV, | |
2101 | .int_bits = 4, | |
3f919581 EA |
2102 | .frac_bits = 8, |
2103 | .tcnt_mux = 22), | |
8c0de581 | 2104 | [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK( |
ee0a5a90 | 2105 | SOC_ALL, |
33b68960 MS |
2106 | .name = "pcm", |
2107 | .ctl_reg = CM_PCMCTL, | |
2108 | .div_reg = CM_PCMDIV, | |
2109 | .int_bits = 12, | |
2110 | .frac_bits = 12, | |
3f919581 | 2111 | .is_mash_clock = true, |
3542976d | 2112 | .low_jitter = true, |
3f919581 | 2113 | .tcnt_mux = 23), |
3b15afef | 2114 | [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( |
ee0a5a90 | 2115 | SOC_ALL, |
3b15afef MS |
2116 | .name = "pwm", |
2117 | .ctl_reg = CM_PWMCTL, | |
2118 | .div_reg = CM_PWMDIV, | |
2119 | .int_bits = 12, | |
2120 | .frac_bits = 12, | |
3f919581 EA |
2121 | .is_mash_clock = true, |
2122 | .tcnt_mux = 24), | |
d3d6f15f | 2123 | [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( |
ee0a5a90 | 2124 | SOC_ALL, |
d3d6f15f MS |
2125 | .name = "slim", |
2126 | .ctl_reg = CM_SLIMCTL, | |
2127 | .div_reg = CM_SLIMDIV, | |
2128 | .int_bits = 12, | |
2129 | .frac_bits = 12, | |
3f919581 EA |
2130 | .is_mash_clock = true, |
2131 | .tcnt_mux = 25), | |
d3d6f15f | 2132 | [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( |
ee0a5a90 | 2133 | SOC_ALL, |
d3d6f15f MS |
2134 | .name = "smi", |
2135 | .ctl_reg = CM_SMICTL, | |
2136 | .div_reg = CM_SMIDIV, | |
2137 | .int_bits = 4, | |
3f919581 EA |
2138 | .frac_bits = 8, |
2139 | .tcnt_mux = 27), | |
3b15afef | 2140 | [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( |
ee0a5a90 | 2141 | SOC_ALL, |
3b15afef MS |
2142 | .name = "uart", |
2143 | .ctl_reg = CM_UARTCTL, | |
2144 | .div_reg = CM_UARTDIV, | |
2145 | .int_bits = 10, | |
3f919581 EA |
2146 | .frac_bits = 12, |
2147 | .tcnt_mux = 28), | |
d3d6f15f | 2148 | |
3b15afef MS |
2149 | /* TV encoder clock. Only operating frequency is 108Mhz. */ |
2150 | [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( | |
ee0a5a90 | 2151 | SOC_ALL, |
3b15afef MS |
2152 | .name = "vec", |
2153 | .ctl_reg = CM_VECCTL, | |
2154 | .div_reg = CM_VECDIV, | |
2155 | .int_bits = 4, | |
d86d46af BB |
2156 | .frac_bits = 0, |
2157 | /* | |
2158 | * Allow rate change propagation only on PLLH_AUX which is | |
2159 | * assigned index 7 in the parent array. | |
2160 | */ | |
3f919581 EA |
2161 | .set_rate_parent = BIT(7), |
2162 | .tcnt_mux = 29), | |
3b15afef | 2163 | |
d3d6f15f MS |
2164 | /* dsi clocks */ |
2165 | [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( | |
ee0a5a90 | 2166 | SOC_ALL, |
d3d6f15f MS |
2167 | .name = "dsi0e", |
2168 | .ctl_reg = CM_DSI0ECTL, | |
2169 | .div_reg = CM_DSI0EDIV, | |
2170 | .int_bits = 4, | |
3f919581 EA |
2171 | .frac_bits = 8, |
2172 | .tcnt_mux = 18), | |
d3d6f15f | 2173 | [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( |
ee0a5a90 | 2174 | SOC_ALL, |
d3d6f15f MS |
2175 | .name = "dsi1e", |
2176 | .ctl_reg = CM_DSI1ECTL, | |
2177 | .div_reg = CM_DSI1EDIV, | |
2178 | .int_bits = 4, | |
3f919581 EA |
2179 | .frac_bits = 8, |
2180 | .tcnt_mux = 19), | |
8a39e9fa | 2181 | [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( |
ee0a5a90 | 2182 | SOC_ALL, |
8a39e9fa EA |
2183 | .name = "dsi0p", |
2184 | .ctl_reg = CM_DSI0PCTL, | |
2185 | .div_reg = CM_DSI0PDIV, | |
2186 | .int_bits = 0, | |
3f919581 EA |
2187 | .frac_bits = 0, |
2188 | .tcnt_mux = 12), | |
8a39e9fa | 2189 | [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( |
ee0a5a90 | 2190 | SOC_ALL, |
8a39e9fa EA |
2191 | .name = "dsi1p", |
2192 | .ctl_reg = CM_DSI1PCTL, | |
2193 | .div_reg = CM_DSI1PDIV, | |
2194 | .int_bits = 0, | |
3f919581 EA |
2195 | .frac_bits = 0, |
2196 | .tcnt_mux = 13), | |
d3d6f15f | 2197 | |
56eb3a2e | 2198 | /* the gates */ |
3b15afef MS |
2199 | |
2200 | /* | |
2201 | * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if | |
2202 | * you have the debug bit set in the power manager, which we | |
2203 | * don't bother exposing) are individual gates off of the | |
2204 | * non-stop vpu clock. | |
2205 | */ | |
56eb3a2e | 2206 | [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( |
ee0a5a90 | 2207 | SOC_ALL, |
3b15afef MS |
2208 | .name = "peri_image", |
2209 | .parent = "vpu", | |
2210 | .ctl_reg = CM_PERIICTL), | |
56eb3a2e MS |
2211 | }; |
2212 | ||
9e400c5c EA |
2213 | /* |
2214 | * Permanently take a reference on the parent of the SDRAM clock. | |
2215 | * | |
2216 | * While the SDRAM is being driven by its dedicated PLL most of the | |
2217 | * time, there is a little loop running in the firmware that | |
2218 | * periodically switches the SDRAM to using our CM clock to do PVT | |
2219 | * recalibration, with the assumption that the previously configured | |
2220 | * SDRAM parent is still enabled and running. | |
2221 | */ | |
2222 | static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) | |
2223 | { | |
2224 | struct clk *parent = clk_get_parent(sdc); | |
2225 | ||
2226 | if (IS_ERR(parent)) | |
2227 | return PTR_ERR(parent); | |
2228 | ||
2229 | return clk_prepare_enable(parent); | |
2230 | } | |
2231 | ||
41691b88 EA |
2232 | static int bcm2835_clk_probe(struct platform_device *pdev) |
2233 | { | |
2234 | struct device *dev = &pdev->dev; | |
b19f009d | 2235 | struct clk_hw **hws; |
41691b88 | 2236 | struct bcm2835_cprman *cprman; |
56eb3a2e MS |
2237 | const struct bcm2835_clk_desc *desc; |
2238 | const size_t asize = ARRAY_SIZE(clk_desc_array); | |
ee0a5a90 | 2239 | const struct cprman_plat_data *pdata; |
56eb3a2e | 2240 | size_t i; |
9e400c5c | 2241 | int ret; |
41691b88 | 2242 | |
ee0a5a90 SW |
2243 | pdata = of_device_get_match_data(&pdev->dev); |
2244 | if (!pdata) | |
2245 | return -ENODEV; | |
2246 | ||
0ed2dd03 KC |
2247 | cprman = devm_kzalloc(dev, |
2248 | struct_size(cprman, onecell.hws, asize), | |
56eb3a2e | 2249 | GFP_KERNEL); |
41691b88 EA |
2250 | if (!cprman) |
2251 | return -ENOMEM; | |
2252 | ||
2253 | spin_lock_init(&cprman->regs_lock); | |
2254 | cprman->dev = dev; | |
4d3a3695 | 2255 | cprman->regs = devm_platform_ioremap_resource(pdev, 0); |
41691b88 EA |
2256 | if (IS_ERR(cprman->regs)) |
2257 | return PTR_ERR(cprman->regs); | |
2258 | ||
8a39e9fa EA |
2259 | memcpy(cprman->real_parent_names, cprman_parent_names, |
2260 | sizeof(cprman_parent_names)); | |
2261 | of_clk_parent_fill(dev->of_node, cprman->real_parent_names, | |
2262 | ARRAY_SIZE(cprman_parent_names)); | |
2263 | ||
2264 | /* | |
2265 | * Make sure the external oscillator has been registered. | |
2266 | * | |
2267 | * The other (DSI) clocks are not present on older device | |
2268 | * trees, which we still need to support for backwards | |
2269 | * compatibility. | |
2270 | */ | |
2271 | if (!cprman->real_parent_names[0]) | |
41691b88 EA |
2272 | return -ENODEV; |
2273 | ||
2274 | platform_set_drvdata(pdev, cprman); | |
2275 | ||
b19f009d | 2276 | cprman->onecell.num = asize; |
f34e4651 | 2277 | cprman->soc = pdata->soc; |
b19f009d | 2278 | hws = cprman->onecell.hws; |
41691b88 | 2279 | |
56eb3a2e MS |
2280 | for (i = 0; i < asize; i++) { |
2281 | desc = &clk_desc_array[i]; | |
ee0a5a90 SW |
2282 | if (desc->clk_register && desc->data && |
2283 | (desc->supported & pdata->soc)) { | |
b19f009d | 2284 | hws[i] = desc->clk_register(cprman, desc->data); |
ee0a5a90 | 2285 | } |
56eb3a2e | 2286 | } |
cfbab8fb | 2287 | |
b19f009d | 2288 | ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); |
9e400c5c EA |
2289 | if (ret) |
2290 | return ret; | |
2291 | ||
b19f009d SB |
2292 | return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, |
2293 | &cprman->onecell); | |
41691b88 EA |
2294 | } |
2295 | ||
ee0a5a90 SW |
2296 | static const struct cprman_plat_data cprman_bcm2835_plat_data = { |
2297 | .soc = SOC_BCM2835, | |
2298 | }; | |
2299 | ||
42de9ad4 SW |
2300 | static const struct cprman_plat_data cprman_bcm2711_plat_data = { |
2301 | .soc = SOC_BCM2711, | |
2302 | }; | |
2303 | ||
41691b88 | 2304 | static const struct of_device_id bcm2835_clk_of_match[] = { |
ee0a5a90 | 2305 | { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data }, |
42de9ad4 | 2306 | { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data }, |
41691b88 EA |
2307 | {} |
2308 | }; | |
2309 | MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); | |
2310 | ||
2311 | static struct platform_driver bcm2835_clk_driver = { | |
2312 | .driver = { | |
2313 | .name = "bcm2835-clk", | |
2314 | .of_match_table = bcm2835_clk_of_match, | |
2315 | }, | |
2316 | .probe = bcm2835_clk_probe, | |
2317 | }; | |
2318 | ||
2319 | builtin_platform_driver(bcm2835_clk_driver); | |
2320 | ||
2321 | MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); | |
2322 | MODULE_DESCRIPTION("BCM2835 clock driver"); | |
819ed0ad | 2323 | MODULE_LICENSE("GPL"); |