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01e2113d AB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | #include <linux/clk-provider.h> | |
3 | #include <linux/mfd/syscon.h> | |
4 | #include <linux/slab.h> | |
5 | ||
6 | #include <dt-bindings/clock/at91.h> | |
7 | ||
8 | #include "pmc.h" | |
9 | ||
10 | static DEFINE_SPINLOCK(pmc_pll_lock); | |
7a110b91 | 11 | static DEFINE_SPINLOCK(mck_lock); |
01e2113d AB |
12 | |
13 | static const struct clk_master_characteristics mck_characteristics = { | |
14 | .output = { .min = 140000000, .max = 200000000 }, | |
15 | .divisors = { 1, 2, 4, 3 }, | |
16 | .have_div3_pres = 1, | |
17 | }; | |
18 | ||
19 | static const struct clk_master_layout sam9x60_master_layout = { | |
20 | .mask = 0x373, | |
21 | .pres_shift = 4, | |
22 | .offset = 0x28, | |
23 | }; | |
24 | ||
7b4c162e | 25 | static const struct clk_range plla_outputs[] = { |
390227dc | 26 | { .min = 2343750, .max = 1200000000 }, |
01e2113d AB |
27 | }; |
28 | ||
29 | static const struct clk_pll_characteristics plla_characteristics = { | |
30 | .input = { .min = 12000000, .max = 48000000 }, | |
31 | .num_output = ARRAY_SIZE(plla_outputs), | |
32 | .output = plla_outputs, | |
33 | }; | |
34 | ||
7b4c162e | 35 | static const struct clk_range upll_outputs[] = { |
01e2113d AB |
36 | { .min = 300000000, .max = 500000000 }, |
37 | }; | |
38 | ||
39 | static const struct clk_pll_characteristics upll_characteristics = { | |
40 | .input = { .min = 12000000, .max = 48000000 }, | |
41 | .num_output = ARRAY_SIZE(upll_outputs), | |
42 | .output = upll_outputs, | |
43 | .upll = true, | |
44 | }; | |
45 | ||
43b1bb4a CB |
46 | static const struct clk_pll_layout pll_frac_layout = { |
47 | .mul_mask = GENMASK(31, 24), | |
48 | .frac_mask = GENMASK(21, 0), | |
49 | .mul_shift = 24, | |
50 | .frac_shift = 0, | |
51 | }; | |
52 | ||
53 | static const struct clk_pll_layout pll_div_layout = { | |
54 | .div_mask = GENMASK(7, 0), | |
55 | .endiv_mask = BIT(29), | |
56 | .div_shift = 0, | |
57 | .endiv_shift = 29, | |
58 | }; | |
59 | ||
01e2113d | 60 | static const struct clk_programmable_layout sam9x60_programmable_layout = { |
2200ab6a | 61 | .pres_mask = 0xff, |
01e2113d AB |
62 | .pres_shift = 8, |
63 | .css_mask = 0x1f, | |
64 | .have_slck_mck = 0, | |
66d9f521 | 65 | .is_pres_direct = 1, |
01e2113d AB |
66 | }; |
67 | ||
68 | static const struct clk_pcr_layout sam9x60_pcr_layout = { | |
69 | .offset = 0x88, | |
70 | .cmd = BIT(31), | |
71 | .gckcss_mask = GENMASK(12, 8), | |
72 | .pid_mask = GENMASK(6, 0), | |
73 | }; | |
74 | ||
75 | static const struct { | |
76 | char *n; | |
77 | char *p; | |
68b3b6f1 | 78 | unsigned long flags; |
01e2113d AB |
79 | u8 id; |
80 | } sam9x60_systemck[] = { | |
68b3b6f1 CB |
81 | /* |
82 | * ddrck feeds DDR controller and is enabled by bootloader thus we need | |
83 | * to keep it enabled in case there is no Linux consumer for it. | |
84 | */ | |
85 | { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, | |
01e2113d AB |
86 | { .n = "uhpck", .p = "usbck", .id = 6 }, |
87 | { .n = "pck0", .p = "prog0", .id = 8 }, | |
88 | { .n = "pck1", .p = "prog1", .id = 9 }, | |
7a110b91 | 89 | { .n = "qspick", .p = "masterck_div", .id = 19 }, |
01e2113d AB |
90 | }; |
91 | ||
92 | static const struct { | |
93 | char *n; | |
68b3b6f1 | 94 | unsigned long flags; |
01e2113d AB |
95 | u8 id; |
96 | } sam9x60_periphck[] = { | |
97 | { .n = "pioA_clk", .id = 2, }, | |
98 | { .n = "pioB_clk", .id = 3, }, | |
99 | { .n = "pioC_clk", .id = 4, }, | |
100 | { .n = "flex0_clk", .id = 5, }, | |
101 | { .n = "flex1_clk", .id = 6, }, | |
102 | { .n = "flex2_clk", .id = 7, }, | |
103 | { .n = "flex3_clk", .id = 8, }, | |
104 | { .n = "flex6_clk", .id = 9, }, | |
105 | { .n = "flex7_clk", .id = 10, }, | |
106 | { .n = "flex8_clk", .id = 11, }, | |
107 | { .n = "sdmmc0_clk", .id = 12, }, | |
108 | { .n = "flex4_clk", .id = 13, }, | |
109 | { .n = "flex5_clk", .id = 14, }, | |
110 | { .n = "flex9_clk", .id = 15, }, | |
111 | { .n = "flex10_clk", .id = 16, }, | |
112 | { .n = "tcb0_clk", .id = 17, }, | |
113 | { .n = "pwm_clk", .id = 18, }, | |
114 | { .n = "adc_clk", .id = 19, }, | |
115 | { .n = "dma0_clk", .id = 20, }, | |
116 | { .n = "matrix_clk", .id = 21, }, | |
117 | { .n = "uhphs_clk", .id = 22, }, | |
118 | { .n = "udphs_clk", .id = 23, }, | |
119 | { .n = "macb0_clk", .id = 24, }, | |
120 | { .n = "lcd_clk", .id = 25, }, | |
121 | { .n = "sdmmc1_clk", .id = 26, }, | |
122 | { .n = "macb1_clk", .id = 27, }, | |
123 | { .n = "ssc_clk", .id = 28, }, | |
124 | { .n = "can0_clk", .id = 29, }, | |
125 | { .n = "can1_clk", .id = 30, }, | |
126 | { .n = "flex11_clk", .id = 32, }, | |
127 | { .n = "flex12_clk", .id = 33, }, | |
128 | { .n = "i2s_clk", .id = 34, }, | |
129 | { .n = "qspi_clk", .id = 35, }, | |
130 | { .n = "gfx2d_clk", .id = 36, }, | |
131 | { .n = "pit64b_clk", .id = 37, }, | |
132 | { .n = "trng_clk", .id = 38, }, | |
133 | { .n = "aes_clk", .id = 39, }, | |
134 | { .n = "tdes_clk", .id = 40, }, | |
135 | { .n = "sha_clk", .id = 41, }, | |
136 | { .n = "classd_clk", .id = 42, }, | |
137 | { .n = "isi_clk", .id = 43, }, | |
138 | { .n = "pioD_clk", .id = 44, }, | |
139 | { .n = "tcb1_clk", .id = 45, }, | |
140 | { .n = "dbgu_clk", .id = 47, }, | |
68b3b6f1 CB |
141 | /* |
142 | * mpddr_clk feeds DDR controller and is enabled by bootloader thus we | |
143 | * need to keep it enabled in case there is no Linux consumer for it. | |
144 | */ | |
145 | { .n = "mpddr_clk", .id = 49, .flags = CLK_IS_CRITICAL }, | |
01e2113d AB |
146 | }; |
147 | ||
148 | static const struct { | |
149 | char *n; | |
150 | u8 id; | |
151 | struct clk_range r; | |
01e2113d AB |
152 | } sam9x60_gck[] = { |
153 | { .n = "flex0_gclk", .id = 5, }, | |
154 | { .n = "flex1_gclk", .id = 6, }, | |
155 | { .n = "flex2_gclk", .id = 7, }, | |
156 | { .n = "flex3_gclk", .id = 8, }, | |
157 | { .n = "flex6_gclk", .id = 9, }, | |
158 | { .n = "flex7_gclk", .id = 10, }, | |
159 | { .n = "flex8_gclk", .id = 11, }, | |
160 | { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, }, | |
161 | { .n = "flex4_gclk", .id = 13, }, | |
162 | { .n = "flex5_gclk", .id = 14, }, | |
163 | { .n = "flex9_gclk", .id = 15, }, | |
164 | { .n = "flex10_gclk", .id = 16, }, | |
165 | { .n = "tcb0_gclk", .id = 17, }, | |
166 | { .n = "adc_gclk", .id = 19, }, | |
167 | { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, }, | |
168 | { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, }, | |
169 | { .n = "flex11_gclk", .id = 32, }, | |
170 | { .n = "flex12_gclk", .id = 33, }, | |
5bf7f4a2 | 171 | { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, }, |
01e2113d | 172 | { .n = "pit64b_gclk", .id = 37, }, |
5bf7f4a2 | 173 | { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, }, |
01e2113d AB |
174 | { .n = "tcb1_gclk", .id = 45, }, |
175 | { .n = "dbgu_gclk", .id = 47, }, | |
176 | }; | |
177 | ||
178 | static void __init sam9x60_pmc_setup(struct device_node *np) | |
179 | { | |
180 | struct clk_range range = CLK_RANGE(0, 0); | |
181 | const char *td_slck_name, *md_slck_name, *mainxtal_name; | |
182 | struct pmc_data *sam9x60_pmc; | |
183 | const char *parent_names[6]; | |
43b1bb4a | 184 | struct clk_hw *main_osc_hw; |
01e2113d AB |
185 | struct regmap *regmap; |
186 | struct clk_hw *hw; | |
187 | int i; | |
01e2113d AB |
188 | |
189 | i = of_property_match_string(np, "clock-names", "td_slck"); | |
190 | if (i < 0) | |
191 | return; | |
192 | ||
193 | td_slck_name = of_clk_get_parent_name(np, i); | |
194 | ||
195 | i = of_property_match_string(np, "clock-names", "md_slck"); | |
196 | if (i < 0) | |
197 | return; | |
198 | ||
199 | md_slck_name = of_clk_get_parent_name(np, i); | |
200 | ||
201 | i = of_property_match_string(np, "clock-names", "main_xtal"); | |
202 | if (i < 0) | |
203 | return; | |
204 | mainxtal_name = of_clk_get_parent_name(np, i); | |
205 | ||
153bc1c6 | 206 | regmap = device_node_to_regmap(np); |
01e2113d AB |
207 | if (IS_ERR(regmap)) |
208 | return; | |
209 | ||
03a1ee1d | 210 | sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1, |
01e2113d AB |
211 | nck(sam9x60_systemck), |
212 | nck(sam9x60_periphck), | |
99767cd4 | 213 | nck(sam9x60_gck), 8); |
01e2113d AB |
214 | if (!sam9x60_pmc) |
215 | return; | |
216 | ||
172e7dde | 217 | hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, |
01e2113d AB |
218 | 50000000); |
219 | if (IS_ERR(hw)) | |
220 | goto err_free; | |
221 | ||
b5105e37 | 222 | hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0); |
01e2113d AB |
223 | if (IS_ERR(hw)) |
224 | goto err_free; | |
43b1bb4a | 225 | main_osc_hw = hw; |
01e2113d AB |
226 | |
227 | parent_names[0] = "main_rc_osc"; | |
228 | parent_names[1] = "main_osc"; | |
b5105e37 | 229 | hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); |
01e2113d AB |
230 | if (IS_ERR(hw)) |
231 | goto err_free; | |
232 | ||
233 | sam9x60_pmc->chws[PMC_MAIN] = hw; | |
234 | ||
43b1bb4a CB |
235 | hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", |
236 | "mainck", sam9x60_pmc->chws[PMC_MAIN], | |
237 | 0, &plla_characteristics, | |
8dc4af8b CB |
238 | &pll_frac_layout, |
239 | /* | |
240 | * This feeds pllack_divck which | |
241 | * feeds CPU. It should not be | |
242 | * disabled. | |
243 | */ | |
244 | CLK_IS_CRITICAL | CLK_SET_RATE_GATE); | |
43b1bb4a CB |
245 | if (IS_ERR(hw)) |
246 | goto err_free; | |
247 | ||
248 | hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", | |
249 | "pllack_fracck", 0, &plla_characteristics, | |
8dc4af8b CB |
250 | &pll_div_layout, |
251 | /* | |
252 | * This feeds CPU. It should not | |
253 | * be disabled. | |
254 | */ | |
1e229c21 | 255 | CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); |
01e2113d AB |
256 | if (IS_ERR(hw)) |
257 | goto err_free; | |
258 | ||
03a1ee1d MM |
259 | sam9x60_pmc->chws[PMC_PLLACK] = hw; |
260 | ||
43b1bb4a CB |
261 | hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", |
262 | "main_osc", main_osc_hw, 1, | |
263 | &upll_characteristics, | |
8dc4af8b | 264 | &pll_frac_layout, CLK_SET_RATE_GATE); |
43b1bb4a CB |
265 | if (IS_ERR(hw)) |
266 | goto err_free; | |
267 | ||
268 | hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", | |
269 | "upllck_fracck", 1, &upll_characteristics, | |
8dc4af8b CB |
270 | &pll_div_layout, |
271 | CLK_SET_RATE_GATE | | |
272 | CLK_SET_PARENT_GATE | | |
1e229c21 | 273 | CLK_SET_RATE_PARENT, 0); |
01e2113d AB |
274 | if (IS_ERR(hw)) |
275 | goto err_free; | |
276 | ||
277 | sam9x60_pmc->chws[PMC_UTMI] = hw; | |
278 | ||
279 | parent_names[0] = md_slck_name; | |
280 | parent_names[1] = "mainck"; | |
43b1bb4a | 281 | parent_names[2] = "pllack_divck"; |
7a110b91 CB |
282 | hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, |
283 | parent_names, &sam9x60_master_layout, | |
8e842f02 | 284 | &mck_characteristics, &mck_lock); |
7a110b91 CB |
285 | if (IS_ERR(hw)) |
286 | goto err_free; | |
287 | ||
288 | hw = at91_clk_register_master_div(regmap, "masterck_div", | |
289 | "masterck_pres", &sam9x60_master_layout, | |
290 | &mck_characteristics, &mck_lock, | |
1e229c21 | 291 | CLK_SET_RATE_GATE, 0); |
01e2113d AB |
292 | if (IS_ERR(hw)) |
293 | goto err_free; | |
294 | ||
295 | sam9x60_pmc->chws[PMC_MCK] = hw; | |
296 | ||
43b1bb4a CB |
297 | parent_names[0] = "pllack_divck"; |
298 | parent_names[1] = "upllck_divck"; | |
43b203d3 CB |
299 | parent_names[2] = "main_osc"; |
300 | hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); | |
01e2113d AB |
301 | if (IS_ERR(hw)) |
302 | goto err_free; | |
303 | ||
304 | parent_names[0] = md_slck_name; | |
305 | parent_names[1] = td_slck_name; | |
306 | parent_names[2] = "mainck"; | |
7a110b91 | 307 | parent_names[3] = "masterck_div"; |
43b1bb4a CB |
308 | parent_names[4] = "pllack_divck"; |
309 | parent_names[5] = "upllck_divck"; | |
fcedb589 | 310 | for (i = 0; i < 2; i++) { |
01e2113d AB |
311 | char name[6]; |
312 | ||
313 | snprintf(name, sizeof(name), "prog%d", i); | |
314 | ||
315 | hw = at91_clk_register_programmable(regmap, name, | |
316 | parent_names, 6, i, | |
c57aaaa2 CB |
317 | &sam9x60_programmable_layout, |
318 | NULL); | |
01e2113d AB |
319 | if (IS_ERR(hw)) |
320 | goto err_free; | |
99767cd4 MM |
321 | |
322 | sam9x60_pmc->pchws[i] = hw; | |
01e2113d AB |
323 | } |
324 | ||
325 | for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) { | |
326 | hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n, | |
327 | sam9x60_systemck[i].p, | |
68b3b6f1 CB |
328 | sam9x60_systemck[i].id, |
329 | sam9x60_systemck[i].flags); | |
01e2113d AB |
330 | if (IS_ERR(hw)) |
331 | goto err_free; | |
332 | ||
333 | sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw; | |
334 | } | |
335 | ||
336 | for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { | |
337 | hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, | |
338 | &sam9x60_pcr_layout, | |
339 | sam9x60_periphck[i].n, | |
7a110b91 | 340 | "masterck_div", |
01e2113d | 341 | sam9x60_periphck[i].id, |
68b3b6f1 CB |
342 | &range, INT_MIN, |
343 | sam9x60_periphck[i].flags); | |
01e2113d AB |
344 | if (IS_ERR(hw)) |
345 | goto err_free; | |
346 | ||
347 | sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw; | |
348 | } | |
349 | ||
350 | for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { | |
351 | hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, | |
352 | &sam9x60_pcr_layout, | |
353 | sam9x60_gck[i].n, | |
22a1dfe9 | 354 | parent_names, NULL, 6, |
01e2113d | 355 | sam9x60_gck[i].id, |
64c9247b | 356 | &sam9x60_gck[i].r, INT_MIN); |
01e2113d AB |
357 | if (IS_ERR(hw)) |
358 | goto err_free; | |
359 | ||
360 | sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw; | |
361 | } | |
362 | ||
363 | of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc); | |
364 | ||
365 | return; | |
366 | ||
367 | err_free: | |
7425f246 | 368 | kfree(sam9x60_pmc); |
01e2113d AB |
369 | } |
370 | /* Some clks are used for a clocksource */ | |
371 | CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup); |