Commit | Line | Data |
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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
0ad6125b BB |
2 | /* |
3 | * drivers/clk/at91/pmc.h | |
4 | * | |
5 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | |
0ad6125b BB |
6 | */ |
7 | ||
8 | #ifndef __PMC_H_ | |
9 | #define __PMC_H_ | |
10 | ||
11 | #include <linux/io.h> | |
12 | #include <linux/irqdomain.h> | |
863a81c3 | 13 | #include <linux/regmap.h> |
0ad6125b BB |
14 | #include <linux/spinlock.h> |
15 | ||
36971566 CB |
16 | #include <dt-bindings/clock/at91.h> |
17 | ||
1bdf0232 BB |
18 | extern spinlock_t pmc_pcr_lock; |
19 | ||
b00cd8e4 AB |
20 | struct pmc_data { |
21 | unsigned int ncore; | |
22 | struct clk_hw **chws; | |
23 | unsigned int nsystem; | |
24 | struct clk_hw **shws; | |
25 | unsigned int nperiph; | |
26 | struct clk_hw **phws; | |
27 | unsigned int ngck; | |
28 | struct clk_hw **ghws; | |
99767cd4 MM |
29 | unsigned int npck; |
30 | struct clk_hw **pchws; | |
7425f246 MM |
31 | |
32 | struct clk_hw *hwtable[]; | |
b00cd8e4 AB |
33 | }; |
34 | ||
0ad6125b BB |
35 | struct clk_range { |
36 | unsigned long min; | |
37 | unsigned long max; | |
38 | }; | |
39 | ||
40 | #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,} | |
41 | ||
b2e39dc0 | 42 | struct clk_master_layout { |
e5be5370 | 43 | u32 offset; |
b2e39dc0 AB |
44 | u32 mask; |
45 | u8 pres_shift; | |
46 | }; | |
47 | ||
48 | extern const struct clk_master_layout at91rm9200_master_layout; | |
49 | extern const struct clk_master_layout at91sam9x5_master_layout; | |
50 | ||
51 | struct clk_master_characteristics { | |
52 | struct clk_range output; | |
e26b3006 | 53 | u32 divisors[5]; |
b2e39dc0 AB |
54 | u8 have_div3_pres; |
55 | }; | |
56 | ||
57 | struct clk_pll_layout { | |
58 | u32 pllr_mask; | |
43b1bb4a CB |
59 | u32 mul_mask; |
60 | u32 frac_mask; | |
61 | u32 div_mask; | |
62 | u32 endiv_mask; | |
b2e39dc0 | 63 | u8 mul_shift; |
43b1bb4a CB |
64 | u8 frac_shift; |
65 | u8 div_shift; | |
66 | u8 endiv_shift; | |
b2e39dc0 AB |
67 | }; |
68 | ||
69 | extern const struct clk_pll_layout at91rm9200_pll_layout; | |
70 | extern const struct clk_pll_layout at91sam9g45_pll_layout; | |
71 | extern const struct clk_pll_layout at91sam9g20_pllb_layout; | |
72 | extern const struct clk_pll_layout sama5d3_pll_layout; | |
73 | ||
74 | struct clk_pll_characteristics { | |
75 | struct clk_range input; | |
76 | int num_output; | |
7b4c162e | 77 | const struct clk_range *output; |
b2e39dc0 AB |
78 | u16 *icpll; |
79 | u8 *out; | |
a436c2a4 | 80 | u8 upll : 1; |
b2e39dc0 AB |
81 | }; |
82 | ||
83 | struct clk_programmable_layout { | |
45b06682 | 84 | u8 pres_mask; |
b2e39dc0 AB |
85 | u8 pres_shift; |
86 | u8 css_mask; | |
87 | u8 have_slck_mck; | |
45b06682 | 88 | u8 is_pres_direct; |
b2e39dc0 AB |
89 | }; |
90 | ||
91 | extern const struct clk_programmable_layout at91rm9200_programmable_layout; | |
92 | extern const struct clk_programmable_layout at91sam9g45_programmable_layout; | |
93 | extern const struct clk_programmable_layout at91sam9x5_programmable_layout; | |
94 | ||
cb4f4949 AB |
95 | struct clk_pcr_layout { |
96 | u32 offset; | |
97 | u32 cmd; | |
98 | u32 div_mask; | |
99 | u32 gckcss_mask; | |
100 | u32 pid_mask; | |
101 | }; | |
102 | ||
36971566 CB |
103 | /** |
104 | * struct at91_clk_pms - Power management state for AT91 clock | |
105 | * @rate: clock rate | |
106 | * @parent_rate: clock parent rate | |
107 | * @status: clock status (enabled or disabled) | |
108 | * @parent: clock parent index | |
109 | */ | |
110 | struct at91_clk_pms { | |
111 | unsigned long rate; | |
112 | unsigned long parent_rate; | |
113 | unsigned int status; | |
114 | unsigned int parent; | |
115 | }; | |
116 | ||
cb4f4949 AB |
117 | #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) |
118 | #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) | |
119 | ||
b00cd8e4 AB |
120 | #define ndck(a, s) (a[s - 1].id + 1) |
121 | #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) | |
122 | struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, | |
99767cd4 MM |
123 | unsigned int nperiph, unsigned int ngck, |
124 | unsigned int npck); | |
b00cd8e4 | 125 | |
0ad6125b BB |
126 | int of_at91_get_clk_range(struct device_node *np, const char *propname, |
127 | struct clk_range *range); | |
128 | ||
b2e39dc0 AB |
129 | struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data); |
130 | ||
131 | struct clk_hw * __init | |
132 | at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, | |
133 | const char *parent_name); | |
134 | ||
135 | struct clk_hw * __init | |
136 | at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, | |
137 | const char *parent_name); | |
138 | ||
139 | struct clk_hw * __init | |
140 | at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, | |
141 | const char *parent_name); | |
142 | ||
143 | struct clk_hw * __init | |
144 | at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, | |
e4cfb823 | 145 | const struct clk_pcr_layout *layout, |
b2e39dc0 | 146 | const char *name, const char **parent_names, |
22a1dfe9 | 147 | u32 *mux_table, u8 num_parents, u8 id, |
64c9247b | 148 | const struct clk_range *range, int chg_pid); |
b2e39dc0 AB |
149 | |
150 | struct clk_hw * __init | |
151 | at91_clk_register_h32mx(struct regmap *regmap, const char *name, | |
152 | const char *parent_name); | |
153 | ||
154 | struct clk_hw * __init | |
155 | at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, | |
156 | const char * const *parent_names, | |
157 | unsigned int num_parents, u8 bus_id); | |
158 | ||
159 | struct clk_hw * __init | |
160 | at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, | |
161 | u32 frequency, u32 accuracy); | |
162 | struct clk_hw * __init | |
163 | at91_clk_register_main_osc(struct regmap *regmap, const char *name, | |
164 | const char *parent_name, bool bypass); | |
165 | struct clk_hw * __init | |
166 | at91_clk_register_rm9200_main(struct regmap *regmap, | |
167 | const char *name, | |
168 | const char *parent_name); | |
169 | struct clk_hw * __init | |
170 | at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, | |
171 | const char **parent_names, int num_parents); | |
172 | ||
173 | struct clk_hw * __init | |
7a110b91 CB |
174 | at91_clk_register_master_pres(struct regmap *regmap, const char *name, |
175 | int num_parents, const char **parent_names, | |
176 | const struct clk_master_layout *layout, | |
177 | const struct clk_master_characteristics *characteristics, | |
8e842f02 | 178 | spinlock_t *lock); |
7a110b91 CB |
179 | |
180 | struct clk_hw * __init | |
181 | at91_clk_register_master_div(struct regmap *regmap, const char *name, | |
182 | const char *parent_names, | |
183 | const struct clk_master_layout *layout, | |
184 | const struct clk_master_characteristics *characteristics, | |
7029db09 | 185 | spinlock_t *lock, u32 flags, u32 safe_div); |
b2e39dc0 | 186 | |
75c88143 CB |
187 | struct clk_hw * __init |
188 | at91_clk_sama7g5_register_master(struct regmap *regmap, | |
189 | const char *name, int num_parents, | |
190 | const char **parent_names, u32 *mux_table, | |
191 | spinlock_t *lock, u8 id, bool critical, | |
192 | int chg_pid); | |
193 | ||
b2e39dc0 AB |
194 | struct clk_hw * __init |
195 | at91_clk_register_peripheral(struct regmap *regmap, const char *name, | |
196 | const char *parent_name, u32 id); | |
197 | struct clk_hw * __init | |
198 | at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, | |
cb4f4949 | 199 | const struct clk_pcr_layout *layout, |
b2e39dc0 | 200 | const char *name, const char *parent_name, |
b4c115c7 | 201 | u32 id, const struct clk_range *range, |
68b3b6f1 | 202 | int chg_pid, unsigned long flags); |
b2e39dc0 AB |
203 | |
204 | struct clk_hw * __init | |
205 | at91_clk_register_pll(struct regmap *regmap, const char *name, | |
206 | const char *parent_name, u8 id, | |
207 | const struct clk_pll_layout *layout, | |
208 | const struct clk_pll_characteristics *characteristics); | |
209 | struct clk_hw * __init | |
210 | at91_clk_register_plldiv(struct regmap *regmap, const char *name, | |
211 | const char *parent_name); | |
212 | ||
a436c2a4 | 213 | struct clk_hw * __init |
43b1bb4a CB |
214 | sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, |
215 | const char *name, const char *parent_name, u8 id, | |
216 | const struct clk_pll_characteristics *characteristics, | |
1e229c21 CB |
217 | const struct clk_pll_layout *layout, u32 flags, |
218 | u32 safe_div); | |
43b1bb4a CB |
219 | |
220 | struct clk_hw * __init | |
221 | sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, | |
222 | const char *name, const char *parent_name, | |
223 | struct clk_hw *parent_hw, u8 id, | |
224 | const struct clk_pll_characteristics *characteristics, | |
8dc4af8b | 225 | const struct clk_pll_layout *layout, u32 flags); |
a436c2a4 | 226 | |
b2e39dc0 AB |
227 | struct clk_hw * __init |
228 | at91_clk_register_programmable(struct regmap *regmap, const char *name, | |
229 | const char **parent_names, u8 num_parents, u8 id, | |
c57aaaa2 CB |
230 | const struct clk_programmable_layout *layout, |
231 | u32 *mux_table); | |
b2e39dc0 AB |
232 | |
233 | struct clk_hw * __init | |
234 | at91_clk_register_sam9260_slow(struct regmap *regmap, | |
235 | const char *name, | |
236 | const char **parent_names, | |
237 | int num_parents); | |
238 | ||
239 | struct clk_hw * __init | |
240 | at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, | |
241 | const char **parent_names, u8 num_parents); | |
242 | ||
243 | struct clk_hw * __init | |
244 | at91_clk_register_system(struct regmap *regmap, const char *name, | |
68b3b6f1 | 245 | const char *parent_name, u8 id, unsigned long flags); |
b2e39dc0 AB |
246 | |
247 | struct clk_hw * __init | |
248 | at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, | |
249 | const char **parent_names, u8 num_parents); | |
250 | struct clk_hw * __init | |
251 | at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, | |
252 | const char *parent_name); | |
253 | struct clk_hw * __init | |
2423eeae AB |
254 | sam9x60_clk_register_usb(struct regmap *regmap, const char *name, |
255 | const char **parent_names, u8 num_parents); | |
256 | struct clk_hw * __init | |
b2e39dc0 AB |
257 | at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, |
258 | const char *parent_name, const u32 *divisors); | |
259 | ||
260 | struct clk_hw * __init | |
261 | at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr, | |
262 | const char *name, const char *parent_name); | |
263 | ||
ef396df9 CB |
264 | struct clk_hw * __init |
265 | at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, | |
266 | const char *parent_name); | |
267 | ||
0ad6125b | 268 | #endif /* __PMC_H_ */ |