[linux-block.git] / drivers / clk / at91 / clk-pll.c

/*
 *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/at91_pmc.h>
#include <linux/of.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include "pmc.h"

#define PLL_STATUS_MASK(id)	(1 << (1 + (id)))
#define PLL_REG(id)		(AT91_CKGR_PLLAR + ((id) * 4))
#define PLL_DIV_MASK		0xff
#define PLL_DIV_MAX		PLL_DIV_MASK
#define PLL_DIV(reg)		((reg) & PLL_DIV_MASK)
#define PLL_MUL(reg, layout)	(((reg) >> (layout)->mul_shift) & \
				 (layout)->mul_mask)
#define PLL_MUL_MIN		2
#define PLL_MUL_MASK(layout)	((layout)->mul_mask)
#define PLL_MUL_MAX(layout)	(PLL_MUL_MASK(layout) + 1)
#define PLL_ICPR_SHIFT(id)	((id) * 16)
#define PLL_ICPR_MASK(id)	(0xffff << PLL_ICPR_SHIFT(id))
#define PLL_MAX_COUNT		0x3f
#define PLL_COUNT_SHIFT		8
#define PLL_OUT_SHIFT		14
#define PLL_MAX_ID		1

struct clk_pll_characteristics {
	struct clk_range input;
	int num_output;
	struct clk_range *output;
	u16 *icpll;
	u8 *out;
};

struct clk_pll_layout {
	u32 pllr_mask;
	u16 mul_mask;
	u8 mul_shift;
};

#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)

struct clk_pll {
	struct clk_hw hw;
	struct regmap *regmap;
	u8 id;
	u8 div;
	u8 range;
	u16 mul;
	const struct clk_pll_layout *layout;
	const struct clk_pll_characteristics *characteristics;
};

static inline bool clk_pll_ready(struct regmap *regmap, int id)
{
	unsigned int status;

	regmap_read(regmap, AT91_PMC_SR, &status);

	return status & PLL_STATUS_MASK(id) ? 1 : 0;
}

static int clk_pll_prepare(struct clk_hw *hw)
{
	struct clk_pll *pll = to_clk_pll(hw);
	struct regmap *regmap = pll->regmap;
	const struct clk_pll_layout *layout = pll->layout;
	const struct clk_pll_characteristics *characteristics =
							pll->characteristics;
	u8 id = pll->id;
	u32 mask = PLL_STATUS_MASK(id);
	int offset = PLL_REG(id);
	u8 out = 0;
	unsigned int pllr;
	unsigned int status;
	u8 div;
	u16 mul;

	regmap_read(regmap, offset, &pllr);
	div = PLL_DIV(pllr);
	mul = PLL_MUL(pllr, layout);

	regmap_read(regmap, AT91_PMC_SR, &status);
	if ((status & mask) &&
	    (div == pll->div && mul == pll->mul))
		return 0;

	if (characteristics->out)
		out = characteristics->out[pll->range];

	if (characteristics->icpll)
		regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
			characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));

	regmap_update_bits(regmap, offset, layout->pllr_mask,
			pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
			(out << PLL_OUT_SHIFT) |
			((pll->mul & layout->mul_mask) << layout->mul_shift));

	while (!clk_pll_ready(regmap, pll->id))
		cpu_relax();

	return 0;
}

static int clk_pll_is_prepared(struct clk_hw *hw)
{
	struct clk_pll *pll = to_clk_pll(hw);

	return clk_pll_ready(pll->regmap, pll->id);
}

static void clk_pll_unprepare(struct clk_hw *hw)
{
	struct clk_pll *pll = to_clk_pll(hw);
	unsigned int mask = pll->layout->pllr_mask;

	regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
}

static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
					 unsigned long parent_rate)
{
	struct clk_pll *pll = to_clk_pll(hw);

	return (parent_rate / pll->div) * (pll->mul + 1);
}

static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
				     unsigned long parent_rate,
				     u32 *div, u32 *mul,
				     u32 *index) {
	const struct clk_pll_layout *layout = pll->layout;
	const struct clk_pll_characteristics *characteristics =
							pll->characteristics;
	unsigned long bestremainder = ULONG_MAX;
	unsigned long maxdiv, mindiv, tmpdiv;
	long bestrate = -ERANGE;
	unsigned long bestdiv;
	unsigned long bestmul;
	int i = 0;

	/* Check if parent_rate is a valid input rate */
	if (parent_rate < characteristics->input.min)
		return -ERANGE;

	/*
	 * Calculate minimum divider based on the minimum multiplier, the
	 * parent_rate and the requested rate.
	 * Should always be 2 according to the input and output characteristics
	 * of the PLL blocks.
	 */
	mindiv = (parent_rate * PLL_MUL_MIN) / rate;
	if (!mindiv)
		mindiv = 1;

	if (parent_rate > characteristics->input.max) {
		tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
		if (tmpdiv > PLL_DIV_MAX)
			return -ERANGE;

		if (tmpdiv > mindiv)
			mindiv = tmpdiv;
	}

	/*
	 * Calculate the maximum divider which is limited by PLL register
	 * layout (limited by the MUL or DIV field size).
	 */
	maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
	if (maxdiv > PLL_DIV_MAX)
		maxdiv = PLL_DIV_MAX;

	/*
	 * Iterate over the acceptable divider values to find the best
	 * divider/multiplier pair (the one that generates the closest
	 * rate to the requested one).
	 */
	for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
		unsigned long remainder;
		unsigned long tmprate;
		unsigned long tmpmul;

		/*
		 * Calculate the multiplier associated with the current
		 * divider that provide the closest rate to the requested one.
		 */
		tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
		tmprate = (parent_rate / tmpdiv) * tmpmul;
		if (tmprate > rate)
			remainder = tmprate - rate;
		else
			remainder = rate - tmprate;

		/*
		 * Compare the remainder with the best remainder found until
		 * now and elect a new best multiplier/divider pair if the
		 * current remainder is smaller than the best one.
		 */
		if (remainder < bestremainder) {
			bestremainder = remainder;
			bestdiv = tmpdiv;
			bestmul = tmpmul;
			bestrate = tmprate;
		}

		/*
		 * We've found a perfect match!
		 * Stop searching now and use this multiplier/divider pair.
		 */
		if (!remainder)
			break;
	}

	/* We haven't found any multiplier/divider pair => return -ERANGE */
	if (bestrate < 0)
		return bestrate;

	/* Check if bestrate is a valid output rate  */
	for (i = 0; i < characteristics->num_output; i++) {
		if (bestrate >= characteristics->output[i].min &&
		    bestrate <= characteristics->output[i].max)
			break;
	}

	if (i >= characteristics->num_output)
		return -ERANGE;

	if (div)
		*div = bestdiv;
	if (mul)
		*mul = bestmul - 1;
	if (index)
		*index = i;

	return bestrate;
}

static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
					unsigned long *parent_rate)
{
	struct clk_pll *pll = to_clk_pll(hw);

	return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
					NULL, NULL, NULL);
}

static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
			    unsigned long parent_rate)
{
	struct clk_pll *pll = to_clk_pll(hw);
	long ret;
	u32 div;
	u32 mul;
	u32 index;

	ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
				       &div, &mul, &index);
	if (ret < 0)
		return ret;

	pll->range = index;
	pll->div = div;
	pll->mul = mul;

	return 0;
}

static const struct clk_ops pll_ops = {
	.prepare = clk_pll_prepare,
	.unprepare = clk_pll_unprepare,
	.is_prepared = clk_pll_is_prepared,
	.recalc_rate = clk_pll_recalc_rate,
	.round_rate = clk_pll_round_rate,
	.set_rate = clk_pll_set_rate,
};

static struct clk_hw * __init
at91_clk_register_pll(struct regmap *regmap, const char *name,
		      const char *parent_name, u8 id,
		      const struct clk_pll_layout *layout,
		      const struct clk_pll_characteristics *characteristics)
{
	struct clk_pll *pll;
	struct clk_hw *hw;
	struct clk_init_data init;
	int offset = PLL_REG(id);
	unsigned int pllr;
	int ret;

	if (id > PLL_MAX_ID)
		return ERR_PTR(-EINVAL);

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (!pll)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &pll_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = CLK_SET_RATE_GATE;

	pll->id = id;
	pll->hw.init = &init;
	pll->layout = layout;
	pll->characteristics = characteristics;
	pll->regmap = regmap;
	regmap_read(regmap, offset, &pllr);
	pll->div = PLL_DIV(pllr);
	pll->mul = PLL_MUL(pllr, layout);

	hw = &pll->hw;
	ret = clk_hw_register(NULL, &pll->hw);
	if (ret) {
		kfree(pll);
		hw = ERR_PTR(ret);
	}

	return hw;
}


static const struct clk_pll_layout at91rm9200_pll_layout = {
	.pllr_mask = 0x7FFFFFF,
	.mul_shift = 16,
	.mul_mask = 0x7FF,
};

static const struct clk_pll_layout at91sam9g45_pll_layout = {
	.pllr_mask = 0xFFFFFF,
	.mul_shift = 16,
	.mul_mask = 0xFF,
};

static const struct clk_pll_layout at91sam9g20_pllb_layout = {
	.pllr_mask = 0x3FFFFF,
	.mul_shift = 16,
	.mul_mask = 0x3F,
};

static const struct clk_pll_layout sama5d3_pll_layout = {
	.pllr_mask = 0x1FFFFFF,
	.mul_shift = 18,
	.mul_mask = 0x7F,
};


static struct clk_pll_characteristics * __init
of_at91_clk_pll_get_characteristics(struct device_node *np)
{
	int i;
	int offset;
	u32 tmp;
	int num_output;
	u32 num_cells;
	struct clk_range input;
	struct clk_range *output;
	u8 *out = NULL;
	u16 *icpll = NULL;
	struct clk_pll_characteristics *characteristics;

	if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
		return NULL;

	if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
				 &num_cells))
		return NULL;

	if (num_cells < 2 || num_cells > 4)
		return NULL;

	if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
		return NULL;
	num_output = tmp / (sizeof(u32) * num_cells);

	characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
	if (!characteristics)
		return NULL;

	output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
	if (!output)
		goto out_free_characteristics;

	if (num_cells > 2) {
		out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
		if (!out)
			goto out_free_output;
	}

	if (num_cells > 3) {
		icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
		if (!icpll)
			goto out_free_output;
	}

	for (i = 0; i < num_output; i++) {
		offset = i * num_cells;
		if (of_property_read_u32_index(np,
					       "atmel,pll-clk-output-ranges",
					       offset, &tmp))
			goto out_free_output;
		output[i].min = tmp;
		if (of_property_read_u32_index(np,
					       "atmel,pll-clk-output-ranges",
					       offset + 1, &tmp))
			goto out_free_output;
		output[i].max = tmp;

		if (num_cells == 2)
			continue;

		if (of_property_read_u32_index(np,
					       "atmel,pll-clk-output-ranges",
					       offset + 2, &tmp))
			goto out_free_output;
		out[i] = tmp;

		if (num_cells == 3)
			continue;

		if (of_property_read_u32_index(np,
					       "atmel,pll-clk-output-ranges",
					       offset + 3, &tmp))
			goto out_free_output;
		icpll[i] = tmp;
	}

	characteristics->input = input;
	characteristics->num_output = num_output;
	characteristics->output = output;
	characteristics->out = out;
	characteristics->icpll = icpll;
	return characteristics;

out_free_output:
	kfree(icpll);
	kfree(out);
	kfree(output);
out_free_characteristics:
	kfree(characteristics);
	return NULL;
}

static void __init
of_at91_clk_pll_setup(struct device_node *np,
		      const struct clk_pll_layout *layout)
{
	u32 id;
	struct clk_hw *hw;
	struct regmap *regmap;
	const char *parent_name;
	const char *name = np->name;
	struct clk_pll_characteristics *characteristics;

	if (of_property_read_u32(np, "reg", &id))
		return;

	parent_name = of_clk_get_parent_name(np, 0);

	of_property_read_string(np, "clock-output-names", &name);

	regmap = syscon_node_to_regmap(of_get_parent(np));
	if (IS_ERR(regmap))
		return;

	characteristics = of_at91_clk_pll_get_characteristics(np);
	if (!characteristics)
		return;

	hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
				    characteristics);
	if (IS_ERR(hw))
		goto out_free_characteristics;

	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
	return;

out_free_characteristics:
	kfree(characteristics);
}

static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
{
	of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
}
CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
	       of_at91rm9200_clk_pll_setup);

static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
{
	of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
}
CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
	       of_at91sam9g45_clk_pll_setup);

static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
{
	of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
}
CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
	       of_at91sam9g20_clk_pllb_setup);

static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
{
	of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
}
CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
	       of_sama5d3_clk_pll_setup);
Commit	Line	Data
1a748d2b BB	1	/*
	2	* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	*/
	10
	11	#include <linux/clk-provider.h>
	12	#include <linux/clkdev.h>
	13	#include <linux/clk/at91_pmc.h>
	14	#include <linux/of.h>
1bdf0232 BB	15	#include <linux/mfd/syscon.h>
1bdf0232 BB	16	#include <linux/regmap.h>
1a748d2b BB	17
	18	#include "pmc.h"
	19
	20	#define PLL_STATUS_MASK(id) (1 << (1 + (id)))
	21	#define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
	22	#define PLL_DIV_MASK 0xff
	23	#define PLL_DIV_MAX PLL_DIV_MASK
	24	#define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
	25	#define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
	26	(layout)->mul_mask)
3ef9dd2b BB	27	#define PLL_MUL_MIN 2
	28	#define PLL_MUL_MASK(layout) ((layout)->mul_mask)
	29	#define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
1a748d2b BB	30	#define PLL_ICPR_SHIFT(id) ((id) * 16)
1a748d2b BB	31	#define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
078a3eb5	32	#define PLL_MAX_COUNT 0x3f
1a748d2b BB	33	#define PLL_COUNT_SHIFT 8
	34	#define PLL_OUT_SHIFT 14
	35	#define PLL_MAX_ID 1
	36
	37	struct clk_pll_characteristics {
	38	struct clk_range input;
	39	int num_output;
	40	struct clk_range *output;
	41	u16 *icpll;
	42	u8 *out;
	43	};
	44
	45	struct clk_pll_layout {
	46	u32 pllr_mask;
	47	u16 mul_mask;
	48	u8 mul_shift;
	49	};
	50
	51	#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
	52
	53	struct clk_pll {
	54	struct clk_hw hw;
1bdf0232	55	struct regmap *regmap;
1a748d2b BB	56	u8 id;
	57	u8 div;
	58	u8 range;
	59	u16 mul;
	60	const struct clk_pll_layout *layout;
	61	const struct clk_pll_characteristics *characteristics;
	62	};
	63
1bdf0232 BB	64	static inline bool clk_pll_ready(struct regmap *regmap, int id)
	65	{
	66	unsigned int status;
	67
	68	regmap_read(regmap, AT91_PMC_SR, &status);
	69
	70	return status & PLL_STATUS_MASK(id) ? 1 : 0;
	71	}
	72
1a748d2b BB	73	static int clk_pll_prepare(struct clk_hw *hw)
	74	{
	75	struct clk_pll *pll = to_clk_pll(hw);
1bdf0232	76	struct regmap *regmap = pll->regmap;
1a748d2b	77	const struct clk_pll_layout *layout = pll->layout;
e442d234 BB	78	const struct clk_pll_characteristics *characteristics =
e442d234 BB	79	pll->characteristics;
1a748d2b BB	80	u8 id = pll->id;
	81	u32 mask = PLL_STATUS_MASK(id);
	82	int offset = PLL_REG(id);
	83	u8 out = 0;
1bdf0232 BB	84	unsigned int pllr;
1bdf0232 BB	85	unsigned int status;
1a748d2b BB	86	u8 div;
	87	u16 mul;
	88
1bdf0232	89	regmap_read(regmap, offset, &pllr);
1a748d2b BB	90	div = PLL_DIV(pllr);
	91	mul = PLL_MUL(pllr, layout);
	92
1bdf0232 BB	93	regmap_read(regmap, AT91_PMC_SR, &status);
1bdf0232 BB	94	if ((status & mask) &&
1a748d2b BB	95	(div == pll->div && mul == pll->mul))
	96	return 0;
	97
	98	if (characteristics->out)
	99	out = characteristics->out[pll->range];
1a748d2b	100
1bdf0232 BB	101	if (characteristics->icpll)
	102	regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
	103	characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));
1a748d2b	104
1bdf0232 BB	105	regmap_update_bits(regmap, offset, layout->pllr_mask,
	106	pll->div \| (PLL_MAX_COUNT << PLL_COUNT_SHIFT) \|
	107	(out << PLL_OUT_SHIFT) \|
	108	((pll->mul & layout->mul_mask) << layout->mul_shift));
	109
99a81706 AB	110	while (!clk_pll_ready(regmap, pll->id))
99a81706 AB	111	cpu_relax();
1a748d2b BB	112
	113	return 0;
	114	}
	115
	116	static int clk_pll_is_prepared(struct clk_hw *hw)
	117	{
	118	struct clk_pll *pll = to_clk_pll(hw);
1a748d2b	119
1bdf0232	120	return clk_pll_ready(pll->regmap, pll->id);
1a748d2b BB	121	}
	122
	123	static void clk_pll_unprepare(struct clk_hw *hw)
	124	{
	125	struct clk_pll *pll = to_clk_pll(hw);
1bdf0232	126	unsigned int mask = pll->layout->pllr_mask;
1a748d2b	127
1bdf0232	128	regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
1a748d2b BB	129	}
	130
	131	static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
	132	unsigned long parent_rate)
	133	{
	134	struct clk_pll *pll = to_clk_pll(hw);
1a748d2b	135
a982e45d	136	return (parent_rate / pll->div) * (pll->mul + 1);
1a748d2b BB	137	}
	138
	139	static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
	140	unsigned long parent_rate,
	141	u32 div, u32 mul,
	142	u32 *index) {
1a748d2b BB	143	const struct clk_pll_layout *layout = pll->layout;
	144	const struct clk_pll_characteristics *characteristics =
	145	pll->characteristics;
3ef9dd2b BB	146	unsigned long bestremainder = ULONG_MAX;
	147	unsigned long maxdiv, mindiv, tmpdiv;
	148	long bestrate = -ERANGE;
	149	unsigned long bestdiv;
	150	unsigned long bestmul;
	151	int i = 0;
1a748d2b	152
3ef9dd2b	153	/* Check if parent_rate is a valid input rate */
6c7b03e1	154	if (parent_rate < characteristics->input.min)
1a748d2b BB	155	return -ERANGE;
1a748d2b BB	156
3ef9dd2b BB	157	/*
	158	* Calculate minimum divider based on the minimum multiplier, the
	159	* parent_rate and the requested rate.
	160	* Should always be 2 according to the input and output characteristics
	161	* of the PLL blocks.
	162	*/
	163	mindiv = (parent_rate * PLL_MUL_MIN) / rate;
	164	if (!mindiv)
	165	mindiv = 1;
	166
6c7b03e1 BB	167	if (parent_rate > characteristics->input.max) {
	168	tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
	169	if (tmpdiv > PLL_DIV_MAX)
	170	return -ERANGE;
	171
	172	if (tmpdiv > mindiv)
	173	mindiv = tmpdiv;
	174	}
	175
3ef9dd2b BB	176	/*
	177	* Calculate the maximum divider which is limited by PLL register
	178	* layout (limited by the MUL or DIV field size).
	179	*/
	180	maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
	181	if (maxdiv > PLL_DIV_MAX)
	182	maxdiv = PLL_DIV_MAX;
	183
	184	/*
	185	* Iterate over the acceptable divider values to find the best
	186	* divider/multiplier pair (the one that generates the closest
	187	* rate to the requested one).
	188	*/
	189	for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
	190	unsigned long remainder;
	191	unsigned long tmprate;
	192	unsigned long tmpmul;
	193
	194	/*
	195	* Calculate the multiplier associated with the current
	196	* divider that provide the closest rate to the requested one.
	197	*/
	198	tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
	199	tmprate = (parent_rate / tmpdiv) * tmpmul;
	200	if (tmprate > rate)
	201	remainder = tmprate - rate;
	202	else
	203	remainder = rate - tmprate;
	204
	205	/*
	206	* Compare the remainder with the best remainder found until
	207	* now and elect a new best multiplier/divider pair if the
	208	* current remainder is smaller than the best one.
	209	*/
1a748d2b BB	210	if (remainder < bestremainder) {
1a748d2b BB	211	bestremainder = remainder;
1a748d2b	212	bestdiv = tmpdiv;
3ef9dd2b BB	213	bestmul = tmpmul;
3ef9dd2b BB	214	bestrate = tmprate;
1a748d2b BB	215	}
1a748d2b BB	216
3ef9dd2b BB	217	/*
	218	* We've found a perfect match!
	219	* Stop searching now and use this multiplier/divider pair.
	220	*/
1a748d2b BB	221	if (!remainder)
	222	break;
	223	}
	224
3ef9dd2b BB	225	/* We haven't found any multiplier/divider pair => return -ERANGE */
	226	if (bestrate < 0)
	227	return bestrate;
	228
	229	/* Check if bestrate is a valid output rate */
	230	for (i = 0; i < characteristics->num_output; i++) {
	231	if (bestrate >= characteristics->output[i].min &&
	232	bestrate <= characteristics->output[i].max)
	233	break;
	234	}
	235
	236	if (i >= characteristics->num_output)
	237	return -ERANGE;
1a748d2b BB	238
	239	if (div)
	240	*div = bestdiv;
	241	if (mul)
3ef9dd2b	242	*mul = bestmul - 1;
1a748d2b BB	243	if (index)
	244	*index = i;
	245
3ef9dd2b	246	return bestrate;
1a748d2b BB	247	}
	248
	249	static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
	250	unsigned long *parent_rate)
	251	{
	252	struct clk_pll *pll = to_clk_pll(hw);
	253
	254	return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
	255	NULL, NULL, NULL);
	256	}
	257
	258	static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
	259	unsigned long parent_rate)
	260	{
	261	struct clk_pll *pll = to_clk_pll(hw);
1a748d2b BB	262	long ret;
	263	u32 div;
	264	u32 mul;
	265	u32 index;
1a748d2b BB	266
	267	ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
	268	&div, &mul, &index);
	269	if (ret < 0)
	270	return ret;
	271
	272	pll->range = index;
	273	pll->div = div;
	274	pll->mul = mul;
	275
	276	return 0;
	277	}
	278
	279	static const struct clk_ops pll_ops = {
	280	.prepare = clk_pll_prepare,
	281	.unprepare = clk_pll_unprepare,
	282	.is_prepared = clk_pll_is_prepared,
	283	.recalc_rate = clk_pll_recalc_rate,
	284	.round_rate = clk_pll_round_rate,
	285	.set_rate = clk_pll_set_rate,
	286	};
	287
f5644f10	288	static struct clk_hw * __init
99a81706	289	at91_clk_register_pll(struct regmap regmap, const char name,
1a748d2b BB	290	const char *parent_name, u8 id,
	291	const struct clk_pll_layout *layout,
	292	const struct clk_pll_characteristics *characteristics)
	293	{
	294	struct clk_pll *pll;
f5644f10	295	struct clk_hw *hw;
1a748d2b	296	struct clk_init_data init;
1a748d2b	297	int offset = PLL_REG(id);
1bdf0232	298	unsigned int pllr;
f5644f10	299	int ret;
1a748d2b BB	300
	301	if (id > PLL_MAX_ID)
	302	return ERR_PTR(-EINVAL);
	303
	304	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	305	if (!pll)
	306	return ERR_PTR(-ENOMEM);
	307
	308	init.name = name;
	309	init.ops = &pll_ops;
	310	init.parent_names = &parent_name;
	311	init.num_parents = 1;
	312	init.flags = CLK_SET_RATE_GATE;
	313
	314	pll->id = id;
	315	pll->hw.init = &init;
	316	pll->layout = layout;
	317	pll->characteristics = characteristics;
1bdf0232	318	pll->regmap = regmap;
1bdf0232 BB	319	regmap_read(regmap, offset, &pllr);
	320	pll->div = PLL_DIV(pllr);
	321	pll->mul = PLL_MUL(pllr, layout);
1a748d2b	322
f5644f10 SB	323	hw = &pll->hw;
	324	ret = clk_hw_register(NULL, &pll->hw);
	325	if (ret) {
1a748d2b	326	kfree(pll);
f5644f10	327	hw = ERR_PTR(ret);
c76a024e	328	}
1a748d2b	329
f5644f10	330	return hw;
1a748d2b BB	331	}
	332
	333
	334	static const struct clk_pll_layout at91rm9200_pll_layout = {
	335	.pllr_mask = 0x7FFFFFF,
	336	.mul_shift = 16,
	337	.mul_mask = 0x7FF,
	338	};
	339
	340	static const struct clk_pll_layout at91sam9g45_pll_layout = {
	341	.pllr_mask = 0xFFFFFF,
	342	.mul_shift = 16,
	343	.mul_mask = 0xFF,
	344	};
	345
	346	static const struct clk_pll_layout at91sam9g20_pllb_layout = {
	347	.pllr_mask = 0x3FFFFF,
	348	.mul_shift = 16,
	349	.mul_mask = 0x3F,
	350	};
	351
	352	static const struct clk_pll_layout sama5d3_pll_layout = {
	353	.pllr_mask = 0x1FFFFFF,
	354	.mul_shift = 18,
	355	.mul_mask = 0x7F,
	356	};
	357
	358
	359	static struct clk_pll_characteristics * __init
	360	of_at91_clk_pll_get_characteristics(struct device_node *np)
	361	{
	362	int i;
	363	int offset;
	364	u32 tmp;
	365	int num_output;
	366	u32 num_cells;
	367	struct clk_range input;
	368	struct clk_range *output;
	369	u8 *out = NULL;
	370	u16 *icpll = NULL;
	371	struct clk_pll_characteristics *characteristics;
	372
	373	if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
	374	return NULL;
	375
	376	if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
	377	&num_cells))
	378	return NULL;
	379
	380	if (num_cells < 2 \|\| num_cells > 4)
	381	return NULL;
	382
	383	if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
	384	return NULL;
	385	num_output = tmp / (sizeof(u32) * num_cells);
	386
	387	characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
	388	if (!characteristics)
	389	return NULL;
	390
1e5c8444	391	output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
1a748d2b BB	392	if (!output)
	393	goto out_free_characteristics;
	394
	395	if (num_cells > 2) {
1e5c8444	396	out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
1a748d2b BB	397	if (!out)
	398	goto out_free_output;
	399	}
	400
	401	if (num_cells > 3) {
1e5c8444	402	icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
1a748d2b BB	403	if (!icpll)
	404	goto out_free_output;
	405	}
	406
	407	for (i = 0; i < num_output; i++) {
	408	offset = i * num_cells;
	409	if (of_property_read_u32_index(np,
	410	"atmel,pll-clk-output-ranges",
	411	offset, &tmp))
	412	goto out_free_output;
	413	output[i].min = tmp;
	414	if (of_property_read_u32_index(np,
	415	"atmel,pll-clk-output-ranges",
	416	offset + 1, &tmp))
	417	goto out_free_output;
	418	output[i].max = tmp;
	419
	420	if (num_cells == 2)
	421	continue;
	422
	423	if (of_property_read_u32_index(np,
	424	"atmel,pll-clk-output-ranges",
	425	offset + 2, &tmp))
	426	goto out_free_output;
	427	out[i] = tmp;
	428
	429	if (num_cells == 3)
	430	continue;
	431
	432	if (of_property_read_u32_index(np,
	433	"atmel,pll-clk-output-ranges",
	434	offset + 3, &tmp))
	435	goto out_free_output;
	436	icpll[i] = tmp;
	437	}
	438
	439	characteristics->input = input;
	440	characteristics->num_output = num_output;
	441	characteristics->output = output;
	442	characteristics->out = out;
	443	characteristics->icpll = icpll;
	444	return characteristics;
	445
	446	out_free_output:
	447	kfree(icpll);
	448	kfree(out);
	449	kfree(output);
	450	out_free_characteristics:
	451	kfree(characteristics);
	452	return NULL;
	453	}
	454
	455	static void __init
1bdf0232	456	of_at91_clk_pll_setup(struct device_node *np,
1a748d2b BB	457	const struct clk_pll_layout *layout)
	458	{
	459	u32 id;
f5644f10	460	struct clk_hw *hw;
1bdf0232	461	struct regmap *regmap;
1a748d2b BB	462	const char *parent_name;
	463	const char *name = np->name;
	464	struct clk_pll_characteristics *characteristics;
	465
	466	if (of_property_read_u32(np, "reg", &id))
	467	return;
	468
	469	parent_name = of_clk_get_parent_name(np, 0);
	470
	471	of_property_read_string(np, "clock-output-names", &name);
	472
1bdf0232 BB	473	regmap = syscon_node_to_regmap(of_get_parent(np));
	474	if (IS_ERR(regmap))
	475	return;
	476
1a748d2b BB	477	characteristics = of_at91_clk_pll_get_characteristics(np);
	478	if (!characteristics)
	479	return;
	480
f5644f10	481	hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
1a748d2b	482	characteristics);
f5644f10	483	if (IS_ERR(hw))
1a748d2b BB	484	goto out_free_characteristics;
1a748d2b BB	485
f5644f10	486	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
1a748d2b BB	487	return;
	488
	489	out_free_characteristics:
	490	kfree(characteristics);
	491	}
	492
1bdf0232	493	static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
1a748d2b	494	{
1bdf0232	495	of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
1a748d2b	496	}
1bdf0232 BB	497	CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
1bdf0232 BB	498	of_at91rm9200_clk_pll_setup);
1a748d2b	499
1bdf0232	500	static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
1a748d2b	501	{
1bdf0232	502	of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
1a748d2b	503	}
1bdf0232 BB	504	CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
1bdf0232 BB	505	of_at91sam9g45_clk_pll_setup);
1a748d2b	506
1bdf0232	507	static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
1a748d2b	508	{
1bdf0232	509	of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
1a748d2b	510	}
1bdf0232 BB	511	CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
1bdf0232 BB	512	of_at91sam9g20_clk_pllb_setup);
1a748d2b	513
1bdf0232	514	static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
1a748d2b	515	{
1bdf0232	516	of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
1a748d2b	517	}
1bdf0232 BB	518	CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
1bdf0232 BB	519	of_sama5d3_clk_pll_setup);