[linux-2.6-block.git] / drivers / clk / at91 / clk-generated.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Copyright (C) 2015 Atmel Corporation,
 *                     Nicolas Ferre <nicolas.ferre@atmel.com>
 *
 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
 */

#include <linux/bitfield.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/at91_pmc.h>
#include <linux/of.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include "pmc.h"

#define GENERATED_MAX_DIV	255

struct clk_generated {
	struct clk_hw hw;
	struct regmap *regmap;
	struct clk_range range;
	spinlock_t *lock;
	u32 *mux_table;
	u32 id;
	u32 gckdiv;
	const struct clk_pcr_layout *layout;
	struct at91_clk_pms pms;
	u8 parent_id;
	int chg_pid;
};

#define to_clk_generated(hw) \
	container_of(hw, struct clk_generated, hw)

static int clk_generated_set(struct clk_generated *gck, int status)
{
	unsigned long flags;
	unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0;

	spin_lock_irqsave(gck->lock, flags);
	regmap_write(gck->regmap, gck->layout->offset,
		     (gck->id & gck->layout->pid_mask));
	regmap_update_bits(gck->regmap, gck->layout->offset,
			   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
			   gck->layout->cmd | enable,
			   field_prep(gck->layout->gckcss_mask, gck->parent_id) |
			   gck->layout->cmd |
			   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
			   enable);
	spin_unlock_irqrestore(gck->lock, flags);

	return 0;
}

static int clk_generated_enable(struct clk_hw *hw)
{
	struct clk_generated *gck = to_clk_generated(hw);

	pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
		 __func__, gck->gckdiv, gck->parent_id);

	clk_generated_set(gck, 1);

	return 0;
}

static void clk_generated_disable(struct clk_hw *hw)
{
	struct clk_generated *gck = to_clk_generated(hw);
	unsigned long flags;

	spin_lock_irqsave(gck->lock, flags);
	regmap_write(gck->regmap, gck->layout->offset,
		     (gck->id & gck->layout->pid_mask));
	regmap_update_bits(gck->regmap, gck->layout->offset,
			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
			   gck->layout->cmd);
	spin_unlock_irqrestore(gck->lock, flags);
}

static int clk_generated_is_enabled(struct clk_hw *hw)
{
	struct clk_generated *gck = to_clk_generated(hw);
	unsigned long flags;
	unsigned int status;

	spin_lock_irqsave(gck->lock, flags);
	regmap_write(gck->regmap, gck->layout->offset,
		     (gck->id & gck->layout->pid_mask));
	regmap_read(gck->regmap, gck->layout->offset, &status);
	spin_unlock_irqrestore(gck->lock, flags);

	return !!(status & AT91_PMC_PCR_GCKEN);
}

static unsigned long
clk_generated_recalc_rate(struct clk_hw *hw,
			  unsigned long parent_rate)
{
	struct clk_generated *gck = to_clk_generated(hw);

	return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
}

static void clk_generated_best_diff(struct clk_rate_request *req,
				    struct clk_hw *parent,
				    unsigned long parent_rate, u32 div,
				    int *best_diff, long *best_rate)
{
	unsigned long tmp_rate;
	int tmp_diff;

	if (!div)
		tmp_rate = parent_rate;
	else
		tmp_rate = parent_rate / div;

	if (tmp_rate < req->min_rate || tmp_rate > req->max_rate)
		return;

	tmp_diff = abs(req->rate - tmp_rate);

	if (*best_diff < 0 || *best_diff >= tmp_diff) {
		*best_rate = tmp_rate;
		*best_diff = tmp_diff;
		req->best_parent_rate = parent_rate;
		req->best_parent_hw = parent;
	}
}

static int clk_generated_determine_rate(struct clk_hw *hw,
					struct clk_rate_request *req)
{
	struct clk_generated *gck = to_clk_generated(hw);
	struct clk_hw *parent = NULL;
	long best_rate = -EINVAL;
	unsigned long min_rate, parent_rate;
	int best_diff = -1;
	int i;
	u32 div;

	/* do not look for a rate that is outside of our range */
	if (gck->range.max && req->rate > gck->range.max)
		req->rate = gck->range.max;
	if (gck->range.min && req->rate < gck->range.min)
		req->rate = gck->range.min;

	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
		if (gck->chg_pid == i)
			continue;

		parent = clk_hw_get_parent_by_index(hw, i);
		if (!parent)
			continue;

		parent_rate = clk_hw_get_rate(parent);
		min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
		if (!parent_rate ||
		    (gck->range.max && min_rate > gck->range.max))
			continue;

		div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
		if (div > GENERATED_MAX_DIV + 1)
			div = GENERATED_MAX_DIV + 1;

		clk_generated_best_diff(req, parent, parent_rate, div,
					&best_diff, &best_rate);

		if (!best_diff)
			break;
	}

	/*
	 * The audio_pll rate can be modified, unlike the five others clocks
	 * that should never be altered.
	 * The audio_pll can technically be used by multiple consumers. However,
	 * with the rate locking, the first consumer to enable to clock will be
	 * the one definitely setting the rate of the clock.
	 * Since audio IPs are most likely to request the same rate, we enforce
	 * that the only clks able to modify gck rate are those of audio IPs.
	 */

	if (gck->chg_pid < 0)
		goto end;

	parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
	if (!parent)
		goto end;

	for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
		struct clk_rate_request req_parent;

		clk_hw_forward_rate_request(hw, req, parent, &req_parent, req->rate * div);
		if (__clk_determine_rate(parent, &req_parent))
			continue;
		clk_generated_best_diff(req, parent, req_parent.rate, div,
					&best_diff, &best_rate);

		if (!best_diff)
			break;
	}

end:
	pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
		 __func__, best_rate,
		 __clk_get_name((req->best_parent_hw)->clk),
		 req->best_parent_rate);

	if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
		return -EINVAL;

	req->rate = best_rate;
	return 0;
}

/* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_generated *gck = to_clk_generated(hw);

	if (index >= clk_hw_get_num_parents(hw))
		return -EINVAL;

	if (gck->mux_table)
		gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
	else
		gck->parent_id = index;

	return 0;
}

static u8 clk_generated_get_parent(struct clk_hw *hw)
{
	struct clk_generated *gck = to_clk_generated(hw);

	return gck->parent_id;
}

/* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
static int clk_generated_set_rate(struct clk_hw *hw,
				  unsigned long rate,
				  unsigned long parent_rate)
{
	struct clk_generated *gck = to_clk_generated(hw);
	u32 div;

	if (!rate)
		return -EINVAL;

	if (gck->range.max && rate > gck->range.max)
		return -EINVAL;

	div = DIV_ROUND_CLOSEST(parent_rate, rate);
	if (div > GENERATED_MAX_DIV + 1 || !div)
		return -EINVAL;

	gck->gckdiv = div - 1;
	return 0;
}

static int clk_generated_save_context(struct clk_hw *hw)
{
	struct clk_generated *gck = to_clk_generated(hw);

	gck->pms.status = clk_generated_is_enabled(&gck->hw);

	return 0;
}

static void clk_generated_restore_context(struct clk_hw *hw)
{
	struct clk_generated *gck = to_clk_generated(hw);

	if (gck->pms.status)
		clk_generated_set(gck, gck->pms.status);
}

static const struct clk_ops generated_ops = {
	.enable = clk_generated_enable,
	.disable = clk_generated_disable,
	.is_enabled = clk_generated_is_enabled,
	.recalc_rate = clk_generated_recalc_rate,
	.determine_rate = clk_generated_determine_rate,
	.get_parent = clk_generated_get_parent,
	.set_parent = clk_generated_set_parent,
	.set_rate = clk_generated_set_rate,
	.save_context = clk_generated_save_context,
	.restore_context = clk_generated_restore_context,
};

/**
 * clk_generated_startup - Initialize a given clock to its default parent and
 * divisor parameter.
 *
 * @gck:	Generated clock to set the startup parameters for.
 *
 * Take parameters from the hardware and update local clock configuration
 * accordingly.
 */
static void clk_generated_startup(struct clk_generated *gck)
{
	u32 tmp;
	unsigned long flags;

	spin_lock_irqsave(gck->lock, flags);
	regmap_write(gck->regmap, gck->layout->offset,
		     (gck->id & gck->layout->pid_mask));
	regmap_read(gck->regmap, gck->layout->offset, &tmp);
	spin_unlock_irqrestore(gck->lock, flags);

	gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
	gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
}

struct clk_hw * __init
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
			    const struct clk_pcr_layout *layout,
			    const char *name, const char **parent_names,
			    struct clk_hw **parent_hws,
			    u32 *mux_table, u8 num_parents, u8 id,
			    const struct clk_range *range,
			    int chg_pid)
{
	struct clk_generated *gck;
	struct clk_init_data init = {};
	struct clk_hw *hw;
	int ret;

	if (!(parent_names || parent_hws))
		return ERR_PTR(-ENOMEM);

	gck = kzalloc(sizeof(*gck), GFP_KERNEL);
	if (!gck)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &generated_ops;
	if (parent_hws)
		init.parent_hws = (const struct clk_hw **)parent_hws;
	else
		init.parent_names = parent_names;
	init.num_parents = num_parents;
	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
	if (chg_pid >= 0)
		init.flags |= CLK_SET_RATE_PARENT;

	gck->id = id;
	gck->hw.init = &init;
	gck->regmap = regmap;
	gck->lock = lock;
	gck->range = *range;
	gck->chg_pid = chg_pid;
	gck->layout = layout;
	gck->mux_table = mux_table;

	clk_generated_startup(gck);
	hw = &gck->hw;
	ret = clk_hw_register(NULL, &gck->hw);
	if (ret) {
		kfree(gck);
		hw = ERR_PTR(ret);
	}

	return hw;
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
df70aeef NF	2	/*
	3	* Copyright (C) 2015 Atmel Corporation,
	4	* Nicolas Ferre <nicolas.ferre@atmel.com>
	5	*
	6	* Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
df70aeef NF	7	*/
df70aeef NF	8
e4cfb823	9	#include <linux/bitfield.h>
df70aeef NF	10	#include <linux/clk-provider.h>
	11	#include <linux/clkdev.h>
	12	#include <linux/clk/at91_pmc.h>
	13	#include <linux/of.h>
1bdf0232 BB	14	#include <linux/mfd/syscon.h>
1bdf0232 BB	15	#include <linux/regmap.h>
df70aeef NF	16
	17	#include "pmc.h"
	18
df70aeef NF	19	#define GENERATED_MAX_DIV 255
	20
	21	struct clk_generated {
	22	struct clk_hw hw;
1bdf0232	23	struct regmap *regmap;
df70aeef	24	struct clk_range range;
1bdf0232	25	spinlock_t *lock;
22a1dfe9	26	u32 *mux_table;
df70aeef NF	27	u32 id;
df70aeef NF	28	u32 gckdiv;
e4cfb823	29	const struct clk_pcr_layout *layout;
36971566	30	struct at91_clk_pms pms;
df70aeef	31	u8 parent_id;
64c9247b	32	int chg_pid;
df70aeef NF	33	};
	34
	35	#define to_clk_generated(hw) \
	36	container_of(hw, struct clk_generated, hw)
	37
36971566	38	static int clk_generated_set(struct clk_generated *gck, int status)
df70aeef	39	{
1bdf0232	40	unsigned long flags;
36971566	41	unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0;
df70aeef	42
1bdf0232	43	spin_lock_irqsave(gck->lock, flags);
e4cfb823 AB	44	regmap_write(gck->regmap, gck->layout->offset,
	45	(gck->id & gck->layout->pid_mask));
	46	regmap_update_bits(gck->regmap, gck->layout->offset,
	47	AT91_PMC_PCR_GCKDIV_MASK \| gck->layout->gckcss_mask \|
36971566	48	gck->layout->cmd \| enable,
e4cfb823 AB	49	field_prep(gck->layout->gckcss_mask, gck->parent_id) \|
	50	gck->layout->cmd \|
	51	FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) \|
36971566	52	enable);
1bdf0232	53	spin_unlock_irqrestore(gck->lock, flags);
36971566 CB	54
	55	return 0;
	56	}
	57
	58	static int clk_generated_enable(struct clk_hw *hw)
	59	{
	60	struct clk_generated *gck = to_clk_generated(hw);
	61
	62	pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
	63	__func__, gck->gckdiv, gck->parent_id);
	64
	65	clk_generated_set(gck, 1);
	66
df70aeef NF	67	return 0;
	68	}
	69
	70	static void clk_generated_disable(struct clk_hw *hw)
	71	{
	72	struct clk_generated *gck = to_clk_generated(hw);
1bdf0232 BB	73	unsigned long flags;
	74
	75	spin_lock_irqsave(gck->lock, flags);
e4cfb823 AB	76	regmap_write(gck->regmap, gck->layout->offset,
	77	(gck->id & gck->layout->pid_mask));
	78	regmap_update_bits(gck->regmap, gck->layout->offset,
	79	gck->layout->cmd \| AT91_PMC_PCR_GCKEN,
	80	gck->layout->cmd);
1bdf0232	81	spin_unlock_irqrestore(gck->lock, flags);
df70aeef NF	82	}
	83
	84	static int clk_generated_is_enabled(struct clk_hw *hw)
	85	{
	86	struct clk_generated *gck = to_clk_generated(hw);
1bdf0232 BB	87	unsigned long flags;
1bdf0232 BB	88	unsigned int status;
df70aeef	89
1bdf0232	90	spin_lock_irqsave(gck->lock, flags);
e4cfb823 AB	91	regmap_write(gck->regmap, gck->layout->offset,
	92	(gck->id & gck->layout->pid_mask));
	93	regmap_read(gck->regmap, gck->layout->offset, &status);
1bdf0232	94	spin_unlock_irqrestore(gck->lock, flags);
df70aeef	95
42324d95	96	return !!(status & AT91_PMC_PCR_GCKEN);
df70aeef NF	97	}
	98
	99	static unsigned long
	100	clk_generated_recalc_rate(struct clk_hw *hw,
	101	unsigned long parent_rate)
	102	{
	103	struct clk_generated *gck = to_clk_generated(hw);
	104
	105	return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
	106	}
	107
8a8f4bf0 QS	108	static void clk_generated_best_diff(struct clk_rate_request *req,
	109	struct clk_hw *parent,
	110	unsigned long parent_rate, u32 div,
	111	int best_diff, long best_rate)
	112	{
	113	unsigned long tmp_rate;
	114	int tmp_diff;
	115
	116	if (!div)
	117	tmp_rate = parent_rate;
	118	else
	119	tmp_rate = parent_rate / div;
d0031e6f CC	120
	121	if (tmp_rate < req->min_rate \|\| tmp_rate > req->max_rate)
	122	return;
	123
8a8f4bf0 QS	124	tmp_diff = abs(req->rate - tmp_rate);
8a8f4bf0 QS	125
64c9247b	126	if (best_diff < 0 \|\| best_diff >= tmp_diff) {
8a8f4bf0 QS	127	*best_rate = tmp_rate;
	128	*best_diff = tmp_diff;
	129	req->best_parent_rate = parent_rate;
	130	req->best_parent_hw = parent;
	131	}
	132	}
	133
df70aeef NF	134	static int clk_generated_determine_rate(struct clk_hw *hw,
	135	struct clk_rate_request *req)
	136	{
	137	struct clk_generated *gck = to_clk_generated(hw);
	138	struct clk_hw *parent = NULL;
	139	long best_rate = -EINVAL;
1a1a36d7	140	unsigned long min_rate, parent_rate;
df70aeef	141	int best_diff = -1;
df70aeef	142	int i;
1a1a36d7	143	u32 div;
df70aeef	144
af7651e6 CC	145	/* do not look for a rate that is outside of our range */
	146	if (gck->range.max && req->rate > gck->range.max)
	147	req->rate = gck->range.max;
	148	if (gck->range.min && req->rate < gck->range.min)
	149	req->rate = gck->range.min;
	150
64c9247b CB	151	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
	152	if (gck->chg_pid == i)
	153	continue;
	154
df70aeef NF	155	parent = clk_hw_get_parent_by_index(hw, i);
	156	if (!parent)
	157	continue;
	158
	159	parent_rate = clk_hw_get_rate(parent);
	160	min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
	161	if (!parent_rate \|\|
	162	(gck->range.max && min_rate > gck->range.max))
	163	continue;
	164
8c7aa632	165	div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
1573eebe CC	166	if (div > GENERATED_MAX_DIV + 1)
1573eebe CC	167	div = GENERATED_MAX_DIV + 1;
8a8f4bf0 QS	168
	169	clk_generated_best_diff(req, parent, parent_rate, div,
	170	&best_diff, &best_rate);
	171
1a1a36d7 QS	172	if (!best_diff)
	173	break;
	174	}
	175
	176	/*
	177	* The audio_pll rate can be modified, unlike the five others clocks
	178	* that should never be altered.
	179	* The audio_pll can technically be used by multiple consumers. However,
	180	* with the rate locking, the first consumer to enable to clock will be
	181	* the one definitely setting the rate of the clock.
	182	* Since audio IPs are most likely to request the same rate, we enforce
	183	* that the only clks able to modify gck rate are those of audio IPs.
	184	*/
	185
64c9247b	186	if (gck->chg_pid < 0)
1a1a36d7 QS	187	goto end;
1a1a36d7 QS	188
64c9247b	189	parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
1a1a36d7 QS	190	if (!parent)
	191	goto end;
	192
	193	for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
262ca38f MR	194	struct clk_rate_request req_parent;
	195
	196	clk_hw_forward_rate_request(hw, req, parent, &req_parent, req->rate * div);
3a5c42b1 CB	197	if (__clk_determine_rate(parent, &req_parent))
3a5c42b1 CB	198	continue;
1a1a36d7 QS	199	clk_generated_best_diff(req, parent, req_parent.rate, div,
1a1a36d7 QS	200	&best_diff, &best_rate);
df70aeef NF	201
	202	if (!best_diff)
	203	break;
	204	}
	205
1a1a36d7	206	end:
df70aeef NF	207	pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
	208	__func__, best_rate,
	209	__clk_get_name((req->best_parent_hw)->clk),
	210	req->best_parent_rate);
	211
83331bfc CB	212	if (best_rate < 0 \|\| (gck->range.max && best_rate > gck->range.max))
83331bfc CB	213	return -EINVAL;
df70aeef NF	214
	215	req->rate = best_rate;
	216	return 0;
	217	}
	218
	219	/* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
	220	static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
	221	{
	222	struct clk_generated *gck = to_clk_generated(hw);
	223
	224	if (index >= clk_hw_get_num_parents(hw))
	225	return -EINVAL;
	226
22a1dfe9 CB	227	if (gck->mux_table)
	228	gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
	229	else
	230	gck->parent_id = index;
	231
df70aeef NF	232	return 0;
	233	}
	234
	235	static u8 clk_generated_get_parent(struct clk_hw *hw)
	236	{
	237	struct clk_generated *gck = to_clk_generated(hw);
	238
	239	return gck->parent_id;
	240	}
	241
	242	/* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
	243	static int clk_generated_set_rate(struct clk_hw *hw,
	244	unsigned long rate,
	245	unsigned long parent_rate)
	246	{
	247	struct clk_generated *gck = to_clk_generated(hw);
	248	u32 div;
	249
	250	if (!rate)
	251	return -EINVAL;
	252
	253	if (gck->range.max && rate > gck->range.max)
	254	return -EINVAL;
	255
	256	div = DIV_ROUND_CLOSEST(parent_rate, rate);
	257	if (div > GENERATED_MAX_DIV + 1 \|\| !div)
	258	return -EINVAL;
	259
	260	gck->gckdiv = div - 1;
	261	return 0;
	262	}
	263
36971566 CB	264	static int clk_generated_save_context(struct clk_hw *hw)
	265	{
	266	struct clk_generated *gck = to_clk_generated(hw);
	267
	268	gck->pms.status = clk_generated_is_enabled(&gck->hw);
	269
	270	return 0;
	271	}
	272
	273	static void clk_generated_restore_context(struct clk_hw *hw)
	274	{
	275	struct clk_generated *gck = to_clk_generated(hw);
	276
	277	if (gck->pms.status)
	278	clk_generated_set(gck, gck->pms.status);
	279	}
	280
df70aeef NF	281	static const struct clk_ops generated_ops = {
	282	.enable = clk_generated_enable,
	283	.disable = clk_generated_disable,
	284	.is_enabled = clk_generated_is_enabled,
	285	.recalc_rate = clk_generated_recalc_rate,
	286	.determine_rate = clk_generated_determine_rate,
	287	.get_parent = clk_generated_get_parent,
	288	.set_parent = clk_generated_set_parent,
	289	.set_rate = clk_generated_set_rate,
36971566 CB	290	.save_context = clk_generated_save_context,
36971566 CB	291	.restore_context = clk_generated_restore_context,
df70aeef NF	292	};
	293
	294	/**
	295	* clk_generated_startup - Initialize a given clock to its default parent and
	296	* divisor parameter.
	297	*
	298	* @gck: Generated clock to set the startup parameters for.
	299	*
	300	* Take parameters from the hardware and update local clock configuration
	301	* accordingly.
	302	*/
	303	static void clk_generated_startup(struct clk_generated *gck)
	304	{
df70aeef	305	u32 tmp;
1bdf0232	306	unsigned long flags;
df70aeef	307
1bdf0232	308	spin_lock_irqsave(gck->lock, flags);
e4cfb823 AB	309	regmap_write(gck->regmap, gck->layout->offset,
	310	(gck->id & gck->layout->pid_mask));
	311	regmap_read(gck->regmap, gck->layout->offset, &tmp);
1bdf0232	312	spin_unlock_irqrestore(gck->lock, flags);
df70aeef	313
e4cfb823 AB	314	gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
e4cfb823 AB	315	gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
df70aeef NF	316	}
df70aeef NF	317
b2e39dc0	318	struct clk_hw * __init
f5644f10	319	at91_clk_register_generated(struct regmap regmap, spinlock_t lock,
e4cfb823	320	const struct clk_pcr_layout *layout,
f5644f10	321	const char name, const char *parent_names,
00bd581b	322	struct clk_hw **parent_hws,
22a1dfe9 CB	323	u32 *mux_table, u8 num_parents, u8 id,
	324	const struct clk_range *range,
	325	int chg_pid)
df70aeef NF	326	{
df70aeef NF	327	struct clk_generated *gck;
00bd581b	328	struct clk_init_data init = {};
f5644f10 SB	329	struct clk_hw *hw;
f5644f10 SB	330	int ret;
df70aeef	331
00bd581b CB	332	if (!(parent_names \|\| parent_hws))
	333	return ERR_PTR(-ENOMEM);
	334
df70aeef NF	335	gck = kzalloc(sizeof(*gck), GFP_KERNEL);
	336	if (!gck)
	337	return ERR_PTR(-ENOMEM);
	338
	339	init.name = name;
	340	init.ops = &generated_ops;
00bd581b CB	341	if (parent_hws)
	342	init.parent_hws = (const struct clk_hw **)parent_hws;
	343	else
	344	init.parent_names = parent_names;
df70aeef	345	init.num_parents = num_parents;
64c9247b CB	346	init.flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE;
	347	if (chg_pid >= 0)
	348	init.flags \|= CLK_SET_RATE_PARENT;
df70aeef NF	349
	350	gck->id = id;
	351	gck->hw.init = &init;
1bdf0232 BB	352	gck->regmap = regmap;
1bdf0232 BB	353	gck->lock = lock;
df70aeef	354	gck->range = *range;
64c9247b	355	gck->chg_pid = chg_pid;
e4cfb823	356	gck->layout = layout;
22a1dfe9	357	gck->mux_table = mux_table;
df70aeef	358
8e56133e	359	clk_generated_startup(gck);
f5644f10 SB	360	hw = &gck->hw;
	361	ret = clk_hw_register(NULL, &gck->hw);
	362	if (ret) {
df70aeef	363	kfree(gck);
f5644f10	364	hw = ERR_PTR(ret);
4a5f06a0	365	}
df70aeef	366
f5644f10	367	return hw;
df70aeef	368	}