[linux-2.6-block.git] / drivers / clk / at91 / clk-audio-pll.c

/*
 *  Copyright (C) 2016 Atmel Corporation,
 *		       Songjun Wu <songjun.wu@atmel.com>,
 *                     Nicolas Ferre <nicolas.ferre@atmel.com>
 *  Copyright (C) 2017 Free Electrons,
 *		       Quentin Schulz <quentin.schulz@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
 * asked rate.
 *
 * Traits of FRAC clock:
 * enable - clk_enable writes nd, fracr parameters and enables PLL
 * rate - rate is adjustable.
 *        clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
 * parent - fixed parent.  No clk_set_parent support
 *
 * Traits of PMC clock:
 * enable - clk_enable writes qdpmc, and enables PMC output
 * rate - rate is adjustable.
 *        clk->rate = parent->rate / (qdpmc + 1)
 * parent - fixed parent.  No clk_set_parent support
 *
 * Traits of PAD clock:
 * enable - clk_enable writes divisors and enables PAD output
 * rate - rate is adjustable.
 *        clk->rate = parent->rate / (qdaudio * div))
 * parent - fixed parent.  No clk_set_parent support
 *
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/at91_pmc.h>
#include <linux/of.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#include "pmc.h"

#define AUDIO_PLL_DIV_FRAC	BIT(22)
#define AUDIO_PLL_ND_MAX	(AT91_PMC_AUDIO_PLL_ND_MASK >> \
					AT91_PMC_AUDIO_PLL_ND_OFFSET)

#define AUDIO_PLL_QDPAD(qd, div)	((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \
					  AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \
					 (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
					  AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK))

#define AUDIO_PLL_QDPMC_MAX		(AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \
						AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)

#define AUDIO_PLL_FOUT_MIN	620000000UL
#define AUDIO_PLL_FOUT_MAX	700000000UL

struct clk_audio_frac {
	struct clk_hw hw;
	struct regmap *regmap;
	u32 fracr;
	u8 nd;
};

struct clk_audio_pad {
	struct clk_hw hw;
	struct regmap *regmap;
	u8 qdaudio;
	u8 div;
};

struct clk_audio_pmc {
	struct clk_hw hw;
	struct regmap *regmap;
	u8 qdpmc;
};

#define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw)
#define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw)
#define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw)

static int clk_audio_pll_frac_enable(struct clk_hw *hw)
{
	struct clk_audio_frac *frac = to_clk_audio_frac(hw);

	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_RESETN, 0);
	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_RESETN,
			   AT91_PMC_AUDIO_PLL_RESETN);
	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1,
			   AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr);

	/*
	 * reset and enable have to be done in 2 separated writes
	 * for AT91_PMC_AUDIO_PLL0
	 */
	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_PLLEN |
			   AT91_PMC_AUDIO_PLL_ND_MASK,
			   AT91_PMC_AUDIO_PLL_PLLEN |
			   AT91_PMC_AUDIO_PLL_ND(frac->nd));

	return 0;
}

static int clk_audio_pll_pad_enable(struct clk_hw *hw)
{
	struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);

	regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1,
			   AT91_PMC_AUDIO_PLL_QDPAD_MASK,
			   AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div));
	regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN);

	return 0;
}

static int clk_audio_pll_pmc_enable(struct clk_hw *hw)
{
	struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);

	regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_PMCEN |
			   AT91_PMC_AUDIO_PLL_QDPMC_MASK,
			   AT91_PMC_AUDIO_PLL_PMCEN |
			   AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc));
	return 0;
}

static void clk_audio_pll_frac_disable(struct clk_hw *hw)
{
	struct clk_audio_frac *frac = to_clk_audio_frac(hw);

	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_PLLEN, 0);
	/* do it in 2 separated writes */
	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_RESETN, 0);
}

static void clk_audio_pll_pad_disable(struct clk_hw *hw)
{
	struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);

	regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_PADEN, 0);
}

static void clk_audio_pll_pmc_disable(struct clk_hw *hw)
{
	struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);

	regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
			   AT91_PMC_AUDIO_PLL_PMCEN, 0);
}

static unsigned long clk_audio_pll_fout(unsigned long parent_rate,
					unsigned long nd, unsigned long fracr)
{
	unsigned long long fr = (unsigned long long)parent_rate * fracr;

	pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);

	fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC);

	pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);

	return parent_rate * (nd + 1) + fr;
}

static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw,
						    unsigned long parent_rate)
{
	struct clk_audio_frac *frac = to_clk_audio_frac(hw);
	unsigned long fout;

	fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr);

	pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__,
		 fout, frac->nd, (unsigned long)frac->fracr);

	return fout;
}

static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw,
						   unsigned long parent_rate)
{
	struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
	unsigned long apad_rate = 0;

	if (apad_ck->qdaudio && apad_ck->div)
		apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);

	pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n",
		 __func__, apad_rate, apad_ck->div, apad_ck->qdaudio);

	return apad_rate;
}

static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw,
						   unsigned long parent_rate)
{
	struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
	unsigned long apmc_rate = 0;

	apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);

	pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__,
		 apmc_rate, apmc_ck->qdpmc);

	return apmc_rate;
}

static int clk_audio_pll_frac_compute_frac(unsigned long rate,
					   unsigned long parent_rate,
					   unsigned long *nd,
					   unsigned long *fracr)
{
	unsigned long long tmp, rem;

	if (!rate)
		return -EINVAL;

	tmp = rate;
	rem = do_div(tmp, parent_rate);
	if (!tmp || tmp >= AUDIO_PLL_ND_MAX)
		return -EINVAL;

	*nd = tmp - 1;

	tmp = rem * AUDIO_PLL_DIV_FRAC;
	tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate);
	if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK)
		return -EINVAL;

	/* we can cast here as we verified the bounds just above */
	*fracr = (unsigned long)tmp;

	return 0;
}

static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw,
					     struct clk_rate_request *req)
{
	unsigned long fracr, nd;
	int ret;

	pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__,
		 req->rate, req->best_parent_rate);

	req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX);

	req->min_rate = max(req->min_rate, AUDIO_PLL_FOUT_MIN);
	req->max_rate = min(req->max_rate, AUDIO_PLL_FOUT_MAX);

	ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate,
					      &nd, &fracr);
	if (ret)
		return ret;

	req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr);

	req->best_parent_hw = clk_hw_get_parent(hw);

	pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n",
		 __func__, req->rate, nd, fracr);

	return 0;
}

static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
					 unsigned long *parent_rate)
{
	struct clk_hw *pclk = clk_hw_get_parent(hw);
	long best_rate = -EINVAL;
	unsigned long best_parent_rate;
	unsigned long tmp_qd;
	u32 div;
	long tmp_rate;
	int tmp_diff;
	int best_diff = -1;

	pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
		 rate, *parent_rate);

	/*
	 * Rate divisor is actually made of two different divisors, multiplied
	 * between themselves before dividing the rate.
	 * tmp_qd goes from 1 to 31 and div is either 2 or 3.
	 * In order to avoid testing twice the rate divisor (e.g. divisor 12 can
	 * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop
	 * for a rate divisor when div is 2 and tmp_qd is a multiple of 3.
	 * We cannot inverse it (condition div is 3 and tmp_qd is even) or we
	 * would miss some rate divisor that aren't reachable with div being 2
	 * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus
	 * tmp_qd is even so we skip it because we think div 2 could make this
	 * rate divisor which isn't possible since tmp_qd has to be <= 31).
	 */
	for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++)
		for (div = 2; div <= 3; div++) {
			if (div == 2 && tmp_qd % 3 == 0)
				continue;

			best_parent_rate = clk_hw_round_rate(pclk,
							rate * tmp_qd * div);
			tmp_rate = best_parent_rate / (div * tmp_qd);
			tmp_diff = abs(rate - tmp_rate);

			if (best_diff < 0 || best_diff > tmp_diff) {
				*parent_rate = best_parent_rate;
				best_rate = tmp_rate;
				best_diff = tmp_diff;
			}
		}

	pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
		 __func__, best_rate, best_parent_rate);

	return best_rate;
}

static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
					 unsigned long *parent_rate)
{
	struct clk_hw *pclk = clk_hw_get_parent(hw);
	long best_rate = -EINVAL;
	unsigned long best_parent_rate = 0;
	u32 tmp_qd = 0, div;
	long tmp_rate;
	int tmp_diff;
	int best_diff = -1;

	pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
		 rate, *parent_rate);

	for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) {
		best_parent_rate = clk_round_rate(pclk->clk, rate * div);
		tmp_rate = best_parent_rate / div;
		tmp_diff = abs(rate - tmp_rate);

		if (best_diff < 0 || best_diff > tmp_diff) {
			*parent_rate = best_parent_rate;
			best_rate = tmp_rate;
			best_diff = tmp_diff;
			tmp_qd = div;
		}
	}

	pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n",
		 __func__, best_rate, *parent_rate, tmp_qd - 1);

	return best_rate;
}

static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate,
				       unsigned long parent_rate)
{
	struct clk_audio_frac *frac = to_clk_audio_frac(hw);
	unsigned long fracr, nd;
	int ret;

	pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
		 parent_rate);

	if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX)
		return -EINVAL;

	ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr);
	if (ret)
		return ret;

	frac->nd = nd;
	frac->fracr = fracr;

	return 0;
}

static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long parent_rate)
{
	struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
	u8 tmp_div;

	pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
		 rate, parent_rate);

	if (!rate)
		return -EINVAL;

	tmp_div = parent_rate / rate;
	if (tmp_div % 3 == 0) {
		apad_ck->qdaudio = tmp_div / 3;
		apad_ck->div = 3;
	} else {
		apad_ck->qdaudio = tmp_div / 2;
		apad_ck->div = 2;
	}

	return 0;
}

static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long parent_rate)
{
	struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);

	if (!rate)
		return -EINVAL;

	pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
		 rate, parent_rate);

	apmc_ck->qdpmc = parent_rate / rate - 1;

	return 0;
}

static const struct clk_ops audio_pll_frac_ops = {
	.enable = clk_audio_pll_frac_enable,
	.disable = clk_audio_pll_frac_disable,
	.recalc_rate = clk_audio_pll_frac_recalc_rate,
	.determine_rate = clk_audio_pll_frac_determine_rate,
	.set_rate = clk_audio_pll_frac_set_rate,
};

static const struct clk_ops audio_pll_pad_ops = {
	.enable = clk_audio_pll_pad_enable,
	.disable = clk_audio_pll_pad_disable,
	.recalc_rate = clk_audio_pll_pad_recalc_rate,
	.round_rate = clk_audio_pll_pad_round_rate,
	.set_rate = clk_audio_pll_pad_set_rate,
};

static const struct clk_ops audio_pll_pmc_ops = {
	.enable = clk_audio_pll_pmc_enable,
	.disable = clk_audio_pll_pmc_disable,
	.recalc_rate = clk_audio_pll_pmc_recalc_rate,
	.round_rate = clk_audio_pll_pmc_round_rate,
	.set_rate = clk_audio_pll_pmc_set_rate,
};

struct clk_hw * __init
at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
				 const char *parent_name)
{
	struct clk_audio_frac *frac_ck;
	struct clk_init_data init = {};
	int ret;

	frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
	if (!frac_ck)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &audio_pll_frac_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = CLK_SET_RATE_GATE;

	frac_ck->hw.init = &init;
	frac_ck->regmap = regmap;

	ret = clk_hw_register(NULL, &frac_ck->hw);
	if (ret) {
		kfree(frac_ck);
		return ERR_PTR(ret);
	}

	return &frac_ck->hw;
}

struct clk_hw * __init
at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
				const char *parent_name)
{
	struct clk_audio_pad *apad_ck;
	struct clk_init_data init;
	int ret;

	apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
	if (!apad_ck)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &audio_pll_pad_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
		CLK_SET_RATE_PARENT;

	apad_ck->hw.init = &init;
	apad_ck->regmap = regmap;

	ret = clk_hw_register(NULL, &apad_ck->hw);
	if (ret) {
		kfree(apad_ck);
		return ERR_PTR(ret);
	}

	return &apad_ck->hw;
}

struct clk_hw * __init
at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
				const char *parent_name)
{
	struct clk_audio_pmc *apmc_ck;
	struct clk_init_data init;
	int ret;

	apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
	if (!apmc_ck)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &audio_pll_pmc_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
		CLK_SET_RATE_PARENT;

	apmc_ck->hw.init = &init;
	apmc_ck->regmap = regmap;

	ret = clk_hw_register(NULL, &apmc_ck->hw);
	if (ret) {
		kfree(apmc_ck);
		return ERR_PTR(ret);
	}

	return &apmc_ck->hw;
}
Commit	Line	Data
0865805d QS	1	/*
	2	* Copyright (C) 2016 Atmel Corporation,
	3	* Songjun Wu <songjun.wu@atmel.com>,
	4	* Nicolas Ferre <nicolas.ferre@atmel.com>
	5	* Copyright (C) 2017 Free Electrons,
	6	* Quentin Schulz <quentin.schulz@free-electrons.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
	14	* (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
	15	* its own parent. PMC and PAD can then divide the FRAC rate to best match the
	16	* asked rate.
	17	*
	18	* Traits of FRAC clock:
	19	* enable - clk_enable writes nd, fracr parameters and enables PLL
	20	* rate - rate is adjustable.
	21	* clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
	22	* parent - fixed parent. No clk_set_parent support
	23	*
	24	* Traits of PMC clock:
	25	* enable - clk_enable writes qdpmc, and enables PMC output
	26	* rate - rate is adjustable.
	27	* clk->rate = parent->rate / (qdpmc + 1)
	28	* parent - fixed parent. No clk_set_parent support
	29	*
	30	* Traits of PAD clock:
	31	* enable - clk_enable writes divisors and enables PAD output
	32	* rate - rate is adjustable.
	33	* clk->rate = parent->rate / (qdaudio * div))
	34	* parent - fixed parent. No clk_set_parent support
	35	*
	36	*/
	37
	38	#include <linux/clk.h>
	39	#include <linux/clk-provider.h>
	40	#include <linux/clk/at91_pmc.h>
	41	#include <linux/of.h>
	42	#include <linux/mfd/syscon.h>
	43	#include <linux/regmap.h>
	44	#include <linux/slab.h>
	45
08979ee5 AB	46	#include "pmc.h"
08979ee5 AB	47
0865805d QS	48	#define AUDIO_PLL_DIV_FRAC BIT(22)
	49	#define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \
	50	AT91_PMC_AUDIO_PLL_ND_OFFSET)
	51
	52	#define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \
	53	AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) \| \
	54	(AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
	55	AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK))
	56
	57	#define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \
	58	AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
	59
	60	#define AUDIO_PLL_FOUT_MIN 620000000UL
	61	#define AUDIO_PLL_FOUT_MAX 700000000UL
	62
	63	struct clk_audio_frac {
	64	struct clk_hw hw;
	65	struct regmap *regmap;
	66	u32 fracr;
	67	u8 nd;
	68	};
	69
	70	struct clk_audio_pad {
	71	struct clk_hw hw;
	72	struct regmap *regmap;
	73	u8 qdaudio;
	74	u8 div;
	75	};
	76
	77	struct clk_audio_pmc {
	78	struct clk_hw hw;
	79	struct regmap *regmap;
	80	u8 qdpmc;
	81	};
	82
	83	#define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw)
	84	#define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw)
	85	#define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw)
	86
	87	static int clk_audio_pll_frac_enable(struct clk_hw *hw)
	88	{
	89	struct clk_audio_frac *frac = to_clk_audio_frac(hw);
	90
	91	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
	92	AT91_PMC_AUDIO_PLL_RESETN, 0);
	93	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
	94	AT91_PMC_AUDIO_PLL_RESETN,
	95	AT91_PMC_AUDIO_PLL_RESETN);
	96	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1,
	97	AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr);
	98
	99	/*
	100	* reset and enable have to be done in 2 separated writes
	101	* for AT91_PMC_AUDIO_PLL0
	102	*/
	103	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
	104	AT91_PMC_AUDIO_PLL_PLLEN \|
	105	AT91_PMC_AUDIO_PLL_ND_MASK,
	106	AT91_PMC_AUDIO_PLL_PLLEN \|
	107	AT91_PMC_AUDIO_PLL_ND(frac->nd));
	108
	109	return 0;
	110	}
	111
112	static int clk_audio_pll_pad_enable(struct clk_hw *hw)
113	{
114	struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
115
116	regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1,
117	AT91_PMC_AUDIO_PLL_QDPAD_MASK,
118	AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div));
119	regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
120	AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN);
121
122	return 0;
123	}
124
125	static int clk_audio_pll_pmc_enable(struct clk_hw *hw)
126	{
127	struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
128
129	regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
130	AT91_PMC_AUDIO_PLL_PMCEN \|
131	AT91_PMC_AUDIO_PLL_QDPMC_MASK,
132	AT91_PMC_AUDIO_PLL_PMCEN \|
133	AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc));
134	return 0;
135	}
136
137	static void clk_audio_pll_frac_disable(struct clk_hw *hw)
138	{
139	struct clk_audio_frac *frac = to_clk_audio_frac(hw);
140
141	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
142	AT91_PMC_AUDIO_PLL_PLLEN, 0);
143	/* do it in 2 separated writes */
144	regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
145	AT91_PMC_AUDIO_PLL_RESETN, 0);
146	}
147
148	static void clk_audio_pll_pad_disable(struct clk_hw *hw)
149	{
150	struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
151
152	regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
153	AT91_PMC_AUDIO_PLL_PADEN, 0);
154	}
155
156	static void clk_audio_pll_pmc_disable(struct clk_hw *hw)
157	{
158	struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
159
160	regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
161	AT91_PMC_AUDIO_PLL_PMCEN, 0);
162	}
163
164	static unsigned long clk_audio_pll_fout(unsigned long parent_rate,
165	unsigned long nd, unsigned long fracr)
166	{
167	unsigned long long fr = (unsigned long long)parent_rate * fracr;
168
169	pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
170
171	fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC);
172
173	pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
174
175	return parent_rate * (nd + 1) + fr;
176	}
177
178	static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw,
179	unsigned long parent_rate)
180	{
181	struct clk_audio_frac *frac = to_clk_audio_frac(hw);
182	unsigned long fout;
183
184	fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr);
185
186	pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__,
187	fout, frac->nd, (unsigned long)frac->fracr);
188
189	return fout;
190	}
191
192	static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw,
193	unsigned long parent_rate)
194	{
195	struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
196	unsigned long apad_rate = 0;
197
198	if (apad_ck->qdaudio && apad_ck->div)
199	apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);
200
201	pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n",
202	__func__, apad_rate, apad_ck->div, apad_ck->qdaudio);
203
204	return apad_rate;
205	}
206
207	static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw,
208	unsigned long parent_rate)
209	{
210	struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
211	unsigned long apmc_rate = 0;
212
213	apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);
214
215	pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__,
216	apmc_rate, apmc_ck->qdpmc);
217
218	return apmc_rate;
219	}
220
221	static int clk_audio_pll_frac_compute_frac(unsigned long rate,
222	unsigned long parent_rate,
223	unsigned long *nd,
224	unsigned long *fracr)
225	{
226	unsigned long long tmp, rem;
227
228	if (!rate)
229	return -EINVAL;
230
231	tmp = rate;
232	rem = do_div(tmp, parent_rate);
233	if (!tmp \|\| tmp >= AUDIO_PLL_ND_MAX)
234	return -EINVAL;
235
236	*nd = tmp - 1;
237
238	tmp = rem * AUDIO_PLL_DIV_FRAC;
239	tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate);
240	if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK)
241	return -EINVAL;
242
243	/* we can cast here as we verified the bounds just above */
244	*fracr = (unsigned long)tmp;
245
246	return 0;
247	}
248
249	static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw,
250	struct clk_rate_request *req)
251	{
252	unsigned long fracr, nd;
253	int ret;
254
255	pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__,
256	req->rate, req->best_parent_rate);
257
258	req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX);
259
260	req->min_rate = max(req->min_rate, AUDIO_PLL_FOUT_MIN);
261	req->max_rate = min(req->max_rate, AUDIO_PLL_FOUT_MAX);
262
263	ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate,
264	&nd, &fracr);
265	if (ret)
266	return ret;
267
268	req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr);
269
270	req->best_parent_hw = clk_hw_get_parent(hw);
271
272	pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n",
273	__func__, req->rate, nd, fracr);
274
275	return 0;
276	}
277
278	static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
279	unsigned long *parent_rate)
280	{
281	struct clk_hw *pclk = clk_hw_get_parent(hw);
282	long best_rate = -EINVAL;
283	unsigned long best_parent_rate;
284	unsigned long tmp_qd;
285	u32 div;
286	long tmp_rate;
287	int tmp_diff;
288	int best_diff = -1;
289
290	pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
291	rate, *parent_rate);
292
293	/*
294	* Rate divisor is actually made of two different divisors, multiplied
295	* between themselves before dividing the rate.
296	* tmp_qd goes from 1 to 31 and div is either 2 or 3.
297	* In order to avoid testing twice the rate divisor (e.g. divisor 12 can
298	* be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop
299	* for a rate divisor when div is 2 and tmp_qd is a multiple of 3.
300	* We cannot inverse it (condition div is 3 and tmp_qd is even) or we
301	* would miss some rate divisor that aren't reachable with div being 2
302	* (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus
303	* tmp_qd is even so we skip it because we think div 2 could make this
304	* rate divisor which isn't possible since tmp_qd has to be <= 31).
305	*/
306	for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++)
307	for (div = 2; div <= 3; div++) {
308	if (div == 2 && tmp_qd % 3 == 0)
309	continue;
310
311	best_parent_rate = clk_hw_round_rate(pclk,
312	rate * tmp_qd * div);
313	tmp_rate = best_parent_rate / (div * tmp_qd);
314	tmp_diff = abs(rate - tmp_rate);
315
316	if (best_diff < 0 \|\| best_diff > tmp_diff) {
317	*parent_rate = best_parent_rate;
318	best_rate = tmp_rate;
319	best_diff = tmp_diff;
320	}
321	}
322
323	pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
324	__func__, best_rate, best_parent_rate);
325
326	return best_rate;
327	}
328
329	static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
330	unsigned long *parent_rate)
331	{
332	struct clk_hw *pclk = clk_hw_get_parent(hw);
333	long best_rate = -EINVAL;
334	unsigned long best_parent_rate = 0;
335	u32 tmp_qd = 0, div;
336	long tmp_rate;
337	int tmp_diff;
338	int best_diff = -1;
339
340	pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
341	rate, *parent_rate);
342
343	for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) {
344	best_parent_rate = clk_round_rate(pclk->clk, rate * div);
345	tmp_rate = best_parent_rate / div;
346	tmp_diff = abs(rate - tmp_rate);
347
348	if (best_diff < 0 \|\| best_diff > tmp_diff) {
349	*parent_rate = best_parent_rate;
350	best_rate = tmp_rate;
351	best_diff = tmp_diff;
352	tmp_qd = div;
353	}
354	}
355
356	pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n",
357	__func__, best_rate, *parent_rate, tmp_qd - 1);
358
359	return best_rate;
360	}
361
362	static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate,
363	unsigned long parent_rate)
364	{
365	struct clk_audio_frac *frac = to_clk_audio_frac(hw);
366	unsigned long fracr, nd;
367	int ret;
368
369	pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
370	parent_rate);
371
372	if (rate < AUDIO_PLL_FOUT_MIN \|\| rate > AUDIO_PLL_FOUT_MAX)
373	return -EINVAL;
374
375	ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr);
376	if (ret)
377	return ret;
378
379	frac->nd = nd;
380	frac->fracr = fracr;
381
382	return 0;
383	}
384
385	static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate,
386	unsigned long parent_rate)
387	{
388	struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
389	u8 tmp_div;
390
391	pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
392	rate, parent_rate);
393
394	if (!rate)
395	return -EINVAL;
396
397	tmp_div = parent_rate / rate;
398	if (tmp_div % 3 == 0) {
399	apad_ck->qdaudio = tmp_div / 3;
400	apad_ck->div = 3;
401	} else {
402	apad_ck->qdaudio = tmp_div / 2;
403	apad_ck->div = 2;
404	}
405
406	return 0;
407	}
408
409	static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate,
410	unsigned long parent_rate)
411	{
412	struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
413
414	if (!rate)
415	return -EINVAL;
416
417	pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
418	rate, parent_rate);
419
420	apmc_ck->qdpmc = parent_rate / rate - 1;
421
422	return 0;
423	}
424
425	static const struct clk_ops audio_pll_frac_ops = {
426	.enable = clk_audio_pll_frac_enable,
427	.disable = clk_audio_pll_frac_disable,
428	.recalc_rate = clk_audio_pll_frac_recalc_rate,
429	.determine_rate = clk_audio_pll_frac_determine_rate,
430	.set_rate = clk_audio_pll_frac_set_rate,
431	};
432
433	static const struct clk_ops audio_pll_pad_ops = {
434	.enable = clk_audio_pll_pad_enable,
435	.disable = clk_audio_pll_pad_disable,
436	.recalc_rate = clk_audio_pll_pad_recalc_rate,
437	.round_rate = clk_audio_pll_pad_round_rate,
438	.set_rate = clk_audio_pll_pad_set_rate,
439	};
440
441	static const struct clk_ops audio_pll_pmc_ops = {
442	.enable = clk_audio_pll_pmc_enable,
443	.disable = clk_audio_pll_pmc_disable,
444	.recalc_rate = clk_audio_pll_pmc_recalc_rate,
445	.round_rate = clk_audio_pll_pmc_round_rate,
446	.set_rate = clk_audio_pll_pmc_set_rate,
447	};
448
08979ee5 AB	449	struct clk_hw * __init
	450	at91_clk_register_audio_pll_frac(struct regmap regmap, const char name,
	451	const char *parent_name)
0865805d	452	{
08979ee5 AB	453	struct clk_audio_frac *frac_ck;
08979ee5 AB	454	struct clk_init_data init = {};
0865805d QS	455	int ret;
0865805d QS	456
08979ee5 AB	457	frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
	458	if (!frac_ck)
	459	return ERR_PTR(-ENOMEM);
0865805d	460
08979ee5 AB	461	init.name = name;
	462	init.ops = &audio_pll_frac_ops;
	463	init.parent_names = &parent_name;
	464	init.num_parents = 1;
	465	init.flags = CLK_SET_RATE_GATE;
0865805d	466
08979ee5 AB	467	frac_ck->hw.init = &init;
08979ee5 AB	468	frac_ck->regmap = regmap;
0865805d	469
08979ee5 AB	470	ret = clk_hw_register(NULL, &frac_ck->hw);
	471	if (ret) {
	472	kfree(frac_ck);
	473	return ERR_PTR(ret);
	474	}
0865805d	475
08979ee5	476	return &frac_ck->hw;
0865805d QS	477	}
0865805d QS	478
08979ee5 AB	479	struct clk_hw * __init
	480	at91_clk_register_audio_pll_pad(struct regmap regmap, const char name,
	481	const char *parent_name)
0865805d QS	482	{
0865805d QS	483	struct clk_audio_pad *apad_ck;
08979ee5 AB	484	struct clk_init_data init;
08979ee5 AB	485	int ret;
0865805d QS	486
	487	apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
	488	if (!apad_ck)
08979ee5	489	return ERR_PTR(-ENOMEM);
0865805d	490
08979ee5	491	init.name = name;
0865805d	492	init.ops = &audio_pll_pad_ops;
08979ee5 AB	493	init.parent_names = &parent_name;
08979ee5 AB	494	init.num_parents = 1;
0865805d QS	495	init.flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE \|
	496	CLK_SET_RATE_PARENT;
	497
08979ee5 AB	498	apad_ck->hw.init = &init;
	499	apad_ck->regmap = regmap;
	500
	501	ret = clk_hw_register(NULL, &apad_ck->hw);
	502	if (ret) {
0865805d	503	kfree(apad_ck);
08979ee5 AB	504	return ERR_PTR(ret);
	505	}
	506
	507	return &apad_ck->hw;
0865805d QS	508	}
0865805d QS	509
08979ee5 AB	510	struct clk_hw * __init
	511	at91_clk_register_audio_pll_pmc(struct regmap regmap, const char name,
	512	const char *parent_name)
0865805d	513	{
7fa75007	514	struct clk_audio_pmc *apmc_ck;
08979ee5 AB	515	struct clk_init_data init;
08979ee5 AB	516	int ret;
0865805d QS	517
	518	apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
	519	if (!apmc_ck)
08979ee5	520	return ERR_PTR(-ENOMEM);
0865805d	521
08979ee5	522	init.name = name;
0865805d	523	init.ops = &audio_pll_pmc_ops;
08979ee5 AB	524	init.parent_names = &parent_name;
08979ee5 AB	525	init.num_parents = 1;
0865805d QS	526	init.flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE \|
	527	CLK_SET_RATE_PARENT;
	528
08979ee5 AB	529	apmc_ck->hw.init = &init;
	530	apmc_ck->regmap = regmap;
	531
	532	ret = clk_hw_register(NULL, &apmc_ck->hw);
	533	if (ret) {
0865805d	534	kfree(apmc_ck);
08979ee5 AB	535	return ERR_PTR(ret);
	536	}
	537
	538	return &apmc_ck->hw;
	539	}