[linux-block.git] / drivers / clk / at91 / at91sam9x5.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/slab.h>

#include <dt-bindings/clock/at91.h>

#include "pmc.h"

static DEFINE_SPINLOCK(mck_lock);

static const struct clk_master_characteristics mck_characteristics = {
	.output = { .min = 0, .max = 133333333 },
	.divisors = { 1, 2, 4, 3 },
	.have_div3_pres = 1,
};

static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };

static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };

static const struct clk_range plla_outputs[] = {
	{ .min = 745000000, .max = 800000000 },
	{ .min = 695000000, .max = 750000000 },
	{ .min = 645000000, .max = 700000000 },
	{ .min = 595000000, .max = 650000000 },
	{ .min = 545000000, .max = 600000000 },
	{ .min = 495000000, .max = 555000000 },
	{ .min = 445000000, .max = 500000000 },
	{ .min = 400000000, .max = 450000000 },
};

static const struct clk_pll_characteristics plla_characteristics = {
	.input = { .min = 2000000, .max = 32000000 },
	.num_output = ARRAY_SIZE(plla_outputs),
	.output = plla_outputs,
	.icpll = plla_icpll,
	.out = plla_out,
};

static const struct {
	char *n;
	char *p;
	unsigned long flags;
	u8 id;
} at91sam9x5_systemck[] = {
	/*
	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
	 * to keep it enabled in case there is no Linux consumer for it.
	 */
	{ .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
	{ .n = "smdck", .p = "smdclk",   .id = 4 },
	{ .n = "uhpck", .p = "usbck",    .id = 6 },
	{ .n = "udpck", .p = "usbck",    .id = 7 },
	{ .n = "pck0",  .p = "prog0",    .id = 8 },
	{ .n = "pck1",  .p = "prog1",    .id = 9 },
};

static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
	.offset = 0x10c,
	.cmd = BIT(12),
	.pid_mask = GENMASK(5, 0),
	.div_mask = GENMASK(17, 16),
};

struct pck {
	char *n;
	u8 id;
};

static const struct pck at91sam9x5_periphck[] = {
	{ .n = "pioAB_clk",  .id = 2, },
	{ .n = "pioCD_clk",  .id = 3, },
	{ .n = "smd_clk",    .id = 4, },
	{ .n = "usart0_clk", .id = 5, },
	{ .n = "usart1_clk", .id = 6, },
	{ .n = "usart2_clk", .id = 7, },
	{ .n = "twi0_clk",   .id = 9, },
	{ .n = "twi1_clk",   .id = 10, },
	{ .n = "twi2_clk",   .id = 11, },
	{ .n = "mci0_clk",   .id = 12, },
	{ .n = "spi0_clk",   .id = 13, },
	{ .n = "spi1_clk",   .id = 14, },
	{ .n = "uart0_clk",  .id = 15, },
	{ .n = "uart1_clk",  .id = 16, },
	{ .n = "tcb0_clk",   .id = 17, },
	{ .n = "pwm_clk",    .id = 18, },
	{ .n = "adc_clk",    .id = 19, },
	{ .n = "dma0_clk",   .id = 20, },
	{ .n = "dma1_clk",   .id = 21, },
	{ .n = "uhphs_clk",  .id = 22, },
	{ .n = "udphs_clk",  .id = 23, },
	{ .n = "mci1_clk",   .id = 26, },
	{ .n = "ssc0_clk",   .id = 28, },
};

static const struct pck at91sam9g15_periphck[] = {
	{ .n = "lcdc_clk", .id = 25, },
	{ /* sentinel */}
};

static const struct pck at91sam9g25_periphck[] = {
	{ .n = "usart3_clk", .id = 8, },
	{ .n = "macb0_clk", .id = 24, },
	{ .n = "isi_clk", .id = 25, },
	{ /* sentinel */}
};

static const struct pck at91sam9g35_periphck[] = {
	{ .n = "macb0_clk", .id = 24, },
	{ .n = "lcdc_clk", .id = 25, },
	{ /* sentinel */}
};

static const struct pck at91sam9x25_periphck[] = {
	{ .n = "usart3_clk", .id = 8, },
	{ .n = "macb0_clk", .id = 24, },
	{ .n = "macb1_clk", .id = 27, },
	{ .n = "can0_clk", .id = 29, },
	{ .n = "can1_clk", .id = 30, },
	{ /* sentinel */}
};

static const struct pck at91sam9x35_periphck[] = {
	{ .n = "macb0_clk", .id = 24, },
	{ .n = "lcdc_clk", .id = 25, },
	{ .n = "can0_clk", .id = 29, },
	{ .n = "can1_clk", .id = 30, },
	{ /* sentinel */}
};

static void __init at91sam9x5_pmc_setup(struct device_node *np,
					const struct pck *extra_pcks,
					bool has_lcdck)
{
	struct clk_range range = CLK_RANGE(0, 0);
	const char *slck_name, *mainxtal_name;
	struct pmc_data *at91sam9x5_pmc;
	const char *parent_names[6];
	struct regmap *regmap;
	struct clk_hw *hw;
	int i;
	bool bypass;

	i = of_property_match_string(np, "clock-names", "slow_clk");
	if (i < 0)
		return;

	slck_name = of_clk_get_parent_name(np, i);

	i = of_property_match_string(np, "clock-names", "main_xtal");
	if (i < 0)
		return;
	mainxtal_name = of_clk_get_parent_name(np, i);

	regmap = device_node_to_regmap(np);
	if (IS_ERR(regmap))
		return;

	at91sam9x5_pmc = pmc_data_allocate(PMC_PLLACK + 1,
					   nck(at91sam9x5_systemck), 31, 0, 2);
	if (!at91sam9x5_pmc)
		return;

	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
					   50000000);
	if (IS_ERR(hw))
		goto err_free;

	bypass = of_property_read_bool(np, "atmel,osc-bypass");

	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
					bypass);
	if (IS_ERR(hw))
		goto err_free;

	parent_names[0] = "main_rc_osc";
	parent_names[1] = "main_osc";
	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
	if (IS_ERR(hw))
		goto err_free;

	at91sam9x5_pmc->chws[PMC_MAIN] = hw;

	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
				   &at91rm9200_pll_layout, &plla_characteristics);
	if (IS_ERR(hw))
		goto err_free;

	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
	if (IS_ERR(hw))
		goto err_free;

	at91sam9x5_pmc->chws[PMC_PLLACK] = hw;

	hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
	if (IS_ERR(hw))
		goto err_free;

	at91sam9x5_pmc->chws[PMC_UTMI] = hw;

	parent_names[0] = slck_name;
	parent_names[1] = "mainck";
	parent_names[2] = "plladivck";
	parent_names[3] = "utmick";
	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
					   parent_names, NULL,
					   &at91sam9x5_master_layout,
					   &mck_characteristics, &mck_lock);
	if (IS_ERR(hw))
		goto err_free;

	hw = at91_clk_register_master_div(regmap, "masterck_div",
					  "masterck_pres", NULL,
					  &at91sam9x5_master_layout,
					  &mck_characteristics, &mck_lock,
					  CLK_SET_RATE_GATE, 0);
	if (IS_ERR(hw))
		goto err_free;

	at91sam9x5_pmc->chws[PMC_MCK] = hw;

	parent_names[0] = "plladivck";
	parent_names[1] = "utmick";
	hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
	if (IS_ERR(hw))
		goto err_free;

	hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
	if (IS_ERR(hw))
		goto err_free;

	parent_names[0] = slck_name;
	parent_names[1] = "mainck";
	parent_names[2] = "plladivck";
	parent_names[3] = "utmick";
	parent_names[4] = "masterck_div";
	for (i = 0; i < 2; i++) {
		char name[6];

		snprintf(name, sizeof(name), "prog%d", i);

		hw = at91_clk_register_programmable(regmap, name,
						    parent_names, NULL, 5, i,
						    &at91sam9x5_programmable_layout,
						    NULL);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->pchws[i] = hw;
	}

	for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
		hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
					      at91sam9x5_systemck[i].p, NULL,
					      at91sam9x5_systemck[i].id,
					      at91sam9x5_systemck[i].flags);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
	}

	if (has_lcdck) {
		hw = at91_clk_register_system(regmap, "lcdck", "masterck_div",
					      NULL, 3, 0);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->shws[3] = hw;
	}

	for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
							 &at91sam9x5_pcr_layout,
							 at91sam9x5_periphck[i].n,
							 "masterck_div", NULL,
							 at91sam9x5_periphck[i].id,
							 &range, INT_MIN, 0);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
	}

	for (i = 0; extra_pcks[i].id; i++) {
		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
							 &at91sam9x5_pcr_layout,
							 extra_pcks[i].n,
							 "masterck_div", NULL,
							 extra_pcks[i].id,
							 &range, INT_MIN, 0);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
	}

	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);

	return;

err_free:
	kfree(at91sam9x5_pmc);
}

static void __init at91sam9g15_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
}

CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup);

static void __init at91sam9g25_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
}

CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup);

static void __init at91sam9g35_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
}

CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup);

static void __init at91sam9x25_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
}

CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup);

static void __init at91sam9x35_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
}

CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup);
Commit	Line	Data
1eabdc2f AB	1	// SPDX-License-Identifier: GPL-2.0
	2	#include <linux/clk-provider.h>
	3	#include <linux/mfd/syscon.h>
	4	#include <linux/slab.h>
	5
	6	#include <dt-bindings/clock/at91.h>
	7
	8	#include "pmc.h"
	9
7a110b91 CB	10	static DEFINE_SPINLOCK(mck_lock);
7a110b91 CB	11
1eabdc2f AB	12	static const struct clk_master_characteristics mck_characteristics = {
	13	.output = { .min = 0, .max = 133333333 },
	14	.divisors = { 1, 2, 4, 3 },
	15	.have_div3_pres = 1,
	16	};
	17
	18	static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
	19
	20	static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
	21
7b4c162e	22	static const struct clk_range plla_outputs[] = {
1eabdc2f AB	23	{ .min = 745000000, .max = 800000000 },
	24	{ .min = 695000000, .max = 750000000 },
	25	{ .min = 645000000, .max = 700000000 },
	26	{ .min = 595000000, .max = 650000000 },
	27	{ .min = 545000000, .max = 600000000 },
	28	{ .min = 495000000, .max = 555000000 },
	29	{ .min = 445000000, .max = 500000000 },
	30	{ .min = 400000000, .max = 450000000 },
	31	};
	32
	33	static const struct clk_pll_characteristics plla_characteristics = {
	34	.input = { .min = 2000000, .max = 32000000 },
	35	.num_output = ARRAY_SIZE(plla_outputs),
	36	.output = plla_outputs,
	37	.icpll = plla_icpll,
	38	.out = plla_out,
	39	};
	40
	41	static const struct {
	42	char *n;
	43	char *p;
68b3b6f1	44	unsigned long flags;
1eabdc2f AB	45	u8 id;
1eabdc2f AB	46	} at91sam9x5_systemck[] = {
68b3b6f1 CB	47	/*
	48	* ddrck feeds DDR controller and is enabled by bootloader thus we need
	49	* to keep it enabled in case there is no Linux consumer for it.
	50	*/
	51	{ .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
1eabdc2f AB	52	{ .n = "smdck", .p = "smdclk", .id = 4 },
	53	{ .n = "uhpck", .p = "usbck", .id = 6 },
	54	{ .n = "udpck", .p = "usbck", .id = 7 },
	55	{ .n = "pck0", .p = "prog0", .id = 8 },
	56	{ .n = "pck1", .p = "prog1", .id = 9 },
	57	};
	58
cb4f4949 AB	59	static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
	60	.offset = 0x10c,
	61	.cmd = BIT(12),
	62	.pid_mask = GENMASK(5, 0),
	63	.div_mask = GENMASK(17, 16),
	64	};
	65
1eabdc2f AB	66	struct pck {
	67	char *n;
	68	u8 id;
	69	};
	70
	71	static const struct pck at91sam9x5_periphck[] = {
	72	{ .n = "pioAB_clk", .id = 2, },
	73	{ .n = "pioCD_clk", .id = 3, },
	74	{ .n = "smd_clk", .id = 4, },
	75	{ .n = "usart0_clk", .id = 5, },
	76	{ .n = "usart1_clk", .id = 6, },
	77	{ .n = "usart2_clk", .id = 7, },
	78	{ .n = "twi0_clk", .id = 9, },
	79	{ .n = "twi1_clk", .id = 10, },
	80	{ .n = "twi2_clk", .id = 11, },
	81	{ .n = "mci0_clk", .id = 12, },
	82	{ .n = "spi0_clk", .id = 13, },
	83	{ .n = "spi1_clk", .id = 14, },
	84	{ .n = "uart0_clk", .id = 15, },
	85	{ .n = "uart1_clk", .id = 16, },
	86	{ .n = "tcb0_clk", .id = 17, },
	87	{ .n = "pwm_clk", .id = 18, },
	88	{ .n = "adc_clk", .id = 19, },
	89	{ .n = "dma0_clk", .id = 20, },
	90	{ .n = "dma1_clk", .id = 21, },
	91	{ .n = "uhphs_clk", .id = 22, },
	92	{ .n = "udphs_clk", .id = 23, },
	93	{ .n = "mci1_clk", .id = 26, },
	94	{ .n = "ssc0_clk", .id = 28, },
	95	};
	96
	97	static const struct pck at91sam9g15_periphck[] = {
	98	{ .n = "lcdc_clk", .id = 25, },
	99	{ /* sentinel */}
	100	};
	101
	102	static const struct pck at91sam9g25_periphck[] = {
	103	{ .n = "usart3_clk", .id = 8, },
	104	{ .n = "macb0_clk", .id = 24, },
	105	{ .n = "isi_clk", .id = 25, },
	106	{ /* sentinel */}
	107	};
	108
	109	static const struct pck at91sam9g35_periphck[] = {
	110	{ .n = "macb0_clk", .id = 24, },
	111	{ .n = "lcdc_clk", .id = 25, },
	112	{ /* sentinel */}
	113	};
	114
	115	static const struct pck at91sam9x25_periphck[] = {
	116	{ .n = "usart3_clk", .id = 8, },
	117	{ .n = "macb0_clk", .id = 24, },
	118	{ .n = "macb1_clk", .id = 27, },
	119	{ .n = "can0_clk", .id = 29, },
	120	{ .n = "can1_clk", .id = 30, },
	121	{ /* sentinel */}
	122	};
	123
	124	static const struct pck at91sam9x35_periphck[] = {
	125	{ .n = "macb0_clk", .id = 24, },
	126	{ .n = "lcdc_clk", .id = 25, },
	127	{ .n = "can0_clk", .id = 29, },
	128	{ .n = "can1_clk", .id = 30, },
	129	{ /* sentinel */}
130	};
131
132	static void __init at91sam9x5_pmc_setup(struct device_node *np,
133	const struct pck *extra_pcks,
134	bool has_lcdck)
135	{
136	struct clk_range range = CLK_RANGE(0, 0);
137	const char slck_name, mainxtal_name;
138	struct pmc_data *at91sam9x5_pmc;
139	const char *parent_names[6];
140	struct regmap *regmap;
141	struct clk_hw *hw;
142	int i;
143	bool bypass;
144
145	i = of_property_match_string(np, "clock-names", "slow_clk");
146	if (i < 0)
147	return;
148
149	slck_name = of_clk_get_parent_name(np, i);
150
151	i = of_property_match_string(np, "clock-names", "main_xtal");
152	if (i < 0)
153	return;
154	mainxtal_name = of_clk_get_parent_name(np, i);
155
6956eb33	156	regmap = device_node_to_regmap(np);
1eabdc2f AB	157	if (IS_ERR(regmap))
	158	return;
	159
03a1ee1d	160	at91sam9x5_pmc = pmc_data_allocate(PMC_PLLACK + 1,
99767cd4	161	nck(at91sam9x5_systemck), 31, 0, 2);
1eabdc2f AB	162	if (!at91sam9x5_pmc)
	163	return;
	164
	165	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
	166	50000000);
	167	if (IS_ERR(hw))
	168	goto err_free;
	169
	170	bypass = of_property_read_bool(np, "atmel,osc-bypass");
	171
b5105e37	172	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
1eabdc2f AB	173	bypass);
	174	if (IS_ERR(hw))
	175	goto err_free;
	176
	177	parent_names[0] = "main_rc_osc";
	178	parent_names[1] = "main_osc";
b5105e37	179	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
1eabdc2f AB	180	if (IS_ERR(hw))
	181	goto err_free;
	182
	183	at91sam9x5_pmc->chws[PMC_MAIN] = hw;
	184
	185	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
	186	&at91rm9200_pll_layout, &plla_characteristics);
	187	if (IS_ERR(hw))
	188	goto err_free;
	189
	190	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
	191	if (IS_ERR(hw))
	192	goto err_free;
	193
03a1ee1d MM	194	at91sam9x5_pmc->chws[PMC_PLLACK] = hw;
03a1ee1d MM	195
077782e3	196	hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
1eabdc2f AB	197	if (IS_ERR(hw))
	198	goto err_free;
	199
	200	at91sam9x5_pmc->chws[PMC_UTMI] = hw;
	201
	202	parent_names[0] = slck_name;
	203	parent_names[1] = "mainck";
	204	parent_names[2] = "plladivck";
	205	parent_names[3] = "utmick";
7a110b91	206	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
171e502c	207	parent_names, NULL,
7a110b91	208	&at91sam9x5_master_layout,
8e842f02	209	&mck_characteristics, &mck_lock);
7a110b91 CB	210	if (IS_ERR(hw))
	211	goto err_free;
	212
	213	hw = at91_clk_register_master_div(regmap, "masterck_div",
171e502c	214	"masterck_pres", NULL,
7a110b91 CB	215	&at91sam9x5_master_layout,
7a110b91 CB	216	&mck_characteristics, &mck_lock,
7029db09	217	CLK_SET_RATE_GATE, 0);
1eabdc2f AB	218	if (IS_ERR(hw))
	219	goto err_free;
	220
	221	at91sam9x5_pmc->chws[PMC_MCK] = hw;
	222
	223	parent_names[0] = "plladivck";
	224	parent_names[1] = "utmick";
	225	hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
	226	if (IS_ERR(hw))
	227	goto err_free;
	228
	229	hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
	230	if (IS_ERR(hw))
	231	goto err_free;
	232
	233	parent_names[0] = slck_name;
	234	parent_names[1] = "mainck";
	235	parent_names[2] = "plladivck";
	236	parent_names[3] = "utmick";
7a110b91	237	parent_names[4] = "masterck_div";
1eabdc2f AB	238	for (i = 0; i < 2; i++) {
	239	char name[6];
	240
	241	snprintf(name, sizeof(name), "prog%d", i);
	242
	243	hw = at91_clk_register_programmable(regmap, name,
1a2669df	244	parent_names, NULL, 5, i,
c57aaaa2 CB	245	&at91sam9x5_programmable_layout,
c57aaaa2 CB	246	NULL);
1eabdc2f AB	247	if (IS_ERR(hw))
1eabdc2f AB	248	goto err_free;
99767cd4 MM	249
99767cd4 MM	250	at91sam9x5_pmc->pchws[i] = hw;
1eabdc2f AB	251	}
	252
	253	for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
	254	hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
1a537f62	255	at91sam9x5_systemck[i].p, NULL,
68b3b6f1 CB	256	at91sam9x5_systemck[i].id,
68b3b6f1 CB	257	at91sam9x5_systemck[i].flags);
1eabdc2f AB	258	if (IS_ERR(hw))
	259	goto err_free;
	260
	261	at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
	262	}
	263
	264	if (has_lcdck) {
68b3b6f1	265	hw = at91_clk_register_system(regmap, "lcdck", "masterck_div",
1a537f62	266	NULL, 3, 0);
1eabdc2f AB	267	if (IS_ERR(hw))
	268	goto err_free;
	269
	270	at91sam9x5_pmc->shws[3] = hw;
	271	}
	272
	273	for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
	274	hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
cb4f4949	275	&at91sam9x5_pcr_layout,
1eabdc2f	276	at91sam9x5_periphck[i].n,
c2f2ca0b	277	"masterck_div", NULL,
1eabdc2f	278	at91sam9x5_periphck[i].id,
68b3b6f1	279	&range, INT_MIN, 0);
1eabdc2f AB	280	if (IS_ERR(hw))
	281	goto err_free;
	282
	283	at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
	284	}
	285
	286	for (i = 0; extra_pcks[i].id; i++) {
	287	hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
cb4f4949	288	&at91sam9x5_pcr_layout,
1eabdc2f	289	extra_pcks[i].n,
c2f2ca0b	290	"masterck_div", NULL,
1eabdc2f	291	extra_pcks[i].id,
68b3b6f1	292	&range, INT_MIN, 0);
1eabdc2f AB	293	if (IS_ERR(hw))
	294	goto err_free;
	295
	296	at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
	297	}
	298
	299	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
	300
	301	return;
	302
	303	err_free:
7425f246	304	kfree(at91sam9x5_pmc);
1eabdc2f AB	305	}
	306
	307	static void __init at91sam9g15_pmc_setup(struct device_node *np)
	308	{
	309	at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
	310	}
428d97e1 TA	311
428d97e1 TA	312	CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup);
1eabdc2f AB	313
	314	static void __init at91sam9g25_pmc_setup(struct device_node *np)
	315	{
	316	at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
	317	}
428d97e1 TA	318
428d97e1 TA	319	CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup);
1eabdc2f AB	320
	321	static void __init at91sam9g35_pmc_setup(struct device_node *np)
	322	{
	323	at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
	324	}
428d97e1 TA	325
428d97e1 TA	326	CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup);
1eabdc2f AB	327
	328	static void __init at91sam9x25_pmc_setup(struct device_node *np)
	329	{
	330	at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
	331	}
428d97e1 TA	332
428d97e1 TA	333	CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup);
1eabdc2f AB	334
	335	static void __init at91sam9x35_pmc_setup(struct device_node *np)
	336	{
	337	at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
	338	}
428d97e1 TA	339
428d97e1 TA	340	CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup);