[linux-block.git] / drivers / clk / at91 / at91sam9n12.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/slab.h>

#include <dt-bindings/clock/at91.h>

#include "pmc.h"

static DEFINE_SPINLOCK(at91sam9n12_mck_lock);

static const struct clk_master_characteristics mck_characteristics = {
	.output = { .min = 0, .max = 133333333 },
	.divisors = { 1, 2, 4, 3 },
	.have_div3_pres = 1,
};

static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };

static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };

static const struct clk_range plla_outputs[] = {
	{ .min = 745000000, .max = 800000000 },
	{ .min = 695000000, .max = 750000000 },
	{ .min = 645000000, .max = 700000000 },
	{ .min = 595000000, .max = 650000000 },
	{ .min = 545000000, .max = 600000000 },
	{ .min = 495000000, .max = 555000000 },
	{ .min = 445000000, .max = 500000000 },
	{ .min = 400000000, .max = 450000000 },
};

static const struct clk_pll_characteristics plla_characteristics = {
	.input = { .min = 2000000, .max = 32000000 },
	.num_output = ARRAY_SIZE(plla_outputs),
	.output = plla_outputs,
	.icpll = plla_icpll,
	.out = plla_out,
};

static u8 pllb_out[] = { 0 };

static const struct clk_range pllb_outputs[] = {
	{ .min = 30000000, .max = 100000000 },
};

static const struct clk_pll_characteristics pllb_characteristics = {
	.input = { .min = 2000000, .max = 32000000 },
	.num_output = ARRAY_SIZE(pllb_outputs),
	.output = pllb_outputs,
	.out = pllb_out,
};

static const struct {
	char *n;
	char *p;
	unsigned long flags;
	u8 id;
} at91sam9n12_systemck[] = {
	/*
	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
	 * to keep it enabled in case there is no Linux consumer for it.
	 */
	{ .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
	{ .n = "lcdck", .p = "masterck_div", .id = 3 },
	{ .n = "uhpck", .p = "usbck",        .id = 6 },
	{ .n = "udpck", .p = "usbck",        .id = 7 },
	{ .n = "pck0",  .p = "prog0",        .id = 8 },
	{ .n = "pck1",  .p = "prog1",        .id = 9 },
};

static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
	.offset = 0x10c,
	.cmd = BIT(12),
	.pid_mask = GENMASK(5, 0),
	.div_mask = GENMASK(17, 16),
};

struct pck {
	char *n;
	u8 id;
};

static const struct pck at91sam9n12_periphck[] = {
	{ .n = "pioAB_clk",  .id = 2, },
	{ .n = "pioCD_clk",  .id = 3, },
	{ .n = "fuse_clk",   .id = 4, },
	{ .n = "usart0_clk", .id = 5, },
	{ .n = "usart1_clk", .id = 6, },
	{ .n = "usart2_clk", .id = 7, },
	{ .n = "usart3_clk", .id = 8, },
	{ .n = "twi0_clk",   .id = 9, },
	{ .n = "twi1_clk",   .id = 10, },
	{ .n = "mci0_clk",   .id = 12, },
	{ .n = "spi0_clk",   .id = 13, },
	{ .n = "spi1_clk",   .id = 14, },
	{ .n = "uart0_clk",  .id = 15, },
	{ .n = "uart1_clk",  .id = 16, },
	{ .n = "tcb_clk",    .id = 17, },
	{ .n = "pwm_clk",    .id = 18, },
	{ .n = "adc_clk",    .id = 19, },
	{ .n = "dma0_clk",   .id = 20, },
	{ .n = "uhphs_clk",  .id = 22, },
	{ .n = "udphs_clk",  .id = 23, },
	{ .n = "lcdc_clk",   .id = 25, },
	{ .n = "sha_clk",    .id = 27, },
	{ .n = "ssc0_clk",   .id = 28, },
	{ .n = "aes_clk",    .id = 29, },
	{ .n = "trng_clk",   .id = 30, },
};

static void __init at91sam9n12_pmc_setup(struct device_node *np)
{
	struct clk_range range = CLK_RANGE(0, 0);
	const char *slck_name, *mainxtal_name;
	struct pmc_data *at91sam9n12_pmc;
	const char *parent_names[6];
	struct regmap *regmap;
	struct clk_hw *hw;
	int i;
	bool bypass;

	i = of_property_match_string(np, "clock-names", "slow_clk");
	if (i < 0)
		return;

	slck_name = of_clk_get_parent_name(np, i);

	i = of_property_match_string(np, "clock-names", "main_xtal");
	if (i < 0)
		return;
	mainxtal_name = of_clk_get_parent_name(np, i);

	regmap = device_node_to_regmap(np);
	if (IS_ERR(regmap))
		return;

	at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
					   nck(at91sam9n12_systemck), 31, 0, 2);
	if (!at91sam9n12_pmc)
		return;

	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
					   50000000);
	if (IS_ERR(hw))
		goto err_free;

	bypass = of_property_read_bool(np, "atmel,osc-bypass");

	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
					bypass);
	if (IS_ERR(hw))
		goto err_free;

	parent_names[0] = "main_rc_osc";
	parent_names[1] = "main_osc";
	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
	if (IS_ERR(hw))
		goto err_free;

	at91sam9n12_pmc->chws[PMC_MAIN] = hw;

	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
				   &at91rm9200_pll_layout, &plla_characteristics);
	if (IS_ERR(hw))
		goto err_free;

	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
	if (IS_ERR(hw))
		goto err_free;

	at91sam9n12_pmc->chws[PMC_PLLACK] = hw;

	hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
				   &at91rm9200_pll_layout, &pllb_characteristics);
	if (IS_ERR(hw))
		goto err_free;

	at91sam9n12_pmc->chws[PMC_PLLBCK] = hw;

	parent_names[0] = slck_name;
	parent_names[1] = "mainck";
	parent_names[2] = "plladivck";
	parent_names[3] = "pllbck";
	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
					   parent_names,
					   &at91sam9x5_master_layout,
					   &mck_characteristics,
					   &at91sam9n12_mck_lock);
	if (IS_ERR(hw))
		goto err_free;

	hw = at91_clk_register_master_div(regmap, "masterck_div",
					  "masterck_pres",
					  &at91sam9x5_master_layout,
					  &mck_characteristics,
					  &at91sam9n12_mck_lock,
					  CLK_SET_RATE_GATE, 0);
	if (IS_ERR(hw))
		goto err_free;

	at91sam9n12_pmc->chws[PMC_MCK] = hw;

	hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck");
	if (IS_ERR(hw))
		goto err_free;

	parent_names[0] = slck_name;
	parent_names[1] = "mainck";
	parent_names[2] = "plladivck";
	parent_names[3] = "pllbck";
	parent_names[4] = "masterck_div";
	for (i = 0; i < 2; i++) {
		char name[6];

		snprintf(name, sizeof(name), "prog%d", i);

		hw = at91_clk_register_programmable(regmap, name,
						    parent_names, 5, i,
						    &at91sam9x5_programmable_layout,
						    NULL);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9n12_pmc->pchws[i] = hw;
	}

	for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
		hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
					      at91sam9n12_systemck[i].p,
					      at91sam9n12_systemck[i].id,
					      at91sam9n12_systemck[i].flags);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw;
	}

	for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) {
		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
							 &at91sam9n12_pcr_layout,
							 at91sam9n12_periphck[i].n,
							 "masterck_div",
							 at91sam9n12_periphck[i].id,
							 &range, INT_MIN, 0);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw;
	}

	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc);

	return;

err_free:
	kfree(at91sam9n12_pmc);
}
/*
 * The TCB is used as the clocksource so its clock is needed early. This means
 * this can't be a platform driver.
 */
CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);
Commit	Line	Data
143e04da AB	1	// SPDX-License-Identifier: GPL-2.0
	2	#include <linux/clk-provider.h>
	3	#include <linux/mfd/syscon.h>
	4	#include <linux/slab.h>
	5
	6	#include <dt-bindings/clock/at91.h>
	7
	8	#include "pmc.h"
	9
7a110b91 CB	10	static DEFINE_SPINLOCK(at91sam9n12_mck_lock);
7a110b91 CB	11
143e04da AB	12	static const struct clk_master_characteristics mck_characteristics = {
	13	.output = { .min = 0, .max = 133333333 },
	14	.divisors = { 1, 2, 4, 3 },
	15	.have_div3_pres = 1,
	16	};
	17
	18	static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
	19
	20	static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
	21
	22	static const struct clk_range plla_outputs[] = {
	23	{ .min = 745000000, .max = 800000000 },
	24	{ .min = 695000000, .max = 750000000 },
	25	{ .min = 645000000, .max = 700000000 },
	26	{ .min = 595000000, .max = 650000000 },
	27	{ .min = 545000000, .max = 600000000 },
	28	{ .min = 495000000, .max = 555000000 },
	29	{ .min = 445000000, .max = 500000000 },
	30	{ .min = 400000000, .max = 450000000 },
	31	};
	32
	33	static const struct clk_pll_characteristics plla_characteristics = {
	34	.input = { .min = 2000000, .max = 32000000 },
	35	.num_output = ARRAY_SIZE(plla_outputs),
	36	.output = plla_outputs,
	37	.icpll = plla_icpll,
	38	.out = plla_out,
	39	};
	40
	41	static u8 pllb_out[] = { 0 };
	42
	43	static const struct clk_range pllb_outputs[] = {
	44	{ .min = 30000000, .max = 100000000 },
	45	};
	46
	47	static const struct clk_pll_characteristics pllb_characteristics = {
	48	.input = { .min = 2000000, .max = 32000000 },
	49	.num_output = ARRAY_SIZE(pllb_outputs),
	50	.output = pllb_outputs,
	51	.out = pllb_out,
	52	};
	53
	54	static const struct {
	55	char *n;
	56	char *p;
68b3b6f1	57	unsigned long flags;
143e04da AB	58	u8 id;
143e04da AB	59	} at91sam9n12_systemck[] = {
68b3b6f1 CB	60	/*
	61	* ddrck feeds DDR controller and is enabled by bootloader thus we need
	62	* to keep it enabled in case there is no Linux consumer for it.
	63	*/
	64	{ .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
7a110b91 CB	65	{ .n = "lcdck", .p = "masterck_div", .id = 3 },
	66	{ .n = "uhpck", .p = "usbck", .id = 6 },
	67	{ .n = "udpck", .p = "usbck", .id = 7 },
	68	{ .n = "pck0", .p = "prog0", .id = 8 },
	69	{ .n = "pck1", .p = "prog1", .id = 9 },
143e04da AB	70	};
	71
	72	static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
	73	.offset = 0x10c,
	74	.cmd = BIT(12),
	75	.pid_mask = GENMASK(5, 0),
	76	.div_mask = GENMASK(17, 16),
	77	};
	78
	79	struct pck {
	80	char *n;
	81	u8 id;
	82	};
	83
	84	static const struct pck at91sam9n12_periphck[] = {
	85	{ .n = "pioAB_clk", .id = 2, },
	86	{ .n = "pioCD_clk", .id = 3, },
	87	{ .n = "fuse_clk", .id = 4, },
	88	{ .n = "usart0_clk", .id = 5, },
	89	{ .n = "usart1_clk", .id = 6, },
	90	{ .n = "usart2_clk", .id = 7, },
	91	{ .n = "usart3_clk", .id = 8, },
	92	{ .n = "twi0_clk", .id = 9, },
	93	{ .n = "twi1_clk", .id = 10, },
	94	{ .n = "mci0_clk", .id = 12, },
	95	{ .n = "spi0_clk", .id = 13, },
	96	{ .n = "spi1_clk", .id = 14, },
	97	{ .n = "uart0_clk", .id = 15, },
	98	{ .n = "uart1_clk", .id = 16, },
	99	{ .n = "tcb_clk", .id = 17, },
	100	{ .n = "pwm_clk", .id = 18, },
	101	{ .n = "adc_clk", .id = 19, },
	102	{ .n = "dma0_clk", .id = 20, },
	103	{ .n = "uhphs_clk", .id = 22, },
	104	{ .n = "udphs_clk", .id = 23, },
	105	{ .n = "lcdc_clk", .id = 25, },
	106	{ .n = "sha_clk", .id = 27, },
	107	{ .n = "ssc0_clk", .id = 28, },
	108	{ .n = "aes_clk", .id = 29, },
	109	{ .n = "trng_clk", .id = 30, },
	110	};
	111
	112	static void __init at91sam9n12_pmc_setup(struct device_node *np)
	113	{
	114	struct clk_range range = CLK_RANGE(0, 0);
	115	const char slck_name, mainxtal_name;
	116	struct pmc_data *at91sam9n12_pmc;
	117	const char *parent_names[6];
	118	struct regmap *regmap;
	119	struct clk_hw *hw;
	120	int i;
	121	bool bypass;
	122
	123	i = of_property_match_string(np, "clock-names", "slow_clk");
	124	if (i < 0)
	125	return;
	126
	127	slck_name = of_clk_get_parent_name(np, i);
	128
	129	i = of_property_match_string(np, "clock-names", "main_xtal");
	130	if (i < 0)
	131	return;
	132	mainxtal_name = of_clk_get_parent_name(np, i);
	133
153bc1c6	134	regmap = device_node_to_regmap(np);
143e04da AB	135	if (IS_ERR(regmap))
	136	return;
	137
03a1ee1d	138	at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
99767cd4	139	nck(at91sam9n12_systemck), 31, 0, 2);
143e04da AB	140	if (!at91sam9n12_pmc)
	141	return;
	142
	143	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
	144	50000000);
	145	if (IS_ERR(hw))
	146	goto err_free;
	147
	148	bypass = of_property_read_bool(np, "atmel,osc-bypass");
	149
b5105e37	150	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
143e04da AB	151	bypass);
	152	if (IS_ERR(hw))
	153	goto err_free;
	154
	155	parent_names[0] = "main_rc_osc";
	156	parent_names[1] = "main_osc";
b5105e37	157	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
143e04da AB	158	if (IS_ERR(hw))
	159	goto err_free;
	160
	161	at91sam9n12_pmc->chws[PMC_MAIN] = hw;
	162
	163	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
	164	&at91rm9200_pll_layout, &plla_characteristics);
	165	if (IS_ERR(hw))
	166	goto err_free;
	167
	168	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
	169	if (IS_ERR(hw))
	170	goto err_free;
	171
03a1ee1d MM	172	at91sam9n12_pmc->chws[PMC_PLLACK] = hw;
03a1ee1d MM	173
143e04da AB	174	hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
	175	&at91rm9200_pll_layout, &pllb_characteristics);
	176	if (IS_ERR(hw))
	177	goto err_free;
	178
03a1ee1d MM	179	at91sam9n12_pmc->chws[PMC_PLLBCK] = hw;
03a1ee1d MM	180
143e04da AB	181	parent_names[0] = slck_name;
	182	parent_names[1] = "mainck";
	183	parent_names[2] = "plladivck";
	184	parent_names[3] = "pllbck";
7a110b91 CB	185	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
	186	parent_names,
	187	&at91sam9x5_master_layout,
	188	&mck_characteristics,
8e842f02	189	&at91sam9n12_mck_lock);
7a110b91 CB	190	if (IS_ERR(hw))
	191	goto err_free;
	192
	193	hw = at91_clk_register_master_div(regmap, "masterck_div",
	194	"masterck_pres",
	195	&at91sam9x5_master_layout,
	196	&mck_characteristics,
	197	&at91sam9n12_mck_lock,
7029db09	198	CLK_SET_RATE_GATE, 0);
143e04da AB	199	if (IS_ERR(hw))
	200	goto err_free;
	201
	202	at91sam9n12_pmc->chws[PMC_MCK] = hw;
	203
	204	hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck");
	205	if (IS_ERR(hw))
	206	goto err_free;
	207
	208	parent_names[0] = slck_name;
	209	parent_names[1] = "mainck";
	210	parent_names[2] = "plladivck";
	211	parent_names[3] = "pllbck";
7a110b91	212	parent_names[4] = "masterck_div";
143e04da AB	213	for (i = 0; i < 2; i++) {
	214	char name[6];
	215
	216	snprintf(name, sizeof(name), "prog%d", i);
	217
	218	hw = at91_clk_register_programmable(regmap, name,
	219	parent_names, 5, i,
c57aaaa2 CB	220	&at91sam9x5_programmable_layout,
c57aaaa2 CB	221	NULL);
143e04da AB	222	if (IS_ERR(hw))
143e04da AB	223	goto err_free;
99767cd4 MM	224
99767cd4 MM	225	at91sam9n12_pmc->pchws[i] = hw;
143e04da AB	226	}
	227
	228	for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
	229	hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
	230	at91sam9n12_systemck[i].p,
68b3b6f1 CB	231	at91sam9n12_systemck[i].id,
68b3b6f1 CB	232	at91sam9n12_systemck[i].flags);
143e04da AB	233	if (IS_ERR(hw))
	234	goto err_free;
	235
	236	at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw;
	237	}
	238
	239	for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) {
	240	hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
	241	&at91sam9n12_pcr_layout,
	242	at91sam9n12_periphck[i].n,
7a110b91	243	"masterck_div",
143e04da	244	at91sam9n12_periphck[i].id,
68b3b6f1	245	&range, INT_MIN, 0);
143e04da AB	246	if (IS_ERR(hw))
	247	goto err_free;
	248
	249	at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw;
	250	}
	251
	252	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc);
	253
	254	return;
	255
	256	err_free:
7425f246	257	kfree(at91sam9n12_pmc);
143e04da AB	258	}
	259	/*
	260	* The TCB is used as the clocksource so its clock is needed early. This means
	261	* this can't be a platform driver.
	262	*/
428d97e1	263	CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);