Commit | Line | Data |
---|---|---|
7b9487a9 | 1 | # SPDX-License-Identifier: GPL-2.0 |
6d803ba7 | 2 | |
bc8c945e SB |
3 | config HAVE_CLK |
4 | bool | |
5 | help | |
6 | The <linux/clk.h> calls support software clock gating and | |
7 | thus are a key power management tool on many systems. | |
8 | ||
5c77f560 SG |
9 | config HAVE_CLK_PREPARE |
10 | bool | |
11 | ||
bbd7ffdb | 12 | config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated |
8fb61e33 | 13 | bool |
bbd7ffdb SB |
14 | select HAVE_CLK |
15 | help | |
16 | Select this option when the clock API in <linux/clk.h> is implemented | |
17 | by platform/architecture code. This method is deprecated. Modern | |
18 | code should select COMMON_CLK instead and not define a custom | |
19 | 'struct clk'. | |
20 | ||
21 | menuconfig COMMON_CLK | |
22 | bool "Common Clock Framework" | |
23 | depends on !HAVE_LEGACY_CLK | |
b2476490 | 24 | select HAVE_CLK_PREPARE |
2f4574dd | 25 | select HAVE_CLK |
83fe27ea | 26 | select SRCU |
0777591e | 27 | select RATIONAL |
a7f7f624 | 28 | help |
b2476490 MT |
29 | The common clock framework is a single definition of struct |
30 | clk, useful across many platforms, as well as an | |
31 | implementation of the clock API in include/linux/clk.h. | |
32 | Architectures utilizing the common struct clk should select | |
8fb61e33 | 33 | this option. |
b2476490 | 34 | |
bbd7ffdb | 35 | if COMMON_CLK |
b2476490 | 36 | |
f05259a6 MB |
37 | config COMMON_CLK_WM831X |
38 | tristate "Clock driver for WM831x/2x PMICs" | |
39 | depends on MFD_WM831X | |
a7f7f624 | 40 | help |
333d2d19 | 41 | Supports the clocking subsystem of the WM831x/2x series of |
fe4e4372 | 42 | PMICs from Wolfson Microelectronics. |
f05259a6 | 43 | |
5ee2b877 | 44 | source "drivers/clk/versatile/Kconfig" |
f9a6aa43 | 45 | |
daeeb438 EP |
46 | config CLK_HSDK |
47 | bool "PLL Driver for HSDK platform" | |
f6bade68 | 48 | depends on ARC_SOC_HSDK || COMPILE_TEST |
bd8548d0 | 49 | depends on HAS_IOMEM |
a7f7f624 | 50 | help |
daeeb438 EP |
51 | This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs |
52 | control. | |
53 | ||
3bc61cfd LB |
54 | config LMK04832 |
55 | tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner" | |
97a1c5cb | 56 | depends on SPI |
3bc61cfd LB |
57 | select REGMAP_SPI |
58 | help | |
59 | Say yes here to build support for Texas Instruments' LMK04832 Ultra | |
60 | Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs | |
61 | ||
73118e61 | 62 | config COMMON_CLK_MAX77686 |
5a227cd1 | 63 | tristate "Clock driver for Maxim 77620/77686/77802 MFD" |
9c1b305c | 64 | depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST |
a7f7f624 | 65 | help |
5a227cd1 LD |
66 | This driver supports Maxim 77620/77686/77802 crystal oscillator |
67 | clock. | |
83ccf16c | 68 | |
33f51046 DM |
69 | config COMMON_CLK_MAX9485 |
70 | tristate "Maxim 9485 Programmable Clock Generator" | |
71 | depends on I2C | |
72 | help | |
73 | This driver supports Maxim 9485 Programmable Audio Clock Generator | |
74 | ||
038b892a | 75 | config COMMON_CLK_RK808 |
8ed14401 | 76 | tristate "Clock driver for RK805/RK808/RK809/RK817/RK818" |
038b892a | 77 | depends on MFD_RK808 |
a7f7f624 | 78 | help |
8ed14401 TX |
79 | This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock. |
80 | These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. | |
81 | Clkout1 is always on, Clkout2 can off by control register. | |
038b892a | 82 | |
b68adc23 | 83 | config COMMON_CLK_HI655X |
3a49afb8 RV |
84 | tristate "Clock driver for Hi655x" if EXPERT |
85 | depends on (MFD_HI655X_PMIC || COMPILE_TEST) | |
86 | depends on REGMAP | |
87 | default MFD_HI655X_PMIC | |
a7f7f624 | 88 | help |
b68adc23 DL |
89 | This driver supports the hi655x PMIC clock. This |
90 | multi-function device has one fixed-rate oscillator, clocked | |
91 | at 32KHz. | |
92 | ||
6d6a1d82 SH |
93 | config COMMON_CLK_SCMI |
94 | tristate "Clock driver controlled via SCMI interface" | |
95 | depends on ARM_SCMI_PROTOCOL || COMPILE_TEST | |
a7f7f624 | 96 | help |
6d6a1d82 SH |
97 | This driver provides support for clocks that are controlled |
98 | by firmware that implements the SCMI interface. | |
99 | ||
100 | This driver uses SCMI Message Protocol to interact with the | |
101 | firmware providing all the clock controls. | |
102 | ||
cd52c2a4 SH |
103 | config COMMON_CLK_SCPI |
104 | tristate "Clock driver controlled via SCPI interface" | |
105 | depends on ARM_SCPI_PROTOCOL || COMPILE_TEST | |
a7f7f624 | 106 | help |
cd52c2a4 SH |
107 | This driver provides support for clocks that are controlled |
108 | by firmware that implements the SCPI interface. | |
109 | ||
110 | This driver uses SCPI Message Protocol to interact with the | |
111 | firmware providing all the clock controls. | |
112 | ||
3044a860 ML |
113 | config COMMON_CLK_SI5341 |
114 | tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices" | |
115 | depends on I2C | |
116 | select REGMAP_I2C | |
117 | help | |
118 | This driver supports Silicon Labs Si5341 and Si5340 programmable clock | |
119 | generators. Not all features of these chips are currently supported | |
120 | by the driver, in particular it only supports XTAL input. The chip can | |
121 | be pre-programmed to support other configurations and features not yet | |
122 | implemented in the driver. | |
123 | ||
9abd5f05 SH |
124 | config COMMON_CLK_SI5351 |
125 | tristate "Clock driver for SiLabs 5351A/B/C" | |
126 | depends on I2C | |
127 | select REGMAP_I2C | |
a7f7f624 | 128 | help |
9abd5f05 SH |
129 | This driver supports Silicon Labs 5351A/B/C programmable clock |
130 | generators. | |
131 | ||
8ce20e66 ML |
132 | config COMMON_CLK_SI514 |
133 | tristate "Clock driver for SiLabs 514 devices" | |
134 | depends on I2C | |
135 | depends on OF | |
136 | select REGMAP_I2C | |
137 | help | |
8ce20e66 ML |
138 | This driver supports the Silicon Labs 514 programmable clock |
139 | generator. | |
140 | ||
953cc3e8 ML |
141 | config COMMON_CLK_SI544 |
142 | tristate "Clock driver for SiLabs 544 devices" | |
143 | depends on I2C | |
144 | select REGMAP_I2C | |
145 | help | |
953cc3e8 ML |
146 | This driver supports the Silicon Labs 544 programmable clock |
147 | generator. | |
8ce20e66 | 148 | |
1459c837 SB |
149 | config COMMON_CLK_SI570 |
150 | tristate "Clock driver for SiLabs 570 and compatible devices" | |
151 | depends on I2C | |
152 | depends on OF | |
153 | select REGMAP_I2C | |
154 | help | |
1459c837 SB |
155 | This driver supports Silicon Labs 570/571/598/599 programmable |
156 | clock generators. | |
157 | ||
1ab4601d MS |
158 | config COMMON_CLK_BM1880 |
159 | bool "Clock driver for Bitmain BM1880 SoC" | |
160 | depends on ARCH_BITMAIN || COMPILE_TEST | |
161 | default ARCH_BITMAIN | |
162 | help | |
163 | This driver supports the clocks on Bitmain BM1880 SoC. | |
164 | ||
c7d5a46b ML |
165 | config COMMON_CLK_CDCE706 |
166 | tristate "Clock driver for TI CDCE706 clock synthesizer" | |
167 | depends on I2C | |
168 | select REGMAP_I2C | |
a7f7f624 | 169 | help |
c7d5a46b ML |
170 | This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. |
171 | ||
19fbbbbc | 172 | config COMMON_CLK_CDCE925 |
5508124c | 173 | tristate "Clock driver for TI CDCE913/925/937/949 devices" |
19fbbbbc ML |
174 | depends on I2C |
175 | depends on OF | |
176 | select REGMAP_I2C | |
177 | help | |
5508124c AM |
178 | This driver supports the TI CDCE913/925/937/949 programmable clock |
179 | synthesizer. Each chip has different number of PLLs and outputs. | |
180 | For example, the CDCE925 contains two PLLs with spread-spectrum | |
181 | clocking support and five output dividers. The driver only supports | |
182 | the following setup, and uses a fixed setting for the output muxes. | |
19fbbbbc ML |
183 | Y1 is derived from the input clock |
184 | Y2 and Y3 derive from PLL1 | |
185 | Y4 and Y5 derive from PLL2 | |
186 | Given a target output frequency, the driver will set the PLL and | |
187 | divider to best approximate the desired output. | |
188 | ||
64dfbe24 KM |
189 | config COMMON_CLK_CS2000_CP |
190 | tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier" | |
191 | depends on I2C | |
192 | help | |
193 | If you say yes here you get support for the CS2000 clock multiplier. | |
194 | ||
fcf77be8 MW |
195 | config COMMON_CLK_FSL_FLEXSPI |
196 | tristate "Clock driver for FlexSPI on Layerscape SoCs" | |
197 | depends on ARCH_LAYERSCAPE || COMPILE_TEST | |
198 | default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI | |
199 | help | |
200 | On Layerscape SoCs there is a special clock for the FlexSPI | |
201 | interface. | |
202 | ||
9cd10205 MW |
203 | config COMMON_CLK_FSL_SAI |
204 | bool "Clock driver for BCLK of Freescale SAI cores" | |
205 | depends on ARCH_LAYERSCAPE || COMPILE_TEST | |
206 | help | |
207 | This driver supports the Freescale SAI (Synchronous Audio Interface) | |
208 | to be used as a generic clock output. Some SoCs have restrictions | |
209 | regarding the possible pin multiplexer settings. Eg. on some SoCs | |
210 | two SAI interfaces can only be enabled together. If just one is | |
211 | needed, the BCLK pin of the second one can be used as general | |
212 | purpose clock output. Ideally, it can be used to drive an audio | |
213 | codec (sometimes known as MCLK). | |
214 | ||
846423f9 LW |
215 | config COMMON_CLK_GEMINI |
216 | bool "Clock driver for Cortina Systems Gemini SoC" | |
217 | depends on ARCH_GEMINI || COMPILE_TEST | |
218 | select MFD_SYSCON | |
219 | select RESET_CONTROLLER | |
a7f7f624 | 220 | help |
846423f9 LW |
221 | This driver supports the SoC clocks on the Cortina Systems Gemini |
222 | platform, also known as SL3516 or CS3516. | |
223 | ||
5eda5d79 JS |
224 | config COMMON_CLK_ASPEED |
225 | bool "Clock driver for Aspeed BMC SoCs" | |
226 | depends on ARCH_ASPEED || COMPILE_TEST | |
227 | default ARCH_ASPEED | |
228 | select MFD_SYSCON | |
229 | select RESET_CONTROLLER | |
a7f7f624 | 230 | help |
5eda5d79 JS |
231 | This driver supports the SoC clocks on the Aspeed BMC platforms. |
232 | ||
233 | The G4 and G5 series, including the ast2400 and ast2500, are supported | |
234 | by this driver. | |
235 | ||
7cc560de | 236 | config COMMON_CLK_S2MPS11 |
e8b60a45 | 237 | tristate "Clock driver for S2MPS1X/S5M8767 MFD" |
9c1b305c | 238 | depends on MFD_SEC_CORE || COMPILE_TEST |
a7f7f624 | 239 | help |
e8b60a45 KK |
240 | This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator |
241 | clock. These multi-function devices have two (S2MPS14) or three | |
242 | (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. | |
7cc560de | 243 | |
f9f8c043 PU |
244 | config CLK_TWL6040 |
245 | tristate "External McPDM functional clock from twl6040" | |
246 | depends on TWL6040_CORE | |
a7f7f624 | 247 | help |
f9f8c043 PU |
248 | Enable the external functional clock support on OMAP4+ platforms for |
249 | McPDM. McPDM module is using the external bit clock on the McPDM bus | |
250 | as functional clock. | |
251 | ||
0e646c52 LPC |
252 | config COMMON_CLK_AXI_CLKGEN |
253 | tristate "AXI clkgen driver" | |
324a8105 AA |
254 | depends on HAS_IOMEM || COMPILE_TEST |
255 | depends on OF | |
0e646c52 | 256 | help |
0e646c52 LPC |
257 | Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx |
258 | FPGAs. It is commonly used in Analog Devices' reference designs. | |
259 | ||
93a17c05 TY |
260 | config CLK_QORIQ |
261 | bool "Clock driver for Freescale QorIQ platforms" | |
b8bcece8 GU |
262 | depends on OF |
263 | depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST | |
a7f7f624 | 264 | help |
93a17c05 TY |
265 | This adds the clock driver support for Freescale QorIQ platforms |
266 | using common clock framework. | |
555eae97 | 267 | |
d37010a3 WH |
268 | config CLK_LS1028A_PLLDIG |
269 | tristate "Clock driver for LS1028A Display output" | |
270 | depends on ARCH_LAYERSCAPE || COMPILE_TEST | |
271 | default ARCH_LAYERSCAPE | |
272 | help | |
273 | This driver support the Display output interfaces(LCD, DPHY) pixel clocks | |
274 | of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all | |
275 | features of the PLL are currently supported by the driver. By default, | |
276 | configured bypass mode with this PLL. | |
277 | ||
308964ca LH |
278 | config COMMON_CLK_XGENE |
279 | bool "Clock driver for APM XGene SoC" | |
ce9a1046 | 280 | default ARCH_XGENE |
4a7748c3 | 281 | depends on ARM64 || COMPILE_TEST |
a7f7f624 | 282 | help |
4fe02fef | 283 | Support for the APM X-Gene SoC reference, PLL, and device clocks. |
308964ca | 284 | |
76c54783 CK |
285 | config COMMON_CLK_LOCHNAGAR |
286 | tristate "Cirrus Logic Lochnagar clock driver" | |
287 | depends on MFD_LOCHNAGAR | |
288 | help | |
289 | This driver supports the clocking features of the Cirrus Logic | |
290 | Lochnagar audio development board. | |
291 | ||
f7c82a60 VZ |
292 | config COMMON_CLK_NXP |
293 | def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX) | |
294 | select REGMAP_MMIO if ARCH_LPC32XX | |
72ad679a | 295 | select MFD_SYSCON if ARCH_LPC18XX |
a7f7f624 | 296 | help |
f7c82a60 VZ |
297 | Support for clock providers on NXP platforms. |
298 | ||
942d1d67 PU |
299 | config COMMON_CLK_PALMAS |
300 | tristate "Clock driver for TI Palmas devices" | |
301 | depends on MFD_PALMAS | |
a7f7f624 | 302 | help |
942d1d67 PU |
303 | This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO |
304 | using common clock framework. | |
305 | ||
9a74ccdb PZ |
306 | config COMMON_CLK_PWM |
307 | tristate "Clock driver for PWMs used as clock outputs" | |
308 | depends on PWM | |
a7f7f624 | 309 | help |
9a74ccdb PZ |
310 | Adapter driver so that any PWM output can be (mis)used as clock signal |
311 | at 50% duty cycle. | |
312 | ||
98d147f5 RJ |
313 | config COMMON_CLK_PXA |
314 | def_bool COMMON_CLK && ARCH_PXA | |
a7f7f624 | 315 | help |
048c58b4 | 316 | Support for the Marvell PXA SoC. |
98d147f5 | 317 | |
ce6e1188 PCM |
318 | config COMMON_CLK_PIC32 |
319 | def_bool COMMON_CLK && MACH_PIC32 | |
320 | ||
0bbd72b4 NA |
321 | config COMMON_CLK_OXNAS |
322 | bool "Clock driver for the OXNAS SoC Family" | |
821f9946 | 323 | depends on ARCH_OXNAS || COMPILE_TEST |
0bbd72b4 | 324 | select MFD_SYSCON |
a7f7f624 | 325 | help |
0bbd72b4 NA |
326 | Support for the OXNAS SoC Family clocks. |
327 | ||
3e1aec4e | 328 | config COMMON_CLK_VC5 |
dbf6b16f | 329 | tristate "Clock driver for IDT VersaClock 5,6 devices" |
3e1aec4e MV |
330 | depends on I2C |
331 | depends on OF | |
332 | select REGMAP_I2C | |
333 | help | |
dbf6b16f MV |
334 | This driver supports the IDT VersaClock 5 and VersaClock 6 |
335 | programmable clock generators. | |
3e1aec4e | 336 | |
9bee94e7 GF |
337 | config COMMON_CLK_STM32MP157 |
338 | def_bool COMMON_CLK && MACH_STM32MP157 | |
339 | help | |
9bee94e7 GF |
340 | Support for stm32mp157 SoC family clocks |
341 | ||
21e74330 GF |
342 | config COMMON_CLK_STM32MP157_SCMI |
343 | bool "stm32mp157 Clock driver with Trusted Firmware" | |
344 | depends on COMMON_CLK_STM32MP157 | |
345 | select COMMON_CLK_SCMI | |
346 | select ARM_SCMI_PROTOCOL | |
347 | default y | |
348 | help | |
349 | Support for stm32mp157 SoC family clocks with Trusted Firmware using | |
350 | SCMI protocol. | |
351 | ||
da32d353 | 352 | config COMMON_CLK_STM32F |
9a160601 | 353 | def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) |
da32d353 | 354 | help |
da32d353 BG |
355 | Support for stm32f4 and stm32f7 SoC families clocks |
356 | ||
357 | config COMMON_CLK_STM32H7 | |
9a160601 | 358 | def_bool COMMON_CLK && MACH_STM32H743 |
da32d353 | 359 | help |
da32d353 BG |
360 | Support for stm32h7 SoC family clocks |
361 | ||
a9372a5f LR |
362 | config COMMON_CLK_MMP2 |
363 | def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT) | |
364 | help | |
365 | Support for Marvell MMP2 and MMP3 SoC clocks | |
366 | ||
725262d2 LR |
367 | config COMMON_CLK_MMP2_AUDIO |
368 | tristate "Clock driver for MMP2 Audio subsystem" | |
369 | depends on COMMON_CLK_MMP2 || COMPILE_TEST | |
370 | help | |
371 | This driver supports clocks for Audio subsystem on MMP2 SoC. | |
372 | ||
2e62246b | 373 | config COMMON_CLK_BD718XX |
ae866dec | 374 | tristate "Clock driver for 32K clk gates on ROHM PMICs" |
fa5b6541 | 375 | depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828 |
2e62246b | 376 | help |
fa5b6541 MV |
377 | This driver supports ROHM BD71837, BD71847, BD71850, BD71815 |
378 | and BD71828 PMICs clock gates. | |
2e62246b | 379 | |
50cc4caf JK |
380 | config COMMON_CLK_FIXED_MMIO |
381 | bool "Clock driver for Memory Mapped Fixed values" | |
382 | depends on COMMON_CLK && OF | |
383 | help | |
384 | Support for Memory Mapped IO Fixed clocks | |
385 | ||
c6ca7616 DLM |
386 | config COMMON_CLK_K210 |
387 | bool "Clock driver for the Canaan Kendryte K210 SoC" | |
388 | depends on OF && RISCV && SOC_CANAAN | |
389 | default SOC_CANAAN | |
390 | help | |
391 | Support for the Canaan Kendryte K210 RISC-V SoC clocks. | |
392 | ||
3495e295 | 393 | source "drivers/clk/actions/Kconfig" |
7b9487a9 | 394 | source "drivers/clk/analogbits/Kconfig" |
b7d950b9 | 395 | source "drivers/clk/baikal-t1/Kconfig" |
64a12c56 | 396 | source "drivers/clk/bcm/Kconfig" |
72ea4861 | 397 | source "drivers/clk/hisilicon/Kconfig" |
6b0fd6c1 | 398 | source "drivers/clk/imgtec/Kconfig" |
3a48d918 | 399 | source "drivers/clk/imx/Kconfig" |
0880fb86 | 400 | source "drivers/clk/ingenic/Kconfig" |
b745c079 | 401 | source "drivers/clk/keystone/Kconfig" |
2886c846 | 402 | source "drivers/clk/mediatek/Kconfig" |
cb7c47d7 | 403 | source "drivers/clk/meson/Kconfig" |
bef7a78d | 404 | source "drivers/clk/mstar/Kconfig" |
97fa4cf4 | 405 | source "drivers/clk/mvebu/Kconfig" |
b9e65ebc | 406 | source "drivers/clk/qcom/Kconfig" |
48df7a26 | 407 | source "drivers/clk/ralink/Kconfig" |
a5bd7f7a | 408 | source "drivers/clk/renesas/Kconfig" |
4d98ed1e | 409 | source "drivers/clk/rockchip/Kconfig" |
4ce9b85e | 410 | source "drivers/clk/samsung/Kconfig" |
30b8e27e | 411 | source "drivers/clk/sifive/Kconfig" |
3b218baa | 412 | source "drivers/clk/socfpga/Kconfig" |
d41f59fd | 413 | source "drivers/clk/sprd/Kconfig" |
49c726d5 | 414 | source "drivers/clk/sunxi/Kconfig" |
1d80c142 | 415 | source "drivers/clk/sunxi-ng/Kconfig" |
31b52ba4 | 416 | source "drivers/clk/tegra/Kconfig" |
21330497 | 417 | source "drivers/clk/ti/Kconfig" |
734d82f4 | 418 | source "drivers/clk/uniphier/Kconfig" |
d058fd9e | 419 | source "drivers/clk/x86/Kconfig" |
a2fe7baa | 420 | source "drivers/clk/xilinx/Kconfig" |
3fde0e16 | 421 | source "drivers/clk/zynqmp/Kconfig" |
b9e65ebc | 422 | |
bbd7ffdb | 423 | endif |