Commit | Line | Data |
---|---|---|
7b9487a9 | 1 | # SPDX-License-Identifier: GPL-2.0 |
6d803ba7 | 2 | |
bc8c945e SB |
3 | config HAVE_CLK |
4 | bool | |
5 | help | |
6 | The <linux/clk.h> calls support software clock gating and | |
7 | thus are a key power management tool on many systems. | |
8 | ||
5c77f560 SG |
9 | config HAVE_CLK_PREPARE |
10 | bool | |
11 | ||
bbd7ffdb | 12 | config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated |
8fb61e33 | 13 | bool |
bbd7ffdb SB |
14 | select HAVE_CLK |
15 | help | |
16 | Select this option when the clock API in <linux/clk.h> is implemented | |
17 | by platform/architecture code. This method is deprecated. Modern | |
18 | code should select COMMON_CLK instead and not define a custom | |
19 | 'struct clk'. | |
20 | ||
21 | menuconfig COMMON_CLK | |
22 | bool "Common Clock Framework" | |
23 | depends on !HAVE_LEGACY_CLK | |
b2476490 | 24 | select HAVE_CLK_PREPARE |
2f4574dd | 25 | select HAVE_CLK |
0777591e | 26 | select RATIONAL |
a7f7f624 | 27 | help |
b2476490 MT |
28 | The common clock framework is a single definition of struct |
29 | clk, useful across many platforms, as well as an | |
30 | implementation of the clock API in include/linux/clk.h. | |
31 | Architectures utilizing the common struct clk should select | |
8fb61e33 | 32 | this option. |
b2476490 | 33 | |
bbd7ffdb | 34 | if COMMON_CLK |
b2476490 | 35 | |
f05259a6 MB |
36 | config COMMON_CLK_WM831X |
37 | tristate "Clock driver for WM831x/2x PMICs" | |
38 | depends on MFD_WM831X | |
a7f7f624 | 39 | help |
333d2d19 | 40 | Supports the clocking subsystem of the WM831x/2x series of |
fe4e4372 | 41 | PMICs from Wolfson Microelectronics. |
f05259a6 | 42 | |
5ee2b877 | 43 | source "drivers/clk/versatile/Kconfig" |
f9a6aa43 | 44 | |
daeeb438 EP |
45 | config CLK_HSDK |
46 | bool "PLL Driver for HSDK platform" | |
f6bade68 | 47 | depends on ARC_SOC_HSDK || COMPILE_TEST |
bd8548d0 | 48 | depends on HAS_IOMEM |
a7f7f624 | 49 | help |
daeeb438 EP |
50 | This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs |
51 | control. | |
52 | ||
3bc61cfd LB |
53 | config LMK04832 |
54 | tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner" | |
97a1c5cb | 55 | depends on SPI |
3bc61cfd LB |
56 | select REGMAP_SPI |
57 | help | |
58 | Say yes here to build support for Texas Instruments' LMK04832 Ultra | |
59 | Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs | |
60 | ||
6641057d | 61 | config COMMON_CLK_APPLE_NCO |
236541ac | 62 | tristate "Clock driver for Apple SoC NCOs" |
6641057d MP |
63 | depends on ARCH_APPLE || COMPILE_TEST |
64 | default ARCH_APPLE | |
65 | help | |
66 | This driver supports NCO (Numerically Controlled Oscillator) blocks | |
67 | found on Apple SoCs such as t8103 (M1). The blocks are typically | |
68 | generators of audio clocks. | |
69 | ||
73118e61 | 70 | config COMMON_CLK_MAX77686 |
5a227cd1 | 71 | tristate "Clock driver for Maxim 77620/77686/77802 MFD" |
9c1b305c | 72 | depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST |
a7f7f624 | 73 | help |
5a227cd1 LD |
74 | This driver supports Maxim 77620/77686/77802 crystal oscillator |
75 | clock. | |
83ccf16c | 76 | |
33f51046 DM |
77 | config COMMON_CLK_MAX9485 |
78 | tristate "Maxim 9485 Programmable Clock Generator" | |
79 | depends on I2C | |
80 | help | |
81 | This driver supports Maxim 9485 Programmable Audio Clock Generator | |
82 | ||
038b892a | 83 | config COMMON_CLK_RK808 |
8ed14401 | 84 | tristate "Clock driver for RK805/RK808/RK809/RK817/RK818" |
c20e8c5b | 85 | depends on MFD_RK8XX |
a7f7f624 | 86 | help |
8ed14401 TX |
87 | This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock. |
88 | These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. | |
89 | Clkout1 is always on, Clkout2 can off by control register. | |
038b892a | 90 | |
b68adc23 | 91 | config COMMON_CLK_HI655X |
3a49afb8 RV |
92 | tristate "Clock driver for Hi655x" if EXPERT |
93 | depends on (MFD_HI655X_PMIC || COMPILE_TEST) | |
0ffad677 | 94 | select REGMAP |
3a49afb8 | 95 | default MFD_HI655X_PMIC |
a7f7f624 | 96 | help |
b68adc23 DL |
97 | This driver supports the hi655x PMIC clock. This |
98 | multi-function device has one fixed-rate oscillator, clocked | |
99 | at 32KHz. | |
100 | ||
6d6a1d82 SH |
101 | config COMMON_CLK_SCMI |
102 | tristate "Clock driver controlled via SCMI interface" | |
103 | depends on ARM_SCMI_PROTOCOL || COMPILE_TEST | |
a7f7f624 | 104 | help |
6d6a1d82 SH |
105 | This driver provides support for clocks that are controlled |
106 | by firmware that implements the SCMI interface. | |
107 | ||
108 | This driver uses SCMI Message Protocol to interact with the | |
109 | firmware providing all the clock controls. | |
110 | ||
cd52c2a4 SH |
111 | config COMMON_CLK_SCPI |
112 | tristate "Clock driver controlled via SCPI interface" | |
113 | depends on ARM_SCPI_PROTOCOL || COMPILE_TEST | |
a7f7f624 | 114 | help |
cd52c2a4 SH |
115 | This driver provides support for clocks that are controlled |
116 | by firmware that implements the SCPI interface. | |
117 | ||
118 | This driver uses SCPI Message Protocol to interact with the | |
119 | firmware providing all the clock controls. | |
120 | ||
3044a860 ML |
121 | config COMMON_CLK_SI5341 |
122 | tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices" | |
123 | depends on I2C | |
124 | select REGMAP_I2C | |
125 | help | |
126 | This driver supports Silicon Labs Si5341 and Si5340 programmable clock | |
127 | generators. Not all features of these chips are currently supported | |
128 | by the driver, in particular it only supports XTAL input. The chip can | |
129 | be pre-programmed to support other configurations and features not yet | |
130 | implemented in the driver. | |
131 | ||
9abd5f05 SH |
132 | config COMMON_CLK_SI5351 |
133 | tristate "Clock driver for SiLabs 5351A/B/C" | |
134 | depends on I2C | |
135 | select REGMAP_I2C | |
a7f7f624 | 136 | help |
9abd5f05 SH |
137 | This driver supports Silicon Labs 5351A/B/C programmable clock |
138 | generators. | |
139 | ||
8ce20e66 ML |
140 | config COMMON_CLK_SI514 |
141 | tristate "Clock driver for SiLabs 514 devices" | |
142 | depends on I2C | |
143 | depends on OF | |
144 | select REGMAP_I2C | |
145 | help | |
8ce20e66 ML |
146 | This driver supports the Silicon Labs 514 programmable clock |
147 | generator. | |
148 | ||
953cc3e8 ML |
149 | config COMMON_CLK_SI544 |
150 | tristate "Clock driver for SiLabs 544 devices" | |
151 | depends on I2C | |
152 | select REGMAP_I2C | |
153 | help | |
953cc3e8 ML |
154 | This driver supports the Silicon Labs 544 programmable clock |
155 | generator. | |
8ce20e66 | 156 | |
1459c837 SB |
157 | config COMMON_CLK_SI570 |
158 | tristate "Clock driver for SiLabs 570 and compatible devices" | |
159 | depends on I2C | |
160 | depends on OF | |
161 | select REGMAP_I2C | |
162 | help | |
1459c837 SB |
163 | This driver supports Silicon Labs 570/571/598/599 programmable |
164 | clock generators. | |
165 | ||
1ab4601d MS |
166 | config COMMON_CLK_BM1880 |
167 | bool "Clock driver for Bitmain BM1880 SoC" | |
168 | depends on ARCH_BITMAIN || COMPILE_TEST | |
169 | default ARCH_BITMAIN | |
170 | help | |
171 | This driver supports the clocks on Bitmain BM1880 SoC. | |
172 | ||
c7d5a46b ML |
173 | config COMMON_CLK_CDCE706 |
174 | tristate "Clock driver for TI CDCE706 clock synthesizer" | |
175 | depends on I2C | |
176 | select REGMAP_I2C | |
a7f7f624 | 177 | help |
c7d5a46b ML |
178 | This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. |
179 | ||
ff5f87cb HG |
180 | config COMMON_CLK_TPS68470 |
181 | tristate "Clock Driver for TI TPS68470 PMIC" | |
182 | depends on I2C | |
183 | depends on INTEL_SKL_INT3472 || COMPILE_TEST | |
184 | select REGMAP_I2C | |
185 | help | |
186 | This driver supports the clocks provided by the TPS68470 PMIC. | |
187 | ||
19fbbbbc | 188 | config COMMON_CLK_CDCE925 |
5508124c | 189 | tristate "Clock driver for TI CDCE913/925/937/949 devices" |
19fbbbbc ML |
190 | depends on I2C |
191 | depends on OF | |
192 | select REGMAP_I2C | |
193 | help | |
5508124c AM |
194 | This driver supports the TI CDCE913/925/937/949 programmable clock |
195 | synthesizer. Each chip has different number of PLLs and outputs. | |
196 | For example, the CDCE925 contains two PLLs with spread-spectrum | |
197 | clocking support and five output dividers. The driver only supports | |
198 | the following setup, and uses a fixed setting for the output muxes. | |
19fbbbbc ML |
199 | Y1 is derived from the input clock |
200 | Y2 and Y3 derive from PLL1 | |
201 | Y4 and Y5 derive from PLL2 | |
202 | Given a target output frequency, the driver will set the PLL and | |
203 | divider to best approximate the desired output. | |
204 | ||
64dfbe24 KM |
205 | config COMMON_CLK_CS2000_CP |
206 | tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier" | |
207 | depends on I2C | |
5edffb98 | 208 | select REGMAP_I2C |
64dfbe24 KM |
209 | help |
210 | If you say yes here you get support for the CS2000 clock multiplier. | |
211 | ||
1e627317 FF |
212 | config COMMON_CLK_EN7523 |
213 | bool "Clock driver for Airoha EN7523 SoC system clocks" | |
214 | depends on OF | |
215 | depends on ARCH_AIROHA || COMPILE_TEST | |
216 | default ARCH_AIROHA | |
217 | help | |
218 | This driver provides the fixed clocks and gates present on Airoha | |
219 | ARM silicon. | |
220 | ||
fcf77be8 MW |
221 | config COMMON_CLK_FSL_FLEXSPI |
222 | tristate "Clock driver for FlexSPI on Layerscape SoCs" | |
223 | depends on ARCH_LAYERSCAPE || COMPILE_TEST | |
224 | default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI | |
225 | help | |
226 | On Layerscape SoCs there is a special clock for the FlexSPI | |
227 | interface. | |
228 | ||
9cd10205 MW |
229 | config COMMON_CLK_FSL_SAI |
230 | bool "Clock driver for BCLK of Freescale SAI cores" | |
231 | depends on ARCH_LAYERSCAPE || COMPILE_TEST | |
232 | help | |
233 | This driver supports the Freescale SAI (Synchronous Audio Interface) | |
234 | to be used as a generic clock output. Some SoCs have restrictions | |
235 | regarding the possible pin multiplexer settings. Eg. on some SoCs | |
236 | two SAI interfaces can only be enabled together. If just one is | |
237 | needed, the BCLK pin of the second one can be used as general | |
238 | purpose clock output. Ideally, it can be used to drive an audio | |
239 | codec (sometimes known as MCLK). | |
240 | ||
846423f9 LW |
241 | config COMMON_CLK_GEMINI |
242 | bool "Clock driver for Cortina Systems Gemini SoC" | |
243 | depends on ARCH_GEMINI || COMPILE_TEST | |
244 | select MFD_SYSCON | |
245 | select RESET_CONTROLLER | |
a7f7f624 | 246 | help |
846423f9 LW |
247 | This driver supports the SoC clocks on the Cortina Systems Gemini |
248 | platform, also known as SL3516 or CS3516. | |
249 | ||
54104ee0 | 250 | config COMMON_CLK_LAN966X |
8a977bbb | 251 | tristate "Generic Clock Controller driver for LAN966X SoC" |
aa091a6a HV |
252 | depends on HAS_IOMEM |
253 | depends on OF | |
7cd5c560 | 254 | depends on SOC_LAN966 || COMPILE_TEST |
54104ee0 KK |
255 | help |
256 | This driver provides support for Generic Clock Controller(GCK) on | |
257 | LAN966X SoC. GCK generates and supplies clock to various peripherals | |
258 | within the SoC. | |
259 | ||
5eda5d79 JS |
260 | config COMMON_CLK_ASPEED |
261 | bool "Clock driver for Aspeed BMC SoCs" | |
262 | depends on ARCH_ASPEED || COMPILE_TEST | |
263 | default ARCH_ASPEED | |
264 | select MFD_SYSCON | |
265 | select RESET_CONTROLLER | |
a7f7f624 | 266 | help |
5eda5d79 JS |
267 | This driver supports the SoC clocks on the Aspeed BMC platforms. |
268 | ||
269 | The G4 and G5 series, including the ast2400 and ast2500, are supported | |
270 | by this driver. | |
271 | ||
7cc560de | 272 | config COMMON_CLK_S2MPS11 |
e8b60a45 | 273 | tristate "Clock driver for S2MPS1X/S5M8767 MFD" |
9c1b305c | 274 | depends on MFD_SEC_CORE || COMPILE_TEST |
a7f7f624 | 275 | help |
e8b60a45 KK |
276 | This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator |
277 | clock. These multi-function devices have two (S2MPS14) or three | |
278 | (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. | |
7cc560de | 279 | |
4eb15b03 AK |
280 | config CLK_TWL |
281 | tristate "Clock driver for the TWL PMIC family" | |
282 | depends on TWL4030_CORE | |
283 | help | |
284 | Enable support for controlling the clock resources on TWL family | |
285 | PMICs. These devices have some 32K clock outputs which can be | |
286 | controlled by software. For now, only the TWL6032 clocks are | |
287 | supported. | |
288 | ||
f9f8c043 PU |
289 | config CLK_TWL6040 |
290 | tristate "External McPDM functional clock from twl6040" | |
291 | depends on TWL6040_CORE | |
a7f7f624 | 292 | help |
f9f8c043 PU |
293 | Enable the external functional clock support on OMAP4+ platforms for |
294 | McPDM. McPDM module is using the external bit clock on the McPDM bus | |
295 | as functional clock. | |
296 | ||
0e646c52 LPC |
297 | config COMMON_CLK_AXI_CLKGEN |
298 | tristate "AXI clkgen driver" | |
324a8105 AA |
299 | depends on HAS_IOMEM || COMPILE_TEST |
300 | depends on OF | |
0e646c52 | 301 | help |
0e646c52 LPC |
302 | Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx |
303 | FPGAs. It is commonly used in Analog Devices' reference designs. | |
304 | ||
93a17c05 TY |
305 | config CLK_QORIQ |
306 | bool "Clock driver for Freescale QorIQ platforms" | |
b8bcece8 GU |
307 | depends on OF |
308 | depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST | |
a7f7f624 | 309 | help |
93a17c05 TY |
310 | This adds the clock driver support for Freescale QorIQ platforms |
311 | using common clock framework. | |
555eae97 | 312 | |
d37010a3 WH |
313 | config CLK_LS1028A_PLLDIG |
314 | tristate "Clock driver for LS1028A Display output" | |
315 | depends on ARCH_LAYERSCAPE || COMPILE_TEST | |
316 | default ARCH_LAYERSCAPE | |
317 | help | |
318 | This driver support the Display output interfaces(LCD, DPHY) pixel clocks | |
319 | of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all | |
320 | features of the PLL are currently supported by the driver. By default, | |
321 | configured bypass mode with this PLL. | |
322 | ||
308964ca LH |
323 | config COMMON_CLK_XGENE |
324 | bool "Clock driver for APM XGene SoC" | |
ce9a1046 | 325 | default ARCH_XGENE |
4a7748c3 | 326 | depends on ARM64 || COMPILE_TEST |
a7f7f624 | 327 | help |
4fe02fef | 328 | Support for the APM X-Gene SoC reference, PLL, and device clocks. |
308964ca | 329 | |
76c54783 CK |
330 | config COMMON_CLK_LOCHNAGAR |
331 | tristate "Cirrus Logic Lochnagar clock driver" | |
332 | depends on MFD_LOCHNAGAR | |
333 | help | |
334 | This driver supports the clocking features of the Cirrus Logic | |
335 | Lochnagar audio development board. | |
336 | ||
acc0ccff YZ |
337 | config COMMON_CLK_LOONGSON2 |
338 | bool "Clock driver for Loongson-2 SoC" | |
339 | depends on LOONGARCH || COMPILE_TEST | |
340 | help | |
341 | This driver provides support for clock controller on Loongson-2 SoC. | |
342 | The clock controller can generates and supplies clock to various | |
343 | peripherals within the SoC. | |
344 | Say Y here to support Loongson-2 SoC clock driver. | |
345 | ||
f7c82a60 VZ |
346 | config COMMON_CLK_NXP |
347 | def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX) | |
348 | select REGMAP_MMIO if ARCH_LPC32XX | |
72ad679a | 349 | select MFD_SYSCON if ARCH_LPC18XX |
a7f7f624 | 350 | help |
f7c82a60 VZ |
351 | Support for clock providers on NXP platforms. |
352 | ||
942d1d67 PU |
353 | config COMMON_CLK_PALMAS |
354 | tristate "Clock driver for TI Palmas devices" | |
355 | depends on MFD_PALMAS | |
a7f7f624 | 356 | help |
942d1d67 PU |
357 | This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO |
358 | using common clock framework. | |
359 | ||
9a74ccdb PZ |
360 | config COMMON_CLK_PWM |
361 | tristate "Clock driver for PWMs used as clock outputs" | |
362 | depends on PWM | |
a7f7f624 | 363 | help |
9a74ccdb PZ |
364 | Adapter driver so that any PWM output can be (mis)used as clock signal |
365 | at 50% duty cycle. | |
366 | ||
98d147f5 RJ |
367 | config COMMON_CLK_PXA |
368 | def_bool COMMON_CLK && ARCH_PXA | |
a7f7f624 | 369 | help |
048c58b4 | 370 | Support for the Marvell PXA SoC. |
98d147f5 | 371 | |
892e0dde MV |
372 | config COMMON_CLK_RS9_PCIE |
373 | tristate "Clock driver for Renesas 9-series PCIe clock generators" | |
374 | depends on I2C | |
375 | depends on OF | |
376 | select REGMAP_I2C | |
377 | help | |
378 | This driver supports the Renesas 9-series PCIe clock generator | |
379 | models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ. | |
380 | ||
edc12763 MV |
381 | config COMMON_CLK_SI521XX |
382 | tristate "Clock driver for SkyWorks Si521xx PCIe clock generators" | |
383 | depends on I2C | |
384 | depends on OF | |
385 | select REGMAP_I2C | |
386 | help | |
387 | This driver supports the SkyWorks Si521xx PCIe clock generator | |
388 | models Si52144/Si52146/Si52147. | |
389 | ||
6e9aff55 BD |
390 | config COMMON_CLK_VC3 |
391 | tristate "Clock driver for Renesas VersaClock 3 devices" | |
392 | depends on I2C | |
393 | depends on OF | |
394 | select REGMAP_I2C | |
395 | help | |
396 | This driver supports the Renesas VersaClock 3 programmable clock | |
397 | generators. | |
398 | ||
3e1aec4e | 399 | config COMMON_CLK_VC5 |
dbf6b16f | 400 | tristate "Clock driver for IDT VersaClock 5,6 devices" |
3e1aec4e MV |
401 | depends on I2C |
402 | depends on OF | |
403 | select REGMAP_I2C | |
404 | help | |
dbf6b16f MV |
405 | This driver supports the IDT VersaClock 5 and VersaClock 6 |
406 | programmable clock generators. | |
3e1aec4e | 407 | |
48c5e98f AH |
408 | config COMMON_CLK_VC7 |
409 | tristate "Clock driver for Renesas Versaclock 7 devices" | |
410 | depends on I2C | |
411 | depends on OF | |
412 | select REGMAP_I2C | |
413 | help | |
414 | Renesas Versaclock7 is a family of configurable clock generator | |
415 | and jitter attenuator ICs with fractional and integer dividers. | |
416 | ||
da32d353 | 417 | config COMMON_CLK_STM32F |
9a160601 | 418 | def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) |
da32d353 | 419 | help |
da32d353 BG |
420 | Support for stm32f4 and stm32f7 SoC families clocks |
421 | ||
422 | config COMMON_CLK_STM32H7 | |
9a160601 | 423 | def_bool COMMON_CLK && MACH_STM32H743 |
da32d353 | 424 | help |
da32d353 BG |
425 | Support for stm32h7 SoC family clocks |
426 | ||
a9372a5f LR |
427 | config COMMON_CLK_MMP2 |
428 | def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT) | |
429 | help | |
430 | Support for Marvell MMP2 and MMP3 SoC clocks | |
431 | ||
725262d2 LR |
432 | config COMMON_CLK_MMP2_AUDIO |
433 | tristate "Clock driver for MMP2 Audio subsystem" | |
434 | depends on COMMON_CLK_MMP2 || COMPILE_TEST | |
435 | help | |
436 | This driver supports clocks for Audio subsystem on MMP2 SoC. | |
437 | ||
2e62246b | 438 | config COMMON_CLK_BD718XX |
ae866dec | 439 | tristate "Clock driver for 32K clk gates on ROHM PMICs" |
fa5b6541 | 440 | depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828 |
2e62246b | 441 | help |
fa5b6541 MV |
442 | This driver supports ROHM BD71837, BD71847, BD71850, BD71815 |
443 | and BD71828 PMICs clock gates. | |
2e62246b | 444 | |
50cc4caf JK |
445 | config COMMON_CLK_FIXED_MMIO |
446 | bool "Clock driver for Memory Mapped Fixed values" | |
447 | depends on COMMON_CLK && OF | |
e7dd44f4 | 448 | depends on HAS_IOMEM |
50cc4caf JK |
449 | help |
450 | Support for Memory Mapped IO Fixed clocks | |
451 | ||
c6ca7616 DLM |
452 | config COMMON_CLK_K210 |
453 | bool "Clock driver for the Canaan Kendryte K210 SoC" | |
454 | depends on OF && RISCV && SOC_CANAAN | |
455 | default SOC_CANAAN | |
456 | help | |
457 | Support for the Canaan Kendryte K210 RISC-V SoC clocks. | |
458 | ||
d54c1fd4 QJ |
459 | config COMMON_CLK_SP7021 |
460 | tristate "Clock driver for Sunplus SP7021 SoC" | |
461 | depends on SOC_SP7021 || COMPILE_TEST | |
462 | default SOC_SP7021 | |
463 | help | |
464 | This driver supports the Sunplus SP7021 SoC clocks. | |
465 | It implements SP7021 PLLs/gate. | |
466 | Not all features of the PLL are currently supported | |
467 | by the driver. | |
468 | ||
3495e295 | 469 | source "drivers/clk/actions/Kconfig" |
7b9487a9 | 470 | source "drivers/clk/analogbits/Kconfig" |
b7d950b9 | 471 | source "drivers/clk/baikal-t1/Kconfig" |
64a12c56 | 472 | source "drivers/clk/bcm/Kconfig" |
72ea4861 | 473 | source "drivers/clk/hisilicon/Kconfig" |
6b0fd6c1 | 474 | source "drivers/clk/imgtec/Kconfig" |
3a48d918 | 475 | source "drivers/clk/imx/Kconfig" |
0880fb86 | 476 | source "drivers/clk/ingenic/Kconfig" |
b745c079 | 477 | source "drivers/clk/keystone/Kconfig" |
2886c846 | 478 | source "drivers/clk/mediatek/Kconfig" |
cb7c47d7 | 479 | source "drivers/clk/meson/Kconfig" |
bef7a78d | 480 | source "drivers/clk/mstar/Kconfig" |
635e5e73 | 481 | source "drivers/clk/microchip/Kconfig" |
97fa4cf4 | 482 | source "drivers/clk/mvebu/Kconfig" |
691521a3 | 483 | source "drivers/clk/nuvoton/Kconfig" |
90429205 | 484 | source "drivers/clk/pistachio/Kconfig" |
b9e65ebc | 485 | source "drivers/clk/qcom/Kconfig" |
48df7a26 | 486 | source "drivers/clk/ralink/Kconfig" |
a5bd7f7a | 487 | source "drivers/clk/renesas/Kconfig" |
4d98ed1e | 488 | source "drivers/clk/rockchip/Kconfig" |
4ce9b85e | 489 | source "drivers/clk/samsung/Kconfig" |
30b8e27e | 490 | source "drivers/clk/sifive/Kconfig" |
3b218baa | 491 | source "drivers/clk/socfpga/Kconfig" |
d41f59fd | 492 | source "drivers/clk/sprd/Kconfig" |
4210be66 | 493 | source "drivers/clk/starfive/Kconfig" |
49c726d5 | 494 | source "drivers/clk/sunxi/Kconfig" |
1d80c142 | 495 | source "drivers/clk/sunxi-ng/Kconfig" |
31b52ba4 | 496 | source "drivers/clk/tegra/Kconfig" |
3ac7ca59 | 497 | source "drivers/clk/stm32/Kconfig" |
21330497 | 498 | source "drivers/clk/ti/Kconfig" |
734d82f4 | 499 | source "drivers/clk/uniphier/Kconfig" |
b4cbe606 | 500 | source "drivers/clk/visconti/Kconfig" |
d058fd9e | 501 | source "drivers/clk/x86/Kconfig" |
a2fe7baa | 502 | source "drivers/clk/xilinx/Kconfig" |
3fde0e16 | 503 | source "drivers/clk/zynqmp/Kconfig" |
b9e65ebc | 504 | |
a992acbb | 505 | # Kunit test cases |
723d0530 MR |
506 | config CLK_KUNIT_TEST |
507 | tristate "Basic Clock Framework Kunit Tests" if !KUNIT_ALL_TESTS | |
508 | depends on KUNIT | |
509 | default KUNIT_ALL_TESTS | |
510 | help | |
511 | Kunit tests for the common clock framework. | |
512 | ||
a992acbb SB |
513 | config CLK_GATE_KUNIT_TEST |
514 | tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS | |
515 | depends on KUNIT | |
516 | default KUNIT_ALL_TESTS | |
517 | help | |
518 | Kunit test for the basic clk gate type. | |
519 | ||
2790e2a3 FO |
520 | config CLK_FD_KUNIT_TEST |
521 | tristate "Basic fractional divider type Kunit test" if !KUNIT_ALL_TESTS | |
522 | depends on KUNIT | |
523 | default KUNIT_ALL_TESTS | |
524 | help | |
525 | Kunit test for the clk-fractional-divider type. | |
526 | ||
bbd7ffdb | 527 | endif |