Merge branch 'for-next-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/nab...
[linux-2.6-block.git] / drivers / clk / Kconfig
CommitLineData
6d803ba7
JCPV
1
2config CLKDEV_LOOKUP
3 bool
4 select HAVE_CLK
aa3831cf 5
5c77f560
SG
6config HAVE_CLK_PREPARE
7 bool
8
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AB
9config COMMON_CLK
10 bool
b2476490 11 select HAVE_CLK_PREPARE
01033be1 12 select CLKDEV_LOOKUP
83fe27ea 13 select SRCU
0777591e 14 select RATIONAL
b2476490
MT
15 ---help---
16 The common clock framework is a single definition of struct
17 clk, useful across many platforms, as well as an
18 implementation of the clock API in include/linux/clk.h.
19 Architectures utilizing the common struct clk should select
8fb61e33 20 this option.
b2476490 21
8fb61e33
AB
22menu "Common Clock Framework"
23 depends on COMMON_CLK
b2476490 24
f05259a6
MB
25config COMMON_CLK_WM831X
26 tristate "Clock driver for WM831x/2x PMICs"
27 depends on MFD_WM831X
28 ---help---
29 Supports the clocking subsystem of the WM831x/2x series of
fe4e4372 30 PMICs from Wolfson Microelectronics.
f05259a6 31
5ee2b877 32source "drivers/clk/versatile/Kconfig"
f9a6aa43 33
5dbbb00f
JMC
34config COMMON_CLK_MAX_GEN
35 bool
36
73118e61
JL
37config COMMON_CLK_MAX77686
38 tristate "Clock driver for Maxim 77686 MFD"
39 depends on MFD_MAX77686
1887d693 40 select COMMON_CLK_MAX_GEN
73118e61
JL
41 ---help---
42 This driver supports Maxim 77686 crystal oscillator clock.
43
83ccf16c
JMC
44config COMMON_CLK_MAX77802
45 tristate "Clock driver for Maxim 77802 PMIC"
46 depends on MFD_MAX77686
47 select COMMON_CLK_MAX_GEN
48 ---help---
49 This driver supports Maxim 77802 crystal oscillator clock.
50
038b892a
CZ
51config COMMON_CLK_RK808
52 tristate "Clock driver for RK808"
53 depends on MFD_RK808
54 ---help---
55 This driver supports RK808 crystal oscillator clock. These
56 multi-function devices have two fixed-rate oscillators,
57 clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
58 by control register.
59
cd52c2a4
SH
60config COMMON_CLK_SCPI
61 tristate "Clock driver controlled via SCPI interface"
62 depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
63 ---help---
64 This driver provides support for clocks that are controlled
65 by firmware that implements the SCPI interface.
66
67 This driver uses SCPI Message Protocol to interact with the
68 firmware providing all the clock controls.
69
9abd5f05
SH
70config COMMON_CLK_SI5351
71 tristate "Clock driver for SiLabs 5351A/B/C"
72 depends on I2C
73 select REGMAP_I2C
74 select RATIONAL
75 ---help---
76 This driver supports Silicon Labs 5351A/B/C programmable clock
77 generators.
78
8ce20e66
ML
79config COMMON_CLK_SI514
80 tristate "Clock driver for SiLabs 514 devices"
81 depends on I2C
82 depends on OF
83 select REGMAP_I2C
84 help
85 ---help---
86 This driver supports the Silicon Labs 514 programmable clock
87 generator.
88
1459c837
SB
89config COMMON_CLK_SI570
90 tristate "Clock driver for SiLabs 570 and compatible devices"
91 depends on I2C
92 depends on OF
93 select REGMAP_I2C
94 help
95 ---help---
96 This driver supports Silicon Labs 570/571/598/599 programmable
97 clock generators.
98
c7d5a46b
ML
99config COMMON_CLK_CDCE706
100 tristate "Clock driver for TI CDCE706 clock synthesizer"
101 depends on I2C
102 select REGMAP_I2C
103 select RATIONAL
104 ---help---
105 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
106
19fbbbbc
ML
107config COMMON_CLK_CDCE925
108 tristate "Clock driver for TI CDCE925 devices"
109 depends on I2C
110 depends on OF
111 select REGMAP_I2C
112 help
113 ---help---
114 This driver supports the TI CDCE925 programmable clock synthesizer.
115 The chip contains two PLLs with spread-spectrum clocking support and
116 five output dividers. The driver only supports the following setup,
117 and uses a fixed setting for the output muxes.
118 Y1 is derived from the input clock
119 Y2 and Y3 derive from PLL1
120 Y4 and Y5 derive from PLL2
121 Given a target output frequency, the driver will set the PLL and
122 divider to best approximate the desired output.
123
64dfbe24
KM
124config COMMON_CLK_CS2000_CP
125 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
126 depends on I2C
127 help
128 If you say yes here you get support for the CS2000 clock multiplier.
129
7cc560de 130config COMMON_CLK_S2MPS11
e8b60a45 131 tristate "Clock driver for S2MPS1X/S5M8767 MFD"
7cc560de
YSB
132 depends on MFD_SEC_CORE
133 ---help---
e8b60a45
KK
134 This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
135 clock. These multi-function devices have two (S2MPS14) or three
136 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
7cc560de 137
f9f8c043
PU
138config CLK_TWL6040
139 tristate "External McPDM functional clock from twl6040"
140 depends on TWL6040_CORE
141 ---help---
142 Enable the external functional clock support on OMAP4+ platforms for
143 McPDM. McPDM module is using the external bit clock on the McPDM bus
144 as functional clock.
145
0e646c52
LPC
146config COMMON_CLK_AXI_CLKGEN
147 tristate "AXI clkgen driver"
4a7748c3 148 depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
0e646c52
LPC
149 help
150 ---help---
151 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
152 FPGAs. It is commonly used in Analog Devices' reference designs.
153
93a17c05
TY
154config CLK_QORIQ
155 bool "Clock driver for Freescale QorIQ platforms"
2f4bf528 156 depends on (PPC_E500MC || ARM || ARM64 || COMPILE_TEST) && OF
555eae97 157 ---help---
93a17c05
TY
158 This adds the clock driver support for Freescale QorIQ platforms
159 using common clock framework.
555eae97 160
308964ca
LH
161config COMMON_CLK_XGENE
162 bool "Clock driver for APM XGene SoC"
163 default y
4a7748c3 164 depends on ARM64 || COMPILE_TEST
308964ca
LH
165 ---help---
166 Sypport for the APM X-Gene SoC reference, PLL, and device clocks.
167
6cfc229d
SS
168config COMMON_CLK_KEYSTONE
169 tristate "Clock drivers for Keystone based SOCs"
4a7748c3 170 depends on (ARCH_KEYSTONE || COMPILE_TEST) && OF
6cfc229d
SS
171 ---help---
172 Supports clock drivers for Keystone based SOCs. These SOCs have local
173 a power sleep control module that gate the clock to the IPs and PLLs.
174
f7c82a60
VZ
175config COMMON_CLK_NXP
176 def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
177 select REGMAP_MMIO if ARCH_LPC32XX
178 ---help---
179 Support for clock providers on NXP platforms.
180
942d1d67
PU
181config COMMON_CLK_PALMAS
182 tristate "Clock driver for TI Palmas devices"
183 depends on MFD_PALMAS
184 ---help---
185 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
186 using common clock framework.
187
9a74ccdb
PZ
188config COMMON_CLK_PWM
189 tristate "Clock driver for PWMs used as clock outputs"
190 depends on PWM
191 ---help---
192 Adapter driver so that any PWM output can be (mis)used as clock signal
193 at 50% duty cycle.
194
98d147f5
RJ
195config COMMON_CLK_PXA
196 def_bool COMMON_CLK && ARCH_PXA
197 ---help---
048c58b4 198 Support for the Marvell PXA SoC.
98d147f5 199
64a12c56 200source "drivers/clk/bcm/Kconfig"
72ea4861 201source "drivers/clk/hisilicon/Kconfig"
97fa4cf4 202source "drivers/clk/mvebu/Kconfig"
b9e65ebc 203source "drivers/clk/qcom/Kconfig"
4ce9b85e 204source "drivers/clk/samsung/Kconfig"
31b52ba4 205source "drivers/clk/tegra/Kconfig"
21330497 206source "drivers/clk/ti/Kconfig"
b9e65ebc
JL
207
208endmenu