fbdev: imsttfb: Fix use after free bug in imsttfb_probe
[linux-block.git] / drivers / clk / Kconfig
CommitLineData
7b9487a9 1# SPDX-License-Identifier: GPL-2.0
6d803ba7 2
bc8c945e
SB
3config HAVE_CLK
4 bool
5 help
6 The <linux/clk.h> calls support software clock gating and
7 thus are a key power management tool on many systems.
8
5c77f560
SG
9config HAVE_CLK_PREPARE
10 bool
11
bbd7ffdb 12config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated
8fb61e33 13 bool
bbd7ffdb
SB
14 select HAVE_CLK
15 help
16 Select this option when the clock API in <linux/clk.h> is implemented
17 by platform/architecture code. This method is deprecated. Modern
18 code should select COMMON_CLK instead and not define a custom
19 'struct clk'.
20
21menuconfig COMMON_CLK
22 bool "Common Clock Framework"
23 depends on !HAVE_LEGACY_CLK
b2476490 24 select HAVE_CLK_PREPARE
2f4574dd 25 select HAVE_CLK
0777591e 26 select RATIONAL
a7f7f624 27 help
b2476490
MT
28 The common clock framework is a single definition of struct
29 clk, useful across many platforms, as well as an
30 implementation of the clock API in include/linux/clk.h.
31 Architectures utilizing the common struct clk should select
8fb61e33 32 this option.
b2476490 33
bbd7ffdb 34if COMMON_CLK
b2476490 35
f05259a6
MB
36config COMMON_CLK_WM831X
37 tristate "Clock driver for WM831x/2x PMICs"
38 depends on MFD_WM831X
a7f7f624 39 help
333d2d19 40 Supports the clocking subsystem of the WM831x/2x series of
fe4e4372 41 PMICs from Wolfson Microelectronics.
f05259a6 42
5ee2b877 43source "drivers/clk/versatile/Kconfig"
f9a6aa43 44
daeeb438
EP
45config CLK_HSDK
46 bool "PLL Driver for HSDK platform"
f6bade68 47 depends on ARC_SOC_HSDK || COMPILE_TEST
bd8548d0 48 depends on HAS_IOMEM
a7f7f624 49 help
daeeb438
EP
50 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
51 control.
52
3bc61cfd
LB
53config LMK04832
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
97a1c5cb 55 depends on SPI
3bc61cfd
LB
56 select REGMAP_SPI
57 help
58 Say yes here to build support for Texas Instruments' LMK04832 Ultra
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
60
6641057d 61config COMMON_CLK_APPLE_NCO
236541ac 62 tristate "Clock driver for Apple SoC NCOs"
6641057d
MP
63 depends on ARCH_APPLE || COMPILE_TEST
64 default ARCH_APPLE
65 help
66 This driver supports NCO (Numerically Controlled Oscillator) blocks
67 found on Apple SoCs such as t8103 (M1). The blocks are typically
68 generators of audio clocks.
69
73118e61 70config COMMON_CLK_MAX77686
5a227cd1 71 tristate "Clock driver for Maxim 77620/77686/77802 MFD"
9c1b305c 72 depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
a7f7f624 73 help
5a227cd1
LD
74 This driver supports Maxim 77620/77686/77802 crystal oscillator
75 clock.
83ccf16c 76
33f51046
DM
77config COMMON_CLK_MAX9485
78 tristate "Maxim 9485 Programmable Clock Generator"
79 depends on I2C
80 help
81 This driver supports Maxim 9485 Programmable Audio Clock Generator
82
038b892a 83config COMMON_CLK_RK808
8ed14401 84 tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
038b892a 85 depends on MFD_RK808
a7f7f624 86 help
8ed14401
TX
87 This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
89 Clkout1 is always on, Clkout2 can off by control register.
038b892a 90
b68adc23 91config COMMON_CLK_HI655X
3a49afb8
RV
92 tristate "Clock driver for Hi655x" if EXPERT
93 depends on (MFD_HI655X_PMIC || COMPILE_TEST)
0ffad677 94 select REGMAP
3a49afb8 95 default MFD_HI655X_PMIC
a7f7f624 96 help
b68adc23
DL
97 This driver supports the hi655x PMIC clock. This
98 multi-function device has one fixed-rate oscillator, clocked
99 at 32KHz.
100
6d6a1d82
SH
101config COMMON_CLK_SCMI
102 tristate "Clock driver controlled via SCMI interface"
103 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
a7f7f624 104 help
6d6a1d82
SH
105 This driver provides support for clocks that are controlled
106 by firmware that implements the SCMI interface.
107
108 This driver uses SCMI Message Protocol to interact with the
109 firmware providing all the clock controls.
110
cd52c2a4
SH
111config COMMON_CLK_SCPI
112 tristate "Clock driver controlled via SCPI interface"
113 depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
a7f7f624 114 help
cd52c2a4
SH
115 This driver provides support for clocks that are controlled
116 by firmware that implements the SCPI interface.
117
118 This driver uses SCPI Message Protocol to interact with the
119 firmware providing all the clock controls.
120
3044a860
ML
121config COMMON_CLK_SI5341
122 tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
123 depends on I2C
124 select REGMAP_I2C
125 help
126 This driver supports Silicon Labs Si5341 and Si5340 programmable clock
127 generators. Not all features of these chips are currently supported
128 by the driver, in particular it only supports XTAL input. The chip can
129 be pre-programmed to support other configurations and features not yet
130 implemented in the driver.
131
9abd5f05
SH
132config COMMON_CLK_SI5351
133 tristate "Clock driver for SiLabs 5351A/B/C"
134 depends on I2C
135 select REGMAP_I2C
a7f7f624 136 help
9abd5f05
SH
137 This driver supports Silicon Labs 5351A/B/C programmable clock
138 generators.
139
8ce20e66
ML
140config COMMON_CLK_SI514
141 tristate "Clock driver for SiLabs 514 devices"
142 depends on I2C
143 depends on OF
144 select REGMAP_I2C
145 help
8ce20e66
ML
146 This driver supports the Silicon Labs 514 programmable clock
147 generator.
148
953cc3e8
ML
149config COMMON_CLK_SI544
150 tristate "Clock driver for SiLabs 544 devices"
151 depends on I2C
152 select REGMAP_I2C
153 help
953cc3e8
ML
154 This driver supports the Silicon Labs 544 programmable clock
155 generator.
8ce20e66 156
1459c837
SB
157config COMMON_CLK_SI570
158 tristate "Clock driver for SiLabs 570 and compatible devices"
159 depends on I2C
160 depends on OF
161 select REGMAP_I2C
162 help
1459c837
SB
163 This driver supports Silicon Labs 570/571/598/599 programmable
164 clock generators.
165
1ab4601d
MS
166config COMMON_CLK_BM1880
167 bool "Clock driver for Bitmain BM1880 SoC"
168 depends on ARCH_BITMAIN || COMPILE_TEST
169 default ARCH_BITMAIN
170 help
171 This driver supports the clocks on Bitmain BM1880 SoC.
172
c7d5a46b
ML
173config COMMON_CLK_CDCE706
174 tristate "Clock driver for TI CDCE706 clock synthesizer"
175 depends on I2C
176 select REGMAP_I2C
a7f7f624 177 help
c7d5a46b
ML
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
179
ff5f87cb
HG
180config COMMON_CLK_TPS68470
181 tristate "Clock Driver for TI TPS68470 PMIC"
182 depends on I2C
183 depends on INTEL_SKL_INT3472 || COMPILE_TEST
184 select REGMAP_I2C
185 help
186 This driver supports the clocks provided by the TPS68470 PMIC.
187
19fbbbbc 188config COMMON_CLK_CDCE925
5508124c 189 tristate "Clock driver for TI CDCE913/925/937/949 devices"
19fbbbbc
ML
190 depends on I2C
191 depends on OF
192 select REGMAP_I2C
193 help
5508124c
AM
194 This driver supports the TI CDCE913/925/937/949 programmable clock
195 synthesizer. Each chip has different number of PLLs and outputs.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
197 clocking support and five output dividers. The driver only supports
198 the following setup, and uses a fixed setting for the output muxes.
19fbbbbc
ML
199 Y1 is derived from the input clock
200 Y2 and Y3 derive from PLL1
201 Y4 and Y5 derive from PLL2
202 Given a target output frequency, the driver will set the PLL and
203 divider to best approximate the desired output.
204
64dfbe24
KM
205config COMMON_CLK_CS2000_CP
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
207 depends on I2C
5edffb98 208 select REGMAP_I2C
64dfbe24
KM
209 help
210 If you say yes here you get support for the CS2000 clock multiplier.
211
1e627317
FF
212config COMMON_CLK_EN7523
213 bool "Clock driver for Airoha EN7523 SoC system clocks"
214 depends on OF
215 depends on ARCH_AIROHA || COMPILE_TEST
216 default ARCH_AIROHA
217 help
218 This driver provides the fixed clocks and gates present on Airoha
219 ARM silicon.
220
fcf77be8
MW
221config COMMON_CLK_FSL_FLEXSPI
222 tristate "Clock driver for FlexSPI on Layerscape SoCs"
223 depends on ARCH_LAYERSCAPE || COMPILE_TEST
224 default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI
225 help
226 On Layerscape SoCs there is a special clock for the FlexSPI
227 interface.
228
9cd10205
MW
229config COMMON_CLK_FSL_SAI
230 bool "Clock driver for BCLK of Freescale SAI cores"
231 depends on ARCH_LAYERSCAPE || COMPILE_TEST
232 help
233 This driver supports the Freescale SAI (Synchronous Audio Interface)
234 to be used as a generic clock output. Some SoCs have restrictions
235 regarding the possible pin multiplexer settings. Eg. on some SoCs
236 two SAI interfaces can only be enabled together. If just one is
237 needed, the BCLK pin of the second one can be used as general
238 purpose clock output. Ideally, it can be used to drive an audio
239 codec (sometimes known as MCLK).
240
846423f9
LW
241config COMMON_CLK_GEMINI
242 bool "Clock driver for Cortina Systems Gemini SoC"
243 depends on ARCH_GEMINI || COMPILE_TEST
244 select MFD_SYSCON
245 select RESET_CONTROLLER
a7f7f624 246 help
846423f9
LW
247 This driver supports the SoC clocks on the Cortina Systems Gemini
248 platform, also known as SL3516 or CS3516.
249
54104ee0 250config COMMON_CLK_LAN966X
8a977bbb 251 tristate "Generic Clock Controller driver for LAN966X SoC"
aa091a6a
HV
252 depends on HAS_IOMEM
253 depends on OF
7cd5c560 254 depends on SOC_LAN966 || COMPILE_TEST
54104ee0
KK
255 help
256 This driver provides support for Generic Clock Controller(GCK) on
257 LAN966X SoC. GCK generates and supplies clock to various peripherals
258 within the SoC.
259
5eda5d79
JS
260config COMMON_CLK_ASPEED
261 bool "Clock driver for Aspeed BMC SoCs"
262 depends on ARCH_ASPEED || COMPILE_TEST
263 default ARCH_ASPEED
264 select MFD_SYSCON
265 select RESET_CONTROLLER
a7f7f624 266 help
5eda5d79
JS
267 This driver supports the SoC clocks on the Aspeed BMC platforms.
268
269 The G4 and G5 series, including the ast2400 and ast2500, are supported
270 by this driver.
271
7cc560de 272config COMMON_CLK_S2MPS11
e8b60a45 273 tristate "Clock driver for S2MPS1X/S5M8767 MFD"
9c1b305c 274 depends on MFD_SEC_CORE || COMPILE_TEST
a7f7f624 275 help
e8b60a45
KK
276 This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
277 clock. These multi-function devices have two (S2MPS14) or three
278 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
7cc560de 279
f9f8c043
PU
280config CLK_TWL6040
281 tristate "External McPDM functional clock from twl6040"
282 depends on TWL6040_CORE
a7f7f624 283 help
f9f8c043
PU
284 Enable the external functional clock support on OMAP4+ platforms for
285 McPDM. McPDM module is using the external bit clock on the McPDM bus
286 as functional clock.
287
0e646c52
LPC
288config COMMON_CLK_AXI_CLKGEN
289 tristate "AXI clkgen driver"
324a8105
AA
290 depends on HAS_IOMEM || COMPILE_TEST
291 depends on OF
0e646c52 292 help
0e646c52
LPC
293 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
294 FPGAs. It is commonly used in Analog Devices' reference designs.
295
93a17c05
TY
296config CLK_QORIQ
297 bool "Clock driver for Freescale QorIQ platforms"
b8bcece8
GU
298 depends on OF
299 depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
a7f7f624 300 help
93a17c05
TY
301 This adds the clock driver support for Freescale QorIQ platforms
302 using common clock framework.
555eae97 303
d37010a3
WH
304config CLK_LS1028A_PLLDIG
305 tristate "Clock driver for LS1028A Display output"
306 depends on ARCH_LAYERSCAPE || COMPILE_TEST
307 default ARCH_LAYERSCAPE
308 help
309 This driver support the Display output interfaces(LCD, DPHY) pixel clocks
310 of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
311 features of the PLL are currently supported by the driver. By default,
312 configured bypass mode with this PLL.
313
308964ca
LH
314config COMMON_CLK_XGENE
315 bool "Clock driver for APM XGene SoC"
ce9a1046 316 default ARCH_XGENE
4a7748c3 317 depends on ARM64 || COMPILE_TEST
a7f7f624 318 help
4fe02fef 319 Support for the APM X-Gene SoC reference, PLL, and device clocks.
308964ca 320
76c54783
CK
321config COMMON_CLK_LOCHNAGAR
322 tristate "Cirrus Logic Lochnagar clock driver"
323 depends on MFD_LOCHNAGAR
324 help
325 This driver supports the clocking features of the Cirrus Logic
326 Lochnagar audio development board.
327
acc0ccff
YZ
328config COMMON_CLK_LOONGSON2
329 bool "Clock driver for Loongson-2 SoC"
330 depends on LOONGARCH || COMPILE_TEST
331 help
332 This driver provides support for clock controller on Loongson-2 SoC.
333 The clock controller can generates and supplies clock to various
334 peripherals within the SoC.
335 Say Y here to support Loongson-2 SoC clock driver.
336
f7c82a60
VZ
337config COMMON_CLK_NXP
338 def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
339 select REGMAP_MMIO if ARCH_LPC32XX
72ad679a 340 select MFD_SYSCON if ARCH_LPC18XX
a7f7f624 341 help
f7c82a60
VZ
342 Support for clock providers on NXP platforms.
343
942d1d67
PU
344config COMMON_CLK_PALMAS
345 tristate "Clock driver for TI Palmas devices"
346 depends on MFD_PALMAS
a7f7f624 347 help
942d1d67
PU
348 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
349 using common clock framework.
350
9a74ccdb
PZ
351config COMMON_CLK_PWM
352 tristate "Clock driver for PWMs used as clock outputs"
353 depends on PWM
a7f7f624 354 help
9a74ccdb
PZ
355 Adapter driver so that any PWM output can be (mis)used as clock signal
356 at 50% duty cycle.
357
98d147f5
RJ
358config COMMON_CLK_PXA
359 def_bool COMMON_CLK && ARCH_PXA
a7f7f624 360 help
048c58b4 361 Support for the Marvell PXA SoC.
98d147f5 362
0bbd72b4
NA
363config COMMON_CLK_OXNAS
364 bool "Clock driver for the OXNAS SoC Family"
821f9946 365 depends on ARCH_OXNAS || COMPILE_TEST
0bbd72b4 366 select MFD_SYSCON
a7f7f624 367 help
0bbd72b4
NA
368 Support for the OXNAS SoC Family clocks.
369
892e0dde
MV
370config COMMON_CLK_RS9_PCIE
371 tristate "Clock driver for Renesas 9-series PCIe clock generators"
372 depends on I2C
373 depends on OF
374 select REGMAP_I2C
375 help
376 This driver supports the Renesas 9-series PCIe clock generator
377 models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.
378
edc12763
MV
379config COMMON_CLK_SI521XX
380 tristate "Clock driver for SkyWorks Si521xx PCIe clock generators"
381 depends on I2C
382 depends on OF
383 select REGMAP_I2C
384 help
385 This driver supports the SkyWorks Si521xx PCIe clock generator
386 models Si52144/Si52146/Si52147.
387
3e1aec4e 388config COMMON_CLK_VC5
dbf6b16f 389 tristate "Clock driver for IDT VersaClock 5,6 devices"
3e1aec4e
MV
390 depends on I2C
391 depends on OF
392 select REGMAP_I2C
393 help
dbf6b16f
MV
394 This driver supports the IDT VersaClock 5 and VersaClock 6
395 programmable clock generators.
3e1aec4e 396
48c5e98f
AH
397config COMMON_CLK_VC7
398 tristate "Clock driver for Renesas Versaclock 7 devices"
399 depends on I2C
400 depends on OF
401 select REGMAP_I2C
402 help
403 Renesas Versaclock7 is a family of configurable clock generator
404 and jitter attenuator ICs with fractional and integer dividers.
405
637cee5f
GF
406config COMMON_CLK_STM32MP135
407 def_bool COMMON_CLK && MACH_STM32MP13
408 help
409 Support for stm32mp135 SoC family clocks
410
9bee94e7
GF
411config COMMON_CLK_STM32MP157
412 def_bool COMMON_CLK && MACH_STM32MP157
413 help
9bee94e7
GF
414 Support for stm32mp157 SoC family clocks
415
da32d353 416config COMMON_CLK_STM32F
9a160601 417 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
da32d353 418 help
da32d353
BG
419 Support for stm32f4 and stm32f7 SoC families clocks
420
421config COMMON_CLK_STM32H7
9a160601 422 def_bool COMMON_CLK && MACH_STM32H743
da32d353 423 help
da32d353
BG
424 Support for stm32h7 SoC family clocks
425
a9372a5f
LR
426config COMMON_CLK_MMP2
427 def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
428 help
429 Support for Marvell MMP2 and MMP3 SoC clocks
430
725262d2
LR
431config COMMON_CLK_MMP2_AUDIO
432 tristate "Clock driver for MMP2 Audio subsystem"
433 depends on COMMON_CLK_MMP2 || COMPILE_TEST
434 help
435 This driver supports clocks for Audio subsystem on MMP2 SoC.
436
2e62246b 437config COMMON_CLK_BD718XX
ae866dec 438 tristate "Clock driver for 32K clk gates on ROHM PMICs"
fa5b6541 439 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
2e62246b 440 help
fa5b6541
MV
441 This driver supports ROHM BD71837, BD71847, BD71850, BD71815
442 and BD71828 PMICs clock gates.
2e62246b 443
50cc4caf
JK
444config COMMON_CLK_FIXED_MMIO
445 bool "Clock driver for Memory Mapped Fixed values"
446 depends on COMMON_CLK && OF
447 help
448 Support for Memory Mapped IO Fixed clocks
449
c6ca7616
DLM
450config COMMON_CLK_K210
451 bool "Clock driver for the Canaan Kendryte K210 SoC"
452 depends on OF && RISCV && SOC_CANAAN
453 default SOC_CANAAN
454 help
455 Support for the Canaan Kendryte K210 RISC-V SoC clocks.
456
d54c1fd4
QJ
457config COMMON_CLK_SP7021
458 tristate "Clock driver for Sunplus SP7021 SoC"
459 depends on SOC_SP7021 || COMPILE_TEST
460 default SOC_SP7021
461 help
462 This driver supports the Sunplus SP7021 SoC clocks.
463 It implements SP7021 PLLs/gate.
464 Not all features of the PLL are currently supported
465 by the driver.
466
3495e295 467source "drivers/clk/actions/Kconfig"
7b9487a9 468source "drivers/clk/analogbits/Kconfig"
b7d950b9 469source "drivers/clk/baikal-t1/Kconfig"
64a12c56 470source "drivers/clk/bcm/Kconfig"
72ea4861 471source "drivers/clk/hisilicon/Kconfig"
6b0fd6c1 472source "drivers/clk/imgtec/Kconfig"
3a48d918 473source "drivers/clk/imx/Kconfig"
0880fb86 474source "drivers/clk/ingenic/Kconfig"
b745c079 475source "drivers/clk/keystone/Kconfig"
2886c846 476source "drivers/clk/mediatek/Kconfig"
cb7c47d7 477source "drivers/clk/meson/Kconfig"
bef7a78d 478source "drivers/clk/mstar/Kconfig"
635e5e73 479source "drivers/clk/microchip/Kconfig"
97fa4cf4 480source "drivers/clk/mvebu/Kconfig"
90429205 481source "drivers/clk/pistachio/Kconfig"
b9e65ebc 482source "drivers/clk/qcom/Kconfig"
48df7a26 483source "drivers/clk/ralink/Kconfig"
a5bd7f7a 484source "drivers/clk/renesas/Kconfig"
4d98ed1e 485source "drivers/clk/rockchip/Kconfig"
4ce9b85e 486source "drivers/clk/samsung/Kconfig"
30b8e27e 487source "drivers/clk/sifive/Kconfig"
3b218baa 488source "drivers/clk/socfpga/Kconfig"
d41f59fd 489source "drivers/clk/sprd/Kconfig"
4210be66 490source "drivers/clk/starfive/Kconfig"
49c726d5 491source "drivers/clk/sunxi/Kconfig"
1d80c142 492source "drivers/clk/sunxi-ng/Kconfig"
31b52ba4 493source "drivers/clk/tegra/Kconfig"
21330497 494source "drivers/clk/ti/Kconfig"
734d82f4 495source "drivers/clk/uniphier/Kconfig"
b4cbe606 496source "drivers/clk/visconti/Kconfig"
d058fd9e 497source "drivers/clk/x86/Kconfig"
a2fe7baa 498source "drivers/clk/xilinx/Kconfig"
3fde0e16 499source "drivers/clk/zynqmp/Kconfig"
b9e65ebc 500
a992acbb 501# Kunit test cases
723d0530
MR
502config CLK_KUNIT_TEST
503 tristate "Basic Clock Framework Kunit Tests" if !KUNIT_ALL_TESTS
504 depends on KUNIT
505 default KUNIT_ALL_TESTS
506 help
507 Kunit tests for the common clock framework.
508
a992acbb
SB
509config CLK_GATE_KUNIT_TEST
510 tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS
511 depends on KUNIT
512 default KUNIT_ALL_TESTS
513 help
514 Kunit test for the basic clk gate type.
515
bbd7ffdb 516endif