[linux-2.6-block.git] / drivers / char / xillybus / xillybus.h

/*
 * linux/drivers/misc/xillybus.h
 *
 * Copyright 2011 Xillybus Ltd, http://xillybus.com
 *
 * Header file for the Xillybus FPGA/host framework.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the smems of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 */

#ifndef __XILLYBUS_H
#define __XILLYBUS_H

#include <linux/list.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/cdev.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>

struct xilly_endpoint_hardware;

struct xilly_buffer {
	void *addr;
	dma_addr_t dma_addr;
	int end_offset; /* Counting elements, not bytes */
};

struct xilly_idt_handle {
	unsigned char *chandesc;
	unsigned char *idt;
	int entries;
};

/*
 * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
 * wr_* buffers are those consumed by read(), since the FPGA writes to them
 * and vice versa.
 */

struct xilly_channel {
	struct xilly_endpoint *endpoint;
	int chan_num;
	int log2_element_size;
	int seekable;

	struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
	int num_wr_buffers;
	unsigned int wr_buf_size; /* In bytes */
	int wr_fpga_buf_idx;
	int wr_host_buf_idx;
	int wr_host_buf_pos;
	int wr_empty;
	int wr_ready; /* Significant only when wr_empty == 1 */
	int wr_sleepy;
	int wr_eof;
	int wr_hangup;
	spinlock_t wr_spinlock;
	struct mutex wr_mutex;
	wait_queue_head_t wr_wait;
	wait_queue_head_t wr_ready_wait;
	int wr_ref_count;
	int wr_synchronous;
	int wr_allow_partial;
	int wr_exclusive_open;
	int wr_supports_nonempty;

	struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
	int num_rd_buffers;
	unsigned int rd_buf_size; /* In bytes */
	int rd_fpga_buf_idx;
	int rd_host_buf_pos;
	int rd_host_buf_idx;
	int rd_full;
	spinlock_t rd_spinlock;
	struct mutex rd_mutex;
	wait_queue_head_t rd_wait;
	int rd_ref_count;
	int rd_allow_partial;
	int rd_synchronous;
	int rd_exclusive_open;
	struct delayed_work rd_workitem;
	unsigned char rd_leftovers[4];
};

struct xilly_endpoint {
	/*
	 * One of pdev and dev is always NULL, and the other is a valid
	 * pointer, depending on the type of device
	 */
	struct pci_dev *pdev;
	struct device *dev;
	struct xilly_endpoint_hardware *ephw;

	struct list_head ep_list;
	int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
	__iomem void *registers;
	int fatal_error;

	struct mutex register_mutex;
	wait_queue_head_t ep_wait;

	/* Channels and message handling */
	struct cdev cdev;

	int major;
	int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */

	int num_channels; /* EXCLUDING message buffer */
	struct xilly_channel **channels;
	int msg_counter;
	int failed_messages;
	int idtlen;

	u32 *msgbuf_addr;
	dma_addr_t msgbuf_dma_addr;
	unsigned int msg_buf_size;
};

struct xilly_endpoint_hardware {
	struct module *owner;
	void (*hw_sync_sgl_for_cpu)(struct xilly_endpoint *,
				    dma_addr_t,
				    size_t,
				    int);
	void (*hw_sync_sgl_for_device)(struct xilly_endpoint *,
				       dma_addr_t,
				       size_t,
				       int);
	int (*map_single)(struct xilly_endpoint *,
			  void *,
			  size_t,
			  int,
			  dma_addr_t *);
};

struct xilly_mapping {
	void *device;
	dma_addr_t dma_addr;
	size_t size;
	int direction;
};

irqreturn_t xillybus_isr(int irq, void *data);

struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev,
					      struct device *dev,
					      struct xilly_endpoint_hardware
					      *ephw);

int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);

void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);

#endif /* __XILLYBUS_H */
Commit	Line	Data
48bae050 EB	1	/*
	2	* linux/drivers/misc/xillybus.h
	3	*
	4	* Copyright 2011 Xillybus Ltd, http://xillybus.com
	5	*
	6	* Header file for the Xillybus FPGA/host framework.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the smems of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*/
	12
	13	#ifndef __XILLYBUS_H
	14	#define __XILLYBUS_H
	15
	16	#include <linux/list.h>
	17	#include <linux/device.h>
	18	#include <linux/dma-mapping.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/sched.h>
	21	#include <linux/cdev.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/mutex.h>
48bae050 EB	24	#include <linux/workqueue.h>
48bae050 EB	25
48bae050 EB	26	struct xilly_endpoint_hardware;
48bae050 EB	27
48bae050 EB	28	struct xilly_buffer {
	29	void *addr;
	30	dma_addr_t dma_addr;
	31	int end_offset; /* Counting elements, not bytes */
	32	};
	33
48bae050 EB	34	struct xilly_idt_handle {
	35	unsigned char *chandesc;
	36	unsigned char *idt;
	37	int entries;
	38	};
	39
	40	/*
	41	* Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
	42	* wr_* buffers are those consumed by read(), since the FPGA writes to them
	43	* and vice versa.
	44	*/
	45
	46	struct xilly_channel {
	47	struct xilly_endpoint *endpoint;
	48	int chan_num;
	49	int log2_element_size;
	50	int seekable;
	51
	52	struct xilly_buffer *wr_buffers; / FPGA writes, driver reads! */
	53	int num_wr_buffers;
	54	unsigned int wr_buf_size; /* In bytes */
	55	int wr_fpga_buf_idx;
	56	int wr_host_buf_idx;
	57	int wr_host_buf_pos;
	58	int wr_empty;
	59	int wr_ready; /* Significant only when wr_empty == 1 */
	60	int wr_sleepy;
	61	int wr_eof;
	62	int wr_hangup;
	63	spinlock_t wr_spinlock;
	64	struct mutex wr_mutex;
	65	wait_queue_head_t wr_wait;
	66	wait_queue_head_t wr_ready_wait;
	67	int wr_ref_count;
	68	int wr_synchronous;
	69	int wr_allow_partial;
	70	int wr_exclusive_open;
	71	int wr_supports_nonempty;
	72
	73	struct xilly_buffer *rd_buffers; / FPGA reads, driver writes! */
	74	int num_rd_buffers;
	75	unsigned int rd_buf_size; /* In bytes */
	76	int rd_fpga_buf_idx;
	77	int rd_host_buf_pos;
	78	int rd_host_buf_idx;
	79	int rd_full;
	80	spinlock_t rd_spinlock;
	81	struct mutex rd_mutex;
	82	wait_queue_head_t rd_wait;
	83	int rd_ref_count;
	84	int rd_allow_partial;
	85	int rd_synchronous;
	86	int rd_exclusive_open;
	87	struct delayed_work rd_workitem;
	88	unsigned char rd_leftovers[4];
	89	};
	90
	91	struct xilly_endpoint {
	92	/*
	93	* One of pdev and dev is always NULL, and the other is a valid
	94	* pointer, depending on the type of device
	95	*/
	96	struct pci_dev *pdev;
	97	struct device *dev;
48bae050 EB	98	struct xilly_endpoint_hardware *ephw;
	99
	100	struct list_head ep_list;
	101	int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
539889ee	102	__iomem void *registers;
48bae050 EB	103	int fatal_error;
	104
	105	struct mutex register_mutex;
	106	wait_queue_head_t ep_wait;
	107
48bae050 EB	108	/* Channels and message handling */
	109	struct cdev cdev;
	110
	111	int major;
	112	int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */
	113
	114	int num_channels; /* EXCLUDING message buffer */
	115	struct xilly_channel **channels;
	116	int msg_counter;
	117	int failed_messages;
	118	int idtlen;
	119
	120	u32 *msgbuf_addr;
	121	dma_addr_t msgbuf_dma_addr;
	122	unsigned int msg_buf_size;
	123	};
	124
	125	struct xilly_endpoint_hardware {
	126	struct module *owner;
7ee9ded2	127	void (hw_sync_sgl_for_cpu)(struct xilly_endpoint ,
48bae050 EB	128	dma_addr_t,
	129	size_t,
	130	int);
7ee9ded2	131	void (hw_sync_sgl_for_device)(struct xilly_endpoint ,
48bae050 EB	132	dma_addr_t,
	133	size_t,
	134	int);
525be905 EB	135	int (map_single)(struct xilly_endpoint ,
	136	void *,
	137	size_t,
	138	int,
	139	dma_addr_t *);
48bae050 EB	140	};
48bae050 EB	141
525be905 EB	142	struct xilly_mapping {
	143	void *device;
	144	dma_addr_t dma_addr;
	145	size_t size;
	146	int direction;
	147	};
48bae050	148
525be905	149	irqreturn_t xillybus_isr(int irq, void *data);
48bae050 EB	150
	151	struct xilly_endpoint xillybus_init_endpoint(struct pci_dev pdev,
	152	struct device *dev,
	153	struct xilly_endpoint_hardware
	154	*ephw);
	155
	156	int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);
	157
	158	void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);
	159
	160	#endif /* __XILLYBUS_H */