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b886d83c | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
57dacc2b CR |
2 | /* |
3 | * Copyright (C) 2005, 2006 IBM Corporation | |
4 | * Copyright (C) 2014, 2015 Intel Corporation | |
5 | * | |
6 | * Authors: | |
7 | * Leendert van Doorn <leendert@watson.ibm.com> | |
8 | * Kylene Hall <kjhall@us.ibm.com> | |
9 | * | |
10 | * Maintained by: <tpmdd-devel@lists.sourceforge.net> | |
11 | * | |
12 | * Device driver for TCG/TCPA TPM (trusted platform module). | |
13 | * Specifications at www.trustedcomputinggroup.org | |
14 | * | |
15 | * This device driver implements the TPM interface as defined in | |
16 | * the TCG TPM Interface Spec version 1.2, revision 1.0. | |
57dacc2b CR |
17 | */ |
18 | ||
19 | #ifndef __TPM_TIS_CORE_H__ | |
20 | #define __TPM_TIS_CORE_H__ | |
21 | ||
22 | #include "tpm.h" | |
23 | ||
41a5e1cf CR |
24 | enum tis_access { |
25 | TPM_ACCESS_VALID = 0x80, | |
26 | TPM_ACCESS_ACTIVE_LOCALITY = 0x20, | |
27 | TPM_ACCESS_REQUEST_PENDING = 0x04, | |
28 | TPM_ACCESS_REQUEST_USE = 0x02, | |
29 | }; | |
30 | ||
31 | enum tis_status { | |
32 | TPM_STS_VALID = 0x80, | |
33 | TPM_STS_COMMAND_READY = 0x40, | |
34 | TPM_STS_GO = 0x20, | |
35 | TPM_STS_DATA_AVAIL = 0x10, | |
36 | TPM_STS_DATA_EXPECT = 0x08, | |
55707d53 | 37 | TPM_STS_READ_ZERO = 0x23, /* bits that must be zero on read */ |
41a5e1cf CR |
38 | }; |
39 | ||
40 | enum tis_int_flags { | |
41 | TPM_GLOBAL_INT_ENABLE = 0x80000000, | |
42 | TPM_INTF_BURST_COUNT_STATIC = 0x100, | |
43 | TPM_INTF_CMD_READY_INT = 0x080, | |
44 | TPM_INTF_INT_EDGE_FALLING = 0x040, | |
45 | TPM_INTF_INT_EDGE_RISING = 0x020, | |
46 | TPM_INTF_INT_LEVEL_LOW = 0x010, | |
47 | TPM_INTF_INT_LEVEL_HIGH = 0x008, | |
48 | TPM_INTF_LOCALITY_CHANGE_INT = 0x004, | |
49 | TPM_INTF_STS_VALID_INT = 0x002, | |
50 | TPM_INTF_DATA_AVAIL_INT = 0x001, | |
51 | }; | |
52 | ||
53 | enum tis_defaults { | |
54 | TIS_MEM_LEN = 0x5000, | |
55 | TIS_SHORT_TIMEOUT = 750, /* ms */ | |
56 | TIS_LONG_TIMEOUT = 2000, /* 2 sec */ | |
79ca6f74 HW |
57 | TIS_TIMEOUT_MIN_ATML = 14700, /* usecs */ |
58 | TIS_TIMEOUT_MAX_ATML = 15000, /* usecs */ | |
41a5e1cf CR |
59 | }; |
60 | ||
61 | /* Some timeout values are needed before it is known whether the chip is | |
62 | * TPM 1.0 or TPM 2.0. | |
63 | */ | |
3c8ba0d6 KC |
64 | #define TIS_TIMEOUT_A_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A) |
65 | #define TIS_TIMEOUT_B_MAX max_t(int, TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B) | |
66 | #define TIS_TIMEOUT_C_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C) | |
67 | #define TIS_TIMEOUT_D_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D) | |
41a5e1cf CR |
68 | |
69 | #define TPM_ACCESS(l) (0x0000 | ((l) << 12)) | |
70 | #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) | |
71 | #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12)) | |
72 | #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12)) | |
73 | #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) | |
74 | #define TPM_STS(l) (0x0018 | ((l) << 12)) | |
75 | #define TPM_STS3(l) (0x001b | ((l) << 12)) | |
76 | #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) | |
77 | ||
78 | #define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) | |
79 | #define TPM_RID(l) (0x0F04 | ((l) << 12)) | |
80 | ||
b3e958ce AS |
81 | #define LPC_CNTRL_OFFSET 0x84 |
82 | #define LPC_CLKRUN_EN (1 << 2) | |
c382babc AS |
83 | #define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000 |
84 | #define ILB_REMAP_SIZE 0x100 | |
85 | ||
41a5e1cf | 86 | enum tpm_tis_flags { |
1d70fe9d | 87 | TPM_TIS_ITPM_WORKAROUND = BIT(0), |
0178f9d0 | 88 | TPM_TIS_INVALID_STATUS = BIT(1), |
7bfda9c7 | 89 | TPM_TIS_DEFAULT_CANCELLATION = BIT(2), |
41a5e1cf CR |
90 | }; |
91 | ||
57dacc2b CR |
92 | struct tpm_tis_data { |
93 | u16 manufacturer_id; | |
94 | int locality; | |
95 | int irq; | |
96 | bool irq_tested; | |
0178f9d0 | 97 | unsigned long flags; |
c382babc | 98 | void __iomem *ilb_base_addr; |
b3e958ce | 99 | u16 clkrun_enabled; |
57dacc2b CR |
100 | wait_queue_head_t int_queue; |
101 | wait_queue_head_t read_queue; | |
1107d065 | 102 | const struct tpm_tis_phy_ops *phy_ops; |
7a64c559 | 103 | unsigned short rng_quality; |
79ca6f74 HW |
104 | unsigned int timeout_min; /* usecs */ |
105 | unsigned int timeout_max; /* usecs */ | |
57dacc2b CR |
106 | }; |
107 | ||
6422cbd3 JH |
108 | /* |
109 | * IO modes to indicate how many bytes should be read/written at once in the | |
110 | * tpm_tis_phy_ops read_bytes/write_bytes calls. Use TPM_TIS_PHYS_8 to | |
111 | * receive/transmit byte-wise, TPM_TIS_PHYS_16 for two bytes etc. | |
112 | */ | |
113 | enum tpm_tis_io_mode { | |
114 | TPM_TIS_PHYS_8, | |
115 | TPM_TIS_PHYS_16, | |
116 | TPM_TIS_PHYS_32, | |
117 | }; | |
118 | ||
1107d065 | 119 | struct tpm_tis_phy_ops { |
6422cbd3 | 120 | /* data is passed in little endian */ |
1107d065 | 121 | int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len, |
6422cbd3 | 122 | u8 *result, enum tpm_tis_io_mode mode); |
1107d065 | 123 | int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len, |
6422cbd3 | 124 | const u8 *value, enum tpm_tis_io_mode mode); |
f25534a6 AS |
125 | int (*verify_crc)(struct tpm_tis_data *data, size_t len, |
126 | const u8 *value); | |
1107d065 CR |
127 | }; |
128 | ||
129 | static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr, | |
130 | u16 len, u8 *result) | |
131 | { | |
6422cbd3 JH |
132 | return data->phy_ops->read_bytes(data, addr, len, result, |
133 | TPM_TIS_PHYS_8); | |
1107d065 CR |
134 | } |
135 | ||
136 | static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result) | |
137 | { | |
6422cbd3 | 138 | return data->phy_ops->read_bytes(data, addr, 1, result, TPM_TIS_PHYS_8); |
1107d065 CR |
139 | } |
140 | ||
141 | static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr, | |
142 | u16 *result) | |
143 | { | |
6422cbd3 JH |
144 | __le16 result_le; |
145 | int rc; | |
146 | ||
147 | rc = data->phy_ops->read_bytes(data, addr, sizeof(u16), | |
148 | (u8 *)&result_le, TPM_TIS_PHYS_16); | |
149 | if (!rc) | |
150 | *result = le16_to_cpu(result_le); | |
151 | ||
152 | return rc; | |
1107d065 CR |
153 | } |
154 | ||
155 | static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr, | |
156 | u32 *result) | |
157 | { | |
6422cbd3 JH |
158 | __le32 result_le; |
159 | int rc; | |
160 | ||
161 | rc = data->phy_ops->read_bytes(data, addr, sizeof(u32), | |
162 | (u8 *)&result_le, TPM_TIS_PHYS_32); | |
163 | if (!rc) | |
164 | *result = le32_to_cpu(result_le); | |
165 | ||
166 | return rc; | |
1107d065 CR |
167 | } |
168 | ||
169 | static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr, | |
c37fbc09 | 170 | u16 len, const u8 *value) |
1107d065 | 171 | { |
6422cbd3 JH |
172 | return data->phy_ops->write_bytes(data, addr, len, value, |
173 | TPM_TIS_PHYS_8); | |
1107d065 CR |
174 | } |
175 | ||
176 | static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value) | |
177 | { | |
6422cbd3 JH |
178 | return data->phy_ops->write_bytes(data, addr, 1, &value, |
179 | TPM_TIS_PHYS_8); | |
1107d065 CR |
180 | } |
181 | ||
182 | static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr, | |
183 | u32 value) | |
184 | { | |
6422cbd3 JH |
185 | __le32 value_le; |
186 | int rc; | |
187 | ||
188 | value_le = cpu_to_le32(value); | |
189 | rc = data->phy_ops->write_bytes(data, addr, sizeof(u32), | |
190 | (u8 *)&value_le, TPM_TIS_PHYS_32); | |
191 | return rc; | |
1107d065 CR |
192 | } |
193 | ||
f25534a6 AS |
194 | static inline int tpm_tis_verify_crc(struct tpm_tis_data *data, size_t len, |
195 | const u8 *value) | |
196 | { | |
197 | if (!data->phy_ops->verify_crc) | |
198 | return 0; | |
199 | return data->phy_ops->verify_crc(data, len, value); | |
200 | } | |
201 | ||
c382babc AS |
202 | static inline bool is_bsw(void) |
203 | { | |
204 | #ifdef CONFIG_X86 | |
205 | return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0); | |
206 | #else | |
207 | return false; | |
208 | #endif | |
209 | } | |
210 | ||
41a5e1cf CR |
211 | void tpm_tis_remove(struct tpm_chip *chip); |
212 | int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq, | |
213 | const struct tpm_tis_phy_ops *phy_ops, | |
214 | acpi_handle acpi_dev_handle); | |
215 | ||
216 | #ifdef CONFIG_PM_SLEEP | |
217 | int tpm_tis_resume(struct device *dev); | |
218 | #endif | |
219 | ||
57dacc2b | 220 | #endif |