tpm, tpm_crb: fix unaligned read of the command buffer address
[linux-2.6-block.git] / drivers / char / tpm / tpm_tis.c
CommitLineData
27084efe
LD
1/*
2 * Copyright (C) 2005, 2006 IBM Corporation
aec04cbd 3 * Copyright (C) 2014 Intel Corporation
27084efe
LD
4 *
5 * Authors:
6 * Leendert van Doorn <leendert@watson.ibm.com>
7 * Kylene Hall <kjhall@us.ibm.com>
8 *
8e81cc13
KY
9 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
10 *
27084efe
LD
11 * Device driver for TCG/TCPA TPM (trusted platform module).
12 * Specifications at www.trustedcomputinggroup.org
13 *
14 * This device driver implements the TPM interface as defined in
15 * the TCG TPM Interface Spec version 1.2, revision 1.0.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation, version 2 of the
20 * License.
21 */
57135568
KJH
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
27084efe 25#include <linux/pnp.h>
5a0e3ad6 26#include <linux/slab.h>
27084efe
LD
27#include <linux/interrupt.h>
28#include <linux/wait.h>
3f0d3d01 29#include <linux/acpi.h>
20b87bbf 30#include <linux/freezer.h>
27084efe
LD
31#include "tpm.h"
32
27084efe
LD
33enum tis_access {
34 TPM_ACCESS_VALID = 0x80,
35 TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
36 TPM_ACCESS_REQUEST_PENDING = 0x04,
37 TPM_ACCESS_REQUEST_USE = 0x02,
38};
39
40enum tis_status {
41 TPM_STS_VALID = 0x80,
42 TPM_STS_COMMAND_READY = 0x40,
43 TPM_STS_GO = 0x20,
44 TPM_STS_DATA_AVAIL = 0x10,
45 TPM_STS_DATA_EXPECT = 0x08,
46};
47
48enum tis_int_flags {
49 TPM_GLOBAL_INT_ENABLE = 0x80000000,
50 TPM_INTF_BURST_COUNT_STATIC = 0x100,
51 TPM_INTF_CMD_READY_INT = 0x080,
52 TPM_INTF_INT_EDGE_FALLING = 0x040,
53 TPM_INTF_INT_EDGE_RISING = 0x020,
54 TPM_INTF_INT_LEVEL_LOW = 0x010,
55 TPM_INTF_INT_LEVEL_HIGH = 0x008,
56 TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
57 TPM_INTF_STS_VALID_INT = 0x002,
58 TPM_INTF_DATA_AVAIL_INT = 0x001,
59};
60
36b20020 61enum tis_defaults {
2a7362f5 62 TIS_MEM_BASE = 0xFED40000,
b09d5300 63 TIS_MEM_LEN = 0x5000,
cb535425
KJH
64 TIS_SHORT_TIMEOUT = 750, /* ms */
65 TIS_LONG_TIMEOUT = 2000, /* 2 sec */
36b20020
KJH
66};
67
aec04cbd
JS
68
69/* Some timeout values are needed before it is known whether the chip is
70 * TPM 1.0 or TPM 2.0.
71 */
72#define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
73#define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
74#define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
75#define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
76
27084efe
LD
77#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
78#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
79#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
80#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
81#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
82#define TPM_STS(l) (0x0018 | ((l) << 12))
aec04cbd 83#define TPM_STS3(l) (0x001b | ((l) << 12))
27084efe
LD
84#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
85
86#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
87#define TPM_RID(l) (0x0F04 | ((l) << 12))
88
448e9c55
SD
89struct priv_data {
90 bool irq_tested;
91};
92
1560ffe6 93#if defined(CONFIG_PNP) && defined(CONFIG_ACPI)
3f0d3d01
MG
94static int is_itpm(struct pnp_dev *dev)
95{
96 struct acpi_device *acpi = pnp_acpi_device(dev);
97 struct acpi_hardware_id *id;
98
6e38bfaa
KY
99 if (!acpi)
100 return 0;
101
3f0d3d01
MG
102 list_for_each_entry(id, &acpi->pnp.ids, list) {
103 if (!strcmp("INTC0102", id->id))
104 return 1;
105 }
106
107 return 0;
108}
1560ffe6
RD
109#else
110static inline int is_itpm(struct pnp_dev *dev)
111{
112 return 0;
113}
3f0d3d01
MG
114#endif
115
7240b983
JG
116/* Before we attempt to access the TPM we must see that the valid bit is set.
117 * The specification says that this bit is 0 at reset and remains 0 until the
118 * 'TPM has gone through its self test and initialization and has established
119 * correct values in the other bits.' */
120static int wait_startup(struct tpm_chip *chip, int l)
121{
122 unsigned long stop = jiffies + chip->vendor.timeout_a;
123 do {
124 if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
125 TPM_ACCESS_VALID)
126 return 0;
127 msleep(TPM_TIMEOUT);
128 } while (time_before(jiffies, stop));
129 return -1;
130}
131
27084efe
LD
132static int check_locality(struct tpm_chip *chip, int l)
133{
134 if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
135 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
136 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
137 return chip->vendor.locality = l;
138
139 return -1;
140}
141
142static void release_locality(struct tpm_chip *chip, int l, int force)
143{
144 if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
145 (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
146 (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
147 iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
148 chip->vendor.iobase + TPM_ACCESS(l));
149}
150
151static int request_locality(struct tpm_chip *chip, int l)
152{
20b87bbf 153 unsigned long stop, timeout;
27084efe
LD
154 long rc;
155
156 if (check_locality(chip, l) >= 0)
157 return l;
158
159 iowrite8(TPM_ACCESS_REQUEST_USE,
160 chip->vendor.iobase + TPM_ACCESS(l));
161
20b87bbf
SB
162 stop = jiffies + chip->vendor.timeout_a;
163
27084efe 164 if (chip->vendor.irq) {
20b87bbf
SB
165again:
166 timeout = stop - jiffies;
167 if ((long)timeout <= 0)
168 return -1;
36b20020 169 rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
27084efe
LD
170 (check_locality
171 (chip, l) >= 0),
20b87bbf 172 timeout);
27084efe
LD
173 if (rc > 0)
174 return l;
20b87bbf
SB
175 if (rc == -ERESTARTSYS && freezing(current)) {
176 clear_thread_flag(TIF_SIGPENDING);
177 goto again;
178 }
27084efe
LD
179 } else {
180 /* wait for burstcount */
27084efe
LD
181 do {
182 if (check_locality(chip, l) >= 0)
183 return l;
184 msleep(TPM_TIMEOUT);
185 }
186 while (time_before(jiffies, stop));
187 }
188 return -1;
189}
190
191static u8 tpm_tis_status(struct tpm_chip *chip)
192{
193 return ioread8(chip->vendor.iobase +
194 TPM_STS(chip->vendor.locality));
195}
196
197static void tpm_tis_ready(struct tpm_chip *chip)
198{
199 /* this causes the current command to be aborted */
200 iowrite8(TPM_STS_COMMAND_READY,
201 chip->vendor.iobase + TPM_STS(chip->vendor.locality));
202}
203
204static int get_burstcount(struct tpm_chip *chip)
205{
206 unsigned long stop;
207 int burstcnt;
208
209 /* wait for burstcount */
210 /* which timeout value, spec has 2 answers (c & d) */
36b20020 211 stop = jiffies + chip->vendor.timeout_d;
27084efe
LD
212 do {
213 burstcnt = ioread8(chip->vendor.iobase +
214 TPM_STS(chip->vendor.locality) + 1);
215 burstcnt += ioread8(chip->vendor.iobase +
216 TPM_STS(chip->vendor.locality) +
217 2) << 8;
218 if (burstcnt)
219 return burstcnt;
220 msleep(TPM_TIMEOUT);
221 } while (time_before(jiffies, stop));
222 return -EBUSY;
223}
224
cb535425 225static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
27084efe
LD
226{
227 int size = 0, burstcnt;
228 while (size < count &&
fd048866
RA
229 wait_for_tpm_stat(chip,
230 TPM_STS_DATA_AVAIL | TPM_STS_VALID,
231 chip->vendor.timeout_c,
78f09cc2 232 &chip->vendor.read_queue, true)
27084efe
LD
233 == 0) {
234 burstcnt = get_burstcount(chip);
235 for (; burstcnt > 0 && size < count; burstcnt--)
236 buf[size++] = ioread8(chip->vendor.iobase +
237 TPM_DATA_FIFO(chip->vendor.
238 locality));
239 }
240 return size;
241}
242
cb535425 243static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
27084efe
LD
244{
245 int size = 0;
246 int expected, status;
247
248 if (count < TPM_HEADER_SIZE) {
249 size = -EIO;
250 goto out;
251 }
252
253 /* read first 10 bytes, including tag, paramsize, and result */
254 if ((size =
255 recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
71ed848f 256 dev_err(chip->pdev, "Unable to read header\n");
27084efe
LD
257 goto out;
258 }
259
260 expected = be32_to_cpu(*(__be32 *) (buf + 2));
261 if (expected > count) {
262 size = -EIO;
263 goto out;
264 }
265
266 if ((size +=
267 recv_data(chip, &buf[TPM_HEADER_SIZE],
268 expected - TPM_HEADER_SIZE)) < expected) {
71ed848f 269 dev_err(chip->pdev, "Unable to read remainder of result\n");
27084efe
LD
270 size = -ETIME;
271 goto out;
272 }
273
fd048866 274 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 275 &chip->vendor.int_queue, false);
27084efe
LD
276 status = tpm_tis_status(chip);
277 if (status & TPM_STS_DATA_AVAIL) { /* retry? */
71ed848f 278 dev_err(chip->pdev, "Error left over data\n");
27084efe
LD
279 size = -EIO;
280 goto out;
281 }
282
283out:
284 tpm_tis_ready(chip);
285 release_locality(chip, chip->vendor.locality, 0);
286 return size;
287}
288
90ab5ee9 289static bool itpm;
3507d612
RA
290module_param(itpm, bool, 0444);
291MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)");
292
27084efe
LD
293/*
294 * If interrupts are used (signaled by an irq set in the vendor structure)
295 * tpm.c can skip polling for the data to be available as the interrupt is
296 * waited for here
297 */
9519de3f 298static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
27084efe
LD
299{
300 int rc, status, burstcnt;
301 size_t count = 0;
27084efe
LD
302
303 if (request_locality(chip, 0) < 0)
304 return -EBUSY;
305
306 status = tpm_tis_status(chip);
307 if ((status & TPM_STS_COMMAND_READY) == 0) {
308 tpm_tis_ready(chip);
fd048866 309 if (wait_for_tpm_stat
27084efe 310 (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
78f09cc2 311 &chip->vendor.int_queue, false) < 0) {
27084efe
LD
312 rc = -ETIME;
313 goto out_err;
314 }
315 }
316
317 while (count < len - 1) {
318 burstcnt = get_burstcount(chip);
319 for (; burstcnt > 0 && count < len - 1; burstcnt--) {
320 iowrite8(buf[count], chip->vendor.iobase +
321 TPM_DATA_FIFO(chip->vendor.locality));
322 count++;
323 }
324
fd048866 325 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 326 &chip->vendor.int_queue, false);
27084efe 327 status = tpm_tis_status(chip);
3507d612 328 if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
27084efe
LD
329 rc = -EIO;
330 goto out_err;
331 }
332 }
333
334 /* write last byte */
335 iowrite8(buf[count],
9519de3f 336 chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality));
fd048866 337 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 338 &chip->vendor.int_queue, false);
27084efe
LD
339 status = tpm_tis_status(chip);
340 if ((status & TPM_STS_DATA_EXPECT) != 0) {
341 rc = -EIO;
342 goto out_err;
343 }
344
9519de3f
SB
345 return 0;
346
347out_err:
348 tpm_tis_ready(chip);
349 release_locality(chip, chip->vendor.locality, 0);
350 return rc;
351}
352
448e9c55
SD
353static void disable_interrupts(struct tpm_chip *chip)
354{
355 u32 intmask;
356
357 intmask =
358 ioread32(chip->vendor.iobase +
359 TPM_INT_ENABLE(chip->vendor.locality));
360 intmask &= ~TPM_GLOBAL_INT_ENABLE;
361 iowrite32(intmask,
362 chip->vendor.iobase +
363 TPM_INT_ENABLE(chip->vendor.locality));
364 free_irq(chip->vendor.irq, chip);
365 chip->vendor.irq = 0;
366}
367
9519de3f
SB
368/*
369 * If interrupts are used (signaled by an irq set in the vendor structure)
370 * tpm.c can skip polling for the data to be available as the interrupt is
371 * waited for here
372 */
448e9c55 373static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len)
9519de3f
SB
374{
375 int rc;
376 u32 ordinal;
aec04cbd 377 unsigned long dur;
9519de3f
SB
378
379 rc = tpm_tis_send_data(chip, buf, len);
380 if (rc < 0)
381 return rc;
382
27084efe
LD
383 /* go and do it */
384 iowrite8(TPM_STS_GO,
385 chip->vendor.iobase + TPM_STS(chip->vendor.locality));
386
387 if (chip->vendor.irq) {
388 ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
aec04cbd
JS
389
390 if (chip->flags & TPM_CHIP_FLAG_TPM2)
391 dur = tpm2_calc_ordinal_duration(chip, ordinal);
392 else
393 dur = tpm_calc_ordinal_duration(chip, ordinal);
394
fd048866 395 if (wait_for_tpm_stat
aec04cbd 396 (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur,
78f09cc2 397 &chip->vendor.read_queue, false) < 0) {
27084efe
LD
398 rc = -ETIME;
399 goto out_err;
400 }
401 }
402 return len;
403out_err:
404 tpm_tis_ready(chip);
405 release_locality(chip, chip->vendor.locality, 0);
406 return rc;
407}
408
448e9c55
SD
409static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
410{
411 int rc, irq;
412 struct priv_data *priv = chip->vendor.priv;
413
414 if (!chip->vendor.irq || priv->irq_tested)
415 return tpm_tis_send_main(chip, buf, len);
416
417 /* Verify receipt of the expected IRQ */
418 irq = chip->vendor.irq;
419 chip->vendor.irq = 0;
420 rc = tpm_tis_send_main(chip, buf, len);
421 chip->vendor.irq = irq;
422 if (!priv->irq_tested)
423 msleep(1);
424 if (!priv->irq_tested) {
425 disable_interrupts(chip);
71ed848f 426 dev_err(chip->pdev,
448e9c55
SD
427 FW_BUG "TPM interrupt not working, polling instead\n");
428 }
429 priv->irq_tested = true;
430 return rc;
431}
432
8e54caf4
JG
433struct tis_vendor_timeout_override {
434 u32 did_vid;
435 unsigned long timeout_us[4];
436};
437
438static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
439 /* Atmel 3204 */
440 { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
441 (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
442};
443
444static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
445 unsigned long *timeout_cap)
446{
447 int i;
448 u32 did_vid;
449
450 did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
451
452 for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
453 if (vendor_timeout_overrides[i].did_vid != did_vid)
454 continue;
455 memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
456 sizeof(vendor_timeout_overrides[i].timeout_us));
457 return true;
458 }
459
460 return false;
461}
462
9519de3f
SB
463/*
464 * Early probing for iTPM with STS_DATA_EXPECT flaw.
465 * Try sending command without itpm flag set and if that
466 * fails, repeat with itpm flag set.
467 */
468static int probe_itpm(struct tpm_chip *chip)
469{
470 int rc = 0;
471 u8 cmd_getticks[] = {
472 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
473 0x00, 0x00, 0x00, 0xf1
474 };
475 size_t len = sizeof(cmd_getticks);
968de8e2 476 bool rem_itpm = itpm;
4e401fb0
SB
477 u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0));
478
479 /* probe only iTPMS */
480 if (vendor != TPM_VID_INTEL)
481 return 0;
9519de3f 482
73249695 483 itpm = false;
9519de3f
SB
484
485 rc = tpm_tis_send_data(chip, cmd_getticks, len);
486 if (rc == 0)
487 goto out;
488
489 tpm_tis_ready(chip);
490 release_locality(chip, chip->vendor.locality, 0);
491
73249695 492 itpm = true;
9519de3f
SB
493
494 rc = tpm_tis_send_data(chip, cmd_getticks, len);
495 if (rc == 0) {
71ed848f 496 dev_info(chip->pdev, "Detected an iTPM.\n");
9519de3f
SB
497 rc = 1;
498 } else
499 rc = -EFAULT;
500
501out:
502 itpm = rem_itpm;
503 tpm_tis_ready(chip);
504 release_locality(chip, chip->vendor.locality, 0);
505
506 return rc;
507}
508
1f866057
SB
509static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
510{
511 switch (chip->vendor.manufacturer_id) {
512 case TPM_VID_WINBOND:
513 return ((status == TPM_STS_VALID) ||
514 (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
515 case TPM_VID_STM:
516 return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
517 default:
518 return (status == TPM_STS_COMMAND_READY);
519 }
520}
521
01ad1fa7 522static const struct tpm_class_ops tpm_tis = {
27084efe
LD
523 .status = tpm_tis_status,
524 .recv = tpm_tis_recv,
525 .send = tpm_tis_send,
526 .cancel = tpm_tis_ready,
8e54caf4 527 .update_timeouts = tpm_tis_update_timeouts,
27084efe
LD
528 .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
529 .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
1f866057 530 .req_canceled = tpm_tis_req_canceled,
27084efe
LD
531};
532
7d12e780 533static irqreturn_t tis_int_probe(int irq, void *dev_id)
27084efe 534{
06efcad0 535 struct tpm_chip *chip = dev_id;
27084efe
LD
536 u32 interrupt;
537
538 interrupt = ioread32(chip->vendor.iobase +
539 TPM_INT_STATUS(chip->vendor.locality));
540
541 if (interrupt == 0)
542 return IRQ_NONE;
543
a7b66822 544 chip->vendor.probed_irq = irq;
27084efe
LD
545
546 /* Clear interrupts handled with TPM_EOI */
547 iowrite32(interrupt,
548 chip->vendor.iobase +
549 TPM_INT_STATUS(chip->vendor.locality));
550 return IRQ_HANDLED;
551}
552
a6f97b29 553static irqreturn_t tis_int_handler(int dummy, void *dev_id)
27084efe 554{
06efcad0 555 struct tpm_chip *chip = dev_id;
27084efe
LD
556 u32 interrupt;
557 int i;
558
559 interrupt = ioread32(chip->vendor.iobase +
560 TPM_INT_STATUS(chip->vendor.locality));
561
562 if (interrupt == 0)
563 return IRQ_NONE;
564
448e9c55 565 ((struct priv_data *)chip->vendor.priv)->irq_tested = true;
27084efe
LD
566 if (interrupt & TPM_INTF_DATA_AVAIL_INT)
567 wake_up_interruptible(&chip->vendor.read_queue);
568 if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
569 for (i = 0; i < 5; i++)
570 if (check_locality(chip, i) >= 0)
571 break;
572 if (interrupt &
573 (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
574 TPM_INTF_CMD_READY_INT))
575 wake_up_interruptible(&chip->vendor.int_queue);
576
577 /* Clear interrupts handled with TPM_EOI */
578 iowrite32(interrupt,
579 chip->vendor.iobase +
580 TPM_INT_STATUS(chip->vendor.locality));
cab091ea 581 ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
27084efe
LD
582 return IRQ_HANDLED;
583}
584
73249695 585static bool interrupts = true;
57135568
KJH
586module_param(interrupts, bool, 0444);
587MODULE_PARM_DESC(interrupts, "Enable interrupts");
588
afb5abc2
JS
589static void tpm_tis_remove(struct tpm_chip *chip)
590{
74d6b3ce
JS
591 if (chip->flags & TPM_CHIP_FLAG_TPM2)
592 tpm2_shutdown(chip, TPM2_SU_CLEAR);
593
afb5abc2
JS
594 iowrite32(~TPM_GLOBAL_INT_ENABLE &
595 ioread32(chip->vendor.iobase +
596 TPM_INT_ENABLE(chip->vendor.
597 locality)),
598 chip->vendor.iobase +
599 TPM_INT_ENABLE(chip->vendor.locality));
600 release_locality(chip, chip->vendor.locality, 1);
601}
602
0dc55365
JS
603static int tpm_tis_init(struct device *dev, acpi_handle acpi_dev_handle,
604 resource_size_t start, resource_size_t len,
605 unsigned int irq)
27084efe
LD
606{
607 u32 vendor, intfcaps, intmask;
968de8e2 608 int rc, i, irq_s, irq_e, probe;
27084efe 609 struct tpm_chip *chip;
448e9c55 610 struct priv_data *priv;
27084efe 611
448e9c55
SD
612 priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL);
613 if (priv == NULL)
614 return -ENOMEM;
afb5abc2
JS
615
616 chip = tpmm_chip_alloc(dev, &tpm_tis);
617 if (IS_ERR(chip))
618 return PTR_ERR(chip);
619
448e9c55 620 chip->vendor.priv = priv;
aec04cbd 621#ifdef CONFIG_ACPI
0dc55365 622 chip->acpi_dev_handle = acpi_dev_handle;
aec04cbd 623#endif
27084efe 624
afb5abc2
JS
625 chip->vendor.iobase = devm_ioremap(dev, start, len);
626 if (!chip->vendor.iobase)
627 return -EIO;
27084efe 628
aec04cbd
JS
629 /* Maximum timeouts */
630 chip->vendor.timeout_a = TIS_TIMEOUT_A_MAX;
631 chip->vendor.timeout_b = TIS_TIMEOUT_B_MAX;
632 chip->vendor.timeout_c = TIS_TIMEOUT_C_MAX;
633 chip->vendor.timeout_d = TIS_TIMEOUT_D_MAX;
ec579358 634
7240b983
JG
635 if (wait_startup(chip, 0) != 0) {
636 rc = -ENODEV;
637 goto out_err;
638 }
639
05a462af
MS
640 if (request_locality(chip, 0) != 0) {
641 rc = -ENODEV;
642 goto out_err;
643 }
644
4d5f2051
JS
645 rc = tpm2_probe(chip);
646 if (rc)
647 goto out_err;
aec04cbd 648
27084efe 649 vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
3e3a5e90 650 chip->vendor.manufacturer_id = vendor;
27084efe 651
aec04cbd
JS
652 dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
653 (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
27084efe
LD
654 vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
655
9519de3f 656 if (!itpm) {
968de8e2
SB
657 probe = probe_itpm(chip);
658 if (probe < 0) {
9519de3f
SB
659 rc = -ENODEV;
660 goto out_err;
661 }
73249695 662 itpm = !!probe;
9519de3f
SB
663 }
664
3507d612
RA
665 if (itpm)
666 dev_info(dev, "Intel iTPM workaround enabled\n");
667
668
27084efe
LD
669 /* Figure out the capabilities */
670 intfcaps =
671 ioread32(chip->vendor.iobase +
672 TPM_INTF_CAPS(chip->vendor.locality));
9e323d3e 673 dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
27084efe
LD
674 intfcaps);
675 if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
9e323d3e 676 dev_dbg(dev, "\tBurst Count Static\n");
27084efe 677 if (intfcaps & TPM_INTF_CMD_READY_INT)
9e323d3e 678 dev_dbg(dev, "\tCommand Ready Int Support\n");
27084efe 679 if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
9e323d3e 680 dev_dbg(dev, "\tInterrupt Edge Falling\n");
27084efe 681 if (intfcaps & TPM_INTF_INT_EDGE_RISING)
9e323d3e 682 dev_dbg(dev, "\tInterrupt Edge Rising\n");
27084efe 683 if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
9e323d3e 684 dev_dbg(dev, "\tInterrupt Level Low\n");
27084efe 685 if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
9e323d3e 686 dev_dbg(dev, "\tInterrupt Level High\n");
27084efe 687 if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
9e323d3e 688 dev_dbg(dev, "\tLocality Change Int Support\n");
27084efe 689 if (intfcaps & TPM_INTF_STS_VALID_INT)
9e323d3e 690 dev_dbg(dev, "\tSts Valid Int Support\n");
27084efe 691 if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
9e323d3e 692 dev_dbg(dev, "\tData Avail Int Support\n");
27084efe 693
27084efe
LD
694 /* INTERRUPT Setup */
695 init_waitqueue_head(&chip->vendor.read_queue);
696 init_waitqueue_head(&chip->vendor.int_queue);
697
698 intmask =
699 ioread32(chip->vendor.iobase +
700 TPM_INT_ENABLE(chip->vendor.locality));
701
702 intmask |= TPM_INTF_CMD_READY_INT
703 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
704 | TPM_INTF_STS_VALID_INT;
705
706 iowrite32(intmask,
707 chip->vendor.iobase +
708 TPM_INT_ENABLE(chip->vendor.locality));
7917ff9a
BH
709 if (interrupts)
710 chip->vendor.irq = irq;
711 if (interrupts && !chip->vendor.irq) {
a7b66822 712 irq_s =
57135568
KJH
713 ioread8(chip->vendor.iobase +
714 TPM_INT_VECTOR(chip->vendor.locality));
a7b66822
SB
715 if (irq_s) {
716 irq_e = irq_s;
717 } else {
718 irq_s = 3;
719 irq_e = 15;
720 }
57135568 721
a7b66822 722 for (i = irq_s; i <= irq_e && chip->vendor.irq == 0; i++) {
57135568 723 iowrite8(i, chip->vendor.iobase +
a7b66822 724 TPM_INT_VECTOR(chip->vendor.locality));
afb5abc2
JS
725 if (devm_request_irq
726 (dev, i, tis_int_probe, IRQF_SHARED,
313d21ee 727 chip->devname, chip) != 0) {
71ed848f 728 dev_info(chip->pdev,
57135568
KJH
729 "Unable to request irq: %d for probe\n",
730 i);
731 continue;
732 }
27084efe 733
57135568
KJH
734 /* Clear all existing */
735 iowrite32(ioread32
736 (chip->vendor.iobase +
737 TPM_INT_STATUS(chip->vendor.locality)),
738 chip->vendor.iobase +
739 TPM_INT_STATUS(chip->vendor.locality));
740
741 /* Turn on */
742 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
743 chip->vendor.iobase +
744 TPM_INT_ENABLE(chip->vendor.locality));
745
a7b66822
SB
746 chip->vendor.probed_irq = 0;
747
57135568 748 /* Generate Interrupts */
aec04cbd 749 if (chip->flags & TPM_CHIP_FLAG_TPM2)
4d5f2051 750 tpm2_gen_interrupt(chip);
aec04cbd
JS
751 else
752 tpm_gen_interrupt(chip);
57135568 753
a7b66822
SB
754 chip->vendor.irq = chip->vendor.probed_irq;
755
756 /* free_irq will call into tis_int_probe;
757 clear all irqs we haven't seen while doing
758 tpm_gen_interrupt */
759 iowrite32(ioread32
760 (chip->vendor.iobase +
761 TPM_INT_STATUS(chip->vendor.locality)),
762 chip->vendor.iobase +
763 TPM_INT_STATUS(chip->vendor.locality));
764
57135568
KJH
765 /* Turn off */
766 iowrite32(intmask,
767 chip->vendor.iobase +
768 TPM_INT_ENABLE(chip->vendor.locality));
27084efe 769 }
27084efe
LD
770 }
771 if (chip->vendor.irq) {
772 iowrite8(chip->vendor.irq,
773 chip->vendor.iobase +
774 TPM_INT_VECTOR(chip->vendor.locality));
afb5abc2
JS
775 if (devm_request_irq
776 (dev, chip->vendor.irq, tis_int_handler, IRQF_SHARED,
313d21ee 777 chip->devname, chip) != 0) {
71ed848f 778 dev_info(chip->pdev,
57135568
KJH
779 "Unable to request irq: %d for use\n",
780 chip->vendor.irq);
27084efe
LD
781 chip->vendor.irq = 0;
782 } else {
783 /* Clear all existing */
784 iowrite32(ioread32
785 (chip->vendor.iobase +
786 TPM_INT_STATUS(chip->vendor.locality)),
787 chip->vendor.iobase +
788 TPM_INT_STATUS(chip->vendor.locality));
789
790 /* Turn on */
791 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
792 chip->vendor.iobase +
793 TPM_INT_ENABLE(chip->vendor.locality));
794 }
795 }
796
aec04cbd
JS
797 if (chip->flags & TPM_CHIP_FLAG_TPM2) {
798 chip->vendor.timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
799 chip->vendor.timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
800 chip->vendor.timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
801 chip->vendor.timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
802 chip->vendor.duration[TPM_SHORT] =
803 msecs_to_jiffies(TPM2_DURATION_SHORT);
804 chip->vendor.duration[TPM_MEDIUM] =
805 msecs_to_jiffies(TPM2_DURATION_MEDIUM);
806 chip->vendor.duration[TPM_LONG] =
807 msecs_to_jiffies(TPM2_DURATION_LONG);
808
809 rc = tpm2_do_selftest(chip);
810 if (rc == TPM2_RC_INITIALIZE) {
811 dev_warn(dev, "Firmware has not started TPM\n");
812 rc = tpm2_startup(chip, TPM2_SU_CLEAR);
813 if (!rc)
814 rc = tpm2_do_selftest(chip);
815 }
448e9c55 816
aec04cbd
JS
817 if (rc) {
818 dev_err(dev, "TPM self test failed\n");
819 if (rc > 0)
820 rc = -ENODEV;
821 goto out_err;
822 }
823 } else {
824 if (tpm_get_timeouts(chip)) {
825 dev_err(dev, "Could not get TPM timeouts and durations\n");
826 rc = -ENODEV;
827 goto out_err;
828 }
829
830 if (tpm_do_selftest(chip)) {
831 dev_err(dev, "TPM self test failed\n");
832 rc = -ENODEV;
833 goto out_err;
834 }
448e9c55
SD
835 }
836
afb5abc2 837 return tpm_chip_register(chip);
27084efe 838out_err:
afb5abc2 839 tpm_tis_remove(chip);
27084efe
LD
840 return rc;
841}
96854310 842
19b94d2d 843#ifdef CONFIG_PM_SLEEP
96854310
SB
844static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
845{
846 u32 intmask;
847
848 /* reenable interrupts that device may have lost or
849 BIOS/firmware may have disabled */
850 iowrite8(chip->vendor.irq, chip->vendor.iobase +
851 TPM_INT_VECTOR(chip->vendor.locality));
852
853 intmask =
854 ioread32(chip->vendor.iobase +
855 TPM_INT_ENABLE(chip->vendor.locality));
856
857 intmask |= TPM_INTF_CMD_READY_INT
858 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
859 | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
860
861 iowrite32(intmask,
862 chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
863}
96854310 864
a2fa3fb0
SK
865static int tpm_tis_resume(struct device *dev)
866{
867 struct tpm_chip *chip = dev_get_drvdata(dev);
74d6b3ce 868 int ret;
a2fa3fb0
SK
869
870 if (chip->vendor.irq)
871 tpm_tis_reenable_interrupts(chip);
872
74d6b3ce
JS
873 ret = tpm_pm_resume(dev);
874 if (ret)
875 return ret;
aec04cbd 876
74d6b3ce
JS
877 /* TPM 1.2 requires self-test on resume. This function actually returns
878 * an error code but for unknown reason it isn't handled.
879 */
880 if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
881 tpm_do_selftest(chip);
a2fa3fb0 882
74d6b3ce 883 return 0;
a2fa3fb0
SK
884}
885#endif
886
887static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
888
7f2ab000 889#ifdef CONFIG_PNP
afc6d369 890static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
9e323d3e
KJH
891 const struct pnp_device_id *pnp_id)
892{
c3c36aa9 893 resource_size_t start, len;
7917ff9a 894 unsigned int irq = 0;
0dc55365 895 acpi_handle acpi_dev_handle = NULL;
7917ff9a 896
9e323d3e
KJH
897 start = pnp_mem_start(pnp_dev, 0);
898 len = pnp_mem_len(pnp_dev, 0);
899
7917ff9a
BH
900 if (pnp_irq_valid(pnp_dev, 0))
901 irq = pnp_irq(pnp_dev, 0);
902 else
73249695 903 interrupts = false;
7917ff9a 904
e5cce6c1 905 if (is_itpm(pnp_dev))
73249695 906 itpm = true;
e5cce6c1 907
961be7ef 908#ifdef CONFIG_ACPI
0dc55365
JS
909 if (pnp_acpi_device(pnp_dev))
910 acpi_dev_handle = pnp_acpi_device(pnp_dev)->handle;
961be7ef 911#endif
0dc55365
JS
912
913 return tpm_tis_init(&pnp_dev->dev, acpi_dev_handle, start, len, irq);
9e323d3e
KJH
914}
915
0bbed20e 916static struct pnp_device_id tpm_pnp_tbl[] = {
27084efe 917 {"PNP0C31", 0}, /* TPM */
93e1b7d4
KJH
918 {"ATM1200", 0}, /* Atmel */
919 {"IFX0102", 0}, /* Infineon */
920 {"BCM0101", 0}, /* Broadcom */
061991ec 921 {"BCM0102", 0}, /* Broadcom */
93e1b7d4 922 {"NSC1200", 0}, /* National */
fb0e7e11 923 {"ICO0102", 0}, /* Intel */
93e1b7d4
KJH
924 /* Add new here */
925 {"", 0}, /* User Specified */
926 {"", 0} /* Terminator */
27084efe 927};
31bde71c 928MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
27084efe 929
39af33fc 930static void tpm_tis_pnp_remove(struct pnp_dev *dev)
253115b7
RA
931{
932 struct tpm_chip *chip = pnp_get_drvdata(dev);
afb5abc2
JS
933 tpm_chip_unregister(chip);
934 tpm_tis_remove(chip);
253115b7
RA
935}
936
27084efe
LD
937static struct pnp_driver tis_pnp_driver = {
938 .name = "tpm_tis",
939 .id_table = tpm_pnp_tbl,
940 .probe = tpm_tis_pnp_init,
253115b7 941 .remove = tpm_tis_pnp_remove,
a2fa3fb0
SK
942 .driver = {
943 .pm = &tpm_tis_pm,
944 },
27084efe
LD
945};
946
93e1b7d4
KJH
947#define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2
948module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id,
949 sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444);
950MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe");
7f2ab000 951#endif
7a192ec3 952
7a192ec3
ML
953static struct platform_driver tis_drv = {
954 .driver = {
afb5abc2 955 .name = "tpm_tis",
b633f050 956 .pm = &tpm_tis_pm,
7a192ec3 957 },
9e323d3e
KJH
958};
959
960static struct platform_device *pdev;
961
90ab5ee9 962static bool force;
9e323d3e
KJH
963module_param(force, bool, 0444);
964MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry");
27084efe
LD
965static int __init init_tis(void)
966{
9e323d3e 967 int rc;
7f2ab000
RA
968#ifdef CONFIG_PNP
969 if (!force)
970 return pnp_register_driver(&tis_pnp_driver);
971#endif
9e323d3e 972
7f2ab000
RA
973 rc = platform_driver_register(&tis_drv);
974 if (rc < 0)
9e323d3e 975 return rc;
4fba3c3b
WY
976 pdev = platform_device_register_simple("tpm_tis", -1, NULL, 0);
977 if (IS_ERR(pdev)) {
978 rc = PTR_ERR(pdev);
979 goto err_dev;
9e323d3e 980 }
0dc55365 981 rc = tpm_tis_init(&pdev->dev, NULL, TIS_MEM_BASE, TIS_MEM_LEN, 0);
4fba3c3b
WY
982 if (rc)
983 goto err_init;
984 return 0;
985err_init:
986 platform_device_unregister(pdev);
987err_dev:
988 platform_driver_unregister(&tis_drv);
7f2ab000 989 return rc;
27084efe
LD
990}
991
992static void __exit cleanup_tis(void)
993{
27084efe 994 struct tpm_chip *chip;
7f2ab000
RA
995#ifdef CONFIG_PNP
996 if (!force) {
9e323d3e 997 pnp_unregister_driver(&tis_pnp_driver);
7f2ab000
RA
998 return;
999 }
1000#endif
afb5abc2
JS
1001 chip = dev_get_drvdata(&pdev->dev);
1002 tpm_chip_unregister(chip);
1003 tpm_tis_remove(chip);
7f2ab000
RA
1004 platform_device_unregister(pdev);
1005 platform_driver_unregister(&tis_drv);
27084efe
LD
1006}
1007
1008module_init(init_tis);
1009module_exit(cleanup_tis);
1010MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
1011MODULE_DESCRIPTION("TPM Driver");
1012MODULE_VERSION("2.0");
1013MODULE_LICENSE("GPL");