[linux-2.6-block.git] / drivers / char / tpm / tpm_crb.c

/*
 * Copyright (C) 2014 Intel Corporation
 *
 * Authors:
 * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
 *
 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
 *
 * This device driver implements the TPM interface as defined in
 * the TCG CRB 2.0 TPM specification.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2
 * of the License.
 */

#include <linux/acpi.h>
#include <linux/highmem.h>
#include <linux/rculist.h>
#include <linux/module.h>
#include "tpm.h"

#define ACPI_SIG_TPM2 "TPM2"

static const u8 CRB_ACPI_START_UUID[] = {
	/* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
	/* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
};

enum crb_defaults {
	CRB_ACPI_START_REVISION_ID = 1,
	CRB_ACPI_START_INDEX = 1,
};

enum crb_ctrl_req {
	CRB_CTRL_REQ_CMD_READY	= BIT(0),
	CRB_CTRL_REQ_GO_IDLE	= BIT(1),
};

enum crb_ctrl_sts {
	CRB_CTRL_STS_ERROR	= BIT(0),
	CRB_CTRL_STS_TPM_IDLE	= BIT(1),
};

enum crb_start {
	CRB_START_INVOKE	= BIT(0),
};

enum crb_cancel {
	CRB_CANCEL_INVOKE	= BIT(0),
};

struct crb_control_area {
	u32 req;
	u32 sts;
	u32 cancel;
	u32 start;
	u32 int_enable;
	u32 int_sts;
	u32 cmd_size;
	u32 cmd_pa_low;
	u32 cmd_pa_high;
	u32 rsp_size;
	u64 rsp_pa;
} __packed;

enum crb_status {
	CRB_DRV_STS_COMPLETE	= BIT(0),
};

enum crb_flags {
	CRB_FL_ACPI_START	= BIT(0),
	CRB_FL_CRB_START	= BIT(1),
};

struct crb_priv {
	unsigned int flags;
	void __iomem *iobase;
	struct crb_control_area __iomem *cca;
	u8 __iomem *cmd;
	u8 __iomem *rsp;
	u32 cmd_size;
};

static SIMPLE_DEV_PM_OPS(crb_pm, tpm_pm_suspend, tpm_pm_resume);

static u8 crb_status(struct tpm_chip *chip)
{
	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
	u8 sts = 0;

	if ((ioread32(&priv->cca->start) & CRB_START_INVOKE) !=
	    CRB_START_INVOKE)
		sts |= CRB_DRV_STS_COMPLETE;

	return sts;
}

static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
{
	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
	unsigned int expected;

	/* sanity check */
	if (count < 6)
		return -EIO;

	if (ioread32(&priv->cca->sts) & CRB_CTRL_STS_ERROR)
		return -EIO;

	memcpy_fromio(buf, priv->rsp, 6);
	expected = be32_to_cpup((__be32 *) &buf[2]);

	if (expected > count)
		return -EIO;

	memcpy_fromio(&buf[6], &priv->rsp[6], expected - 6);

	return expected;
}

static int crb_do_acpi_start(struct tpm_chip *chip)
{
	union acpi_object *obj;
	int rc;

	obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
				CRB_ACPI_START_UUID,
				CRB_ACPI_START_REVISION_ID,
				CRB_ACPI_START_INDEX,
				NULL);
	if (!obj)
		return -ENXIO;
	rc = obj->integer.value == 0 ? 0 : -ENXIO;
	ACPI_FREE(obj);
	return rc;
}

static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
{
	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
	int rc = 0;

	/* Zero the cancel register so that the next command will not get
	 * canceled.
	 */
	iowrite32(0, &priv->cca->cancel);

	if (len > priv->cmd_size) {
		dev_err(&chip->dev, "invalid command count value %zd %d\n",
			len, priv->cmd_size);
		return -E2BIG;
	}

	memcpy_toio(priv->cmd, buf, len);

	/* Make sure that cmd is populated before issuing start. */
	wmb();

	if (priv->flags & CRB_FL_CRB_START)
		iowrite32(CRB_START_INVOKE, &priv->cca->start);

	if (priv->flags & CRB_FL_ACPI_START)
		rc = crb_do_acpi_start(chip);

	return rc;
}

static void crb_cancel(struct tpm_chip *chip)
{
	struct crb_priv *priv = dev_get_drvdata(&chip->dev);

	iowrite32(CRB_CANCEL_INVOKE, &priv->cca->cancel);

	if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
		dev_err(&chip->dev, "ACPI Start failed\n");
}

static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
{
	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
	u32 cancel = ioread32(&priv->cca->cancel);

	return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
}

static const struct tpm_class_ops tpm_crb = {
	.flags = TPM_OPS_AUTO_STARTUP,
	.status = crb_status,
	.recv = crb_recv,
	.send = crb_send,
	.cancel = crb_cancel,
	.req_canceled = crb_req_canceled,
	.req_complete_mask = CRB_DRV_STS_COMPLETE,
	.req_complete_val = CRB_DRV_STS_COMPLETE,
};

static int crb_init(struct acpi_device *device, struct crb_priv *priv)
{
	struct tpm_chip *chip;

	chip = tpmm_chip_alloc(&device->dev, &tpm_crb);
	if (IS_ERR(chip))
		return PTR_ERR(chip);

	dev_set_drvdata(&chip->dev, priv);
	chip->acpi_dev_handle = device->handle;
	chip->flags = TPM_CHIP_FLAG_TPM2;

	return tpm_chip_register(chip);
}

static int crb_check_resource(struct acpi_resource *ares, void *data)
{
	struct resource *io_res = data;
	struct resource res;

	if (acpi_dev_resource_memory(ares, &res)) {
		*io_res = res;
		io_res->name = NULL;
	}

	return 1;
}

static void __iomem *crb_map_res(struct device *dev, struct crb_priv *priv,
				 struct resource *io_res, u64 start, u32 size)
{
	struct resource new_res = {
		.start	= start,
		.end	= start + size - 1,
		.flags	= IORESOURCE_MEM,
	};

	/* Detect a 64 bit address on a 32 bit system */
	if (start != new_res.start)
		return (void __iomem *) ERR_PTR(-EINVAL);

	if (!resource_contains(io_res, &new_res))
		return devm_ioremap_resource(dev, &new_res);

	return priv->iobase + (new_res.start - io_res->start);
}

static int crb_map_io(struct acpi_device *device, struct crb_priv *priv,
		      struct acpi_table_tpm2 *buf)
{
	struct list_head resources;
	struct resource io_res;
	struct device *dev = &device->dev;
	u64 cmd_pa;
	u32 cmd_size;
	u64 rsp_pa;
	u32 rsp_size;
	int ret;

	INIT_LIST_HEAD(&resources);
	ret = acpi_dev_get_resources(device, &resources, crb_check_resource,
				     &io_res);
	if (ret < 0)
		return ret;
	acpi_dev_free_resource_list(&resources);

	if (resource_type(&io_res) != IORESOURCE_MEM) {
		dev_err(dev, FW_BUG "TPM2 ACPI table does not define a memory resource\n");
		return -EINVAL;
	}

	priv->iobase = devm_ioremap_resource(dev, &io_res);
	if (IS_ERR(priv->iobase))
		return PTR_ERR(priv->iobase);

	priv->cca = crb_map_res(dev, priv, &io_res, buf->control_address,
				sizeof(struct crb_control_area));
	if (IS_ERR(priv->cca))
		return PTR_ERR(priv->cca);

	cmd_pa = ((u64) ioread32(&priv->cca->cmd_pa_high) << 32) |
		  (u64) ioread32(&priv->cca->cmd_pa_low);
	cmd_size = ioread32(&priv->cca->cmd_size);
	priv->cmd = crb_map_res(dev, priv, &io_res, cmd_pa, cmd_size);
	if (IS_ERR(priv->cmd))
		return PTR_ERR(priv->cmd);

	memcpy_fromio(&rsp_pa, &priv->cca->rsp_pa, 8);
	rsp_pa = le64_to_cpu(rsp_pa);
	rsp_size = ioread32(&priv->cca->rsp_size);

	if (cmd_pa != rsp_pa) {
		priv->rsp = crb_map_res(dev, priv, &io_res, rsp_pa, rsp_size);
		return PTR_ERR_OR_ZERO(priv->rsp);
	}

	/* According to the PTP specification, overlapping command and response
	 * buffer sizes must be identical.
	 */
	if (cmd_size != rsp_size) {
		dev_err(dev, FW_BUG "overlapping command and response buffer sizes are not identical");
		return -EINVAL;
	}
	priv->cmd_size = cmd_size;

	priv->rsp = priv->cmd;
	return 0;
}

static int crb_acpi_add(struct acpi_device *device)
{
	struct acpi_table_tpm2 *buf;
	struct crb_priv *priv;
	struct device *dev = &device->dev;
	acpi_status status;
	u32 sm;
	int rc;

	status = acpi_get_table(ACPI_SIG_TPM2, 1,
				(struct acpi_table_header **) &buf);
	if (ACPI_FAILURE(status) || buf->header.length < sizeof(*buf)) {
		dev_err(dev, FW_BUG "failed to get TPM2 ACPI table\n");
		return -EINVAL;
	}

	/* Should the FIFO driver handle this? */
	sm = buf->start_method;
	if (sm == ACPI_TPM2_MEMORY_MAPPED)
		return -ENODEV;

	priv = devm_kzalloc(dev, sizeof(struct crb_priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	/* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
	 * report only ACPI start but in practice seems to require both
	 * ACPI start and CRB start.
	 */
	if (sm == ACPI_TPM2_COMMAND_BUFFER || sm == ACPI_TPM2_MEMORY_MAPPED ||
	    !strcmp(acpi_device_hid(device), "MSFT0101"))
		priv->flags |= CRB_FL_CRB_START;

	if (sm == ACPI_TPM2_START_METHOD ||
	    sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD)
		priv->flags |= CRB_FL_ACPI_START;

	rc = crb_map_io(device, priv, buf);
	if (rc)
		return rc;

	return crb_init(device, priv);
}

static int crb_acpi_remove(struct acpi_device *device)
{
	struct device *dev = &device->dev;
	struct tpm_chip *chip = dev_get_drvdata(dev);

	tpm_chip_unregister(chip);

	return 0;
}

static struct acpi_device_id crb_device_ids[] = {
	{"MSFT0101", 0},
	{"", 0},
};
MODULE_DEVICE_TABLE(acpi, crb_device_ids);

static struct acpi_driver crb_acpi_driver = {
	.name = "tpm_crb",
	.ids = crb_device_ids,
	.ops = {
		.add = crb_acpi_add,
		.remove = crb_acpi_remove,
	},
	.drv = {
		.pm = &crb_pm,
	},
};

module_acpi_driver(crb_acpi_driver);
MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
MODULE_DESCRIPTION("TPM2 Driver");
MODULE_VERSION("0.1");
MODULE_LICENSE("GPL");
Commit	Line	Data
30fc8d13 JS	1	/*
	2	* Copyright (C) 2014 Intel Corporation
	3	*
	4	* Authors:
	5	* Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
	6	*
	7	* Maintained by: <tpmdd-devel@lists.sourceforge.net>
	8	*
	9	* This device driver implements the TPM interface as defined in
	10	* the TCG CRB 2.0 TPM specification.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License
	14	* as published by the Free Software Foundation; version 2
	15	* of the License.
	16	*/
	17
	18	#include <linux/acpi.h>
	19	#include <linux/highmem.h>
	20	#include <linux/rculist.h>
	21	#include <linux/module.h>
30fc8d13 JS	22	#include "tpm.h"
	23
	24	#define ACPI_SIG_TPM2 "TPM2"
	25
	26	static const u8 CRB_ACPI_START_UUID[] = {
	27	/* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
	28	/* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
	29	};
	30
	31	enum crb_defaults {
	32	CRB_ACPI_START_REVISION_ID = 1,
	33	CRB_ACPI_START_INDEX = 1,
	34	};
	35
7fd10d61	36	enum crb_ctrl_req {
f39a9e97 JS	37	CRB_CTRL_REQ_CMD_READY = BIT(0),
f39a9e97 JS	38	CRB_CTRL_REQ_GO_IDLE = BIT(1),
30fc8d13 JS	39	};
30fc8d13 JS	40
7fd10d61 JS	41	enum crb_ctrl_sts {
	42	CRB_CTRL_STS_ERROR = BIT(0),
	43	CRB_CTRL_STS_TPM_IDLE = BIT(1),
30fc8d13 JS	44	};
	45
	46	enum crb_start {
	47	CRB_START_INVOKE = BIT(0),
	48	};
	49
	50	enum crb_cancel {
	51	CRB_CANCEL_INVOKE = BIT(0),
	52	};
	53
	54	struct crb_control_area {
	55	u32 req;
	56	u32 sts;
	57	u32 cancel;
	58	u32 start;
	59	u32 int_enable;
	60	u32 int_sts;
	61	u32 cmd_size;
149789ce JS	62	u32 cmd_pa_low;
149789ce JS	63	u32 cmd_pa_high;
30fc8d13 JS	64	u32 rsp_size;
	65	u64 rsp_pa;
	66	} __packed;
	67
	68	enum crb_status {
7fd10d61	69	CRB_DRV_STS_COMPLETE = BIT(0),
30fc8d13 JS	70	};
	71
	72	enum crb_flags {
	73	CRB_FL_ACPI_START = BIT(0),
	74	CRB_FL_CRB_START = BIT(1),
	75	};
	76
	77	struct crb_priv {
	78	unsigned int flags;
1bd047be	79	void __iomem *iobase;
30fc8d13 JS	80	struct crb_control_area __iomem *cca;
	81	u8 __iomem *cmd;
	82	u8 __iomem *rsp;
aa77ea0e	83	u32 cmd_size;
30fc8d13 JS	84	};
30fc8d13 JS	85
4886cd80 JS	86	static SIMPLE_DEV_PM_OPS(crb_pm, tpm_pm_suspend, tpm_pm_resume);
4886cd80 JS	87
30fc8d13 JS	88	static u8 crb_status(struct tpm_chip *chip)
30fc8d13 JS	89	{
9e0d39d8	90	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
30fc8d13 JS	91	u8 sts = 0;
30fc8d13 JS	92
1e3ed59d	93	if ((ioread32(&priv->cca->start) & CRB_START_INVOKE) !=
30fc8d13	94	CRB_START_INVOKE)
7fd10d61	95	sts \|= CRB_DRV_STS_COMPLETE;
30fc8d13 JS	96
	97	return sts;
	98	}
	99
	100	static int crb_recv(struct tpm_chip chip, u8 buf, size_t count)
	101	{
9e0d39d8	102	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
30fc8d13 JS	103	unsigned int expected;
	104
	105	/* sanity check */
	106	if (count < 6)
	107	return -EIO;
	108
7fd10d61	109	if (ioread32(&priv->cca->sts) & CRB_CTRL_STS_ERROR)
30fc8d13 JS	110	return -EIO;
	111
	112	memcpy_fromio(buf, priv->rsp, 6);
	113	expected = be32_to_cpup((__be32 *) &buf[2]);
	114
	115	if (expected > count)
	116	return -EIO;
	117
	118	memcpy_fromio(&buf[6], &priv->rsp[6], expected - 6);
	119
	120	return expected;
	121	}
	122
	123	static int crb_do_acpi_start(struct tpm_chip *chip)
	124	{
	125	union acpi_object *obj;
	126	int rc;
	127
	128	obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
	129	CRB_ACPI_START_UUID,
	130	CRB_ACPI_START_REVISION_ID,
	131	CRB_ACPI_START_INDEX,
	132	NULL);
	133	if (!obj)
	134	return -ENXIO;
	135	rc = obj->integer.value == 0 ? 0 : -ENXIO;
	136	ACPI_FREE(obj);
	137	return rc;
	138	}
	139
	140	static int crb_send(struct tpm_chip chip, u8 buf, size_t len)
	141	{
9e0d39d8	142	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
30fc8d13 JS	143	int rc = 0;
30fc8d13 JS	144
72fd50e1 JS	145	/* Zero the cancel register so that the next command will not get
	146	* canceled.
	147	*/
	148	iowrite32(0, &priv->cca->cancel);
	149
aa77ea0e TW	150	if (len > priv->cmd_size) {
	151	dev_err(&chip->dev, "invalid command count value %zd %d\n",
	152	len, priv->cmd_size);
30fc8d13 JS	153	return -E2BIG;
	154	}
	155
	156	memcpy_toio(priv->cmd, buf, len);
	157
	158	/* Make sure that cmd is populated before issuing start. */
	159	wmb();
	160
	161	if (priv->flags & CRB_FL_CRB_START)
47de683a	162	iowrite32(CRB_START_INVOKE, &priv->cca->start);
30fc8d13 JS	163
	164	if (priv->flags & CRB_FL_ACPI_START)
	165	rc = crb_do_acpi_start(chip);
	166
	167	return rc;
	168	}
	169
	170	static void crb_cancel(struct tpm_chip *chip)
	171	{
9e0d39d8	172	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
30fc8d13	173
47de683a	174	iowrite32(CRB_CANCEL_INVOKE, &priv->cca->cancel);
30fc8d13	175
30fc8d13 JS	176	if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
30fc8d13 JS	177	dev_err(&chip->dev, "ACPI Start failed\n");
30fc8d13 JS	178	}
	179
	180	static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
	181	{
9e0d39d8	182	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
1e3ed59d	183	u32 cancel = ioread32(&priv->cca->cancel);
30fc8d13 JS	184
	185	return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
	186	}
	187
	188	static const struct tpm_class_ops tpm_crb = {
cae8b441	189	.flags = TPM_OPS_AUTO_STARTUP,
30fc8d13 JS	190	.status = crb_status,
	191	.recv = crb_recv,
	192	.send = crb_send,
	193	.cancel = crb_cancel,
	194	.req_canceled = crb_req_canceled,
7fd10d61 JS	195	.req_complete_mask = CRB_DRV_STS_COMPLETE,
7fd10d61 JS	196	.req_complete_val = CRB_DRV_STS_COMPLETE,
30fc8d13 JS	197	};
30fc8d13 JS	198
2b7926ae JS	199	static int crb_init(struct acpi_device device, struct crb_priv priv)
	200	{
	201	struct tpm_chip *chip;
	202
	203	chip = tpmm_chip_alloc(&device->dev, &tpm_crb);
	204	if (IS_ERR(chip))
	205	return PTR_ERR(chip);
	206
	207	dev_set_drvdata(&chip->dev, priv);
	208	chip->acpi_dev_handle = device->handle;
	209	chip->flags = TPM_CHIP_FLAG_TPM2;
	210
	211	return tpm_chip_register(chip);
	212	}
	213
1bd047be JG	214	static int crb_check_resource(struct acpi_resource ares, void data)
1bd047be JG	215	{
14ddfbf4	216	struct resource *io_res = data;
1bd047be JG	217	struct resource res;
1bd047be JG	218
30f9c8c9	219	if (acpi_dev_resource_memory(ares, &res)) {
14ddfbf4 JS	220	*io_res = res;
14ddfbf4 JS	221	io_res->name = NULL;
30f9c8c9	222	}
1bd047be JG	223
	224	return 1;
	225	}
	226
	227	static void __iomem crb_map_res(struct device dev, struct crb_priv *priv,
14ddfbf4	228	struct resource *io_res, u64 start, u32 size)
1bd047be JG	229	{
	230	struct resource new_res = {
	231	.start = start,
	232	.end = start + size - 1,
	233	.flags = IORESOURCE_MEM,
	234	};
	235
	236	/* Detect a 64 bit address on a 32 bit system */
	237	if (start != new_res.start)
f786b752	238	return (void __iomem *) ERR_PTR(-EINVAL);
1bd047be	239
14ddfbf4	240	if (!resource_contains(io_res, &new_res))
1bd047be JG	241	return devm_ioremap_resource(dev, &new_res);
1bd047be JG	242
14ddfbf4	243	return priv->iobase + (new_res.start - io_res->start);
1bd047be JG	244	}
	245
	246	static int crb_map_io(struct acpi_device device, struct crb_priv priv,
	247	struct acpi_table_tpm2 *buf)
	248	{
	249	struct list_head resources;
14ddfbf4	250	struct resource io_res;
1bd047be	251	struct device *dev = &device->dev;
422eac3f JS	252	u64 cmd_pa;
	253	u32 cmd_size;
	254	u64 rsp_pa;
	255	u32 rsp_size;
1bd047be JG	256	int ret;
	257
	258	INIT_LIST_HEAD(&resources);
	259	ret = acpi_dev_get_resources(device, &resources, crb_check_resource,
14ddfbf4	260	&io_res);
1bd047be JG	261	if (ret < 0)
	262	return ret;
	263	acpi_dev_free_resource_list(&resources);
	264
14ddfbf4	265	if (resource_type(&io_res) != IORESOURCE_MEM) {
64fba530	266	dev_err(dev, FW_BUG "TPM2 ACPI table does not define a memory resource\n");
1bd047be JG	267	return -EINVAL;
	268	}
	269
14ddfbf4	270	priv->iobase = devm_ioremap_resource(dev, &io_res);
1bd047be JG	271	if (IS_ERR(priv->iobase))
	272	return PTR_ERR(priv->iobase);
	273
14ddfbf4	274	priv->cca = crb_map_res(dev, priv, &io_res, buf->control_address,
422eac3f	275	sizeof(struct crb_control_area));
1bd047be JG	276	if (IS_ERR(priv->cca))
	277	return PTR_ERR(priv->cca);
	278
cfa18822 JS	279	cmd_pa = ((u64) ioread32(&priv->cca->cmd_pa_high) << 32) \|
cfa18822 JS	280	(u64) ioread32(&priv->cca->cmd_pa_low);
422eac3f JS	281	cmd_size = ioread32(&priv->cca->cmd_size);
422eac3f JS	282	priv->cmd = crb_map_res(dev, priv, &io_res, cmd_pa, cmd_size);
cfa18822 JS	283	if (IS_ERR(priv->cmd))
cfa18822 JS	284	return PTR_ERR(priv->cmd);
1bd047be	285
422eac3f JS	286	memcpy_fromio(&rsp_pa, &priv->cca->rsp_pa, 8);
	287	rsp_pa = le64_to_cpu(rsp_pa);
	288	rsp_size = ioread32(&priv->cca->rsp_size);
	289
	290	if (cmd_pa != rsp_pa) {
	291	priv->rsp = crb_map_res(dev, priv, &io_res, rsp_pa, rsp_size);
cfa18822	292	return PTR_ERR_OR_ZERO(priv->rsp);
422eac3f JS	293	}
	294
	295	/* According to the PTP specification, overlapping command and response
	296	* buffer sizes must be identical.
	297	*/
	298	if (cmd_size != rsp_size) {
	299	dev_err(dev, FW_BUG "overlapping command and response buffer sizes are not identical");
cfa18822	300	return -EINVAL;
422eac3f	301	}
aa77ea0e	302	priv->cmd_size = cmd_size;
422eac3f JS	303
422eac3f JS	304	priv->rsp = priv->cmd;
cfa18822	305	return 0;
1bd047be JG	306	}
	307
	308	static int crb_acpi_add(struct acpi_device *device)
	309	{
55a889c2	310	struct acpi_table_tpm2 *buf;
30fc8d13 JS	311	struct crb_priv *priv;
	312	struct device *dev = &device->dev;
	313	acpi_status status;
	314	u32 sm;
30fc8d13 JS	315	int rc;
30fc8d13 JS	316
30fc8d13 JS	317	status = acpi_get_table(ACPI_SIG_TPM2, 1,
30fc8d13 JS	318	(struct acpi_table_header **) &buf);
55a889c2 JG	319	if (ACPI_FAILURE(status) \|\| buf->header.length < sizeof(*buf)) {
55a889c2 JG	320	dev_err(dev, FW_BUG "failed to get TPM2 ACPI table\n");
1bd047be	321	return -EINVAL;
30fc8d13 JS	322	}
30fc8d13 JS	323
399235dc	324	/* Should the FIFO driver handle this? */
55a889c2 JG	325	sm = buf->start_method;
55a889c2 JG	326	if (sm == ACPI_TPM2_MEMORY_MAPPED)
399235dc JS	327	return -ENODEV;
399235dc JS	328
1bd047be JG	329	priv = devm_kzalloc(dev, sizeof(struct crb_priv), GFP_KERNEL);
1bd047be JG	330	if (!priv)
30fc8d13	331	return -ENOMEM;
30fc8d13	332
30fc8d13 JS	333	/* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
	334	* report only ACPI start but in practice seems to require both
	335	* ACPI start and CRB start.
	336	*/
55a889c2	337	if (sm == ACPI_TPM2_COMMAND_BUFFER \|\| sm == ACPI_TPM2_MEMORY_MAPPED \|\|
30fc8d13 JS	338	!strcmp(acpi_device_hid(device), "MSFT0101"))
	339	priv->flags \|= CRB_FL_CRB_START;
	340
55a889c2 JG	341	if (sm == ACPI_TPM2_START_METHOD \|\|
55a889c2 JG	342	sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD)
30fc8d13 JS	343	priv->flags \|= CRB_FL_ACPI_START;
30fc8d13 JS	344
1bd047be	345	rc = crb_map_io(device, priv, buf);
25112048 JG	346	if (rc)
25112048 JG	347	return rc;
30fc8d13	348
cfa18822	349	return crb_init(device, priv);
30fc8d13 JS	350	}
	351
	352	static int crb_acpi_remove(struct acpi_device *device)
	353	{
	354	struct device *dev = &device->dev;
	355	struct tpm_chip *chip = dev_get_drvdata(dev);
	356
99cda8cb JS	357	tpm_chip_unregister(chip);
99cda8cb JS	358
30fc8d13 JS	359	return 0;
	360	}
	361
	362	static struct acpi_device_id crb_device_ids[] = {
	363	{"MSFT0101", 0},
	364	{"", 0},
	365	};
	366	MODULE_DEVICE_TABLE(acpi, crb_device_ids);
	367
	368	static struct acpi_driver crb_acpi_driver = {
	369	.name = "tpm_crb",
	370	.ids = crb_device_ids,
	371	.ops = {
	372	.add = crb_acpi_add,
	373	.remove = crb_acpi_remove,
	374	},
	375	.drv = {
	376	.pm = &crb_pm,
	377	},
	378	};
	379
	380	module_acpi_driver(crb_acpi_driver);
	381	MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
	382	MODULE_DESCRIPTION("TPM2 Driver");
	383	MODULE_VERSION("0.1");
	384	MODULE_LICENSE("GPL");