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1da177e4 | 1 | /* |
7f3edb94 | 2 | * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $ |
1da177e4 LT |
3 | * |
4 | * Device driver for Microgate SyncLink Multiport | |
5 | * high speed multiprotocol serial adapter. | |
6 | * | |
7 | * written by Paul Fulghum for Microgate Corporation | |
8 | * paulkf@microgate.com | |
9 | * | |
10 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
11 | * | |
12 | * Derived from serial.c written by Theodore Ts'o and Linus Torvalds | |
13 | * This code is released under the GNU General Public License (GPL) | |
14 | * | |
15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
18 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
19 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
20 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
21 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
22 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
23 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
25 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) | |
29 | #if defined(__i386__) | |
30 | # define BREAKPOINT() asm(" int $3"); | |
31 | #else | |
32 | # define BREAKPOINT() { } | |
33 | #endif | |
34 | ||
35 | #define MAX_DEVICES 12 | |
36 | ||
1da177e4 LT |
37 | #include <linux/module.h> |
38 | #include <linux/errno.h> | |
39 | #include <linux/signal.h> | |
40 | #include <linux/sched.h> | |
41 | #include <linux/timer.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/tty.h> | |
45 | #include <linux/tty_flip.h> | |
46 | #include <linux/serial.h> | |
47 | #include <linux/major.h> | |
48 | #include <linux/string.h> | |
49 | #include <linux/fcntl.h> | |
50 | #include <linux/ptrace.h> | |
51 | #include <linux/ioport.h> | |
52 | #include <linux/mm.h> | |
53 | #include <linux/slab.h> | |
54 | #include <linux/netdevice.h> | |
55 | #include <linux/vmalloc.h> | |
56 | #include <linux/init.h> | |
1da177e4 LT |
57 | #include <linux/delay.h> |
58 | #include <linux/ioctl.h> | |
59 | ||
60 | #include <asm/system.h> | |
61 | #include <asm/io.h> | |
62 | #include <asm/irq.h> | |
63 | #include <asm/dma.h> | |
64 | #include <linux/bitops.h> | |
65 | #include <asm/types.h> | |
66 | #include <linux/termios.h> | |
67 | #include <linux/workqueue.h> | |
68 | #include <linux/hdlc.h> | |
69 | ||
af69c7f9 PF |
70 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) |
71 | #define SYNCLINK_GENERIC_HDLC 1 | |
72 | #else | |
73 | #define SYNCLINK_GENERIC_HDLC 0 | |
1da177e4 LT |
74 | #endif |
75 | ||
76 | #define GET_USER(error,value,addr) error = get_user(value,addr) | |
77 | #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 | |
78 | #define PUT_USER(error,value,addr) error = put_user(value,addr) | |
79 | #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 | |
80 | ||
81 | #include <asm/uaccess.h> | |
82 | ||
83 | #include "linux/synclink.h" | |
84 | ||
85 | static MGSL_PARAMS default_params = { | |
86 | MGSL_MODE_HDLC, /* unsigned long mode */ | |
87 | 0, /* unsigned char loopback; */ | |
88 | HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ | |
89 | HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ | |
90 | 0, /* unsigned long clock_speed; */ | |
91 | 0xff, /* unsigned char addr_filter; */ | |
92 | HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ | |
93 | HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ | |
94 | HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ | |
95 | 9600, /* unsigned long data_rate; */ | |
96 | 8, /* unsigned char data_bits; */ | |
97 | 1, /* unsigned char stop_bits; */ | |
98 | ASYNC_PARITY_NONE /* unsigned char parity; */ | |
99 | }; | |
100 | ||
101 | /* size in bytes of DMA data buffers */ | |
102 | #define SCABUFSIZE 1024 | |
103 | #define SCA_MEM_SIZE 0x40000 | |
104 | #define SCA_BASE_SIZE 512 | |
105 | #define SCA_REG_SIZE 16 | |
106 | #define SCA_MAX_PORTS 4 | |
107 | #define SCAMAXDESC 128 | |
108 | ||
109 | #define BUFFERLISTSIZE 4096 | |
110 | ||
111 | /* SCA-I style DMA buffer descriptor */ | |
112 | typedef struct _SCADESC | |
113 | { | |
114 | u16 next; /* lower l6 bits of next descriptor addr */ | |
115 | u16 buf_ptr; /* lower 16 bits of buffer addr */ | |
116 | u8 buf_base; /* upper 8 bits of buffer addr */ | |
117 | u8 pad1; | |
118 | u16 length; /* length of buffer */ | |
119 | u8 status; /* status of buffer */ | |
120 | u8 pad2; | |
121 | } SCADESC, *PSCADESC; | |
122 | ||
123 | typedef struct _SCADESC_EX | |
124 | { | |
125 | /* device driver bookkeeping section */ | |
126 | char *virt_addr; /* virtual address of data buffer */ | |
127 | u16 phys_entry; /* lower 16-bits of physical address of this descriptor */ | |
128 | } SCADESC_EX, *PSCADESC_EX; | |
129 | ||
130 | /* The queue of BH actions to be performed */ | |
131 | ||
132 | #define BH_RECEIVE 1 | |
133 | #define BH_TRANSMIT 2 | |
134 | #define BH_STATUS 4 | |
135 | ||
136 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
137 | ||
1da177e4 LT |
138 | struct _input_signal_events { |
139 | int ri_up; | |
140 | int ri_down; | |
141 | int dsr_up; | |
142 | int dsr_down; | |
143 | int dcd_up; | |
144 | int dcd_down; | |
145 | int cts_up; | |
146 | int cts_down; | |
147 | }; | |
148 | ||
149 | /* | |
150 | * Device instance data structure | |
151 | */ | |
152 | typedef struct _synclinkmp_info { | |
153 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | |
154 | int magic; | |
155 | int flags; | |
156 | int count; /* count of opens */ | |
157 | int line; | |
158 | unsigned short close_delay; | |
159 | unsigned short closing_wait; /* time to wait before closing */ | |
160 | ||
161 | struct mgsl_icount icount; | |
162 | ||
163 | struct tty_struct *tty; | |
164 | int timeout; | |
165 | int x_char; /* xon/xoff character */ | |
166 | int blocked_open; /* # of blocked opens */ | |
167 | u16 read_status_mask1; /* break detection (SR1 indications) */ | |
168 | u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */ | |
169 | unsigned char ignore_status_mask1; /* break detection (SR1 indications) */ | |
170 | unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */ | |
171 | unsigned char *tx_buf; | |
172 | int tx_put; | |
173 | int tx_get; | |
174 | int tx_count; | |
175 | ||
176 | wait_queue_head_t open_wait; | |
177 | wait_queue_head_t close_wait; | |
178 | ||
179 | wait_queue_head_t status_event_wait_q; | |
180 | wait_queue_head_t event_wait_q; | |
181 | struct timer_list tx_timer; /* HDLC transmit timeout timer */ | |
182 | struct _synclinkmp_info *next_device; /* device list link */ | |
183 | struct timer_list status_timer; /* input signal status check timer */ | |
184 | ||
185 | spinlock_t lock; /* spinlock for synchronizing with ISR */ | |
186 | struct work_struct task; /* task structure for scheduling bh */ | |
187 | ||
188 | u32 max_frame_size; /* as set by device config */ | |
189 | ||
190 | u32 pending_bh; | |
191 | ||
192 | int bh_running; /* Protection from multiple */ | |
193 | int isr_overflow; | |
194 | int bh_requested; | |
195 | ||
196 | int dcd_chkcount; /* check counts to prevent */ | |
197 | int cts_chkcount; /* too many IRQs if a signal */ | |
198 | int dsr_chkcount; /* is floating */ | |
199 | int ri_chkcount; | |
200 | ||
201 | char *buffer_list; /* virtual address of Rx & Tx buffer lists */ | |
202 | unsigned long buffer_list_phys; | |
203 | ||
204 | unsigned int rx_buf_count; /* count of total allocated Rx buffers */ | |
205 | SCADESC *rx_buf_list; /* list of receive buffer entries */ | |
206 | SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */ | |
207 | unsigned int current_rx_buf; | |
208 | ||
209 | unsigned int tx_buf_count; /* count of total allocated Tx buffers */ | |
210 | SCADESC *tx_buf_list; /* list of transmit buffer entries */ | |
211 | SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */ | |
212 | unsigned int last_tx_buf; | |
213 | ||
214 | unsigned char *tmp_rx_buf; | |
215 | unsigned int tmp_rx_buf_count; | |
216 | ||
217 | int rx_enabled; | |
218 | int rx_overflow; | |
219 | ||
220 | int tx_enabled; | |
221 | int tx_active; | |
222 | u32 idle_mode; | |
223 | ||
224 | unsigned char ie0_value; | |
225 | unsigned char ie1_value; | |
226 | unsigned char ie2_value; | |
227 | unsigned char ctrlreg_value; | |
228 | unsigned char old_signals; | |
229 | ||
230 | char device_name[25]; /* device instance name */ | |
231 | ||
232 | int port_count; | |
233 | int adapter_num; | |
234 | int port_num; | |
235 | ||
236 | struct _synclinkmp_info *port_array[SCA_MAX_PORTS]; | |
237 | ||
238 | unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */ | |
239 | ||
240 | unsigned int irq_level; /* interrupt level */ | |
241 | unsigned long irq_flags; | |
242 | int irq_requested; /* nonzero if IRQ requested */ | |
243 | ||
244 | MGSL_PARAMS params; /* communications parameters */ | |
245 | ||
246 | unsigned char serial_signals; /* current serial signal states */ | |
247 | ||
248 | int irq_occurred; /* for diagnostics use */ | |
249 | unsigned int init_error; /* Initialization startup error */ | |
250 | ||
251 | u32 last_mem_alloc; | |
252 | unsigned char* memory_base; /* shared memory address (PCI only) */ | |
253 | u32 phys_memory_base; | |
254 | int shared_mem_requested; | |
255 | ||
256 | unsigned char* sca_base; /* HD64570 SCA Memory address */ | |
257 | u32 phys_sca_base; | |
258 | u32 sca_offset; | |
259 | int sca_base_requested; | |
260 | ||
261 | unsigned char* lcr_base; /* local config registers (PCI only) */ | |
262 | u32 phys_lcr_base; | |
263 | u32 lcr_offset; | |
264 | int lcr_mem_requested; | |
265 | ||
266 | unsigned char* statctrl_base; /* status/control register memory */ | |
267 | u32 phys_statctrl_base; | |
268 | u32 statctrl_offset; | |
269 | int sca_statctrl_requested; | |
270 | ||
271 | u32 misc_ctrl_value; | |
272 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; | |
273 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; | |
274 | BOOLEAN drop_rts_on_tx_done; | |
275 | ||
276 | struct _input_signal_events input_signal_events; | |
277 | ||
278 | /* SPPP/Cisco HDLC device parts */ | |
279 | int netcount; | |
280 | int dosyncppp; | |
281 | spinlock_t netlock; | |
282 | ||
af69c7f9 | 283 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
284 | struct net_device *netdev; |
285 | #endif | |
286 | ||
287 | } SLMP_INFO; | |
288 | ||
289 | #define MGSL_MAGIC 0x5401 | |
290 | ||
291 | /* | |
292 | * define serial signal status change macros | |
293 | */ | |
294 | #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */ | |
295 | #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */ | |
296 | #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */ | |
297 | #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */ | |
298 | ||
299 | /* Common Register macros */ | |
300 | #define LPR 0x00 | |
301 | #define PABR0 0x02 | |
302 | #define PABR1 0x03 | |
303 | #define WCRL 0x04 | |
304 | #define WCRM 0x05 | |
305 | #define WCRH 0x06 | |
306 | #define DPCR 0x08 | |
307 | #define DMER 0x09 | |
308 | #define ISR0 0x10 | |
309 | #define ISR1 0x11 | |
310 | #define ISR2 0x12 | |
311 | #define IER0 0x14 | |
312 | #define IER1 0x15 | |
313 | #define IER2 0x16 | |
314 | #define ITCR 0x18 | |
315 | #define INTVR 0x1a | |
316 | #define IMVR 0x1c | |
317 | ||
318 | /* MSCI Register macros */ | |
319 | #define TRB 0x20 | |
320 | #define TRBL 0x20 | |
321 | #define TRBH 0x21 | |
322 | #define SR0 0x22 | |
323 | #define SR1 0x23 | |
324 | #define SR2 0x24 | |
325 | #define SR3 0x25 | |
326 | #define FST 0x26 | |
327 | #define IE0 0x28 | |
328 | #define IE1 0x29 | |
329 | #define IE2 0x2a | |
330 | #define FIE 0x2b | |
331 | #define CMD 0x2c | |
332 | #define MD0 0x2e | |
333 | #define MD1 0x2f | |
334 | #define MD2 0x30 | |
335 | #define CTL 0x31 | |
336 | #define SA0 0x32 | |
337 | #define SA1 0x33 | |
338 | #define IDL 0x34 | |
339 | #define TMC 0x35 | |
340 | #define RXS 0x36 | |
341 | #define TXS 0x37 | |
342 | #define TRC0 0x38 | |
343 | #define TRC1 0x39 | |
344 | #define RRC 0x3a | |
345 | #define CST0 0x3c | |
346 | #define CST1 0x3d | |
347 | ||
348 | /* Timer Register Macros */ | |
349 | #define TCNT 0x60 | |
350 | #define TCNTL 0x60 | |
351 | #define TCNTH 0x61 | |
352 | #define TCONR 0x62 | |
353 | #define TCONRL 0x62 | |
354 | #define TCONRH 0x63 | |
355 | #define TMCS 0x64 | |
356 | #define TEPR 0x65 | |
357 | ||
358 | /* DMA Controller Register macros */ | |
359 | #define DARL 0x80 | |
360 | #define DARH 0x81 | |
361 | #define DARB 0x82 | |
362 | #define BAR 0x80 | |
363 | #define BARL 0x80 | |
364 | #define BARH 0x81 | |
365 | #define BARB 0x82 | |
366 | #define SAR 0x84 | |
367 | #define SARL 0x84 | |
368 | #define SARH 0x85 | |
369 | #define SARB 0x86 | |
370 | #define CPB 0x86 | |
371 | #define CDA 0x88 | |
372 | #define CDAL 0x88 | |
373 | #define CDAH 0x89 | |
374 | #define EDA 0x8a | |
375 | #define EDAL 0x8a | |
376 | #define EDAH 0x8b | |
377 | #define BFL 0x8c | |
378 | #define BFLL 0x8c | |
379 | #define BFLH 0x8d | |
380 | #define BCR 0x8e | |
381 | #define BCRL 0x8e | |
382 | #define BCRH 0x8f | |
383 | #define DSR 0x90 | |
384 | #define DMR 0x91 | |
385 | #define FCT 0x93 | |
386 | #define DIR 0x94 | |
387 | #define DCMD 0x95 | |
388 | ||
389 | /* combine with timer or DMA register address */ | |
390 | #define TIMER0 0x00 | |
391 | #define TIMER1 0x08 | |
392 | #define TIMER2 0x10 | |
393 | #define TIMER3 0x18 | |
394 | #define RXDMA 0x00 | |
395 | #define TXDMA 0x20 | |
396 | ||
397 | /* SCA Command Codes */ | |
398 | #define NOOP 0x00 | |
399 | #define TXRESET 0x01 | |
400 | #define TXENABLE 0x02 | |
401 | #define TXDISABLE 0x03 | |
402 | #define TXCRCINIT 0x04 | |
403 | #define TXCRCEXCL 0x05 | |
404 | #define TXEOM 0x06 | |
405 | #define TXABORT 0x07 | |
406 | #define MPON 0x08 | |
407 | #define TXBUFCLR 0x09 | |
408 | #define RXRESET 0x11 | |
409 | #define RXENABLE 0x12 | |
410 | #define RXDISABLE 0x13 | |
411 | #define RXCRCINIT 0x14 | |
412 | #define RXREJECT 0x15 | |
413 | #define SEARCHMP 0x16 | |
414 | #define RXCRCEXCL 0x17 | |
415 | #define RXCRCCALC 0x18 | |
416 | #define CHRESET 0x21 | |
417 | #define HUNT 0x31 | |
418 | ||
419 | /* DMA command codes */ | |
420 | #define SWABORT 0x01 | |
421 | #define FEICLEAR 0x02 | |
422 | ||
423 | /* IE0 */ | |
424 | #define TXINTE BIT7 | |
425 | #define RXINTE BIT6 | |
426 | #define TXRDYE BIT1 | |
427 | #define RXRDYE BIT0 | |
428 | ||
429 | /* IE1 & SR1 */ | |
430 | #define UDRN BIT7 | |
431 | #define IDLE BIT6 | |
432 | #define SYNCD BIT4 | |
433 | #define FLGD BIT4 | |
434 | #define CCTS BIT3 | |
435 | #define CDCD BIT2 | |
436 | #define BRKD BIT1 | |
437 | #define ABTD BIT1 | |
438 | #define GAPD BIT1 | |
439 | #define BRKE BIT0 | |
440 | #define IDLD BIT0 | |
441 | ||
442 | /* IE2 & SR2 */ | |
443 | #define EOM BIT7 | |
444 | #define PMP BIT6 | |
445 | #define SHRT BIT6 | |
446 | #define PE BIT5 | |
447 | #define ABT BIT5 | |
448 | #define FRME BIT4 | |
449 | #define RBIT BIT4 | |
450 | #define OVRN BIT3 | |
451 | #define CRCE BIT2 | |
452 | ||
453 | ||
454 | /* | |
455 | * Global linked list of SyncLink devices | |
456 | */ | |
457 | static SLMP_INFO *synclinkmp_device_list = NULL; | |
458 | static int synclinkmp_adapter_count = -1; | |
459 | static int synclinkmp_device_count = 0; | |
460 | ||
461 | /* | |
462 | * Set this param to non-zero to load eax with the | |
463 | * .text section address and breakpoint on module load. | |
464 | * This is useful for use with gdb and add-symbol-file command. | |
465 | */ | |
466 | static int break_on_load=0; | |
467 | ||
468 | /* | |
469 | * Driver major number, defaults to zero to get auto | |
470 | * assigned major number. May be forced as module parameter. | |
471 | */ | |
472 | static int ttymajor=0; | |
473 | ||
474 | /* | |
475 | * Array of user specified options for ISA adapters. | |
476 | */ | |
477 | static int debug_level = 0; | |
478 | static int maxframe[MAX_DEVICES] = {0,}; | |
479 | static int dosyncppp[MAX_DEVICES] = {0,}; | |
480 | ||
481 | module_param(break_on_load, bool, 0); | |
482 | module_param(ttymajor, int, 0); | |
483 | module_param(debug_level, int, 0); | |
484 | module_param_array(maxframe, int, NULL, 0); | |
485 | module_param_array(dosyncppp, int, NULL, 0); | |
486 | ||
487 | static char *driver_name = "SyncLink MultiPort driver"; | |
7f3edb94 | 488 | static char *driver_version = "$Revision: 4.38 $"; |
1da177e4 LT |
489 | |
490 | static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent); | |
491 | static void synclinkmp_remove_one(struct pci_dev *dev); | |
492 | ||
493 | static struct pci_device_id synclinkmp_pci_tbl[] = { | |
494 | { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, }, | |
495 | { 0, }, /* terminate list */ | |
496 | }; | |
497 | MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl); | |
498 | ||
499 | MODULE_LICENSE("GPL"); | |
500 | ||
501 | static struct pci_driver synclinkmp_pci_driver = { | |
502 | .name = "synclinkmp", | |
503 | .id_table = synclinkmp_pci_tbl, | |
504 | .probe = synclinkmp_init_one, | |
505 | .remove = __devexit_p(synclinkmp_remove_one), | |
506 | }; | |
507 | ||
508 | ||
509 | static struct tty_driver *serial_driver; | |
510 | ||
511 | /* number of characters left in xmit buffer before we ask for more */ | |
512 | #define WAKEUP_CHARS 256 | |
513 | ||
514 | ||
515 | /* tty callbacks */ | |
516 | ||
517 | static int open(struct tty_struct *tty, struct file * filp); | |
518 | static void close(struct tty_struct *tty, struct file * filp); | |
519 | static void hangup(struct tty_struct *tty); | |
606d099c | 520 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); |
1da177e4 LT |
521 | |
522 | static int write(struct tty_struct *tty, const unsigned char *buf, int count); | |
523 | static void put_char(struct tty_struct *tty, unsigned char ch); | |
524 | static void send_xchar(struct tty_struct *tty, char ch); | |
525 | static void wait_until_sent(struct tty_struct *tty, int timeout); | |
526 | static int write_room(struct tty_struct *tty); | |
527 | static void flush_chars(struct tty_struct *tty); | |
528 | static void flush_buffer(struct tty_struct *tty); | |
529 | static void tx_hold(struct tty_struct *tty); | |
530 | static void tx_release(struct tty_struct *tty); | |
531 | ||
532 | static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg); | |
533 | static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data); | |
534 | static int chars_in_buffer(struct tty_struct *tty); | |
535 | static void throttle(struct tty_struct * tty); | |
536 | static void unthrottle(struct tty_struct * tty); | |
537 | static void set_break(struct tty_struct *tty, int break_state); | |
538 | ||
af69c7f9 | 539 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
540 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
541 | static void hdlcdev_tx_done(SLMP_INFO *info); | |
542 | static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size); | |
543 | static int hdlcdev_init(SLMP_INFO *info); | |
544 | static void hdlcdev_exit(SLMP_INFO *info); | |
545 | #endif | |
546 | ||
547 | /* ioctl handlers */ | |
548 | ||
549 | static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount); | |
550 | static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params); | |
551 | static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params); | |
552 | static int get_txidle(SLMP_INFO *info, int __user *idle_mode); | |
553 | static int set_txidle(SLMP_INFO *info, int idle_mode); | |
554 | static int tx_enable(SLMP_INFO *info, int enable); | |
555 | static int tx_abort(SLMP_INFO *info); | |
556 | static int rx_enable(SLMP_INFO *info, int enable); | |
1da177e4 LT |
557 | static int modem_input_wait(SLMP_INFO *info,int arg); |
558 | static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr); | |
559 | static int tiocmget(struct tty_struct *tty, struct file *file); | |
560 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
561 | unsigned int set, unsigned int clear); | |
562 | static void set_break(struct tty_struct *tty, int break_state); | |
563 | ||
564 | static void add_device(SLMP_INFO *info); | |
565 | static void device_init(int adapter_num, struct pci_dev *pdev); | |
566 | static int claim_resources(SLMP_INFO *info); | |
567 | static void release_resources(SLMP_INFO *info); | |
568 | ||
569 | static int startup(SLMP_INFO *info); | |
570 | static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info); | |
571 | static void shutdown(SLMP_INFO *info); | |
572 | static void program_hw(SLMP_INFO *info); | |
573 | static void change_params(SLMP_INFO *info); | |
574 | ||
575 | static int init_adapter(SLMP_INFO *info); | |
576 | static int register_test(SLMP_INFO *info); | |
577 | static int irq_test(SLMP_INFO *info); | |
578 | static int loopback_test(SLMP_INFO *info); | |
579 | static int adapter_test(SLMP_INFO *info); | |
580 | static int memory_test(SLMP_INFO *info); | |
581 | ||
582 | static void reset_adapter(SLMP_INFO *info); | |
583 | static void reset_port(SLMP_INFO *info); | |
584 | static void async_mode(SLMP_INFO *info); | |
585 | static void hdlc_mode(SLMP_INFO *info); | |
586 | ||
587 | static void rx_stop(SLMP_INFO *info); | |
588 | static void rx_start(SLMP_INFO *info); | |
589 | static void rx_reset_buffers(SLMP_INFO *info); | |
590 | static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last); | |
591 | static int rx_get_frame(SLMP_INFO *info); | |
592 | ||
593 | static void tx_start(SLMP_INFO *info); | |
594 | static void tx_stop(SLMP_INFO *info); | |
595 | static void tx_load_fifo(SLMP_INFO *info); | |
596 | static void tx_set_idle(SLMP_INFO *info); | |
597 | static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count); | |
598 | ||
599 | static void get_signals(SLMP_INFO *info); | |
600 | static void set_signals(SLMP_INFO *info); | |
601 | static void enable_loopback(SLMP_INFO *info, int enable); | |
602 | static void set_rate(SLMP_INFO *info, u32 data_rate); | |
603 | ||
604 | static int bh_action(SLMP_INFO *info); | |
c4028958 | 605 | static void bh_handler(struct work_struct *work); |
1da177e4 LT |
606 | static void bh_receive(SLMP_INFO *info); |
607 | static void bh_transmit(SLMP_INFO *info); | |
608 | static void bh_status(SLMP_INFO *info); | |
609 | static void isr_timer(SLMP_INFO *info); | |
610 | static void isr_rxint(SLMP_INFO *info); | |
611 | static void isr_rxrdy(SLMP_INFO *info); | |
612 | static void isr_txint(SLMP_INFO *info); | |
613 | static void isr_txrdy(SLMP_INFO *info); | |
614 | static void isr_rxdmaok(SLMP_INFO *info); | |
615 | static void isr_rxdmaerror(SLMP_INFO *info); | |
616 | static void isr_txdmaok(SLMP_INFO *info); | |
617 | static void isr_txdmaerror(SLMP_INFO *info); | |
618 | static void isr_io_pin(SLMP_INFO *info, u16 status); | |
619 | ||
620 | static int alloc_dma_bufs(SLMP_INFO *info); | |
621 | static void free_dma_bufs(SLMP_INFO *info); | |
622 | static int alloc_buf_list(SLMP_INFO *info); | |
623 | static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count); | |
624 | static int alloc_tmp_rx_buf(SLMP_INFO *info); | |
625 | static void free_tmp_rx_buf(SLMP_INFO *info); | |
626 | ||
627 | static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count); | |
628 | static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit); | |
629 | static void tx_timeout(unsigned long context); | |
630 | static void status_timeout(unsigned long context); | |
631 | ||
632 | static unsigned char read_reg(SLMP_INFO *info, unsigned char addr); | |
633 | static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val); | |
634 | static u16 read_reg16(SLMP_INFO *info, unsigned char addr); | |
635 | static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val); | |
636 | static unsigned char read_status_reg(SLMP_INFO * info); | |
637 | static void write_control_reg(SLMP_INFO * info); | |
638 | ||
639 | ||
640 | static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes | |
641 | static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes | |
642 | static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes | |
643 | ||
644 | static u32 misc_ctrl_value = 0x007e4040; | |
761a444d | 645 | static u32 lcr1_brdr_value = 0x00800028; |
1da177e4 LT |
646 | |
647 | static u32 read_ahead_count = 8; | |
648 | ||
649 | /* DPCR, DMA Priority Control | |
650 | * | |
651 | * 07..05 Not used, must be 0 | |
652 | * 04 BRC, bus release condition: 0=all transfers complete | |
653 | * 1=release after 1 xfer on all channels | |
654 | * 03 CCC, channel change condition: 0=every cycle | |
655 | * 1=after each channel completes all xfers | |
656 | * 02..00 PR<2..0>, priority 100=round robin | |
657 | * | |
658 | * 00000100 = 0x00 | |
659 | */ | |
660 | static unsigned char dma_priority = 0x04; | |
661 | ||
662 | // Number of bytes that can be written to shared RAM | |
663 | // in a single write operation | |
664 | static u32 sca_pci_load_interval = 64; | |
665 | ||
666 | /* | |
667 | * 1st function defined in .text section. Calling this function in | |
668 | * init_module() followed by a breakpoint allows a remote debugger | |
669 | * (gdb) to get the .text address for the add-symbol-file command. | |
670 | * This allows remote debugging of dynamically loadable modules. | |
671 | */ | |
672 | static void* synclinkmp_get_text_ptr(void); | |
673 | static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;} | |
674 | ||
675 | static inline int sanity_check(SLMP_INFO *info, | |
676 | char *name, const char *routine) | |
677 | { | |
678 | #ifdef SANITY_CHECK | |
679 | static const char *badmagic = | |
680 | "Warning: bad magic number for synclinkmp_struct (%s) in %s\n"; | |
681 | static const char *badinfo = | |
682 | "Warning: null synclinkmp_struct for (%s) in %s\n"; | |
683 | ||
684 | if (!info) { | |
685 | printk(badinfo, name, routine); | |
686 | return 1; | |
687 | } | |
688 | if (info->magic != MGSL_MAGIC) { | |
689 | printk(badmagic, name, routine); | |
690 | return 1; | |
691 | } | |
692 | #else | |
693 | if (!info) | |
694 | return 1; | |
695 | #endif | |
696 | return 0; | |
697 | } | |
698 | ||
699 | /** | |
700 | * line discipline callback wrappers | |
701 | * | |
702 | * The wrappers maintain line discipline references | |
703 | * while calling into the line discipline. | |
704 | * | |
705 | * ldisc_receive_buf - pass receive data to line discipline | |
706 | */ | |
707 | ||
708 | static void ldisc_receive_buf(struct tty_struct *tty, | |
709 | const __u8 *data, char *flags, int count) | |
710 | { | |
711 | struct tty_ldisc *ld; | |
712 | if (!tty) | |
713 | return; | |
714 | ld = tty_ldisc_ref(tty); | |
715 | if (ld) { | |
716 | if (ld->receive_buf) | |
717 | ld->receive_buf(tty, data, flags, count); | |
718 | tty_ldisc_deref(ld); | |
719 | } | |
720 | } | |
721 | ||
722 | /* tty callbacks */ | |
723 | ||
724 | /* Called when a port is opened. Init and enable port. | |
725 | */ | |
726 | static int open(struct tty_struct *tty, struct file *filp) | |
727 | { | |
728 | SLMP_INFO *info; | |
729 | int retval, line; | |
730 | unsigned long flags; | |
731 | ||
732 | line = tty->index; | |
733 | if ((line < 0) || (line >= synclinkmp_device_count)) { | |
734 | printk("%s(%d): open with invalid line #%d.\n", | |
735 | __FILE__,__LINE__,line); | |
736 | return -ENODEV; | |
737 | } | |
738 | ||
739 | info = synclinkmp_device_list; | |
740 | while(info && info->line != line) | |
741 | info = info->next_device; | |
742 | if (sanity_check(info, tty->name, "open")) | |
743 | return -ENODEV; | |
744 | if ( info->init_error ) { | |
745 | printk("%s(%d):%s device is not allocated, init error=%d\n", | |
746 | __FILE__,__LINE__,info->device_name,info->init_error); | |
747 | return -ENODEV; | |
748 | } | |
749 | ||
750 | tty->driver_data = info; | |
751 | info->tty = tty; | |
752 | ||
753 | if (debug_level >= DEBUG_LEVEL_INFO) | |
754 | printk("%s(%d):%s open(), old ref count = %d\n", | |
755 | __FILE__,__LINE__,tty->driver->name, info->count); | |
756 | ||
757 | /* If port is closing, signal caller to try again */ | |
758 | if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){ | |
759 | if (info->flags & ASYNC_CLOSING) | |
760 | interruptible_sleep_on(&info->close_wait); | |
761 | retval = ((info->flags & ASYNC_HUP_NOTIFY) ? | |
762 | -EAGAIN : -ERESTARTSYS); | |
763 | goto cleanup; | |
764 | } | |
765 | ||
766 | info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; | |
767 | ||
768 | spin_lock_irqsave(&info->netlock, flags); | |
769 | if (info->netcount) { | |
770 | retval = -EBUSY; | |
771 | spin_unlock_irqrestore(&info->netlock, flags); | |
772 | goto cleanup; | |
773 | } | |
774 | info->count++; | |
775 | spin_unlock_irqrestore(&info->netlock, flags); | |
776 | ||
777 | if (info->count == 1) { | |
778 | /* 1st open on this device, init hardware */ | |
779 | retval = startup(info); | |
780 | if (retval < 0) | |
781 | goto cleanup; | |
782 | } | |
783 | ||
784 | retval = block_til_ready(tty, filp, info); | |
785 | if (retval) { | |
786 | if (debug_level >= DEBUG_LEVEL_INFO) | |
787 | printk("%s(%d):%s block_til_ready() returned %d\n", | |
788 | __FILE__,__LINE__, info->device_name, retval); | |
789 | goto cleanup; | |
790 | } | |
791 | ||
792 | if (debug_level >= DEBUG_LEVEL_INFO) | |
793 | printk("%s(%d):%s open() success\n", | |
794 | __FILE__,__LINE__, info->device_name); | |
795 | retval = 0; | |
796 | ||
797 | cleanup: | |
798 | if (retval) { | |
799 | if (tty->count == 1) | |
800 | info->tty = NULL; /* tty layer will release tty struct */ | |
801 | if(info->count) | |
802 | info->count--; | |
803 | } | |
804 | ||
805 | return retval; | |
806 | } | |
807 | ||
808 | /* Called when port is closed. Wait for remaining data to be | |
809 | * sent. Disable port and free resources. | |
810 | */ | |
811 | static void close(struct tty_struct *tty, struct file *filp) | |
812 | { | |
813 | SLMP_INFO * info = (SLMP_INFO *)tty->driver_data; | |
814 | ||
815 | if (sanity_check(info, tty->name, "close")) | |
816 | return; | |
817 | ||
818 | if (debug_level >= DEBUG_LEVEL_INFO) | |
819 | printk("%s(%d):%s close() entry, count=%d\n", | |
820 | __FILE__,__LINE__, info->device_name, info->count); | |
821 | ||
822 | if (!info->count) | |
823 | return; | |
824 | ||
825 | if (tty_hung_up_p(filp)) | |
826 | goto cleanup; | |
827 | ||
828 | if ((tty->count == 1) && (info->count != 1)) { | |
829 | /* | |
830 | * tty->count is 1 and the tty structure will be freed. | |
831 | * info->count should be one in this case. | |
832 | * if it's not, correct it so that the port is shutdown. | |
833 | */ | |
834 | printk("%s(%d):%s close: bad refcount; tty->count is 1, " | |
835 | "info->count is %d\n", | |
836 | __FILE__,__LINE__, info->device_name, info->count); | |
837 | info->count = 1; | |
838 | } | |
839 | ||
840 | info->count--; | |
841 | ||
842 | /* if at least one open remaining, leave hardware active */ | |
843 | if (info->count) | |
844 | goto cleanup; | |
845 | ||
846 | info->flags |= ASYNC_CLOSING; | |
847 | ||
848 | /* set tty->closing to notify line discipline to | |
849 | * only process XON/XOFF characters. Only the N_TTY | |
850 | * discipline appears to use this (ppp does not). | |
851 | */ | |
852 | tty->closing = 1; | |
853 | ||
854 | /* wait for transmit data to clear all layers */ | |
855 | ||
856 | if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) { | |
857 | if (debug_level >= DEBUG_LEVEL_INFO) | |
858 | printk("%s(%d):%s close() calling tty_wait_until_sent\n", | |
859 | __FILE__,__LINE__, info->device_name ); | |
860 | tty_wait_until_sent(tty, info->closing_wait); | |
861 | } | |
862 | ||
863 | if (info->flags & ASYNC_INITIALIZED) | |
864 | wait_until_sent(tty, info->timeout); | |
865 | ||
866 | if (tty->driver->flush_buffer) | |
867 | tty->driver->flush_buffer(tty); | |
868 | ||
869 | tty_ldisc_flush(tty); | |
870 | ||
871 | shutdown(info); | |
872 | ||
873 | tty->closing = 0; | |
874 | info->tty = NULL; | |
875 | ||
876 | if (info->blocked_open) { | |
877 | if (info->close_delay) { | |
878 | msleep_interruptible(jiffies_to_msecs(info->close_delay)); | |
879 | } | |
880 | wake_up_interruptible(&info->open_wait); | |
881 | } | |
882 | ||
883 | info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); | |
884 | ||
885 | wake_up_interruptible(&info->close_wait); | |
886 | ||
887 | cleanup: | |
888 | if (debug_level >= DEBUG_LEVEL_INFO) | |
889 | printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__, | |
890 | tty->driver->name, info->count); | |
891 | } | |
892 | ||
893 | /* Called by tty_hangup() when a hangup is signaled. | |
894 | * This is the same as closing all open descriptors for the port. | |
895 | */ | |
896 | static void hangup(struct tty_struct *tty) | |
897 | { | |
898 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
899 | ||
900 | if (debug_level >= DEBUG_LEVEL_INFO) | |
901 | printk("%s(%d):%s hangup()\n", | |
902 | __FILE__,__LINE__, info->device_name ); | |
903 | ||
904 | if (sanity_check(info, tty->name, "hangup")) | |
905 | return; | |
906 | ||
907 | flush_buffer(tty); | |
908 | shutdown(info); | |
909 | ||
910 | info->count = 0; | |
911 | info->flags &= ~ASYNC_NORMAL_ACTIVE; | |
912 | info->tty = NULL; | |
913 | ||
914 | wake_up_interruptible(&info->open_wait); | |
915 | } | |
916 | ||
917 | /* Set new termios settings | |
918 | */ | |
606d099c | 919 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
1da177e4 LT |
920 | { |
921 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
922 | unsigned long flags; | |
923 | ||
924 | if (debug_level >= DEBUG_LEVEL_INFO) | |
925 | printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__, | |
926 | tty->driver->name ); | |
927 | ||
1da177e4 LT |
928 | change_params(info); |
929 | ||
930 | /* Handle transition to B0 status */ | |
931 | if (old_termios->c_cflag & CBAUD && | |
932 | !(tty->termios->c_cflag & CBAUD)) { | |
933 | info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
934 | spin_lock_irqsave(&info->lock,flags); | |
935 | set_signals(info); | |
936 | spin_unlock_irqrestore(&info->lock,flags); | |
937 | } | |
938 | ||
939 | /* Handle transition away from B0 status */ | |
940 | if (!(old_termios->c_cflag & CBAUD) && | |
941 | tty->termios->c_cflag & CBAUD) { | |
942 | info->serial_signals |= SerialSignal_DTR; | |
943 | if (!(tty->termios->c_cflag & CRTSCTS) || | |
944 | !test_bit(TTY_THROTTLED, &tty->flags)) { | |
945 | info->serial_signals |= SerialSignal_RTS; | |
946 | } | |
947 | spin_lock_irqsave(&info->lock,flags); | |
948 | set_signals(info); | |
949 | spin_unlock_irqrestore(&info->lock,flags); | |
950 | } | |
951 | ||
952 | /* Handle turning off CRTSCTS */ | |
953 | if (old_termios->c_cflag & CRTSCTS && | |
954 | !(tty->termios->c_cflag & CRTSCTS)) { | |
955 | tty->hw_stopped = 0; | |
956 | tx_release(tty); | |
957 | } | |
958 | } | |
959 | ||
960 | /* Send a block of data | |
961 | * | |
962 | * Arguments: | |
963 | * | |
964 | * tty pointer to tty information structure | |
965 | * buf pointer to buffer containing send data | |
966 | * count size of send data in bytes | |
967 | * | |
968 | * Return Value: number of characters written | |
969 | */ | |
970 | static int write(struct tty_struct *tty, | |
971 | const unsigned char *buf, int count) | |
972 | { | |
973 | int c, ret = 0; | |
974 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
975 | unsigned long flags; | |
976 | ||
977 | if (debug_level >= DEBUG_LEVEL_INFO) | |
978 | printk("%s(%d):%s write() count=%d\n", | |
979 | __FILE__,__LINE__,info->device_name,count); | |
980 | ||
981 | if (sanity_check(info, tty->name, "write")) | |
982 | goto cleanup; | |
983 | ||
326f28e9 | 984 | if (!info->tx_buf) |
1da177e4 LT |
985 | goto cleanup; |
986 | ||
987 | if (info->params.mode == MGSL_MODE_HDLC) { | |
988 | if (count > info->max_frame_size) { | |
989 | ret = -EIO; | |
990 | goto cleanup; | |
991 | } | |
992 | if (info->tx_active) | |
993 | goto cleanup; | |
994 | if (info->tx_count) { | |
995 | /* send accumulated data from send_char() calls */ | |
996 | /* as frame and wait before accepting more data. */ | |
997 | tx_load_dma_buffer(info, info->tx_buf, info->tx_count); | |
998 | goto start; | |
999 | } | |
1000 | ret = info->tx_count = count; | |
1001 | tx_load_dma_buffer(info, buf, count); | |
1002 | goto start; | |
1003 | } | |
1004 | ||
1005 | for (;;) { | |
1006 | c = min_t(int, count, | |
1007 | min(info->max_frame_size - info->tx_count - 1, | |
1008 | info->max_frame_size - info->tx_put)); | |
1009 | if (c <= 0) | |
1010 | break; | |
1011 | ||
1012 | memcpy(info->tx_buf + info->tx_put, buf, c); | |
1013 | ||
1014 | spin_lock_irqsave(&info->lock,flags); | |
1015 | info->tx_put += c; | |
1016 | if (info->tx_put >= info->max_frame_size) | |
1017 | info->tx_put -= info->max_frame_size; | |
1018 | info->tx_count += c; | |
1019 | spin_unlock_irqrestore(&info->lock,flags); | |
1020 | ||
1021 | buf += c; | |
1022 | count -= c; | |
1023 | ret += c; | |
1024 | } | |
1025 | ||
1026 | if (info->params.mode == MGSL_MODE_HDLC) { | |
1027 | if (count) { | |
1028 | ret = info->tx_count = 0; | |
1029 | goto cleanup; | |
1030 | } | |
1031 | tx_load_dma_buffer(info, info->tx_buf, info->tx_count); | |
1032 | } | |
1033 | start: | |
1034 | if (info->tx_count && !tty->stopped && !tty->hw_stopped) { | |
1035 | spin_lock_irqsave(&info->lock,flags); | |
1036 | if (!info->tx_active) | |
1037 | tx_start(info); | |
1038 | spin_unlock_irqrestore(&info->lock,flags); | |
1039 | } | |
1040 | ||
1041 | cleanup: | |
1042 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1043 | printk( "%s(%d):%s write() returning=%d\n", | |
1044 | __FILE__,__LINE__,info->device_name,ret); | |
1045 | return ret; | |
1046 | } | |
1047 | ||
1048 | /* Add a character to the transmit buffer. | |
1049 | */ | |
1050 | static void put_char(struct tty_struct *tty, unsigned char ch) | |
1051 | { | |
1052 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1053 | unsigned long flags; | |
1054 | ||
1055 | if ( debug_level >= DEBUG_LEVEL_INFO ) { | |
1056 | printk( "%s(%d):%s put_char(%d)\n", | |
1057 | __FILE__,__LINE__,info->device_name,ch); | |
1058 | } | |
1059 | ||
1060 | if (sanity_check(info, tty->name, "put_char")) | |
1061 | return; | |
1062 | ||
326f28e9 | 1063 | if (!info->tx_buf) |
1da177e4 LT |
1064 | return; |
1065 | ||
1066 | spin_lock_irqsave(&info->lock,flags); | |
1067 | ||
1068 | if ( (info->params.mode != MGSL_MODE_HDLC) || | |
1069 | !info->tx_active ) { | |
1070 | ||
1071 | if (info->tx_count < info->max_frame_size - 1) { | |
1072 | info->tx_buf[info->tx_put++] = ch; | |
1073 | if (info->tx_put >= info->max_frame_size) | |
1074 | info->tx_put -= info->max_frame_size; | |
1075 | info->tx_count++; | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | spin_unlock_irqrestore(&info->lock,flags); | |
1080 | } | |
1081 | ||
1082 | /* Send a high-priority XON/XOFF character | |
1083 | */ | |
1084 | static void send_xchar(struct tty_struct *tty, char ch) | |
1085 | { | |
1086 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1087 | unsigned long flags; | |
1088 | ||
1089 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1090 | printk("%s(%d):%s send_xchar(%d)\n", | |
1091 | __FILE__,__LINE__, info->device_name, ch ); | |
1092 | ||
1093 | if (sanity_check(info, tty->name, "send_xchar")) | |
1094 | return; | |
1095 | ||
1096 | info->x_char = ch; | |
1097 | if (ch) { | |
1098 | /* Make sure transmit interrupts are on */ | |
1099 | spin_lock_irqsave(&info->lock,flags); | |
1100 | if (!info->tx_enabled) | |
1101 | tx_start(info); | |
1102 | spin_unlock_irqrestore(&info->lock,flags); | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | /* Wait until the transmitter is empty. | |
1107 | */ | |
1108 | static void wait_until_sent(struct tty_struct *tty, int timeout) | |
1109 | { | |
1110 | SLMP_INFO * info = (SLMP_INFO *)tty->driver_data; | |
1111 | unsigned long orig_jiffies, char_time; | |
1112 | ||
1113 | if (!info ) | |
1114 | return; | |
1115 | ||
1116 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1117 | printk("%s(%d):%s wait_until_sent() entry\n", | |
1118 | __FILE__,__LINE__, info->device_name ); | |
1119 | ||
1120 | if (sanity_check(info, tty->name, "wait_until_sent")) | |
1121 | return; | |
1122 | ||
1123 | if (!(info->flags & ASYNC_INITIALIZED)) | |
1124 | goto exit; | |
1125 | ||
1126 | orig_jiffies = jiffies; | |
1127 | ||
1128 | /* Set check interval to 1/5 of estimated time to | |
1129 | * send a character, and make it at least 1. The check | |
1130 | * interval should also be less than the timeout. | |
1131 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
1132 | */ | |
1133 | ||
1134 | if ( info->params.data_rate ) { | |
1135 | char_time = info->timeout/(32 * 5); | |
1136 | if (!char_time) | |
1137 | char_time++; | |
1138 | } else | |
1139 | char_time = 1; | |
1140 | ||
1141 | if (timeout) | |
1142 | char_time = min_t(unsigned long, char_time, timeout); | |
1143 | ||
1144 | if ( info->params.mode == MGSL_MODE_HDLC ) { | |
1145 | while (info->tx_active) { | |
1146 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
1147 | if (signal_pending(current)) | |
1148 | break; | |
1149 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
1150 | break; | |
1151 | } | |
1152 | } else { | |
1153 | //TODO: determine if there is something similar to USC16C32 | |
1154 | // TXSTATUS_ALL_SENT status | |
1155 | while ( info->tx_active && info->tx_enabled) { | |
1156 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
1157 | if (signal_pending(current)) | |
1158 | break; | |
1159 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
1160 | break; | |
1161 | } | |
1162 | } | |
1163 | ||
1164 | exit: | |
1165 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1166 | printk("%s(%d):%s wait_until_sent() exit\n", | |
1167 | __FILE__,__LINE__, info->device_name ); | |
1168 | } | |
1169 | ||
1170 | /* Return the count of free bytes in transmit buffer | |
1171 | */ | |
1172 | static int write_room(struct tty_struct *tty) | |
1173 | { | |
1174 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1175 | int ret; | |
1176 | ||
1177 | if (sanity_check(info, tty->name, "write_room")) | |
1178 | return 0; | |
1179 | ||
1180 | if (info->params.mode == MGSL_MODE_HDLC) { | |
1181 | ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; | |
1182 | } else { | |
1183 | ret = info->max_frame_size - info->tx_count - 1; | |
1184 | if (ret < 0) | |
1185 | ret = 0; | |
1186 | } | |
1187 | ||
1188 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1189 | printk("%s(%d):%s write_room()=%d\n", | |
1190 | __FILE__, __LINE__, info->device_name, ret); | |
1191 | ||
1192 | return ret; | |
1193 | } | |
1194 | ||
1195 | /* enable transmitter and send remaining buffered characters | |
1196 | */ | |
1197 | static void flush_chars(struct tty_struct *tty) | |
1198 | { | |
1199 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1200 | unsigned long flags; | |
1201 | ||
1202 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1203 | printk( "%s(%d):%s flush_chars() entry tx_count=%d\n", | |
1204 | __FILE__,__LINE__,info->device_name,info->tx_count); | |
1205 | ||
1206 | if (sanity_check(info, tty->name, "flush_chars")) | |
1207 | return; | |
1208 | ||
1209 | if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped || | |
1210 | !info->tx_buf) | |
1211 | return; | |
1212 | ||
1213 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1214 | printk( "%s(%d):%s flush_chars() entry, starting transmitter\n", | |
1215 | __FILE__,__LINE__,info->device_name ); | |
1216 | ||
1217 | spin_lock_irqsave(&info->lock,flags); | |
1218 | ||
1219 | if (!info->tx_active) { | |
1220 | if ( (info->params.mode == MGSL_MODE_HDLC) && | |
1221 | info->tx_count ) { | |
1222 | /* operating in synchronous (frame oriented) mode */ | |
1223 | /* copy data from circular tx_buf to */ | |
1224 | /* transmit DMA buffer. */ | |
1225 | tx_load_dma_buffer(info, | |
1226 | info->tx_buf,info->tx_count); | |
1227 | } | |
1228 | tx_start(info); | |
1229 | } | |
1230 | ||
1231 | spin_unlock_irqrestore(&info->lock,flags); | |
1232 | } | |
1233 | ||
1234 | /* Discard all data in the send buffer | |
1235 | */ | |
1236 | static void flush_buffer(struct tty_struct *tty) | |
1237 | { | |
1238 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1239 | unsigned long flags; | |
1240 | ||
1241 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1242 | printk("%s(%d):%s flush_buffer() entry\n", | |
1243 | __FILE__,__LINE__, info->device_name ); | |
1244 | ||
1245 | if (sanity_check(info, tty->name, "flush_buffer")) | |
1246 | return; | |
1247 | ||
1248 | spin_lock_irqsave(&info->lock,flags); | |
1249 | info->tx_count = info->tx_put = info->tx_get = 0; | |
1250 | del_timer(&info->tx_timer); | |
1251 | spin_unlock_irqrestore(&info->lock,flags); | |
1252 | ||
1da177e4 LT |
1253 | tty_wakeup(tty); |
1254 | } | |
1255 | ||
1256 | /* throttle (stop) transmitter | |
1257 | */ | |
1258 | static void tx_hold(struct tty_struct *tty) | |
1259 | { | |
1260 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1261 | unsigned long flags; | |
1262 | ||
1263 | if (sanity_check(info, tty->name, "tx_hold")) | |
1264 | return; | |
1265 | ||
1266 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1267 | printk("%s(%d):%s tx_hold()\n", | |
1268 | __FILE__,__LINE__,info->device_name); | |
1269 | ||
1270 | spin_lock_irqsave(&info->lock,flags); | |
1271 | if (info->tx_enabled) | |
1272 | tx_stop(info); | |
1273 | spin_unlock_irqrestore(&info->lock,flags); | |
1274 | } | |
1275 | ||
1276 | /* release (start) transmitter | |
1277 | */ | |
1278 | static void tx_release(struct tty_struct *tty) | |
1279 | { | |
1280 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1281 | unsigned long flags; | |
1282 | ||
1283 | if (sanity_check(info, tty->name, "tx_release")) | |
1284 | return; | |
1285 | ||
1286 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1287 | printk("%s(%d):%s tx_release()\n", | |
1288 | __FILE__,__LINE__,info->device_name); | |
1289 | ||
1290 | spin_lock_irqsave(&info->lock,flags); | |
1291 | if (!info->tx_enabled) | |
1292 | tx_start(info); | |
1293 | spin_unlock_irqrestore(&info->lock,flags); | |
1294 | } | |
1295 | ||
1296 | /* Service an IOCTL request | |
1297 | * | |
1298 | * Arguments: | |
1299 | * | |
1300 | * tty pointer to tty instance data | |
1301 | * file pointer to associated file object for device | |
1302 | * cmd IOCTL command code | |
1303 | * arg command argument/context | |
1304 | * | |
1305 | * Return Value: 0 if success, otherwise error code | |
1306 | */ | |
1307 | static int ioctl(struct tty_struct *tty, struct file *file, | |
1308 | unsigned int cmd, unsigned long arg) | |
1309 | { | |
1310 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1311 | int error; | |
1312 | struct mgsl_icount cnow; /* kernel counter temps */ | |
1313 | struct serial_icounter_struct __user *p_cuser; /* user space */ | |
1314 | unsigned long flags; | |
1315 | void __user *argp = (void __user *)arg; | |
1316 | ||
1317 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1318 | printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__, | |
1319 | info->device_name, cmd ); | |
1320 | ||
1321 | if (sanity_check(info, tty->name, "ioctl")) | |
1322 | return -ENODEV; | |
1323 | ||
1324 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
1325 | (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { | |
1326 | if (tty->flags & (1 << TTY_IO_ERROR)) | |
1327 | return -EIO; | |
1328 | } | |
1329 | ||
1330 | switch (cmd) { | |
1331 | case MGSL_IOCGPARAMS: | |
1332 | return get_params(info, argp); | |
1333 | case MGSL_IOCSPARAMS: | |
1334 | return set_params(info, argp); | |
1335 | case MGSL_IOCGTXIDLE: | |
1336 | return get_txidle(info, argp); | |
1337 | case MGSL_IOCSTXIDLE: | |
1338 | return set_txidle(info, (int)arg); | |
1339 | case MGSL_IOCTXENABLE: | |
1340 | return tx_enable(info, (int)arg); | |
1341 | case MGSL_IOCRXENABLE: | |
1342 | return rx_enable(info, (int)arg); | |
1343 | case MGSL_IOCTXABORT: | |
1344 | return tx_abort(info); | |
1345 | case MGSL_IOCGSTATS: | |
1346 | return get_stats(info, argp); | |
1347 | case MGSL_IOCWAITEVENT: | |
1348 | return wait_mgsl_event(info, argp); | |
1349 | case MGSL_IOCLOOPTXDONE: | |
1350 | return 0; // TODO: Not supported, need to document | |
1351 | /* Wait for modem input (DCD,RI,DSR,CTS) change | |
1352 | * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS) | |
1353 | */ | |
1354 | case TIOCMIWAIT: | |
1355 | return modem_input_wait(info,(int)arg); | |
1356 | ||
1357 | /* | |
1358 | * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) | |
1359 | * Return: write counters to the user passed counter struct | |
1360 | * NB: both 1->0 and 0->1 transitions are counted except for | |
1361 | * RI where only 0->1 is counted. | |
1362 | */ | |
1363 | case TIOCGICOUNT: | |
1364 | spin_lock_irqsave(&info->lock,flags); | |
1365 | cnow = info->icount; | |
1366 | spin_unlock_irqrestore(&info->lock,flags); | |
1367 | p_cuser = argp; | |
1368 | PUT_USER(error,cnow.cts, &p_cuser->cts); | |
1369 | if (error) return error; | |
1370 | PUT_USER(error,cnow.dsr, &p_cuser->dsr); | |
1371 | if (error) return error; | |
1372 | PUT_USER(error,cnow.rng, &p_cuser->rng); | |
1373 | if (error) return error; | |
1374 | PUT_USER(error,cnow.dcd, &p_cuser->dcd); | |
1375 | if (error) return error; | |
1376 | PUT_USER(error,cnow.rx, &p_cuser->rx); | |
1377 | if (error) return error; | |
1378 | PUT_USER(error,cnow.tx, &p_cuser->tx); | |
1379 | if (error) return error; | |
1380 | PUT_USER(error,cnow.frame, &p_cuser->frame); | |
1381 | if (error) return error; | |
1382 | PUT_USER(error,cnow.overrun, &p_cuser->overrun); | |
1383 | if (error) return error; | |
1384 | PUT_USER(error,cnow.parity, &p_cuser->parity); | |
1385 | if (error) return error; | |
1386 | PUT_USER(error,cnow.brk, &p_cuser->brk); | |
1387 | if (error) return error; | |
1388 | PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun); | |
1389 | if (error) return error; | |
1390 | return 0; | |
1391 | default: | |
1392 | return -ENOIOCTLCMD; | |
1393 | } | |
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | /* | |
1398 | * /proc fs routines.... | |
1399 | */ | |
1400 | ||
1401 | static inline int line_info(char *buf, SLMP_INFO *info) | |
1402 | { | |
1403 | char stat_buf[30]; | |
1404 | int ret; | |
1405 | unsigned long flags; | |
1406 | ||
1407 | ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n" | |
1408 | "\tIRQ=%d MaxFrameSize=%u\n", | |
1409 | info->device_name, | |
1410 | info->phys_sca_base, | |
1411 | info->phys_memory_base, | |
1412 | info->phys_statctrl_base, | |
1413 | info->phys_lcr_base, | |
1414 | info->irq_level, | |
1415 | info->max_frame_size ); | |
1416 | ||
1417 | /* output current serial signal states */ | |
1418 | spin_lock_irqsave(&info->lock,flags); | |
1419 | get_signals(info); | |
1420 | spin_unlock_irqrestore(&info->lock,flags); | |
1421 | ||
1422 | stat_buf[0] = 0; | |
1423 | stat_buf[1] = 0; | |
1424 | if (info->serial_signals & SerialSignal_RTS) | |
1425 | strcat(stat_buf, "|RTS"); | |
1426 | if (info->serial_signals & SerialSignal_CTS) | |
1427 | strcat(stat_buf, "|CTS"); | |
1428 | if (info->serial_signals & SerialSignal_DTR) | |
1429 | strcat(stat_buf, "|DTR"); | |
1430 | if (info->serial_signals & SerialSignal_DSR) | |
1431 | strcat(stat_buf, "|DSR"); | |
1432 | if (info->serial_signals & SerialSignal_DCD) | |
1433 | strcat(stat_buf, "|CD"); | |
1434 | if (info->serial_signals & SerialSignal_RI) | |
1435 | strcat(stat_buf, "|RI"); | |
1436 | ||
1437 | if (info->params.mode == MGSL_MODE_HDLC) { | |
1438 | ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d", | |
1439 | info->icount.txok, info->icount.rxok); | |
1440 | if (info->icount.txunder) | |
1441 | ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder); | |
1442 | if (info->icount.txabort) | |
1443 | ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort); | |
1444 | if (info->icount.rxshort) | |
1445 | ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort); | |
1446 | if (info->icount.rxlong) | |
1447 | ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong); | |
1448 | if (info->icount.rxover) | |
1449 | ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover); | |
1450 | if (info->icount.rxcrc) | |
1451 | ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc); | |
1452 | } else { | |
1453 | ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d", | |
1454 | info->icount.tx, info->icount.rx); | |
1455 | if (info->icount.frame) | |
1456 | ret += sprintf(buf+ret, " fe:%d", info->icount.frame); | |
1457 | if (info->icount.parity) | |
1458 | ret += sprintf(buf+ret, " pe:%d", info->icount.parity); | |
1459 | if (info->icount.brk) | |
1460 | ret += sprintf(buf+ret, " brk:%d", info->icount.brk); | |
1461 | if (info->icount.overrun) | |
1462 | ret += sprintf(buf+ret, " oe:%d", info->icount.overrun); | |
1463 | } | |
1464 | ||
1465 | /* Append serial signal status to end */ | |
1466 | ret += sprintf(buf+ret, " %s\n", stat_buf+1); | |
1467 | ||
1468 | ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", | |
1469 | info->tx_active,info->bh_requested,info->bh_running, | |
1470 | info->pending_bh); | |
1471 | ||
1472 | return ret; | |
1473 | } | |
1474 | ||
1475 | /* Called to print information about devices | |
1476 | */ | |
1477 | int read_proc(char *page, char **start, off_t off, int count, | |
1478 | int *eof, void *data) | |
1479 | { | |
1480 | int len = 0, l; | |
1481 | off_t begin = 0; | |
1482 | SLMP_INFO *info; | |
1483 | ||
1484 | len += sprintf(page, "synclinkmp driver:%s\n", driver_version); | |
1485 | ||
1486 | info = synclinkmp_device_list; | |
1487 | while( info ) { | |
1488 | l = line_info(page + len, info); | |
1489 | len += l; | |
1490 | if (len+begin > off+count) | |
1491 | goto done; | |
1492 | if (len+begin < off) { | |
1493 | begin += len; | |
1494 | len = 0; | |
1495 | } | |
1496 | info = info->next_device; | |
1497 | } | |
1498 | ||
1499 | *eof = 1; | |
1500 | done: | |
1501 | if (off >= len+begin) | |
1502 | return 0; | |
1503 | *start = page + (off-begin); | |
1504 | return ((count < begin+len-off) ? count : begin+len-off); | |
1505 | } | |
1506 | ||
1507 | /* Return the count of bytes in transmit buffer | |
1508 | */ | |
1509 | static int chars_in_buffer(struct tty_struct *tty) | |
1510 | { | |
1511 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1512 | ||
1513 | if (sanity_check(info, tty->name, "chars_in_buffer")) | |
1514 | return 0; | |
1515 | ||
1516 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1517 | printk("%s(%d):%s chars_in_buffer()=%d\n", | |
1518 | __FILE__, __LINE__, info->device_name, info->tx_count); | |
1519 | ||
1520 | return info->tx_count; | |
1521 | } | |
1522 | ||
1523 | /* Signal remote device to throttle send data (our receive data) | |
1524 | */ | |
1525 | static void throttle(struct tty_struct * tty) | |
1526 | { | |
1527 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1528 | unsigned long flags; | |
1529 | ||
1530 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1531 | printk("%s(%d):%s throttle() entry\n", | |
1532 | __FILE__,__LINE__, info->device_name ); | |
1533 | ||
1534 | if (sanity_check(info, tty->name, "throttle")) | |
1535 | return; | |
1536 | ||
1537 | if (I_IXOFF(tty)) | |
1538 | send_xchar(tty, STOP_CHAR(tty)); | |
1539 | ||
1540 | if (tty->termios->c_cflag & CRTSCTS) { | |
1541 | spin_lock_irqsave(&info->lock,flags); | |
1542 | info->serial_signals &= ~SerialSignal_RTS; | |
1543 | set_signals(info); | |
1544 | spin_unlock_irqrestore(&info->lock,flags); | |
1545 | } | |
1546 | } | |
1547 | ||
1548 | /* Signal remote device to stop throttling send data (our receive data) | |
1549 | */ | |
1550 | static void unthrottle(struct tty_struct * tty) | |
1551 | { | |
1552 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
1553 | unsigned long flags; | |
1554 | ||
1555 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1556 | printk("%s(%d):%s unthrottle() entry\n", | |
1557 | __FILE__,__LINE__, info->device_name ); | |
1558 | ||
1559 | if (sanity_check(info, tty->name, "unthrottle")) | |
1560 | return; | |
1561 | ||
1562 | if (I_IXOFF(tty)) { | |
1563 | if (info->x_char) | |
1564 | info->x_char = 0; | |
1565 | else | |
1566 | send_xchar(tty, START_CHAR(tty)); | |
1567 | } | |
1568 | ||
1569 | if (tty->termios->c_cflag & CRTSCTS) { | |
1570 | spin_lock_irqsave(&info->lock,flags); | |
1571 | info->serial_signals |= SerialSignal_RTS; | |
1572 | set_signals(info); | |
1573 | spin_unlock_irqrestore(&info->lock,flags); | |
1574 | } | |
1575 | } | |
1576 | ||
1577 | /* set or clear transmit break condition | |
1578 | * break_state -1=set break condition, 0=clear | |
1579 | */ | |
1580 | static void set_break(struct tty_struct *tty, int break_state) | |
1581 | { | |
1582 | unsigned char RegValue; | |
1583 | SLMP_INFO * info = (SLMP_INFO *)tty->driver_data; | |
1584 | unsigned long flags; | |
1585 | ||
1586 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1587 | printk("%s(%d):%s set_break(%d)\n", | |
1588 | __FILE__,__LINE__, info->device_name, break_state); | |
1589 | ||
1590 | if (sanity_check(info, tty->name, "set_break")) | |
1591 | return; | |
1592 | ||
1593 | spin_lock_irqsave(&info->lock,flags); | |
1594 | RegValue = read_reg(info, CTL); | |
1595 | if (break_state == -1) | |
1596 | RegValue |= BIT3; | |
1597 | else | |
1598 | RegValue &= ~BIT3; | |
1599 | write_reg(info, CTL, RegValue); | |
1600 | spin_unlock_irqrestore(&info->lock,flags); | |
1601 | } | |
1602 | ||
af69c7f9 | 1603 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
1604 | |
1605 | /** | |
1606 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
1607 | * set encoding and frame check sequence (FCS) options | |
1608 | * | |
1609 | * dev pointer to network device structure | |
1610 | * encoding serial encoding setting | |
1611 | * parity FCS setting | |
1612 | * | |
1613 | * returns 0 if success, otherwise error code | |
1614 | */ | |
1615 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
1616 | unsigned short parity) | |
1617 | { | |
1618 | SLMP_INFO *info = dev_to_port(dev); | |
1619 | unsigned char new_encoding; | |
1620 | unsigned short new_crctype; | |
1621 | ||
1622 | /* return error if TTY interface open */ | |
1623 | if (info->count) | |
1624 | return -EBUSY; | |
1625 | ||
1626 | switch (encoding) | |
1627 | { | |
1628 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
1629 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
1630 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
1631 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
1632 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
1633 | default: return -EINVAL; | |
1634 | } | |
1635 | ||
1636 | switch (parity) | |
1637 | { | |
1638 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
1639 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
1640 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
1641 | default: return -EINVAL; | |
1642 | } | |
1643 | ||
1644 | info->params.encoding = new_encoding; | |
53b3531b | 1645 | info->params.crc_type = new_crctype; |
1da177e4 LT |
1646 | |
1647 | /* if network interface up, reprogram hardware */ | |
1648 | if (info->netcount) | |
1649 | program_hw(info); | |
1650 | ||
1651 | return 0; | |
1652 | } | |
1653 | ||
1654 | /** | |
1655 | * called by generic HDLC layer to send frame | |
1656 | * | |
1657 | * skb socket buffer containing HDLC frame | |
1658 | * dev pointer to network device structure | |
1659 | * | |
1660 | * returns 0 if success, otherwise error code | |
1661 | */ | |
1662 | static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev) | |
1663 | { | |
1664 | SLMP_INFO *info = dev_to_port(dev); | |
1665 | struct net_device_stats *stats = hdlc_stats(dev); | |
1666 | unsigned long flags; | |
1667 | ||
1668 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1669 | printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); | |
1670 | ||
1671 | /* stop sending until this frame completes */ | |
1672 | netif_stop_queue(dev); | |
1673 | ||
1674 | /* copy data to device buffers */ | |
1675 | info->tx_count = skb->len; | |
1676 | tx_load_dma_buffer(info, skb->data, skb->len); | |
1677 | ||
1678 | /* update network statistics */ | |
1679 | stats->tx_packets++; | |
1680 | stats->tx_bytes += skb->len; | |
1681 | ||
1682 | /* done with socket buffer, so free it */ | |
1683 | dev_kfree_skb(skb); | |
1684 | ||
1685 | /* save start time for transmit timeout detection */ | |
1686 | dev->trans_start = jiffies; | |
1687 | ||
1688 | /* start hardware transmitter if necessary */ | |
1689 | spin_lock_irqsave(&info->lock,flags); | |
1690 | if (!info->tx_active) | |
1691 | tx_start(info); | |
1692 | spin_unlock_irqrestore(&info->lock,flags); | |
1693 | ||
1694 | return 0; | |
1695 | } | |
1696 | ||
1697 | /** | |
1698 | * called by network layer when interface enabled | |
1699 | * claim resources and initialize hardware | |
1700 | * | |
1701 | * dev pointer to network device structure | |
1702 | * | |
1703 | * returns 0 if success, otherwise error code | |
1704 | */ | |
1705 | static int hdlcdev_open(struct net_device *dev) | |
1706 | { | |
1707 | SLMP_INFO *info = dev_to_port(dev); | |
1708 | int rc; | |
1709 | unsigned long flags; | |
1710 | ||
1711 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1712 | printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); | |
1713 | ||
1714 | /* generic HDLC layer open processing */ | |
1715 | if ((rc = hdlc_open(dev))) | |
1716 | return rc; | |
1717 | ||
1718 | /* arbitrate between network and tty opens */ | |
1719 | spin_lock_irqsave(&info->netlock, flags); | |
1720 | if (info->count != 0 || info->netcount != 0) { | |
1721 | printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); | |
1722 | spin_unlock_irqrestore(&info->netlock, flags); | |
1723 | return -EBUSY; | |
1724 | } | |
1725 | info->netcount=1; | |
1726 | spin_unlock_irqrestore(&info->netlock, flags); | |
1727 | ||
1728 | /* claim resources and init adapter */ | |
1729 | if ((rc = startup(info)) != 0) { | |
1730 | spin_lock_irqsave(&info->netlock, flags); | |
1731 | info->netcount=0; | |
1732 | spin_unlock_irqrestore(&info->netlock, flags); | |
1733 | return rc; | |
1734 | } | |
1735 | ||
1736 | /* assert DTR and RTS, apply hardware settings */ | |
1737 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; | |
1738 | program_hw(info); | |
1739 | ||
1740 | /* enable network layer transmit */ | |
1741 | dev->trans_start = jiffies; | |
1742 | netif_start_queue(dev); | |
1743 | ||
1744 | /* inform generic HDLC layer of current DCD status */ | |
1745 | spin_lock_irqsave(&info->lock, flags); | |
1746 | get_signals(info); | |
1747 | spin_unlock_irqrestore(&info->lock, flags); | |
fbeff3c1 KH |
1748 | if (info->serial_signals & SerialSignal_DCD) |
1749 | netif_carrier_on(dev); | |
1750 | else | |
1751 | netif_carrier_off(dev); | |
1da177e4 LT |
1752 | return 0; |
1753 | } | |
1754 | ||
1755 | /** | |
1756 | * called by network layer when interface is disabled | |
1757 | * shutdown hardware and release resources | |
1758 | * | |
1759 | * dev pointer to network device structure | |
1760 | * | |
1761 | * returns 0 if success, otherwise error code | |
1762 | */ | |
1763 | static int hdlcdev_close(struct net_device *dev) | |
1764 | { | |
1765 | SLMP_INFO *info = dev_to_port(dev); | |
1766 | unsigned long flags; | |
1767 | ||
1768 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1769 | printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); | |
1770 | ||
1771 | netif_stop_queue(dev); | |
1772 | ||
1773 | /* shutdown adapter and release resources */ | |
1774 | shutdown(info); | |
1775 | ||
1776 | hdlc_close(dev); | |
1777 | ||
1778 | spin_lock_irqsave(&info->netlock, flags); | |
1779 | info->netcount=0; | |
1780 | spin_unlock_irqrestore(&info->netlock, flags); | |
1781 | ||
1782 | return 0; | |
1783 | } | |
1784 | ||
1785 | /** | |
1786 | * called by network layer to process IOCTL call to network device | |
1787 | * | |
1788 | * dev pointer to network device structure | |
1789 | * ifr pointer to network interface request structure | |
1790 | * cmd IOCTL command code | |
1791 | * | |
1792 | * returns 0 if success, otherwise error code | |
1793 | */ | |
1794 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1795 | { | |
1796 | const size_t size = sizeof(sync_serial_settings); | |
1797 | sync_serial_settings new_line; | |
1798 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1799 | SLMP_INFO *info = dev_to_port(dev); | |
1800 | unsigned int flags; | |
1801 | ||
1802 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1803 | printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); | |
1804 | ||
1805 | /* return error if TTY interface open */ | |
1806 | if (info->count) | |
1807 | return -EBUSY; | |
1808 | ||
1809 | if (cmd != SIOCWANDEV) | |
1810 | return hdlc_ioctl(dev, ifr, cmd); | |
1811 | ||
1812 | switch(ifr->ifr_settings.type) { | |
1813 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
1814 | ||
1815 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1816 | if (ifr->ifr_settings.size < size) { | |
1817 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1818 | return -ENOBUFS; | |
1819 | } | |
1820 | ||
1821 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1822 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1823 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1824 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1825 | ||
1826 | switch (flags){ | |
1827 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
1828 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
1829 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
1830 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
1831 | default: new_line.clock_type = CLOCK_DEFAULT; | |
1832 | } | |
1833 | ||
1834 | new_line.clock_rate = info->params.clock_speed; | |
1835 | new_line.loopback = info->params.loopback ? 1:0; | |
1836 | ||
1837 | if (copy_to_user(line, &new_line, size)) | |
1838 | return -EFAULT; | |
1839 | return 0; | |
1840 | ||
1841 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
1842 | ||
1843 | if(!capable(CAP_NET_ADMIN)) | |
1844 | return -EPERM; | |
1845 | if (copy_from_user(&new_line, line, size)) | |
1846 | return -EFAULT; | |
1847 | ||
1848 | switch (new_line.clock_type) | |
1849 | { | |
1850 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
1851 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
1852 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
1853 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
1854 | case CLOCK_DEFAULT: flags = info->params.flags & | |
1855 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1856 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1857 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1858 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
1859 | default: return -EINVAL; | |
1860 | } | |
1861 | ||
1862 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
1863 | return -EINVAL; | |
1864 | ||
1865 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1866 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1867 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1868 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1869 | info->params.flags |= flags; | |
1870 | ||
1871 | info->params.loopback = new_line.loopback; | |
1872 | ||
1873 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
1874 | info->params.clock_speed = new_line.clock_rate; | |
1875 | else | |
1876 | info->params.clock_speed = 0; | |
1877 | ||
1878 | /* if network interface up, reprogram hardware */ | |
1879 | if (info->netcount) | |
1880 | program_hw(info); | |
1881 | return 0; | |
1882 | ||
1883 | default: | |
1884 | return hdlc_ioctl(dev, ifr, cmd); | |
1885 | } | |
1886 | } | |
1887 | ||
1888 | /** | |
1889 | * called by network layer when transmit timeout is detected | |
1890 | * | |
1891 | * dev pointer to network device structure | |
1892 | */ | |
1893 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
1894 | { | |
1895 | SLMP_INFO *info = dev_to_port(dev); | |
1896 | struct net_device_stats *stats = hdlc_stats(dev); | |
1897 | unsigned long flags; | |
1898 | ||
1899 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1900 | printk("hdlcdev_tx_timeout(%s)\n",dev->name); | |
1901 | ||
1902 | stats->tx_errors++; | |
1903 | stats->tx_aborted_errors++; | |
1904 | ||
1905 | spin_lock_irqsave(&info->lock,flags); | |
1906 | tx_stop(info); | |
1907 | spin_unlock_irqrestore(&info->lock,flags); | |
1908 | ||
1909 | netif_wake_queue(dev); | |
1910 | } | |
1911 | ||
1912 | /** | |
1913 | * called by device driver when transmit completes | |
1914 | * reenable network layer transmit if stopped | |
1915 | * | |
1916 | * info pointer to device instance information | |
1917 | */ | |
1918 | static void hdlcdev_tx_done(SLMP_INFO *info) | |
1919 | { | |
1920 | if (netif_queue_stopped(info->netdev)) | |
1921 | netif_wake_queue(info->netdev); | |
1922 | } | |
1923 | ||
1924 | /** | |
1925 | * called by device driver when frame received | |
1926 | * pass frame to network layer | |
1927 | * | |
1928 | * info pointer to device instance information | |
1929 | * buf pointer to buffer contianing frame data | |
1930 | * size count of data bytes in buf | |
1931 | */ | |
1932 | static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size) | |
1933 | { | |
1934 | struct sk_buff *skb = dev_alloc_skb(size); | |
1935 | struct net_device *dev = info->netdev; | |
1936 | struct net_device_stats *stats = hdlc_stats(dev); | |
1937 | ||
1938 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1939 | printk("hdlcdev_rx(%s)\n",dev->name); | |
1940 | ||
1941 | if (skb == NULL) { | |
1942 | printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name); | |
1943 | stats->rx_dropped++; | |
1944 | return; | |
1945 | } | |
1946 | ||
1947 | memcpy(skb_put(skb, size),buf,size); | |
1948 | ||
1949 | skb->protocol = hdlc_type_trans(skb, info->netdev); | |
1950 | ||
1951 | stats->rx_packets++; | |
1952 | stats->rx_bytes += size; | |
1953 | ||
1954 | netif_rx(skb); | |
1955 | ||
1956 | info->netdev->last_rx = jiffies; | |
1957 | } | |
1958 | ||
1959 | /** | |
1960 | * called by device driver when adding device instance | |
1961 | * do generic HDLC initialization | |
1962 | * | |
1963 | * info pointer to device instance information | |
1964 | * | |
1965 | * returns 0 if success, otherwise error code | |
1966 | */ | |
1967 | static int hdlcdev_init(SLMP_INFO *info) | |
1968 | { | |
1969 | int rc; | |
1970 | struct net_device *dev; | |
1971 | hdlc_device *hdlc; | |
1972 | ||
1973 | /* allocate and initialize network and HDLC layer objects */ | |
1974 | ||
1975 | if (!(dev = alloc_hdlcdev(info))) { | |
1976 | printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); | |
1977 | return -ENOMEM; | |
1978 | } | |
1979 | ||
1980 | /* for network layer reporting purposes only */ | |
1981 | dev->mem_start = info->phys_sca_base; | |
1982 | dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1; | |
1983 | dev->irq = info->irq_level; | |
1984 | ||
1985 | /* network layer callbacks and settings */ | |
1986 | dev->do_ioctl = hdlcdev_ioctl; | |
1987 | dev->open = hdlcdev_open; | |
1988 | dev->stop = hdlcdev_close; | |
1989 | dev->tx_timeout = hdlcdev_tx_timeout; | |
1990 | dev->watchdog_timeo = 10*HZ; | |
1991 | dev->tx_queue_len = 50; | |
1992 | ||
1993 | /* generic HDLC layer callbacks and settings */ | |
1994 | hdlc = dev_to_hdlc(dev); | |
1995 | hdlc->attach = hdlcdev_attach; | |
1996 | hdlc->xmit = hdlcdev_xmit; | |
1997 | ||
1998 | /* register objects with HDLC layer */ | |
1999 | if ((rc = register_hdlc_device(dev))) { | |
2000 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); | |
2001 | free_netdev(dev); | |
2002 | return rc; | |
2003 | } | |
2004 | ||
2005 | info->netdev = dev; | |
2006 | return 0; | |
2007 | } | |
2008 | ||
2009 | /** | |
2010 | * called by device driver when removing device instance | |
2011 | * do generic HDLC cleanup | |
2012 | * | |
2013 | * info pointer to device instance information | |
2014 | */ | |
2015 | static void hdlcdev_exit(SLMP_INFO *info) | |
2016 | { | |
2017 | unregister_hdlc_device(info->netdev); | |
2018 | free_netdev(info->netdev); | |
2019 | info->netdev = NULL; | |
2020 | } | |
2021 | ||
2022 | #endif /* CONFIG_HDLC */ | |
2023 | ||
2024 | ||
2025 | /* Return next bottom half action to perform. | |
2026 | * Return Value: BH action code or 0 if nothing to do. | |
2027 | */ | |
2028 | int bh_action(SLMP_INFO *info) | |
2029 | { | |
2030 | unsigned long flags; | |
2031 | int rc = 0; | |
2032 | ||
2033 | spin_lock_irqsave(&info->lock,flags); | |
2034 | ||
2035 | if (info->pending_bh & BH_RECEIVE) { | |
2036 | info->pending_bh &= ~BH_RECEIVE; | |
2037 | rc = BH_RECEIVE; | |
2038 | } else if (info->pending_bh & BH_TRANSMIT) { | |
2039 | info->pending_bh &= ~BH_TRANSMIT; | |
2040 | rc = BH_TRANSMIT; | |
2041 | } else if (info->pending_bh & BH_STATUS) { | |
2042 | info->pending_bh &= ~BH_STATUS; | |
2043 | rc = BH_STATUS; | |
2044 | } | |
2045 | ||
2046 | if (!rc) { | |
2047 | /* Mark BH routine as complete */ | |
2048 | info->bh_running = 0; | |
2049 | info->bh_requested = 0; | |
2050 | } | |
2051 | ||
2052 | spin_unlock_irqrestore(&info->lock,flags); | |
2053 | ||
2054 | return rc; | |
2055 | } | |
2056 | ||
2057 | /* Perform bottom half processing of work items queued by ISR. | |
2058 | */ | |
c4028958 | 2059 | void bh_handler(struct work_struct *work) |
1da177e4 | 2060 | { |
c4028958 | 2061 | SLMP_INFO *info = container_of(work, SLMP_INFO, task); |
1da177e4 LT |
2062 | int action; |
2063 | ||
2064 | if (!info) | |
2065 | return; | |
2066 | ||
2067 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2068 | printk( "%s(%d):%s bh_handler() entry\n", | |
2069 | __FILE__,__LINE__,info->device_name); | |
2070 | ||
2071 | info->bh_running = 1; | |
2072 | ||
2073 | while((action = bh_action(info)) != 0) { | |
2074 | ||
2075 | /* Process work item */ | |
2076 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2077 | printk( "%s(%d):%s bh_handler() work item action=%d\n", | |
2078 | __FILE__,__LINE__,info->device_name, action); | |
2079 | ||
2080 | switch (action) { | |
2081 | ||
2082 | case BH_RECEIVE: | |
2083 | bh_receive(info); | |
2084 | break; | |
2085 | case BH_TRANSMIT: | |
2086 | bh_transmit(info); | |
2087 | break; | |
2088 | case BH_STATUS: | |
2089 | bh_status(info); | |
2090 | break; | |
2091 | default: | |
2092 | /* unknown work item ID */ | |
2093 | printk("%s(%d):%s Unknown work item ID=%08X!\n", | |
2094 | __FILE__,__LINE__,info->device_name,action); | |
2095 | break; | |
2096 | } | |
2097 | } | |
2098 | ||
2099 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2100 | printk( "%s(%d):%s bh_handler() exit\n", | |
2101 | __FILE__,__LINE__,info->device_name); | |
2102 | } | |
2103 | ||
2104 | void bh_receive(SLMP_INFO *info) | |
2105 | { | |
2106 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2107 | printk( "%s(%d):%s bh_receive()\n", | |
2108 | __FILE__,__LINE__,info->device_name); | |
2109 | ||
2110 | while( rx_get_frame(info) ); | |
2111 | } | |
2112 | ||
2113 | void bh_transmit(SLMP_INFO *info) | |
2114 | { | |
2115 | struct tty_struct *tty = info->tty; | |
2116 | ||
2117 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2118 | printk( "%s(%d):%s bh_transmit() entry\n", | |
2119 | __FILE__,__LINE__,info->device_name); | |
2120 | ||
b963a844 | 2121 | if (tty) |
1da177e4 | 2122 | tty_wakeup(tty); |
1da177e4 LT |
2123 | } |
2124 | ||
2125 | void bh_status(SLMP_INFO *info) | |
2126 | { | |
2127 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2128 | printk( "%s(%d):%s bh_status() entry\n", | |
2129 | __FILE__,__LINE__,info->device_name); | |
2130 | ||
2131 | info->ri_chkcount = 0; | |
2132 | info->dsr_chkcount = 0; | |
2133 | info->dcd_chkcount = 0; | |
2134 | info->cts_chkcount = 0; | |
2135 | } | |
2136 | ||
2137 | void isr_timer(SLMP_INFO * info) | |
2138 | { | |
2139 | unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; | |
2140 | ||
2141 | /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */ | |
2142 | write_reg(info, IER2, 0); | |
2143 | ||
2144 | /* TMCS, Timer Control/Status Register | |
2145 | * | |
2146 | * 07 CMF, Compare match flag (read only) 1=match | |
2147 | * 06 ECMI, CMF Interrupt Enable: 0=disabled | |
2148 | * 05 Reserved, must be 0 | |
2149 | * 04 TME, Timer Enable | |
2150 | * 03..00 Reserved, must be 0 | |
2151 | * | |
2152 | * 0000 0000 | |
2153 | */ | |
2154 | write_reg(info, (unsigned char)(timer + TMCS), 0); | |
2155 | ||
2156 | info->irq_occurred = TRUE; | |
2157 | ||
2158 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2159 | printk("%s(%d):%s isr_timer()\n", | |
2160 | __FILE__,__LINE__,info->device_name); | |
2161 | } | |
2162 | ||
2163 | void isr_rxint(SLMP_INFO * info) | |
2164 | { | |
2165 | struct tty_struct *tty = info->tty; | |
2166 | struct mgsl_icount *icount = &info->icount; | |
2167 | unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD); | |
2168 | unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN; | |
2169 | ||
2170 | /* clear status bits */ | |
2171 | if (status) | |
2172 | write_reg(info, SR1, status); | |
2173 | ||
2174 | if (status2) | |
2175 | write_reg(info, SR2, status2); | |
2176 | ||
2177 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2178 | printk("%s(%d):%s isr_rxint status=%02X %02x\n", | |
2179 | __FILE__,__LINE__,info->device_name,status,status2); | |
2180 | ||
2181 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
2182 | if (status & BRKD) { | |
2183 | icount->brk++; | |
2184 | ||
2185 | /* process break detection if tty control | |
2186 | * is not set to ignore it | |
2187 | */ | |
2188 | if ( tty ) { | |
2189 | if (!(status & info->ignore_status_mask1)) { | |
2190 | if (info->read_status_mask1 & BRKD) { | |
33f0f88f | 2191 | tty_insert_flip_char(tty, 0, TTY_BREAK); |
1da177e4 LT |
2192 | if (info->flags & ASYNC_SAK) |
2193 | do_SAK(tty); | |
2194 | } | |
2195 | } | |
2196 | } | |
2197 | } | |
2198 | } | |
2199 | else { | |
2200 | if (status & (FLGD|IDLD)) { | |
2201 | if (status & FLGD) | |
2202 | info->icount.exithunt++; | |
2203 | else if (status & IDLD) | |
2204 | info->icount.rxidle++; | |
2205 | wake_up_interruptible(&info->event_wait_q); | |
2206 | } | |
2207 | } | |
2208 | ||
2209 | if (status & CDCD) { | |
2210 | /* simulate a common modem status change interrupt | |
2211 | * for our handler | |
2212 | */ | |
2213 | get_signals( info ); | |
2214 | isr_io_pin(info, | |
2215 | MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD)); | |
2216 | } | |
2217 | } | |
2218 | ||
2219 | /* | |
2220 | * handle async rx data interrupts | |
2221 | */ | |
2222 | void isr_rxrdy(SLMP_INFO * info) | |
2223 | { | |
2224 | u16 status; | |
2225 | unsigned char DataByte; | |
2226 | struct tty_struct *tty = info->tty; | |
2227 | struct mgsl_icount *icount = &info->icount; | |
2228 | ||
2229 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2230 | printk("%s(%d):%s isr_rxrdy\n", | |
2231 | __FILE__,__LINE__,info->device_name); | |
2232 | ||
2233 | while((status = read_reg(info,CST0)) & BIT0) | |
2234 | { | |
33f0f88f AC |
2235 | int flag = 0; |
2236 | int over = 0; | |
1da177e4 LT |
2237 | DataByte = read_reg(info,TRB); |
2238 | ||
1da177e4 LT |
2239 | icount->rx++; |
2240 | ||
2241 | if ( status & (PE + FRME + OVRN) ) { | |
2242 | printk("%s(%d):%s rxerr=%04X\n", | |
2243 | __FILE__,__LINE__,info->device_name,status); | |
2244 | ||
2245 | /* update error statistics */ | |
2246 | if (status & PE) | |
2247 | icount->parity++; | |
2248 | else if (status & FRME) | |
2249 | icount->frame++; | |
2250 | else if (status & OVRN) | |
2251 | icount->overrun++; | |
2252 | ||
2253 | /* discard char if tty control flags say so */ | |
2254 | if (status & info->ignore_status_mask2) | |
2255 | continue; | |
2256 | ||
2257 | status &= info->read_status_mask2; | |
2258 | ||
2259 | if ( tty ) { | |
2260 | if (status & PE) | |
33f0f88f | 2261 | flag = TTY_PARITY; |
1da177e4 | 2262 | else if (status & FRME) |
33f0f88f | 2263 | flag = TTY_FRAME; |
1da177e4 LT |
2264 | if (status & OVRN) { |
2265 | /* Overrun is special, since it's | |
2266 | * reported immediately, and doesn't | |
2267 | * affect the current character | |
2268 | */ | |
33f0f88f | 2269 | over = 1; |
1da177e4 LT |
2270 | } |
2271 | } | |
2272 | } /* end of if (error) */ | |
2273 | ||
2274 | if ( tty ) { | |
33f0f88f AC |
2275 | tty_insert_flip_char(tty, DataByte, flag); |
2276 | if (over) | |
2277 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
1da177e4 LT |
2278 | } |
2279 | } | |
2280 | ||
2281 | if ( debug_level >= DEBUG_LEVEL_ISR ) { | |
1da177e4 LT |
2282 | printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n", |
2283 | __FILE__,__LINE__,info->device_name, | |
2284 | icount->rx,icount->brk,icount->parity, | |
2285 | icount->frame,icount->overrun); | |
2286 | } | |
2287 | ||
33f0f88f | 2288 | if ( tty ) |
1da177e4 LT |
2289 | tty_flip_buffer_push(tty); |
2290 | } | |
2291 | ||
2292 | static void isr_txeom(SLMP_INFO * info, unsigned char status) | |
2293 | { | |
2294 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2295 | printk("%s(%d):%s isr_txeom status=%02x\n", | |
2296 | __FILE__,__LINE__,info->device_name,status); | |
2297 | ||
2298 | write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ | |
2299 | write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ | |
2300 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
2301 | ||
2302 | if (status & UDRN) { | |
2303 | write_reg(info, CMD, TXRESET); | |
2304 | write_reg(info, CMD, TXENABLE); | |
2305 | } else | |
2306 | write_reg(info, CMD, TXBUFCLR); | |
2307 | ||
2308 | /* disable and clear tx interrupts */ | |
2309 | info->ie0_value &= ~TXRDYE; | |
2310 | info->ie1_value &= ~(IDLE + UDRN); | |
2311 | write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); | |
2312 | write_reg(info, SR1, (unsigned char)(UDRN + IDLE)); | |
2313 | ||
2314 | if ( info->tx_active ) { | |
2315 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2316 | if (status & UDRN) | |
2317 | info->icount.txunder++; | |
2318 | else if (status & IDLE) | |
2319 | info->icount.txok++; | |
2320 | } | |
2321 | ||
2322 | info->tx_active = 0; | |
2323 | info->tx_count = info->tx_put = info->tx_get = 0; | |
2324 | ||
2325 | del_timer(&info->tx_timer); | |
2326 | ||
2327 | if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) { | |
2328 | info->serial_signals &= ~SerialSignal_RTS; | |
2329 | info->drop_rts_on_tx_done = 0; | |
2330 | set_signals(info); | |
2331 | } | |
2332 | ||
af69c7f9 | 2333 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
2334 | if (info->netcount) |
2335 | hdlcdev_tx_done(info); | |
2336 | else | |
2337 | #endif | |
2338 | { | |
2339 | if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) { | |
2340 | tx_stop(info); | |
2341 | return; | |
2342 | } | |
2343 | info->pending_bh |= BH_TRANSMIT; | |
2344 | } | |
2345 | } | |
2346 | } | |
2347 | ||
2348 | ||
2349 | /* | |
2350 | * handle tx status interrupts | |
2351 | */ | |
2352 | void isr_txint(SLMP_INFO * info) | |
2353 | { | |
2354 | unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS); | |
2355 | ||
2356 | /* clear status bits */ | |
2357 | write_reg(info, SR1, status); | |
2358 | ||
2359 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2360 | printk("%s(%d):%s isr_txint status=%02x\n", | |
2361 | __FILE__,__LINE__,info->device_name,status); | |
2362 | ||
2363 | if (status & (UDRN + IDLE)) | |
2364 | isr_txeom(info, status); | |
2365 | ||
2366 | if (status & CCTS) { | |
2367 | /* simulate a common modem status change interrupt | |
2368 | * for our handler | |
2369 | */ | |
2370 | get_signals( info ); | |
2371 | isr_io_pin(info, | |
2372 | MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS)); | |
2373 | ||
2374 | } | |
2375 | } | |
2376 | ||
2377 | /* | |
2378 | * handle async tx data interrupts | |
2379 | */ | |
2380 | void isr_txrdy(SLMP_INFO * info) | |
2381 | { | |
2382 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2383 | printk("%s(%d):%s isr_txrdy() tx_count=%d\n", | |
2384 | __FILE__,__LINE__,info->device_name,info->tx_count); | |
2385 | ||
2386 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2387 | /* disable TXRDY IRQ, enable IDLE IRQ */ | |
2388 | info->ie0_value &= ~TXRDYE; | |
2389 | info->ie1_value |= IDLE; | |
2390 | write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); | |
2391 | return; | |
2392 | } | |
2393 | ||
2394 | if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) { | |
2395 | tx_stop(info); | |
2396 | return; | |
2397 | } | |
2398 | ||
2399 | if ( info->tx_count ) | |
2400 | tx_load_fifo( info ); | |
2401 | else { | |
2402 | info->tx_active = 0; | |
2403 | info->ie0_value &= ~TXRDYE; | |
2404 | write_reg(info, IE0, info->ie0_value); | |
2405 | } | |
2406 | ||
2407 | if (info->tx_count < WAKEUP_CHARS) | |
2408 | info->pending_bh |= BH_TRANSMIT; | |
2409 | } | |
2410 | ||
2411 | void isr_rxdmaok(SLMP_INFO * info) | |
2412 | { | |
2413 | /* BIT7 = EOT (end of transfer) | |
2414 | * BIT6 = EOM (end of message/frame) | |
2415 | */ | |
2416 | unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0; | |
2417 | ||
2418 | /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ | |
2419 | write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); | |
2420 | ||
2421 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2422 | printk("%s(%d):%s isr_rxdmaok(), status=%02x\n", | |
2423 | __FILE__,__LINE__,info->device_name,status); | |
2424 | ||
2425 | info->pending_bh |= BH_RECEIVE; | |
2426 | } | |
2427 | ||
2428 | void isr_rxdmaerror(SLMP_INFO * info) | |
2429 | { | |
2430 | /* BIT5 = BOF (buffer overflow) | |
2431 | * BIT4 = COF (counter overflow) | |
2432 | */ | |
2433 | unsigned char status = read_reg(info,RXDMA + DSR) & 0x30; | |
2434 | ||
2435 | /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ | |
2436 | write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); | |
2437 | ||
2438 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2439 | printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n", | |
2440 | __FILE__,__LINE__,info->device_name,status); | |
2441 | ||
2442 | info->rx_overflow = TRUE; | |
2443 | info->pending_bh |= BH_RECEIVE; | |
2444 | } | |
2445 | ||
2446 | void isr_txdmaok(SLMP_INFO * info) | |
2447 | { | |
2448 | unsigned char status_reg1 = read_reg(info, SR1); | |
2449 | ||
2450 | write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ | |
2451 | write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ | |
2452 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
2453 | ||
2454 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2455 | printk("%s(%d):%s isr_txdmaok(), status=%02x\n", | |
2456 | __FILE__,__LINE__,info->device_name,status_reg1); | |
2457 | ||
2458 | /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */ | |
2459 | write_reg16(info, TRC0, 0); | |
2460 | info->ie0_value |= TXRDYE; | |
2461 | write_reg(info, IE0, info->ie0_value); | |
2462 | } | |
2463 | ||
2464 | void isr_txdmaerror(SLMP_INFO * info) | |
2465 | { | |
2466 | /* BIT5 = BOF (buffer overflow) | |
2467 | * BIT4 = COF (counter overflow) | |
2468 | */ | |
2469 | unsigned char status = read_reg(info,TXDMA + DSR) & 0x30; | |
2470 | ||
2471 | /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ | |
2472 | write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); | |
2473 | ||
2474 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2475 | printk("%s(%d):%s isr_txdmaerror(), status=%02x\n", | |
2476 | __FILE__,__LINE__,info->device_name,status); | |
2477 | } | |
2478 | ||
2479 | /* handle input serial signal changes | |
2480 | */ | |
2481 | void isr_io_pin( SLMP_INFO *info, u16 status ) | |
2482 | { | |
2483 | struct mgsl_icount *icount; | |
2484 | ||
2485 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2486 | printk("%s(%d):isr_io_pin status=%04X\n", | |
2487 | __FILE__,__LINE__,status); | |
2488 | ||
2489 | if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED | | |
2490 | MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) { | |
2491 | icount = &info->icount; | |
2492 | /* update input line counters */ | |
2493 | if (status & MISCSTATUS_RI_LATCHED) { | |
2494 | icount->rng++; | |
2495 | if ( status & SerialSignal_RI ) | |
2496 | info->input_signal_events.ri_up++; | |
2497 | else | |
2498 | info->input_signal_events.ri_down++; | |
2499 | } | |
2500 | if (status & MISCSTATUS_DSR_LATCHED) { | |
2501 | icount->dsr++; | |
2502 | if ( status & SerialSignal_DSR ) | |
2503 | info->input_signal_events.dsr_up++; | |
2504 | else | |
2505 | info->input_signal_events.dsr_down++; | |
2506 | } | |
2507 | if (status & MISCSTATUS_DCD_LATCHED) { | |
2508 | if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { | |
2509 | info->ie1_value &= ~CDCD; | |
2510 | write_reg(info, IE1, info->ie1_value); | |
2511 | } | |
2512 | icount->dcd++; | |
2513 | if (status & SerialSignal_DCD) { | |
2514 | info->input_signal_events.dcd_up++; | |
2515 | } else | |
2516 | info->input_signal_events.dcd_down++; | |
af69c7f9 | 2517 | #if SYNCLINK_GENERIC_HDLC |
fbeff3c1 KH |
2518 | if (info->netcount) { |
2519 | if (status & SerialSignal_DCD) | |
2520 | netif_carrier_on(info->netdev); | |
2521 | else | |
2522 | netif_carrier_off(info->netdev); | |
2523 | } | |
1da177e4 LT |
2524 | #endif |
2525 | } | |
2526 | if (status & MISCSTATUS_CTS_LATCHED) | |
2527 | { | |
2528 | if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { | |
2529 | info->ie1_value &= ~CCTS; | |
2530 | write_reg(info, IE1, info->ie1_value); | |
2531 | } | |
2532 | icount->cts++; | |
2533 | if ( status & SerialSignal_CTS ) | |
2534 | info->input_signal_events.cts_up++; | |
2535 | else | |
2536 | info->input_signal_events.cts_down++; | |
2537 | } | |
2538 | wake_up_interruptible(&info->status_event_wait_q); | |
2539 | wake_up_interruptible(&info->event_wait_q); | |
2540 | ||
2541 | if ( (info->flags & ASYNC_CHECK_CD) && | |
2542 | (status & MISCSTATUS_DCD_LATCHED) ) { | |
2543 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2544 | printk("%s CD now %s...", info->device_name, | |
2545 | (status & SerialSignal_DCD) ? "on" : "off"); | |
2546 | if (status & SerialSignal_DCD) | |
2547 | wake_up_interruptible(&info->open_wait); | |
2548 | else { | |
2549 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2550 | printk("doing serial hangup..."); | |
2551 | if (info->tty) | |
2552 | tty_hangup(info->tty); | |
2553 | } | |
2554 | } | |
2555 | ||
2556 | if ( (info->flags & ASYNC_CTS_FLOW) && | |
2557 | (status & MISCSTATUS_CTS_LATCHED) ) { | |
2558 | if ( info->tty ) { | |
2559 | if (info->tty->hw_stopped) { | |
2560 | if (status & SerialSignal_CTS) { | |
2561 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2562 | printk("CTS tx start..."); | |
2563 | info->tty->hw_stopped = 0; | |
2564 | tx_start(info); | |
2565 | info->pending_bh |= BH_TRANSMIT; | |
2566 | return; | |
2567 | } | |
2568 | } else { | |
2569 | if (!(status & SerialSignal_CTS)) { | |
2570 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2571 | printk("CTS tx stop..."); | |
2572 | info->tty->hw_stopped = 1; | |
2573 | tx_stop(info); | |
2574 | } | |
2575 | } | |
2576 | } | |
2577 | } | |
2578 | } | |
2579 | ||
2580 | info->pending_bh |= BH_STATUS; | |
2581 | } | |
2582 | ||
2583 | /* Interrupt service routine entry point. | |
2584 | * | |
2585 | * Arguments: | |
2586 | * irq interrupt number that caused interrupt | |
2587 | * dev_id device ID supplied during interrupt registration | |
2588 | * regs interrupted processor context | |
2589 | */ | |
7d12e780 | 2590 | static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id) |
1da177e4 LT |
2591 | { |
2592 | SLMP_INFO * info; | |
2593 | unsigned char status, status0, status1=0; | |
2594 | unsigned char dmastatus, dmastatus0, dmastatus1=0; | |
2595 | unsigned char timerstatus0, timerstatus1=0; | |
2596 | unsigned char shift; | |
2597 | unsigned int i; | |
2598 | unsigned short tmp; | |
2599 | ||
2600 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2601 | printk("%s(%d): synclinkmp_interrupt(%d)entry.\n", | |
2602 | __FILE__,__LINE__,irq); | |
2603 | ||
2604 | info = (SLMP_INFO *)dev_id; | |
2605 | if (!info) | |
2606 | return IRQ_NONE; | |
2607 | ||
2608 | spin_lock(&info->lock); | |
2609 | ||
2610 | for(;;) { | |
2611 | ||
2612 | /* get status for SCA0 (ports 0-1) */ | |
2613 | tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */ | |
2614 | status0 = (unsigned char)tmp; | |
2615 | dmastatus0 = (unsigned char)(tmp>>8); | |
2616 | timerstatus0 = read_reg(info, ISR2); | |
2617 | ||
2618 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2619 | printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n", | |
2620 | __FILE__,__LINE__,info->device_name, | |
2621 | status0,dmastatus0,timerstatus0); | |
2622 | ||
2623 | if (info->port_count == 4) { | |
2624 | /* get status for SCA1 (ports 2-3) */ | |
2625 | tmp = read_reg16(info->port_array[2], ISR0); | |
2626 | status1 = (unsigned char)tmp; | |
2627 | dmastatus1 = (unsigned char)(tmp>>8); | |
2628 | timerstatus1 = read_reg(info->port_array[2], ISR2); | |
2629 | ||
2630 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2631 | printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n", | |
2632 | __FILE__,__LINE__,info->device_name, | |
2633 | status1,dmastatus1,timerstatus1); | |
2634 | } | |
2635 | ||
2636 | if (!status0 && !dmastatus0 && !timerstatus0 && | |
2637 | !status1 && !dmastatus1 && !timerstatus1) | |
2638 | break; | |
2639 | ||
2640 | for(i=0; i < info->port_count ; i++) { | |
2641 | if (info->port_array[i] == NULL) | |
2642 | continue; | |
2643 | if (i < 2) { | |
2644 | status = status0; | |
2645 | dmastatus = dmastatus0; | |
2646 | } else { | |
2647 | status = status1; | |
2648 | dmastatus = dmastatus1; | |
2649 | } | |
2650 | ||
2651 | shift = i & 1 ? 4 :0; | |
2652 | ||
2653 | if (status & BIT0 << shift) | |
2654 | isr_rxrdy(info->port_array[i]); | |
2655 | if (status & BIT1 << shift) | |
2656 | isr_txrdy(info->port_array[i]); | |
2657 | if (status & BIT2 << shift) | |
2658 | isr_rxint(info->port_array[i]); | |
2659 | if (status & BIT3 << shift) | |
2660 | isr_txint(info->port_array[i]); | |
2661 | ||
2662 | if (dmastatus & BIT0 << shift) | |
2663 | isr_rxdmaerror(info->port_array[i]); | |
2664 | if (dmastatus & BIT1 << shift) | |
2665 | isr_rxdmaok(info->port_array[i]); | |
2666 | if (dmastatus & BIT2 << shift) | |
2667 | isr_txdmaerror(info->port_array[i]); | |
2668 | if (dmastatus & BIT3 << shift) | |
2669 | isr_txdmaok(info->port_array[i]); | |
2670 | } | |
2671 | ||
2672 | if (timerstatus0 & (BIT5 | BIT4)) | |
2673 | isr_timer(info->port_array[0]); | |
2674 | if (timerstatus0 & (BIT7 | BIT6)) | |
2675 | isr_timer(info->port_array[1]); | |
2676 | if (timerstatus1 & (BIT5 | BIT4)) | |
2677 | isr_timer(info->port_array[2]); | |
2678 | if (timerstatus1 & (BIT7 | BIT6)) | |
2679 | isr_timer(info->port_array[3]); | |
2680 | } | |
2681 | ||
2682 | for(i=0; i < info->port_count ; i++) { | |
2683 | SLMP_INFO * port = info->port_array[i]; | |
2684 | ||
2685 | /* Request bottom half processing if there's something | |
2686 | * for it to do and the bh is not already running. | |
2687 | * | |
2688 | * Note: startup adapter diags require interrupts. | |
2689 | * do not request bottom half processing if the | |
2690 | * device is not open in a normal mode. | |
2691 | */ | |
2692 | if ( port && (port->count || port->netcount) && | |
2693 | port->pending_bh && !port->bh_running && | |
2694 | !port->bh_requested ) { | |
2695 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2696 | printk("%s(%d):%s queueing bh task.\n", | |
2697 | __FILE__,__LINE__,port->device_name); | |
2698 | schedule_work(&port->task); | |
2699 | port->bh_requested = 1; | |
2700 | } | |
2701 | } | |
2702 | ||
2703 | spin_unlock(&info->lock); | |
2704 | ||
2705 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2706 | printk("%s(%d):synclinkmp_interrupt(%d)exit.\n", | |
2707 | __FILE__,__LINE__,irq); | |
2708 | return IRQ_HANDLED; | |
2709 | } | |
2710 | ||
2711 | /* Initialize and start device. | |
2712 | */ | |
2713 | static int startup(SLMP_INFO * info) | |
2714 | { | |
2715 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2716 | printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name); | |
2717 | ||
2718 | if (info->flags & ASYNC_INITIALIZED) | |
2719 | return 0; | |
2720 | ||
2721 | if (!info->tx_buf) { | |
5cbded58 | 2722 | info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); |
1da177e4 LT |
2723 | if (!info->tx_buf) { |
2724 | printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", | |
2725 | __FILE__,__LINE__,info->device_name); | |
2726 | return -ENOMEM; | |
2727 | } | |
2728 | } | |
2729 | ||
2730 | info->pending_bh = 0; | |
2731 | ||
166692e4 PF |
2732 | memset(&info->icount, 0, sizeof(info->icount)); |
2733 | ||
1da177e4 LT |
2734 | /* program hardware for current parameters */ |
2735 | reset_port(info); | |
2736 | ||
2737 | change_params(info); | |
2738 | ||
40565f19 | 2739 | mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); |
1da177e4 LT |
2740 | |
2741 | if (info->tty) | |
2742 | clear_bit(TTY_IO_ERROR, &info->tty->flags); | |
2743 | ||
2744 | info->flags |= ASYNC_INITIALIZED; | |
2745 | ||
2746 | return 0; | |
2747 | } | |
2748 | ||
2749 | /* Called by close() and hangup() to shutdown hardware | |
2750 | */ | |
2751 | static void shutdown(SLMP_INFO * info) | |
2752 | { | |
2753 | unsigned long flags; | |
2754 | ||
2755 | if (!(info->flags & ASYNC_INITIALIZED)) | |
2756 | return; | |
2757 | ||
2758 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2759 | printk("%s(%d):%s synclinkmp_shutdown()\n", | |
2760 | __FILE__,__LINE__, info->device_name ); | |
2761 | ||
2762 | /* clear status wait queue because status changes */ | |
2763 | /* can't happen after shutting down the hardware */ | |
2764 | wake_up_interruptible(&info->status_event_wait_q); | |
2765 | wake_up_interruptible(&info->event_wait_q); | |
2766 | ||
2767 | del_timer(&info->tx_timer); | |
2768 | del_timer(&info->status_timer); | |
2769 | ||
735d5661 JJ |
2770 | kfree(info->tx_buf); |
2771 | info->tx_buf = NULL; | |
1da177e4 LT |
2772 | |
2773 | spin_lock_irqsave(&info->lock,flags); | |
2774 | ||
2775 | reset_port(info); | |
2776 | ||
2777 | if (!info->tty || info->tty->termios->c_cflag & HUPCL) { | |
2778 | info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
2779 | set_signals(info); | |
2780 | } | |
2781 | ||
2782 | spin_unlock_irqrestore(&info->lock,flags); | |
2783 | ||
2784 | if (info->tty) | |
2785 | set_bit(TTY_IO_ERROR, &info->tty->flags); | |
2786 | ||
2787 | info->flags &= ~ASYNC_INITIALIZED; | |
2788 | } | |
2789 | ||
2790 | static void program_hw(SLMP_INFO *info) | |
2791 | { | |
2792 | unsigned long flags; | |
2793 | ||
2794 | spin_lock_irqsave(&info->lock,flags); | |
2795 | ||
2796 | rx_stop(info); | |
2797 | tx_stop(info); | |
2798 | ||
2799 | info->tx_count = info->tx_put = info->tx_get = 0; | |
2800 | ||
2801 | if (info->params.mode == MGSL_MODE_HDLC || info->netcount) | |
2802 | hdlc_mode(info); | |
2803 | else | |
2804 | async_mode(info); | |
2805 | ||
2806 | set_signals(info); | |
2807 | ||
2808 | info->dcd_chkcount = 0; | |
2809 | info->cts_chkcount = 0; | |
2810 | info->ri_chkcount = 0; | |
2811 | info->dsr_chkcount = 0; | |
2812 | ||
2813 | info->ie1_value |= (CDCD|CCTS); | |
2814 | write_reg(info, IE1, info->ie1_value); | |
2815 | ||
2816 | get_signals(info); | |
2817 | ||
2818 | if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) ) | |
2819 | rx_start(info); | |
2820 | ||
2821 | spin_unlock_irqrestore(&info->lock,flags); | |
2822 | } | |
2823 | ||
2824 | /* Reconfigure adapter based on new parameters | |
2825 | */ | |
2826 | static void change_params(SLMP_INFO *info) | |
2827 | { | |
2828 | unsigned cflag; | |
2829 | int bits_per_char; | |
2830 | ||
2831 | if (!info->tty || !info->tty->termios) | |
2832 | return; | |
2833 | ||
2834 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2835 | printk("%s(%d):%s change_params()\n", | |
2836 | __FILE__,__LINE__, info->device_name ); | |
2837 | ||
2838 | cflag = info->tty->termios->c_cflag; | |
2839 | ||
2840 | /* if B0 rate (hangup) specified then negate DTR and RTS */ | |
2841 | /* otherwise assert DTR and RTS */ | |
2842 | if (cflag & CBAUD) | |
2843 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; | |
2844 | else | |
2845 | info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
2846 | ||
2847 | /* byte size and parity */ | |
2848 | ||
2849 | switch (cflag & CSIZE) { | |
2850 | case CS5: info->params.data_bits = 5; break; | |
2851 | case CS6: info->params.data_bits = 6; break; | |
2852 | case CS7: info->params.data_bits = 7; break; | |
2853 | case CS8: info->params.data_bits = 8; break; | |
2854 | /* Never happens, but GCC is too dumb to figure it out */ | |
2855 | default: info->params.data_bits = 7; break; | |
2856 | } | |
2857 | ||
2858 | if (cflag & CSTOPB) | |
2859 | info->params.stop_bits = 2; | |
2860 | else | |
2861 | info->params.stop_bits = 1; | |
2862 | ||
2863 | info->params.parity = ASYNC_PARITY_NONE; | |
2864 | if (cflag & PARENB) { | |
2865 | if (cflag & PARODD) | |
2866 | info->params.parity = ASYNC_PARITY_ODD; | |
2867 | else | |
2868 | info->params.parity = ASYNC_PARITY_EVEN; | |
2869 | #ifdef CMSPAR | |
2870 | if (cflag & CMSPAR) | |
2871 | info->params.parity = ASYNC_PARITY_SPACE; | |
2872 | #endif | |
2873 | } | |
2874 | ||
2875 | /* calculate number of jiffies to transmit a full | |
2876 | * FIFO (32 bytes) at specified data rate | |
2877 | */ | |
2878 | bits_per_char = info->params.data_bits + | |
2879 | info->params.stop_bits + 1; | |
2880 | ||
2881 | /* if port data rate is set to 460800 or less then | |
2882 | * allow tty settings to override, otherwise keep the | |
2883 | * current data rate. | |
2884 | */ | |
2885 | if (info->params.data_rate <= 460800) { | |
2886 | info->params.data_rate = tty_get_baud_rate(info->tty); | |
2887 | } | |
2888 | ||
2889 | if ( info->params.data_rate ) { | |
2890 | info->timeout = (32*HZ*bits_per_char) / | |
2891 | info->params.data_rate; | |
2892 | } | |
2893 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
2894 | ||
2895 | if (cflag & CRTSCTS) | |
2896 | info->flags |= ASYNC_CTS_FLOW; | |
2897 | else | |
2898 | info->flags &= ~ASYNC_CTS_FLOW; | |
2899 | ||
2900 | if (cflag & CLOCAL) | |
2901 | info->flags &= ~ASYNC_CHECK_CD; | |
2902 | else | |
2903 | info->flags |= ASYNC_CHECK_CD; | |
2904 | ||
2905 | /* process tty input control flags */ | |
2906 | ||
2907 | info->read_status_mask2 = OVRN; | |
2908 | if (I_INPCK(info->tty)) | |
2909 | info->read_status_mask2 |= PE | FRME; | |
2910 | if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) | |
2911 | info->read_status_mask1 |= BRKD; | |
2912 | if (I_IGNPAR(info->tty)) | |
2913 | info->ignore_status_mask2 |= PE | FRME; | |
2914 | if (I_IGNBRK(info->tty)) { | |
2915 | info->ignore_status_mask1 |= BRKD; | |
2916 | /* If ignoring parity and break indicators, ignore | |
2917 | * overruns too. (For real raw support). | |
2918 | */ | |
2919 | if (I_IGNPAR(info->tty)) | |
2920 | info->ignore_status_mask2 |= OVRN; | |
2921 | } | |
2922 | ||
2923 | program_hw(info); | |
2924 | } | |
2925 | ||
2926 | static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount) | |
2927 | { | |
2928 | int err; | |
2929 | ||
2930 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2931 | printk("%s(%d):%s get_params()\n", | |
2932 | __FILE__,__LINE__, info->device_name); | |
2933 | ||
166692e4 PF |
2934 | if (!user_icount) { |
2935 | memset(&info->icount, 0, sizeof(info->icount)); | |
2936 | } else { | |
2937 | COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); | |
2938 | if (err) | |
2939 | return -EFAULT; | |
1da177e4 LT |
2940 | } |
2941 | ||
2942 | return 0; | |
2943 | } | |
2944 | ||
2945 | static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params) | |
2946 | { | |
2947 | int err; | |
2948 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2949 | printk("%s(%d):%s get_params()\n", | |
2950 | __FILE__,__LINE__, info->device_name); | |
2951 | ||
2952 | COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); | |
2953 | if (err) { | |
2954 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2955 | printk( "%s(%d):%s get_params() user buffer copy failed\n", | |
2956 | __FILE__,__LINE__,info->device_name); | |
2957 | return -EFAULT; | |
2958 | } | |
2959 | ||
2960 | return 0; | |
2961 | } | |
2962 | ||
2963 | static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params) | |
2964 | { | |
2965 | unsigned long flags; | |
2966 | MGSL_PARAMS tmp_params; | |
2967 | int err; | |
2968 | ||
2969 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2970 | printk("%s(%d):%s set_params\n", | |
2971 | __FILE__,__LINE__,info->device_name ); | |
2972 | COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); | |
2973 | if (err) { | |
2974 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2975 | printk( "%s(%d):%s set_params() user buffer copy failed\n", | |
2976 | __FILE__,__LINE__,info->device_name); | |
2977 | return -EFAULT; | |
2978 | } | |
2979 | ||
2980 | spin_lock_irqsave(&info->lock,flags); | |
2981 | memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); | |
2982 | spin_unlock_irqrestore(&info->lock,flags); | |
2983 | ||
2984 | change_params(info); | |
2985 | ||
2986 | return 0; | |
2987 | } | |
2988 | ||
2989 | static int get_txidle(SLMP_INFO * info, int __user *idle_mode) | |
2990 | { | |
2991 | int err; | |
2992 | ||
2993 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2994 | printk("%s(%d):%s get_txidle()=%d\n", | |
2995 | __FILE__,__LINE__, info->device_name, info->idle_mode); | |
2996 | ||
2997 | COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); | |
2998 | if (err) { | |
2999 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3000 | printk( "%s(%d):%s get_txidle() user buffer copy failed\n", | |
3001 | __FILE__,__LINE__,info->device_name); | |
3002 | return -EFAULT; | |
3003 | } | |
3004 | ||
3005 | return 0; | |
3006 | } | |
3007 | ||
3008 | static int set_txidle(SLMP_INFO * info, int idle_mode) | |
3009 | { | |
3010 | unsigned long flags; | |
3011 | ||
3012 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3013 | printk("%s(%d):%s set_txidle(%d)\n", | |
3014 | __FILE__,__LINE__,info->device_name, idle_mode ); | |
3015 | ||
3016 | spin_lock_irqsave(&info->lock,flags); | |
3017 | info->idle_mode = idle_mode; | |
3018 | tx_set_idle( info ); | |
3019 | spin_unlock_irqrestore(&info->lock,flags); | |
3020 | return 0; | |
3021 | } | |
3022 | ||
3023 | static int tx_enable(SLMP_INFO * info, int enable) | |
3024 | { | |
3025 | unsigned long flags; | |
3026 | ||
3027 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3028 | printk("%s(%d):%s tx_enable(%d)\n", | |
3029 | __FILE__,__LINE__,info->device_name, enable); | |
3030 | ||
3031 | spin_lock_irqsave(&info->lock,flags); | |
3032 | if ( enable ) { | |
3033 | if ( !info->tx_enabled ) { | |
3034 | tx_start(info); | |
3035 | } | |
3036 | } else { | |
3037 | if ( info->tx_enabled ) | |
3038 | tx_stop(info); | |
3039 | } | |
3040 | spin_unlock_irqrestore(&info->lock,flags); | |
3041 | return 0; | |
3042 | } | |
3043 | ||
3044 | /* abort send HDLC frame | |
3045 | */ | |
3046 | static int tx_abort(SLMP_INFO * info) | |
3047 | { | |
3048 | unsigned long flags; | |
3049 | ||
3050 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3051 | printk("%s(%d):%s tx_abort()\n", | |
3052 | __FILE__,__LINE__,info->device_name); | |
3053 | ||
3054 | spin_lock_irqsave(&info->lock,flags); | |
3055 | if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) { | |
3056 | info->ie1_value &= ~UDRN; | |
3057 | info->ie1_value |= IDLE; | |
3058 | write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ | |
3059 | write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ | |
3060 | ||
3061 | write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ | |
3062 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
3063 | ||
3064 | write_reg(info, CMD, TXABORT); | |
3065 | } | |
3066 | spin_unlock_irqrestore(&info->lock,flags); | |
3067 | return 0; | |
3068 | } | |
3069 | ||
3070 | static int rx_enable(SLMP_INFO * info, int enable) | |
3071 | { | |
3072 | unsigned long flags; | |
3073 | ||
3074 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3075 | printk("%s(%d):%s rx_enable(%d)\n", | |
3076 | __FILE__,__LINE__,info->device_name,enable); | |
3077 | ||
3078 | spin_lock_irqsave(&info->lock,flags); | |
3079 | if ( enable ) { | |
3080 | if ( !info->rx_enabled ) | |
3081 | rx_start(info); | |
3082 | } else { | |
3083 | if ( info->rx_enabled ) | |
3084 | rx_stop(info); | |
3085 | } | |
3086 | spin_unlock_irqrestore(&info->lock,flags); | |
3087 | return 0; | |
3088 | } | |
3089 | ||
1da177e4 LT |
3090 | /* wait for specified event to occur |
3091 | */ | |
3092 | static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr) | |
3093 | { | |
3094 | unsigned long flags; | |
3095 | int s; | |
3096 | int rc=0; | |
3097 | struct mgsl_icount cprev, cnow; | |
3098 | int events; | |
3099 | int mask; | |
3100 | struct _input_signal_events oldsigs, newsigs; | |
3101 | DECLARE_WAITQUEUE(wait, current); | |
3102 | ||
3103 | COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); | |
3104 | if (rc) { | |
3105 | return -EFAULT; | |
3106 | } | |
3107 | ||
3108 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3109 | printk("%s(%d):%s wait_mgsl_event(%d)\n", | |
3110 | __FILE__,__LINE__,info->device_name,mask); | |
3111 | ||
3112 | spin_lock_irqsave(&info->lock,flags); | |
3113 | ||
3114 | /* return immediately if state matches requested events */ | |
3115 | get_signals(info); | |
7f3edb94 | 3116 | s = info->serial_signals; |
1da177e4 LT |
3117 | |
3118 | events = mask & | |
3119 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
3120 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
3121 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
3122 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
3123 | if (events) { | |
3124 | spin_unlock_irqrestore(&info->lock,flags); | |
3125 | goto exit; | |
3126 | } | |
3127 | ||
3128 | /* save current irq counts */ | |
3129 | cprev = info->icount; | |
3130 | oldsigs = info->input_signal_events; | |
3131 | ||
3132 | /* enable hunt and idle irqs if needed */ | |
3133 | if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { | |
3134 | unsigned char oldval = info->ie1_value; | |
3135 | unsigned char newval = oldval + | |
3136 | (mask & MgslEvent_ExitHuntMode ? FLGD:0) + | |
3137 | (mask & MgslEvent_IdleReceived ? IDLD:0); | |
3138 | if ( oldval != newval ) { | |
3139 | info->ie1_value = newval; | |
3140 | write_reg(info, IE1, info->ie1_value); | |
3141 | } | |
3142 | } | |
3143 | ||
3144 | set_current_state(TASK_INTERRUPTIBLE); | |
3145 | add_wait_queue(&info->event_wait_q, &wait); | |
3146 | ||
3147 | spin_unlock_irqrestore(&info->lock,flags); | |
3148 | ||
3149 | for(;;) { | |
3150 | schedule(); | |
3151 | if (signal_pending(current)) { | |
3152 | rc = -ERESTARTSYS; | |
3153 | break; | |
3154 | } | |
3155 | ||
3156 | /* get current irq counts */ | |
3157 | spin_lock_irqsave(&info->lock,flags); | |
3158 | cnow = info->icount; | |
3159 | newsigs = info->input_signal_events; | |
3160 | set_current_state(TASK_INTERRUPTIBLE); | |
3161 | spin_unlock_irqrestore(&info->lock,flags); | |
3162 | ||
3163 | /* if no change, wait aborted for some reason */ | |
3164 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
3165 | newsigs.dsr_down == oldsigs.dsr_down && | |
3166 | newsigs.dcd_up == oldsigs.dcd_up && | |
3167 | newsigs.dcd_down == oldsigs.dcd_down && | |
3168 | newsigs.cts_up == oldsigs.cts_up && | |
3169 | newsigs.cts_down == oldsigs.cts_down && | |
3170 | newsigs.ri_up == oldsigs.ri_up && | |
3171 | newsigs.ri_down == oldsigs.ri_down && | |
3172 | cnow.exithunt == cprev.exithunt && | |
3173 | cnow.rxidle == cprev.rxidle) { | |
3174 | rc = -EIO; | |
3175 | break; | |
3176 | } | |
3177 | ||
3178 | events = mask & | |
3179 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
3180 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
3181 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
3182 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
3183 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
3184 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
3185 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
3186 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
3187 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
3188 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
3189 | if (events) | |
3190 | break; | |
3191 | ||
3192 | cprev = cnow; | |
3193 | oldsigs = newsigs; | |
3194 | } | |
3195 | ||
3196 | remove_wait_queue(&info->event_wait_q, &wait); | |
3197 | set_current_state(TASK_RUNNING); | |
3198 | ||
3199 | ||
3200 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
3201 | spin_lock_irqsave(&info->lock,flags); | |
3202 | if (!waitqueue_active(&info->event_wait_q)) { | |
3203 | /* disable enable exit hunt mode/idle rcvd IRQs */ | |
3204 | info->ie1_value &= ~(FLGD|IDLD); | |
3205 | write_reg(info, IE1, info->ie1_value); | |
3206 | } | |
3207 | spin_unlock_irqrestore(&info->lock,flags); | |
3208 | } | |
3209 | exit: | |
3210 | if ( rc == 0 ) | |
3211 | PUT_USER(rc, events, mask_ptr); | |
3212 | ||
3213 | return rc; | |
3214 | } | |
3215 | ||
3216 | static int modem_input_wait(SLMP_INFO *info,int arg) | |
3217 | { | |
3218 | unsigned long flags; | |
3219 | int rc; | |
3220 | struct mgsl_icount cprev, cnow; | |
3221 | DECLARE_WAITQUEUE(wait, current); | |
3222 | ||
3223 | /* save current irq counts */ | |
3224 | spin_lock_irqsave(&info->lock,flags); | |
3225 | cprev = info->icount; | |
3226 | add_wait_queue(&info->status_event_wait_q, &wait); | |
3227 | set_current_state(TASK_INTERRUPTIBLE); | |
3228 | spin_unlock_irqrestore(&info->lock,flags); | |
3229 | ||
3230 | for(;;) { | |
3231 | schedule(); | |
3232 | if (signal_pending(current)) { | |
3233 | rc = -ERESTARTSYS; | |
3234 | break; | |
3235 | } | |
3236 | ||
3237 | /* get new irq counts */ | |
3238 | spin_lock_irqsave(&info->lock,flags); | |
3239 | cnow = info->icount; | |
3240 | set_current_state(TASK_INTERRUPTIBLE); | |
3241 | spin_unlock_irqrestore(&info->lock,flags); | |
3242 | ||
3243 | /* if no change, wait aborted for some reason */ | |
3244 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
3245 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
3246 | rc = -EIO; | |
3247 | break; | |
3248 | } | |
3249 | ||
3250 | /* check for change in caller specified modem input */ | |
3251 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
3252 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
3253 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
3254 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
3255 | rc = 0; | |
3256 | break; | |
3257 | } | |
3258 | ||
3259 | cprev = cnow; | |
3260 | } | |
3261 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
3262 | set_current_state(TASK_RUNNING); | |
3263 | return rc; | |
3264 | } | |
3265 | ||
3266 | /* return the state of the serial control and status signals | |
3267 | */ | |
3268 | static int tiocmget(struct tty_struct *tty, struct file *file) | |
3269 | { | |
3270 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
3271 | unsigned int result; | |
3272 | unsigned long flags; | |
3273 | ||
3274 | spin_lock_irqsave(&info->lock,flags); | |
3275 | get_signals(info); | |
3276 | spin_unlock_irqrestore(&info->lock,flags); | |
3277 | ||
3278 | result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) + | |
3279 | ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) + | |
3280 | ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) + | |
3281 | ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) + | |
3282 | ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) + | |
3283 | ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0); | |
3284 | ||
3285 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3286 | printk("%s(%d):%s tiocmget() value=%08X\n", | |
3287 | __FILE__,__LINE__, info->device_name, result ); | |
3288 | return result; | |
3289 | } | |
3290 | ||
3291 | /* set modem control signals (DTR/RTS) | |
3292 | */ | |
3293 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
3294 | unsigned int set, unsigned int clear) | |
3295 | { | |
3296 | SLMP_INFO *info = (SLMP_INFO *)tty->driver_data; | |
3297 | unsigned long flags; | |
3298 | ||
3299 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3300 | printk("%s(%d):%s tiocmset(%x,%x)\n", | |
3301 | __FILE__,__LINE__,info->device_name, set, clear); | |
3302 | ||
3303 | if (set & TIOCM_RTS) | |
3304 | info->serial_signals |= SerialSignal_RTS; | |
3305 | if (set & TIOCM_DTR) | |
3306 | info->serial_signals |= SerialSignal_DTR; | |
3307 | if (clear & TIOCM_RTS) | |
3308 | info->serial_signals &= ~SerialSignal_RTS; | |
3309 | if (clear & TIOCM_DTR) | |
3310 | info->serial_signals &= ~SerialSignal_DTR; | |
3311 | ||
3312 | spin_lock_irqsave(&info->lock,flags); | |
3313 | set_signals(info); | |
3314 | spin_unlock_irqrestore(&info->lock,flags); | |
3315 | ||
3316 | return 0; | |
3317 | } | |
3318 | ||
3319 | ||
3320 | ||
3321 | /* Block the current process until the specified port is ready to open. | |
3322 | */ | |
3323 | static int block_til_ready(struct tty_struct *tty, struct file *filp, | |
3324 | SLMP_INFO *info) | |
3325 | { | |
3326 | DECLARE_WAITQUEUE(wait, current); | |
3327 | int retval; | |
3328 | int do_clocal = 0, extra_count = 0; | |
3329 | unsigned long flags; | |
3330 | ||
3331 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3332 | printk("%s(%d):%s block_til_ready()\n", | |
3333 | __FILE__,__LINE__, tty->driver->name ); | |
3334 | ||
3335 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ | |
3336 | /* nonblock mode is set or port is not enabled */ | |
3337 | /* just verify that callout device is not active */ | |
3338 | info->flags |= ASYNC_NORMAL_ACTIVE; | |
3339 | return 0; | |
3340 | } | |
3341 | ||
3342 | if (tty->termios->c_cflag & CLOCAL) | |
3343 | do_clocal = 1; | |
3344 | ||
3345 | /* Wait for carrier detect and the line to become | |
3346 | * free (i.e., not in use by the callout). While we are in | |
3347 | * this loop, info->count is dropped by one, so that | |
3348 | * close() knows when to free things. We restore it upon | |
3349 | * exit, either normal or abnormal. | |
3350 | */ | |
3351 | ||
3352 | retval = 0; | |
3353 | add_wait_queue(&info->open_wait, &wait); | |
3354 | ||
3355 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3356 | printk("%s(%d):%s block_til_ready() before block, count=%d\n", | |
3357 | __FILE__,__LINE__, tty->driver->name, info->count ); | |
3358 | ||
3359 | spin_lock_irqsave(&info->lock, flags); | |
3360 | if (!tty_hung_up_p(filp)) { | |
3361 | extra_count = 1; | |
3362 | info->count--; | |
3363 | } | |
3364 | spin_unlock_irqrestore(&info->lock, flags); | |
3365 | info->blocked_open++; | |
3366 | ||
3367 | while (1) { | |
3368 | if ((tty->termios->c_cflag & CBAUD)) { | |
3369 | spin_lock_irqsave(&info->lock,flags); | |
3370 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; | |
3371 | set_signals(info); | |
3372 | spin_unlock_irqrestore(&info->lock,flags); | |
3373 | } | |
3374 | ||
3375 | set_current_state(TASK_INTERRUPTIBLE); | |
3376 | ||
3377 | if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){ | |
3378 | retval = (info->flags & ASYNC_HUP_NOTIFY) ? | |
3379 | -EAGAIN : -ERESTARTSYS; | |
3380 | break; | |
3381 | } | |
3382 | ||
3383 | spin_lock_irqsave(&info->lock,flags); | |
3384 | get_signals(info); | |
3385 | spin_unlock_irqrestore(&info->lock,flags); | |
3386 | ||
3387 | if (!(info->flags & ASYNC_CLOSING) && | |
3388 | (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) { | |
3389 | break; | |
3390 | } | |
3391 | ||
3392 | if (signal_pending(current)) { | |
3393 | retval = -ERESTARTSYS; | |
3394 | break; | |
3395 | } | |
3396 | ||
3397 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3398 | printk("%s(%d):%s block_til_ready() count=%d\n", | |
3399 | __FILE__,__LINE__, tty->driver->name, info->count ); | |
3400 | ||
3401 | schedule(); | |
3402 | } | |
3403 | ||
3404 | set_current_state(TASK_RUNNING); | |
3405 | remove_wait_queue(&info->open_wait, &wait); | |
3406 | ||
3407 | if (extra_count) | |
3408 | info->count++; | |
3409 | info->blocked_open--; | |
3410 | ||
3411 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3412 | printk("%s(%d):%s block_til_ready() after, count=%d\n", | |
3413 | __FILE__,__LINE__, tty->driver->name, info->count ); | |
3414 | ||
3415 | if (!retval) | |
3416 | info->flags |= ASYNC_NORMAL_ACTIVE; | |
3417 | ||
3418 | return retval; | |
3419 | } | |
3420 | ||
3421 | int alloc_dma_bufs(SLMP_INFO *info) | |
3422 | { | |
3423 | unsigned short BuffersPerFrame; | |
3424 | unsigned short BufferCount; | |
3425 | ||
3426 | // Force allocation to start at 64K boundary for each port. | |
3427 | // This is necessary because *all* buffer descriptors for a port | |
3428 | // *must* be in the same 64K block. All descriptors on a port | |
3429 | // share a common 'base' address (upper 8 bits of 24 bits) programmed | |
3430 | // into the CBP register. | |
3431 | info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num; | |
3432 | ||
3433 | /* Calculate the number of DMA buffers necessary to hold the */ | |
3434 | /* largest allowable frame size. Note: If the max frame size is */ | |
3435 | /* not an even multiple of the DMA buffer size then we need to */ | |
3436 | /* round the buffer count per frame up one. */ | |
3437 | ||
3438 | BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE); | |
3439 | if ( info->max_frame_size % SCABUFSIZE ) | |
3440 | BuffersPerFrame++; | |
3441 | ||
3442 | /* calculate total number of data buffers (SCABUFSIZE) possible | |
3443 | * in one ports memory (SCA_MEM_SIZE/4) after allocating memory | |
3444 | * for the descriptor list (BUFFERLISTSIZE). | |
3445 | */ | |
3446 | BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE; | |
3447 | ||
3448 | /* limit number of buffers to maximum amount of descriptors */ | |
3449 | if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC)) | |
3450 | BufferCount = BUFFERLISTSIZE/sizeof(SCADESC); | |
3451 | ||
3452 | /* use enough buffers to transmit one max size frame */ | |
3453 | info->tx_buf_count = BuffersPerFrame + 1; | |
3454 | ||
3455 | /* never use more than half the available buffers for transmit */ | |
3456 | if (info->tx_buf_count > (BufferCount/2)) | |
3457 | info->tx_buf_count = BufferCount/2; | |
3458 | ||
3459 | if (info->tx_buf_count > SCAMAXDESC) | |
3460 | info->tx_buf_count = SCAMAXDESC; | |
3461 | ||
3462 | /* use remaining buffers for receive */ | |
3463 | info->rx_buf_count = BufferCount - info->tx_buf_count; | |
3464 | ||
3465 | if (info->rx_buf_count > SCAMAXDESC) | |
3466 | info->rx_buf_count = SCAMAXDESC; | |
3467 | ||
3468 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3469 | printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n", | |
3470 | __FILE__,__LINE__, info->device_name, | |
3471 | info->tx_buf_count,info->rx_buf_count); | |
3472 | ||
3473 | if ( alloc_buf_list( info ) < 0 || | |
3474 | alloc_frame_bufs(info, | |
3475 | info->rx_buf_list, | |
3476 | info->rx_buf_list_ex, | |
3477 | info->rx_buf_count) < 0 || | |
3478 | alloc_frame_bufs(info, | |
3479 | info->tx_buf_list, | |
3480 | info->tx_buf_list_ex, | |
3481 | info->tx_buf_count) < 0 || | |
3482 | alloc_tmp_rx_buf(info) < 0 ) { | |
3483 | printk("%s(%d):%s Can't allocate DMA buffer memory\n", | |
3484 | __FILE__,__LINE__, info->device_name); | |
3485 | return -ENOMEM; | |
3486 | } | |
3487 | ||
3488 | rx_reset_buffers( info ); | |
3489 | ||
3490 | return 0; | |
3491 | } | |
3492 | ||
3493 | /* Allocate DMA buffers for the transmit and receive descriptor lists. | |
3494 | */ | |
3495 | int alloc_buf_list(SLMP_INFO *info) | |
3496 | { | |
3497 | unsigned int i; | |
3498 | ||
3499 | /* build list in adapter shared memory */ | |
3500 | info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc; | |
3501 | info->buffer_list_phys = info->port_array[0]->last_mem_alloc; | |
3502 | info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE; | |
3503 | ||
3504 | memset(info->buffer_list, 0, BUFFERLISTSIZE); | |
3505 | ||
3506 | /* Save virtual address pointers to the receive and */ | |
3507 | /* transmit buffer lists. (Receive 1st). These pointers will */ | |
3508 | /* be used by the processor to access the lists. */ | |
3509 | info->rx_buf_list = (SCADESC *)info->buffer_list; | |
3510 | ||
3511 | info->tx_buf_list = (SCADESC *)info->buffer_list; | |
3512 | info->tx_buf_list += info->rx_buf_count; | |
3513 | ||
3514 | /* Build links for circular buffer entry lists (tx and rx) | |
3515 | * | |
3516 | * Note: links are physical addresses read by the SCA device | |
3517 | * to determine the next buffer entry to use. | |
3518 | */ | |
3519 | ||
3520 | for ( i = 0; i < info->rx_buf_count; i++ ) { | |
3521 | /* calculate and store physical address of this buffer entry */ | |
3522 | info->rx_buf_list_ex[i].phys_entry = | |
3523 | info->buffer_list_phys + (i * sizeof(SCABUFSIZE)); | |
3524 | ||
3525 | /* calculate and store physical address of */ | |
3526 | /* next entry in cirular list of entries */ | |
3527 | info->rx_buf_list[i].next = info->buffer_list_phys; | |
3528 | if ( i < info->rx_buf_count - 1 ) | |
3529 | info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC); | |
3530 | ||
3531 | info->rx_buf_list[i].length = SCABUFSIZE; | |
3532 | } | |
3533 | ||
3534 | for ( i = 0; i < info->tx_buf_count; i++ ) { | |
3535 | /* calculate and store physical address of this buffer entry */ | |
3536 | info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys + | |
3537 | ((info->rx_buf_count + i) * sizeof(SCADESC)); | |
3538 | ||
3539 | /* calculate and store physical address of */ | |
3540 | /* next entry in cirular list of entries */ | |
3541 | ||
3542 | info->tx_buf_list[i].next = info->buffer_list_phys + | |
3543 | info->rx_buf_count * sizeof(SCADESC); | |
3544 | ||
3545 | if ( i < info->tx_buf_count - 1 ) | |
3546 | info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC); | |
3547 | } | |
3548 | ||
3549 | return 0; | |
3550 | } | |
3551 | ||
3552 | /* Allocate the frame DMA buffers used by the specified buffer list. | |
3553 | */ | |
3554 | int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count) | |
3555 | { | |
3556 | int i; | |
3557 | unsigned long phys_addr; | |
3558 | ||
3559 | for ( i = 0; i < count; i++ ) { | |
3560 | buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc; | |
3561 | phys_addr = info->port_array[0]->last_mem_alloc; | |
3562 | info->port_array[0]->last_mem_alloc += SCABUFSIZE; | |
3563 | ||
3564 | buf_list[i].buf_ptr = (unsigned short)phys_addr; | |
3565 | buf_list[i].buf_base = (unsigned char)(phys_addr >> 16); | |
3566 | } | |
3567 | ||
3568 | return 0; | |
3569 | } | |
3570 | ||
3571 | void free_dma_bufs(SLMP_INFO *info) | |
3572 | { | |
3573 | info->buffer_list = NULL; | |
3574 | info->rx_buf_list = NULL; | |
3575 | info->tx_buf_list = NULL; | |
3576 | } | |
3577 | ||
3578 | /* allocate buffer large enough to hold max_frame_size. | |
3579 | * This buffer is used to pass an assembled frame to the line discipline. | |
3580 | */ | |
3581 | int alloc_tmp_rx_buf(SLMP_INFO *info) | |
3582 | { | |
3583 | info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); | |
3584 | if (info->tmp_rx_buf == NULL) | |
3585 | return -ENOMEM; | |
3586 | return 0; | |
3587 | } | |
3588 | ||
3589 | void free_tmp_rx_buf(SLMP_INFO *info) | |
3590 | { | |
735d5661 | 3591 | kfree(info->tmp_rx_buf); |
1da177e4 LT |
3592 | info->tmp_rx_buf = NULL; |
3593 | } | |
3594 | ||
3595 | int claim_resources(SLMP_INFO *info) | |
3596 | { | |
3597 | if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) { | |
3598 | printk( "%s(%d):%s mem addr conflict, Addr=%08X\n", | |
3599 | __FILE__,__LINE__,info->device_name, info->phys_memory_base); | |
3600 | info->init_error = DiagStatus_AddressConflict; | |
3601 | goto errout; | |
3602 | } | |
3603 | else | |
3604 | info->shared_mem_requested = 1; | |
3605 | ||
3606 | if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) { | |
3607 | printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n", | |
3608 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base); | |
3609 | info->init_error = DiagStatus_AddressConflict; | |
3610 | goto errout; | |
3611 | } | |
3612 | else | |
3613 | info->lcr_mem_requested = 1; | |
3614 | ||
3615 | if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) { | |
3616 | printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n", | |
3617 | __FILE__,__LINE__,info->device_name, info->phys_sca_base); | |
3618 | info->init_error = DiagStatus_AddressConflict; | |
3619 | goto errout; | |
3620 | } | |
3621 | else | |
3622 | info->sca_base_requested = 1; | |
3623 | ||
3624 | if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) { | |
3625 | printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n", | |
3626 | __FILE__,__LINE__,info->device_name, info->phys_statctrl_base); | |
3627 | info->init_error = DiagStatus_AddressConflict; | |
3628 | goto errout; | |
3629 | } | |
3630 | else | |
3631 | info->sca_statctrl_requested = 1; | |
3632 | ||
3633 | info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE); | |
3634 | if (!info->memory_base) { | |
3635 | printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n", | |
3636 | __FILE__,__LINE__,info->device_name, info->phys_memory_base ); | |
3637 | info->init_error = DiagStatus_CantAssignPciResources; | |
3638 | goto errout; | |
3639 | } | |
3640 | ||
3641 | info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE); | |
3642 | if (!info->lcr_base) { | |
3643 | printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n", | |
3644 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); | |
3645 | info->init_error = DiagStatus_CantAssignPciResources; | |
3646 | goto errout; | |
3647 | } | |
3648 | info->lcr_base += info->lcr_offset; | |
3649 | ||
3650 | info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE); | |
3651 | if (!info->sca_base) { | |
3652 | printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n", | |
3653 | __FILE__,__LINE__,info->device_name, info->phys_sca_base ); | |
3654 | info->init_error = DiagStatus_CantAssignPciResources; | |
3655 | goto errout; | |
3656 | } | |
3657 | info->sca_base += info->sca_offset; | |
3658 | ||
3659 | info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE); | |
3660 | if (!info->statctrl_base) { | |
3661 | printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n", | |
3662 | __FILE__,__LINE__,info->device_name, info->phys_statctrl_base ); | |
3663 | info->init_error = DiagStatus_CantAssignPciResources; | |
3664 | goto errout; | |
3665 | } | |
3666 | info->statctrl_base += info->statctrl_offset; | |
3667 | ||
3668 | if ( !memory_test(info) ) { | |
3669 | printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n", | |
3670 | __FILE__,__LINE__,info->device_name, info->phys_memory_base ); | |
3671 | info->init_error = DiagStatus_MemoryError; | |
3672 | goto errout; | |
3673 | } | |
3674 | ||
3675 | return 0; | |
3676 | ||
3677 | errout: | |
3678 | release_resources( info ); | |
3679 | return -ENODEV; | |
3680 | } | |
3681 | ||
3682 | void release_resources(SLMP_INFO *info) | |
3683 | { | |
3684 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3685 | printk( "%s(%d):%s release_resources() entry\n", | |
3686 | __FILE__,__LINE__,info->device_name ); | |
3687 | ||
3688 | if ( info->irq_requested ) { | |
3689 | free_irq(info->irq_level, info); | |
3690 | info->irq_requested = 0; | |
3691 | } | |
3692 | ||
3693 | if ( info->shared_mem_requested ) { | |
3694 | release_mem_region(info->phys_memory_base,SCA_MEM_SIZE); | |
3695 | info->shared_mem_requested = 0; | |
3696 | } | |
3697 | if ( info->lcr_mem_requested ) { | |
3698 | release_mem_region(info->phys_lcr_base + info->lcr_offset,128); | |
3699 | info->lcr_mem_requested = 0; | |
3700 | } | |
3701 | if ( info->sca_base_requested ) { | |
3702 | release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE); | |
3703 | info->sca_base_requested = 0; | |
3704 | } | |
3705 | if ( info->sca_statctrl_requested ) { | |
3706 | release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE); | |
3707 | info->sca_statctrl_requested = 0; | |
3708 | } | |
3709 | ||
3710 | if (info->memory_base){ | |
3711 | iounmap(info->memory_base); | |
3712 | info->memory_base = NULL; | |
3713 | } | |
3714 | ||
3715 | if (info->sca_base) { | |
3716 | iounmap(info->sca_base - info->sca_offset); | |
3717 | info->sca_base=NULL; | |
3718 | } | |
3719 | ||
3720 | if (info->statctrl_base) { | |
3721 | iounmap(info->statctrl_base - info->statctrl_offset); | |
3722 | info->statctrl_base=NULL; | |
3723 | } | |
3724 | ||
3725 | if (info->lcr_base){ | |
3726 | iounmap(info->lcr_base - info->lcr_offset); | |
3727 | info->lcr_base = NULL; | |
3728 | } | |
3729 | ||
3730 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3731 | printk( "%s(%d):%s release_resources() exit\n", | |
3732 | __FILE__,__LINE__,info->device_name ); | |
3733 | } | |
3734 | ||
3735 | /* Add the specified device instance data structure to the | |
3736 | * global linked list of devices and increment the device count. | |
3737 | */ | |
3738 | void add_device(SLMP_INFO *info) | |
3739 | { | |
3740 | info->next_device = NULL; | |
3741 | info->line = synclinkmp_device_count; | |
3742 | sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num); | |
3743 | ||
3744 | if (info->line < MAX_DEVICES) { | |
3745 | if (maxframe[info->line]) | |
3746 | info->max_frame_size = maxframe[info->line]; | |
3747 | info->dosyncppp = dosyncppp[info->line]; | |
3748 | } | |
3749 | ||
3750 | synclinkmp_device_count++; | |
3751 | ||
3752 | if ( !synclinkmp_device_list ) | |
3753 | synclinkmp_device_list = info; | |
3754 | else { | |
3755 | SLMP_INFO *current_dev = synclinkmp_device_list; | |
3756 | while( current_dev->next_device ) | |
3757 | current_dev = current_dev->next_device; | |
3758 | current_dev->next_device = info; | |
3759 | } | |
3760 | ||
3761 | if ( info->max_frame_size < 4096 ) | |
3762 | info->max_frame_size = 4096; | |
3763 | else if ( info->max_frame_size > 65535 ) | |
3764 | info->max_frame_size = 65535; | |
3765 | ||
3766 | printk( "SyncLink MultiPort %s: " | |
3767 | "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", | |
3768 | info->device_name, | |
3769 | info->phys_sca_base, | |
3770 | info->phys_memory_base, | |
3771 | info->phys_statctrl_base, | |
3772 | info->phys_lcr_base, | |
3773 | info->irq_level, | |
3774 | info->max_frame_size ); | |
3775 | ||
af69c7f9 | 3776 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
3777 | hdlcdev_init(info); |
3778 | #endif | |
3779 | } | |
3780 | ||
3781 | /* Allocate and initialize a device instance structure | |
3782 | * | |
3783 | * Return Value: pointer to SLMP_INFO if success, otherwise NULL | |
3784 | */ | |
3785 | static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) | |
3786 | { | |
3787 | SLMP_INFO *info; | |
3788 | ||
5cbded58 | 3789 | info = kmalloc(sizeof(SLMP_INFO), |
1da177e4 LT |
3790 | GFP_KERNEL); |
3791 | ||
3792 | if (!info) { | |
3793 | printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n", | |
3794 | __FILE__,__LINE__, adapter_num, port_num); | |
3795 | } else { | |
3796 | memset(info, 0, sizeof(SLMP_INFO)); | |
3797 | info->magic = MGSL_MAGIC; | |
c4028958 | 3798 | INIT_WORK(&info->task, bh_handler); |
1da177e4 LT |
3799 | info->max_frame_size = 4096; |
3800 | info->close_delay = 5*HZ/10; | |
3801 | info->closing_wait = 30*HZ; | |
3802 | init_waitqueue_head(&info->open_wait); | |
3803 | init_waitqueue_head(&info->close_wait); | |
3804 | init_waitqueue_head(&info->status_event_wait_q); | |
3805 | init_waitqueue_head(&info->event_wait_q); | |
3806 | spin_lock_init(&info->netlock); | |
3807 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
3808 | info->idle_mode = HDLC_TXIDLE_FLAGS; | |
3809 | info->adapter_num = adapter_num; | |
3810 | info->port_num = port_num; | |
3811 | ||
3812 | /* Copy configuration info to device instance data */ | |
3813 | info->irq_level = pdev->irq; | |
3814 | info->phys_lcr_base = pci_resource_start(pdev,0); | |
3815 | info->phys_sca_base = pci_resource_start(pdev,2); | |
3816 | info->phys_memory_base = pci_resource_start(pdev,3); | |
3817 | info->phys_statctrl_base = pci_resource_start(pdev,4); | |
3818 | ||
3819 | /* Because veremap only works on page boundaries we must map | |
3820 | * a larger area than is actually implemented for the LCR | |
3821 | * memory range. We map a full page starting at the page boundary. | |
3822 | */ | |
3823 | info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1); | |
3824 | info->phys_lcr_base &= ~(PAGE_SIZE-1); | |
3825 | ||
3826 | info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1); | |
3827 | info->phys_sca_base &= ~(PAGE_SIZE-1); | |
3828 | ||
3829 | info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1); | |
3830 | info->phys_statctrl_base &= ~(PAGE_SIZE-1); | |
3831 | ||
3832 | info->bus_type = MGSL_BUS_TYPE_PCI; | |
0f2ed4c6 | 3833 | info->irq_flags = IRQF_SHARED; |
1da177e4 | 3834 | |
40565f19 JS |
3835 | setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); |
3836 | setup_timer(&info->status_timer, status_timeout, | |
3837 | (unsigned long)info); | |
1da177e4 LT |
3838 | |
3839 | /* Store the PCI9050 misc control register value because a flaw | |
3840 | * in the PCI9050 prevents LCR registers from being read if | |
3841 | * BIOS assigns an LCR base address with bit 7 set. | |
3842 | * | |
3843 | * Only the misc control register is accessed for which only | |
3844 | * write access is needed, so set an initial value and change | |
3845 | * bits to the device instance data as we write the value | |
3846 | * to the actual misc control register. | |
3847 | */ | |
3848 | info->misc_ctrl_value = 0x087e4546; | |
3849 | ||
3850 | /* initial port state is unknown - if startup errors | |
3851 | * occur, init_error will be set to indicate the | |
3852 | * problem. Once the port is fully initialized, | |
3853 | * this value will be set to 0 to indicate the | |
3854 | * port is available. | |
3855 | */ | |
3856 | info->init_error = -1; | |
3857 | } | |
3858 | ||
3859 | return info; | |
3860 | } | |
3861 | ||
3862 | void device_init(int adapter_num, struct pci_dev *pdev) | |
3863 | { | |
3864 | SLMP_INFO *port_array[SCA_MAX_PORTS]; | |
3865 | int port; | |
3866 | ||
3867 | /* allocate device instances for up to SCA_MAX_PORTS devices */ | |
3868 | for ( port = 0; port < SCA_MAX_PORTS; ++port ) { | |
3869 | port_array[port] = alloc_dev(adapter_num,port,pdev); | |
3870 | if( port_array[port] == NULL ) { | |
3871 | for ( --port; port >= 0; --port ) | |
3872 | kfree(port_array[port]); | |
3873 | return; | |
3874 | } | |
3875 | } | |
3876 | ||
3877 | /* give copy of port_array to all ports and add to device list */ | |
3878 | for ( port = 0; port < SCA_MAX_PORTS; ++port ) { | |
3879 | memcpy(port_array[port]->port_array,port_array,sizeof(port_array)); | |
3880 | add_device( port_array[port] ); | |
3881 | spin_lock_init(&port_array[port]->lock); | |
3882 | } | |
3883 | ||
3884 | /* Allocate and claim adapter resources */ | |
3885 | if ( !claim_resources(port_array[0]) ) { | |
3886 | ||
3887 | alloc_dma_bufs(port_array[0]); | |
3888 | ||
3889 | /* copy resource information from first port to others */ | |
3890 | for ( port = 1; port < SCA_MAX_PORTS; ++port ) { | |
3891 | port_array[port]->lock = port_array[0]->lock; | |
3892 | port_array[port]->irq_level = port_array[0]->irq_level; | |
3893 | port_array[port]->memory_base = port_array[0]->memory_base; | |
3894 | port_array[port]->sca_base = port_array[0]->sca_base; | |
3895 | port_array[port]->statctrl_base = port_array[0]->statctrl_base; | |
3896 | port_array[port]->lcr_base = port_array[0]->lcr_base; | |
3897 | alloc_dma_bufs(port_array[port]); | |
3898 | } | |
3899 | ||
3900 | if ( request_irq(port_array[0]->irq_level, | |
3901 | synclinkmp_interrupt, | |
3902 | port_array[0]->irq_flags, | |
3903 | port_array[0]->device_name, | |
3904 | port_array[0]) < 0 ) { | |
3905 | printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n", | |
3906 | __FILE__,__LINE__, | |
3907 | port_array[0]->device_name, | |
3908 | port_array[0]->irq_level ); | |
3909 | } | |
3910 | else { | |
3911 | port_array[0]->irq_requested = 1; | |
3912 | adapter_test(port_array[0]); | |
3913 | } | |
3914 | } | |
3915 | } | |
3916 | ||
b68e31d0 | 3917 | static const struct tty_operations ops = { |
1da177e4 LT |
3918 | .open = open, |
3919 | .close = close, | |
3920 | .write = write, | |
3921 | .put_char = put_char, | |
3922 | .flush_chars = flush_chars, | |
3923 | .write_room = write_room, | |
3924 | .chars_in_buffer = chars_in_buffer, | |
3925 | .flush_buffer = flush_buffer, | |
3926 | .ioctl = ioctl, | |
3927 | .throttle = throttle, | |
3928 | .unthrottle = unthrottle, | |
3929 | .send_xchar = send_xchar, | |
3930 | .break_ctl = set_break, | |
3931 | .wait_until_sent = wait_until_sent, | |
3932 | .read_proc = read_proc, | |
3933 | .set_termios = set_termios, | |
3934 | .stop = tx_hold, | |
3935 | .start = tx_release, | |
3936 | .hangup = hangup, | |
3937 | .tiocmget = tiocmget, | |
3938 | .tiocmset = tiocmset, | |
3939 | }; | |
3940 | ||
3941 | static void synclinkmp_cleanup(void) | |
3942 | { | |
3943 | int rc; | |
3944 | SLMP_INFO *info; | |
3945 | SLMP_INFO *tmp; | |
3946 | ||
3947 | printk("Unloading %s %s\n", driver_name, driver_version); | |
3948 | ||
3949 | if (serial_driver) { | |
3950 | if ((rc = tty_unregister_driver(serial_driver))) | |
3951 | printk("%s(%d) failed to unregister tty driver err=%d\n", | |
3952 | __FILE__,__LINE__,rc); | |
3953 | put_tty_driver(serial_driver); | |
3954 | } | |
3955 | ||
3956 | /* reset devices */ | |
3957 | info = synclinkmp_device_list; | |
3958 | while(info) { | |
3959 | reset_port(info); | |
3960 | info = info->next_device; | |
3961 | } | |
3962 | ||
3963 | /* release devices */ | |
3964 | info = synclinkmp_device_list; | |
3965 | while(info) { | |
af69c7f9 | 3966 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
3967 | hdlcdev_exit(info); |
3968 | #endif | |
3969 | free_dma_bufs(info); | |
3970 | free_tmp_rx_buf(info); | |
3971 | if ( info->port_num == 0 ) { | |
3972 | if (info->sca_base) | |
3973 | write_reg(info, LPR, 1); /* set low power mode */ | |
3974 | release_resources(info); | |
3975 | } | |
3976 | tmp = info; | |
3977 | info = info->next_device; | |
3978 | kfree(tmp); | |
3979 | } | |
3980 | ||
3981 | pci_unregister_driver(&synclinkmp_pci_driver); | |
3982 | } | |
3983 | ||
3984 | /* Driver initialization entry point. | |
3985 | */ | |
3986 | ||
3987 | static int __init synclinkmp_init(void) | |
3988 | { | |
3989 | int rc; | |
3990 | ||
3991 | if (break_on_load) { | |
3992 | synclinkmp_get_text_ptr(); | |
3993 | BREAKPOINT(); | |
3994 | } | |
3995 | ||
3996 | printk("%s %s\n", driver_name, driver_version); | |
3997 | ||
3998 | if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) { | |
3999 | printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); | |
4000 | return rc; | |
4001 | } | |
4002 | ||
4003 | serial_driver = alloc_tty_driver(128); | |
4004 | if (!serial_driver) { | |
4005 | rc = -ENOMEM; | |
4006 | goto error; | |
4007 | } | |
4008 | ||
4009 | /* Initialize the tty_driver structure */ | |
4010 | ||
4011 | serial_driver->owner = THIS_MODULE; | |
4012 | serial_driver->driver_name = "synclinkmp"; | |
4013 | serial_driver->name = "ttySLM"; | |
4014 | serial_driver->major = ttymajor; | |
4015 | serial_driver->minor_start = 64; | |
4016 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
4017 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
4018 | serial_driver->init_termios = tty_std_termios; | |
4019 | serial_driver->init_termios.c_cflag = | |
4020 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
606d099c AC |
4021 | serial_driver->init_termios.c_ispeed = 9600; |
4022 | serial_driver->init_termios.c_ospeed = 9600; | |
1da177e4 LT |
4023 | serial_driver->flags = TTY_DRIVER_REAL_RAW; |
4024 | tty_set_operations(serial_driver, &ops); | |
4025 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
4026 | printk("%s(%d):Couldn't register serial driver\n", | |
4027 | __FILE__,__LINE__); | |
4028 | put_tty_driver(serial_driver); | |
4029 | serial_driver = NULL; | |
4030 | goto error; | |
4031 | } | |
4032 | ||
4033 | printk("%s %s, tty major#%d\n", | |
4034 | driver_name, driver_version, | |
4035 | serial_driver->major); | |
4036 | ||
4037 | return 0; | |
4038 | ||
4039 | error: | |
4040 | synclinkmp_cleanup(); | |
4041 | return rc; | |
4042 | } | |
4043 | ||
4044 | static void __exit synclinkmp_exit(void) | |
4045 | { | |
4046 | synclinkmp_cleanup(); | |
4047 | } | |
4048 | ||
4049 | module_init(synclinkmp_init); | |
4050 | module_exit(synclinkmp_exit); | |
4051 | ||
4052 | /* Set the port for internal loopback mode. | |
4053 | * The TxCLK and RxCLK signals are generated from the BRG and | |
4054 | * the TxD is looped back to the RxD internally. | |
4055 | */ | |
4056 | void enable_loopback(SLMP_INFO *info, int enable) | |
4057 | { | |
4058 | if (enable) { | |
4059 | /* MD2 (Mode Register 2) | |
4060 | * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback | |
4061 | */ | |
4062 | write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); | |
4063 | ||
4064 | /* degate external TxC clock source */ | |
4065 | info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); | |
4066 | write_control_reg(info); | |
4067 | ||
4068 | /* RXS/TXS (Rx/Tx clock source) | |
4069 | * 07 Reserved, must be 0 | |
4070 | * 06..04 Clock Source, 100=BRG | |
4071 | * 03..00 Clock Divisor, 0000=1 | |
4072 | */ | |
4073 | write_reg(info, RXS, 0x40); | |
4074 | write_reg(info, TXS, 0x40); | |
4075 | ||
4076 | } else { | |
4077 | /* MD2 (Mode Register 2) | |
4078 | * 01..00 CNCT<1..0> Channel connection, 0=normal | |
4079 | */ | |
4080 | write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); | |
4081 | ||
4082 | /* RXS/TXS (Rx/Tx clock source) | |
4083 | * 07 Reserved, must be 0 | |
4084 | * 06..04 Clock Source, 000=RxC/TxC Pin | |
4085 | * 03..00 Clock Divisor, 0000=1 | |
4086 | */ | |
4087 | write_reg(info, RXS, 0x00); | |
4088 | write_reg(info, TXS, 0x00); | |
4089 | } | |
4090 | ||
4091 | /* set LinkSpeed if available, otherwise default to 2Mbps */ | |
4092 | if (info->params.clock_speed) | |
4093 | set_rate(info, info->params.clock_speed); | |
4094 | else | |
4095 | set_rate(info, 3686400); | |
4096 | } | |
4097 | ||
4098 | /* Set the baud rate register to the desired speed | |
4099 | * | |
4100 | * data_rate data rate of clock in bits per second | |
4101 | * A data rate of 0 disables the AUX clock. | |
4102 | */ | |
4103 | void set_rate( SLMP_INFO *info, u32 data_rate ) | |
4104 | { | |
4105 | u32 TMCValue; | |
4106 | unsigned char BRValue; | |
4107 | u32 Divisor=0; | |
4108 | ||
4109 | /* fBRG = fCLK/(TMC * 2^BR) | |
4110 | */ | |
4111 | if (data_rate != 0) { | |
4112 | Divisor = 14745600/data_rate; | |
4113 | if (!Divisor) | |
4114 | Divisor = 1; | |
4115 | ||
4116 | TMCValue = Divisor; | |
4117 | ||
4118 | BRValue = 0; | |
4119 | if (TMCValue != 1 && TMCValue != 2) { | |
4120 | /* BRValue of 0 provides 50/50 duty cycle *only* when | |
4121 | * TMCValue is 1 or 2. BRValue of 1 to 9 always provides | |
4122 | * 50/50 duty cycle. | |
4123 | */ | |
4124 | BRValue = 1; | |
4125 | TMCValue >>= 1; | |
4126 | } | |
4127 | ||
4128 | /* while TMCValue is too big for TMC register, divide | |
4129 | * by 2 and increment BR exponent. | |
4130 | */ | |
4131 | for(; TMCValue > 256 && BRValue < 10; BRValue++) | |
4132 | TMCValue >>= 1; | |
4133 | ||
4134 | write_reg(info, TXS, | |
4135 | (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue)); | |
4136 | write_reg(info, RXS, | |
4137 | (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue)); | |
4138 | write_reg(info, TMC, (unsigned char)TMCValue); | |
4139 | } | |
4140 | else { | |
4141 | write_reg(info, TXS,0); | |
4142 | write_reg(info, RXS,0); | |
4143 | write_reg(info, TMC, 0); | |
4144 | } | |
4145 | } | |
4146 | ||
4147 | /* Disable receiver | |
4148 | */ | |
4149 | void rx_stop(SLMP_INFO *info) | |
4150 | { | |
4151 | if (debug_level >= DEBUG_LEVEL_ISR) | |
4152 | printk("%s(%d):%s rx_stop()\n", | |
4153 | __FILE__,__LINE__, info->device_name ); | |
4154 | ||
4155 | write_reg(info, CMD, RXRESET); | |
4156 | ||
4157 | info->ie0_value &= ~RXRDYE; | |
4158 | write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */ | |
4159 | ||
4160 | write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ | |
4161 | write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ | |
4162 | write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */ | |
4163 | ||
4164 | info->rx_enabled = 0; | |
4165 | info->rx_overflow = 0; | |
4166 | } | |
4167 | ||
4168 | /* enable the receiver | |
4169 | */ | |
4170 | void rx_start(SLMP_INFO *info) | |
4171 | { | |
4172 | int i; | |
4173 | ||
4174 | if (debug_level >= DEBUG_LEVEL_ISR) | |
4175 | printk("%s(%d):%s rx_start()\n", | |
4176 | __FILE__,__LINE__, info->device_name ); | |
4177 | ||
4178 | write_reg(info, CMD, RXRESET); | |
4179 | ||
4180 | if ( info->params.mode == MGSL_MODE_HDLC ) { | |
4181 | /* HDLC, disabe IRQ on rxdata */ | |
4182 | info->ie0_value &= ~RXRDYE; | |
4183 | write_reg(info, IE0, info->ie0_value); | |
4184 | ||
4185 | /* Reset all Rx DMA buffers and program rx dma */ | |
4186 | write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ | |
4187 | write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ | |
4188 | ||
4189 | for (i = 0; i < info->rx_buf_count; i++) { | |
4190 | info->rx_buf_list[i].status = 0xff; | |
4191 | ||
4192 | // throttle to 4 shared memory writes at a time to prevent | |
4193 | // hogging local bus (keep latency time for DMA requests low). | |
4194 | if (!(i % 4)) | |
4195 | read_status_reg(info); | |
4196 | } | |
4197 | info->current_rx_buf = 0; | |
4198 | ||
4199 | /* set current/1st descriptor address */ | |
4200 | write_reg16(info, RXDMA + CDA, | |
4201 | info->rx_buf_list_ex[0].phys_entry); | |
4202 | ||
4203 | /* set new last rx descriptor address */ | |
4204 | write_reg16(info, RXDMA + EDA, | |
4205 | info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry); | |
4206 | ||
4207 | /* set buffer length (shared by all rx dma data buffers) */ | |
4208 | write_reg16(info, RXDMA + BFL, SCABUFSIZE); | |
4209 | ||
4210 | write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */ | |
4211 | write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ | |
4212 | } else { | |
4213 | /* async, enable IRQ on rxdata */ | |
4214 | info->ie0_value |= RXRDYE; | |
4215 | write_reg(info, IE0, info->ie0_value); | |
4216 | } | |
4217 | ||
4218 | write_reg(info, CMD, RXENABLE); | |
4219 | ||
4220 | info->rx_overflow = FALSE; | |
4221 | info->rx_enabled = 1; | |
4222 | } | |
4223 | ||
4224 | /* Enable the transmitter and send a transmit frame if | |
4225 | * one is loaded in the DMA buffers. | |
4226 | */ | |
4227 | void tx_start(SLMP_INFO *info) | |
4228 | { | |
4229 | if (debug_level >= DEBUG_LEVEL_ISR) | |
4230 | printk("%s(%d):%s tx_start() tx_count=%d\n", | |
4231 | __FILE__,__LINE__, info->device_name,info->tx_count ); | |
4232 | ||
4233 | if (!info->tx_enabled ) { | |
4234 | write_reg(info, CMD, TXRESET); | |
4235 | write_reg(info, CMD, TXENABLE); | |
4236 | info->tx_enabled = TRUE; | |
4237 | } | |
4238 | ||
4239 | if ( info->tx_count ) { | |
4240 | ||
4241 | /* If auto RTS enabled and RTS is inactive, then assert */ | |
4242 | /* RTS and set a flag indicating that the driver should */ | |
4243 | /* negate RTS when the transmission completes. */ | |
4244 | ||
4245 | info->drop_rts_on_tx_done = 0; | |
4246 | ||
4247 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
4248 | ||
4249 | if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { | |
4250 | get_signals( info ); | |
4251 | if ( !(info->serial_signals & SerialSignal_RTS) ) { | |
4252 | info->serial_signals |= SerialSignal_RTS; | |
4253 | set_signals( info ); | |
4254 | info->drop_rts_on_tx_done = 1; | |
4255 | } | |
4256 | } | |
4257 | ||
4258 | write_reg16(info, TRC0, | |
4259 | (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level)); | |
4260 | ||
4261 | write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ | |
4262 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
4263 | ||
4264 | /* set TX CDA (current descriptor address) */ | |
4265 | write_reg16(info, TXDMA + CDA, | |
4266 | info->tx_buf_list_ex[0].phys_entry); | |
4267 | ||
4268 | /* set TX EDA (last descriptor address) */ | |
4269 | write_reg16(info, TXDMA + EDA, | |
4270 | info->tx_buf_list_ex[info->last_tx_buf].phys_entry); | |
4271 | ||
4272 | /* enable underrun IRQ */ | |
4273 | info->ie1_value &= ~IDLE; | |
4274 | info->ie1_value |= UDRN; | |
4275 | write_reg(info, IE1, info->ie1_value); | |
4276 | write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); | |
4277 | ||
4278 | write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */ | |
4279 | write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ | |
4280 | ||
40565f19 JS |
4281 | mod_timer(&info->tx_timer, jiffies + |
4282 | msecs_to_jiffies(5000)); | |
1da177e4 LT |
4283 | } |
4284 | else { | |
4285 | tx_load_fifo(info); | |
4286 | /* async, enable IRQ on txdata */ | |
4287 | info->ie0_value |= TXRDYE; | |
4288 | write_reg(info, IE0, info->ie0_value); | |
4289 | } | |
4290 | ||
4291 | info->tx_active = 1; | |
4292 | } | |
4293 | } | |
4294 | ||
4295 | /* stop the transmitter and DMA | |
4296 | */ | |
4297 | void tx_stop( SLMP_INFO *info ) | |
4298 | { | |
4299 | if (debug_level >= DEBUG_LEVEL_ISR) | |
4300 | printk("%s(%d):%s tx_stop()\n", | |
4301 | __FILE__,__LINE__, info->device_name ); | |
4302 | ||
4303 | del_timer(&info->tx_timer); | |
4304 | ||
4305 | write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ | |
4306 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
4307 | ||
4308 | write_reg(info, CMD, TXRESET); | |
4309 | ||
4310 | info->ie1_value &= ~(UDRN + IDLE); | |
4311 | write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ | |
4312 | write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ | |
4313 | ||
4314 | info->ie0_value &= ~TXRDYE; | |
4315 | write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */ | |
4316 | ||
4317 | info->tx_enabled = 0; | |
4318 | info->tx_active = 0; | |
4319 | } | |
4320 | ||
4321 | /* Fill the transmit FIFO until the FIFO is full or | |
4322 | * there is no more data to load. | |
4323 | */ | |
4324 | void tx_load_fifo(SLMP_INFO *info) | |
4325 | { | |
4326 | u8 TwoBytes[2]; | |
4327 | ||
4328 | /* do nothing is now tx data available and no XON/XOFF pending */ | |
4329 | ||
4330 | if ( !info->tx_count && !info->x_char ) | |
4331 | return; | |
4332 | ||
4333 | /* load the Transmit FIFO until FIFOs full or all data sent */ | |
4334 | ||
4335 | while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { | |
4336 | ||
4337 | /* there is more space in the transmit FIFO and */ | |
4338 | /* there is more data in transmit buffer */ | |
4339 | ||
4340 | if ( (info->tx_count > 1) && !info->x_char ) { | |
4341 | /* write 16-bits */ | |
4342 | TwoBytes[0] = info->tx_buf[info->tx_get++]; | |
4343 | if (info->tx_get >= info->max_frame_size) | |
4344 | info->tx_get -= info->max_frame_size; | |
4345 | TwoBytes[1] = info->tx_buf[info->tx_get++]; | |
4346 | if (info->tx_get >= info->max_frame_size) | |
4347 | info->tx_get -= info->max_frame_size; | |
4348 | ||
4349 | write_reg16(info, TRB, *((u16 *)TwoBytes)); | |
4350 | ||
4351 | info->tx_count -= 2; | |
4352 | info->icount.tx += 2; | |
4353 | } else { | |
4354 | /* only 1 byte left to transmit or 1 FIFO slot left */ | |
4355 | ||
4356 | if (info->x_char) { | |
4357 | /* transmit pending high priority char */ | |
4358 | write_reg(info, TRB, info->x_char); | |
4359 | info->x_char = 0; | |
4360 | } else { | |
4361 | write_reg(info, TRB, info->tx_buf[info->tx_get++]); | |
4362 | if (info->tx_get >= info->max_frame_size) | |
4363 | info->tx_get -= info->max_frame_size; | |
4364 | info->tx_count--; | |
4365 | } | |
4366 | info->icount.tx++; | |
4367 | } | |
4368 | } | |
4369 | } | |
4370 | ||
4371 | /* Reset a port to a known state | |
4372 | */ | |
4373 | void reset_port(SLMP_INFO *info) | |
4374 | { | |
4375 | if (info->sca_base) { | |
4376 | ||
4377 | tx_stop(info); | |
4378 | rx_stop(info); | |
4379 | ||
4380 | info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
4381 | set_signals(info); | |
4382 | ||
4383 | /* disable all port interrupts */ | |
4384 | info->ie0_value = 0; | |
4385 | info->ie1_value = 0; | |
4386 | info->ie2_value = 0; | |
4387 | write_reg(info, IE0, info->ie0_value); | |
4388 | write_reg(info, IE1, info->ie1_value); | |
4389 | write_reg(info, IE2, info->ie2_value); | |
4390 | ||
4391 | write_reg(info, CMD, CHRESET); | |
4392 | } | |
4393 | } | |
4394 | ||
4395 | /* Reset all the ports to a known state. | |
4396 | */ | |
4397 | void reset_adapter(SLMP_INFO *info) | |
4398 | { | |
4399 | int i; | |
4400 | ||
4401 | for ( i=0; i < SCA_MAX_PORTS; ++i) { | |
4402 | if (info->port_array[i]) | |
4403 | reset_port(info->port_array[i]); | |
4404 | } | |
4405 | } | |
4406 | ||
4407 | /* Program port for asynchronous communications. | |
4408 | */ | |
4409 | void async_mode(SLMP_INFO *info) | |
4410 | { | |
4411 | ||
4412 | unsigned char RegValue; | |
4413 | ||
4414 | tx_stop(info); | |
4415 | rx_stop(info); | |
4416 | ||
4417 | /* MD0, Mode Register 0 | |
4418 | * | |
4419 | * 07..05 PRCTL<2..0>, Protocol Mode, 000=async | |
4420 | * 04 AUTO, Auto-enable (RTS/CTS/DCD) | |
4421 | * 03 Reserved, must be 0 | |
4422 | * 02 CRCCC, CRC Calculation, 0=disabled | |
4423 | * 01..00 STOP<1..0> Stop bits (00=1,10=2) | |
4424 | * | |
4425 | * 0000 0000 | |
4426 | */ | |
4427 | RegValue = 0x00; | |
4428 | if (info->params.stop_bits != 1) | |
4429 | RegValue |= BIT1; | |
4430 | write_reg(info, MD0, RegValue); | |
4431 | ||
4432 | /* MD1, Mode Register 1 | |
4433 | * | |
4434 | * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64 | |
4435 | * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5 | |
4436 | * 03..02 RXCHR<1..0>, rx char size | |
4437 | * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd | |
4438 | * | |
4439 | * 0100 0000 | |
4440 | */ | |
4441 | RegValue = 0x40; | |
4442 | switch (info->params.data_bits) { | |
4443 | case 7: RegValue |= BIT4 + BIT2; break; | |
4444 | case 6: RegValue |= BIT5 + BIT3; break; | |
4445 | case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; | |
4446 | } | |
4447 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4448 | RegValue |= BIT1; | |
4449 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4450 | RegValue |= BIT0; | |
4451 | } | |
4452 | write_reg(info, MD1, RegValue); | |
4453 | ||
4454 | /* MD2, Mode Register 2 | |
4455 | * | |
4456 | * 07..02 Reserved, must be 0 | |
6e8dcee3 | 4457 | * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback |
1da177e4 LT |
4458 | * |
4459 | * 0000 0000 | |
4460 | */ | |
4461 | RegValue = 0x00; | |
6e8dcee3 PF |
4462 | if (info->params.loopback) |
4463 | RegValue |= (BIT1 + BIT0); | |
1da177e4 LT |
4464 | write_reg(info, MD2, RegValue); |
4465 | ||
4466 | /* RXS, Receive clock source | |
4467 | * | |
4468 | * 07 Reserved, must be 0 | |
4469 | * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL | |
4470 | * 03..00 RXBR<3..0>, rate divisor, 0000=1 | |
4471 | */ | |
4472 | RegValue=BIT6; | |
4473 | write_reg(info, RXS, RegValue); | |
4474 | ||
4475 | /* TXS, Transmit clock source | |
4476 | * | |
4477 | * 07 Reserved, must be 0 | |
4478 | * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock | |
4479 | * 03..00 RXBR<3..0>, rate divisor, 0000=1 | |
4480 | */ | |
4481 | RegValue=BIT6; | |
4482 | write_reg(info, TXS, RegValue); | |
4483 | ||
4484 | /* Control Register | |
4485 | * | |
4486 | * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out | |
4487 | */ | |
4488 | info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); | |
4489 | write_control_reg(info); | |
4490 | ||
4491 | tx_set_idle(info); | |
4492 | ||
4493 | /* RRC Receive Ready Control 0 | |
4494 | * | |
4495 | * 07..05 Reserved, must be 0 | |
4496 | * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte | |
4497 | */ | |
4498 | write_reg(info, RRC, 0x00); | |
4499 | ||
4500 | /* TRC0 Transmit Ready Control 0 | |
4501 | * | |
4502 | * 07..05 Reserved, must be 0 | |
4503 | * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes | |
4504 | */ | |
4505 | write_reg(info, TRC0, 0x10); | |
4506 | ||
4507 | /* TRC1 Transmit Ready Control 1 | |
4508 | * | |
4509 | * 07..05 Reserved, must be 0 | |
4510 | * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1) | |
4511 | */ | |
4512 | write_reg(info, TRC1, 0x1e); | |
4513 | ||
4514 | /* CTL, MSCI control register | |
4515 | * | |
4516 | * 07..06 Reserved, set to 0 | |
4517 | * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) | |
4518 | * 04 IDLC, idle control, 0=mark 1=idle register | |
4519 | * 03 BRK, break, 0=off 1 =on (async) | |
4520 | * 02 SYNCLD, sync char load enable (BSC) 1=enabled | |
4521 | * 01 GOP, go active on poll (LOOP mode) 1=enabled | |
4522 | * 00 RTS, RTS output control, 0=active 1=inactive | |
4523 | * | |
4524 | * 0001 0001 | |
4525 | */ | |
4526 | RegValue = 0x10; | |
4527 | if (!(info->serial_signals & SerialSignal_RTS)) | |
4528 | RegValue |= 0x01; | |
4529 | write_reg(info, CTL, RegValue); | |
4530 | ||
4531 | /* enable status interrupts */ | |
4532 | info->ie0_value |= TXINTE + RXINTE; | |
4533 | write_reg(info, IE0, info->ie0_value); | |
4534 | ||
4535 | /* enable break detect interrupt */ | |
4536 | info->ie1_value = BRKD; | |
4537 | write_reg(info, IE1, info->ie1_value); | |
4538 | ||
4539 | /* enable rx overrun interrupt */ | |
4540 | info->ie2_value = OVRN; | |
4541 | write_reg(info, IE2, info->ie2_value); | |
4542 | ||
4543 | set_rate( info, info->params.data_rate * 16 ); | |
1da177e4 LT |
4544 | } |
4545 | ||
4546 | /* Program the SCA for HDLC communications. | |
4547 | */ | |
4548 | void hdlc_mode(SLMP_INFO *info) | |
4549 | { | |
4550 | unsigned char RegValue; | |
4551 | u32 DpllDivisor; | |
4552 | ||
4553 | // Can't use DPLL because SCA outputs recovered clock on RxC when | |
4554 | // DPLL mode selected. This causes output contention with RxC receiver. | |
4555 | // Use of DPLL would require external hardware to disable RxC receiver | |
4556 | // when DPLL mode selected. | |
4557 | info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL); | |
4558 | ||
4559 | /* disable DMA interrupts */ | |
4560 | write_reg(info, TXDMA + DIR, 0); | |
4561 | write_reg(info, RXDMA + DIR, 0); | |
4562 | ||
4563 | /* MD0, Mode Register 0 | |
4564 | * | |
4565 | * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC | |
4566 | * 04 AUTO, Auto-enable (RTS/CTS/DCD) | |
4567 | * 03 Reserved, must be 0 | |
4568 | * 02 CRCCC, CRC Calculation, 1=enabled | |
4569 | * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16 | |
4570 | * 00 CRC0, CRC initial value, 1 = all 1s | |
4571 | * | |
4572 | * 1000 0001 | |
4573 | */ | |
4574 | RegValue = 0x81; | |
4575 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4576 | RegValue |= BIT4; | |
4577 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4578 | RegValue |= BIT4; | |
4579 | if (info->params.crc_type == HDLC_CRC_16_CCITT) | |
4580 | RegValue |= BIT2 + BIT1; | |
4581 | write_reg(info, MD0, RegValue); | |
4582 | ||
4583 | /* MD1, Mode Register 1 | |
4584 | * | |
4585 | * 07..06 ADDRS<1..0>, Address detect, 00=no addr check | |
4586 | * 05..04 TXCHR<1..0>, tx char size, 00=8 bits | |
4587 | * 03..02 RXCHR<1..0>, rx char size, 00=8 bits | |
4588 | * 01..00 PMPM<1..0>, Parity mode, 00=no parity | |
4589 | * | |
4590 | * 0000 0000 | |
4591 | */ | |
4592 | RegValue = 0x00; | |
4593 | write_reg(info, MD1, RegValue); | |
4594 | ||
4595 | /* MD2, Mode Register 2 | |
4596 | * | |
4597 | * 07 NRZFM, 0=NRZ, 1=FM | |
4598 | * 06..05 CODE<1..0> Encoding, 00=NRZ | |
4599 | * 04..03 DRATE<1..0> DPLL Divisor, 00=8 | |
4600 | * 02 Reserved, must be 0 | |
4601 | * 01..00 CNCT<1..0> Channel connection, 0=normal | |
4602 | * | |
4603 | * 0000 0000 | |
4604 | */ | |
4605 | RegValue = 0x00; | |
4606 | switch(info->params.encoding) { | |
4607 | case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; | |
4608 | case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ | |
4609 | case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ | |
4610 | case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */ | |
4611 | #if 0 | |
4612 | case HDLC_ENCODING_NRZB: /* not supported */ | |
4613 | case HDLC_ENCODING_NRZI_MARK: /* not supported */ | |
4614 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */ | |
4615 | #endif | |
4616 | } | |
4617 | if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) { | |
4618 | DpllDivisor = 16; | |
4619 | RegValue |= BIT3; | |
4620 | } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) { | |
4621 | DpllDivisor = 8; | |
4622 | } else { | |
4623 | DpllDivisor = 32; | |
4624 | RegValue |= BIT4; | |
4625 | } | |
4626 | write_reg(info, MD2, RegValue); | |
4627 | ||
4628 | ||
4629 | /* RXS, Receive clock source | |
4630 | * | |
4631 | * 07 Reserved, must be 0 | |
4632 | * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL | |
4633 | * 03..00 RXBR<3..0>, rate divisor, 0000=1 | |
4634 | */ | |
4635 | RegValue=0; | |
4636 | if (info->params.flags & HDLC_FLAG_RXC_BRG) | |
4637 | RegValue |= BIT6; | |
4638 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4639 | RegValue |= BIT6 + BIT5; | |
4640 | write_reg(info, RXS, RegValue); | |
4641 | ||
4642 | /* TXS, Transmit clock source | |
4643 | * | |
4644 | * 07 Reserved, must be 0 | |
4645 | * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock | |
4646 | * 03..00 RXBR<3..0>, rate divisor, 0000=1 | |
4647 | */ | |
4648 | RegValue=0; | |
4649 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
4650 | RegValue |= BIT6; | |
4651 | if (info->params.flags & HDLC_FLAG_TXC_DPLL) | |
4652 | RegValue |= BIT6 + BIT5; | |
4653 | write_reg(info, TXS, RegValue); | |
4654 | ||
4655 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4656 | set_rate(info, info->params.clock_speed * DpllDivisor); | |
4657 | else | |
4658 | set_rate(info, info->params.clock_speed); | |
4659 | ||
4660 | /* GPDATA (General Purpose I/O Data Register) | |
4661 | * | |
4662 | * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out | |
4663 | */ | |
4664 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
4665 | info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); | |
4666 | else | |
4667 | info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2)); | |
4668 | write_control_reg(info); | |
4669 | ||
4670 | /* RRC Receive Ready Control 0 | |
4671 | * | |
4672 | * 07..05 Reserved, must be 0 | |
4673 | * 04..00 RRC<4..0> Rx FIFO trigger active | |
4674 | */ | |
4675 | write_reg(info, RRC, rx_active_fifo_level); | |
4676 | ||
4677 | /* TRC0 Transmit Ready Control 0 | |
4678 | * | |
4679 | * 07..05 Reserved, must be 0 | |
4680 | * 04..00 TRC<4..0> Tx FIFO trigger active | |
4681 | */ | |
4682 | write_reg(info, TRC0, tx_active_fifo_level); | |
4683 | ||
4684 | /* TRC1 Transmit Ready Control 1 | |
4685 | * | |
4686 | * 07..05 Reserved, must be 0 | |
4687 | * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full) | |
4688 | */ | |
4689 | write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1)); | |
4690 | ||
4691 | /* DMR, DMA Mode Register | |
4692 | * | |
4693 | * 07..05 Reserved, must be 0 | |
4694 | * 04 TMOD, Transfer Mode: 1=chained-block | |
4695 | * 03 Reserved, must be 0 | |
4696 | * 02 NF, Number of Frames: 1=multi-frame | |
4697 | * 01 CNTE, Frame End IRQ Counter enable: 0=disabled | |
4698 | * 00 Reserved, must be 0 | |
4699 | * | |
4700 | * 0001 0100 | |
4701 | */ | |
4702 | write_reg(info, TXDMA + DMR, 0x14); | |
4703 | write_reg(info, RXDMA + DMR, 0x14); | |
4704 | ||
4705 | /* Set chain pointer base (upper 8 bits of 24 bit addr) */ | |
4706 | write_reg(info, RXDMA + CPB, | |
4707 | (unsigned char)(info->buffer_list_phys >> 16)); | |
4708 | ||
4709 | /* Set chain pointer base (upper 8 bits of 24 bit addr) */ | |
4710 | write_reg(info, TXDMA + CPB, | |
4711 | (unsigned char)(info->buffer_list_phys >> 16)); | |
4712 | ||
4713 | /* enable status interrupts. other code enables/disables | |
4714 | * the individual sources for these two interrupt classes. | |
4715 | */ | |
4716 | info->ie0_value |= TXINTE + RXINTE; | |
4717 | write_reg(info, IE0, info->ie0_value); | |
4718 | ||
4719 | /* CTL, MSCI control register | |
4720 | * | |
4721 | * 07..06 Reserved, set to 0 | |
4722 | * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) | |
4723 | * 04 IDLC, idle control, 0=mark 1=idle register | |
4724 | * 03 BRK, break, 0=off 1 =on (async) | |
4725 | * 02 SYNCLD, sync char load enable (BSC) 1=enabled | |
4726 | * 01 GOP, go active on poll (LOOP mode) 1=enabled | |
4727 | * 00 RTS, RTS output control, 0=active 1=inactive | |
4728 | * | |
4729 | * 0001 0001 | |
4730 | */ | |
4731 | RegValue = 0x10; | |
4732 | if (!(info->serial_signals & SerialSignal_RTS)) | |
4733 | RegValue |= 0x01; | |
4734 | write_reg(info, CTL, RegValue); | |
4735 | ||
4736 | /* preamble not supported ! */ | |
4737 | ||
4738 | tx_set_idle(info); | |
4739 | tx_stop(info); | |
4740 | rx_stop(info); | |
4741 | ||
4742 | set_rate(info, info->params.clock_speed); | |
4743 | ||
4744 | if (info->params.loopback) | |
4745 | enable_loopback(info,1); | |
4746 | } | |
4747 | ||
4748 | /* Set the transmit HDLC idle mode | |
4749 | */ | |
4750 | void tx_set_idle(SLMP_INFO *info) | |
4751 | { | |
4752 | unsigned char RegValue = 0xff; | |
4753 | ||
4754 | /* Map API idle mode to SCA register bits */ | |
4755 | switch(info->idle_mode) { | |
4756 | case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break; | |
4757 | case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break; | |
4758 | case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break; | |
4759 | case HDLC_TXIDLE_ONES: RegValue = 0xff; break; | |
4760 | case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break; | |
4761 | case HDLC_TXIDLE_SPACE: RegValue = 0x00; break; | |
4762 | case HDLC_TXIDLE_MARK: RegValue = 0xff; break; | |
4763 | } | |
4764 | ||
4765 | write_reg(info, IDL, RegValue); | |
4766 | } | |
4767 | ||
4768 | /* Query the adapter for the state of the V24 status (input) signals. | |
4769 | */ | |
4770 | void get_signals(SLMP_INFO *info) | |
4771 | { | |
4772 | u16 status = read_reg(info, SR3); | |
4773 | u16 gpstatus = read_status_reg(info); | |
4774 | u16 testbit; | |
4775 | ||
4776 | /* clear all serial signals except DTR and RTS */ | |
4777 | info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS; | |
4778 | ||
4779 | /* set serial signal bits to reflect MISR */ | |
4780 | ||
4781 | if (!(status & BIT3)) | |
4782 | info->serial_signals |= SerialSignal_CTS; | |
4783 | ||
4784 | if ( !(status & BIT2)) | |
4785 | info->serial_signals |= SerialSignal_DCD; | |
4786 | ||
4787 | testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7> | |
4788 | if (!(gpstatus & testbit)) | |
4789 | info->serial_signals |= SerialSignal_RI; | |
4790 | ||
4791 | testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6> | |
4792 | if (!(gpstatus & testbit)) | |
4793 | info->serial_signals |= SerialSignal_DSR; | |
4794 | } | |
4795 | ||
4796 | /* Set the state of DTR and RTS based on contents of | |
4797 | * serial_signals member of device context. | |
4798 | */ | |
4799 | void set_signals(SLMP_INFO *info) | |
4800 | { | |
4801 | unsigned char RegValue; | |
4802 | u16 EnableBit; | |
4803 | ||
4804 | RegValue = read_reg(info, CTL); | |
4805 | if (info->serial_signals & SerialSignal_RTS) | |
4806 | RegValue &= ~BIT0; | |
4807 | else | |
4808 | RegValue |= BIT0; | |
4809 | write_reg(info, CTL, RegValue); | |
4810 | ||
4811 | // Port 0..3 DTR is ctrl reg <1,3,5,7> | |
4812 | EnableBit = BIT1 << (info->port_num*2); | |
4813 | if (info->serial_signals & SerialSignal_DTR) | |
4814 | info->port_array[0]->ctrlreg_value &= ~EnableBit; | |
4815 | else | |
4816 | info->port_array[0]->ctrlreg_value |= EnableBit; | |
4817 | write_control_reg(info); | |
4818 | } | |
4819 | ||
4820 | /*******************/ | |
4821 | /* DMA Buffer Code */ | |
4822 | /*******************/ | |
4823 | ||
4824 | /* Set the count for all receive buffers to SCABUFSIZE | |
4825 | * and set the current buffer to the first buffer. This effectively | |
4826 | * makes all buffers free and discards any data in buffers. | |
4827 | */ | |
4828 | void rx_reset_buffers(SLMP_INFO *info) | |
4829 | { | |
4830 | rx_free_frame_buffers(info, 0, info->rx_buf_count - 1); | |
4831 | } | |
4832 | ||
4833 | /* Free the buffers used by a received frame | |
4834 | * | |
4835 | * info pointer to device instance data | |
4836 | * first index of 1st receive buffer of frame | |
4837 | * last index of last receive buffer of frame | |
4838 | */ | |
4839 | void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last) | |
4840 | { | |
4841 | int done = 0; | |
4842 | ||
4843 | while(!done) { | |
4844 | /* reset current buffer for reuse */ | |
4845 | info->rx_buf_list[first].status = 0xff; | |
4846 | ||
4847 | if (first == last) { | |
4848 | done = 1; | |
4849 | /* set new last rx descriptor address */ | |
4850 | write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry); | |
4851 | } | |
4852 | ||
4853 | first++; | |
4854 | if (first == info->rx_buf_count) | |
4855 | first = 0; | |
4856 | } | |
4857 | ||
4858 | /* set current buffer to next buffer after last buffer of frame */ | |
4859 | info->current_rx_buf = first; | |
4860 | } | |
4861 | ||
4862 | /* Return a received frame from the receive DMA buffers. | |
4863 | * Only frames received without errors are returned. | |
4864 | * | |
4865 | * Return Value: 1 if frame returned, otherwise 0 | |
4866 | */ | |
4867 | int rx_get_frame(SLMP_INFO *info) | |
4868 | { | |
4869 | unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ | |
4870 | unsigned short status; | |
4871 | unsigned int framesize = 0; | |
4872 | int ReturnCode = 0; | |
4873 | unsigned long flags; | |
4874 | struct tty_struct *tty = info->tty; | |
4875 | unsigned char addr_field = 0xff; | |
4876 | SCADESC *desc; | |
4877 | SCADESC_EX *desc_ex; | |
4878 | ||
4879 | CheckAgain: | |
4880 | /* assume no frame returned, set zero length */ | |
4881 | framesize = 0; | |
4882 | addr_field = 0xff; | |
4883 | ||
4884 | /* | |
4885 | * current_rx_buf points to the 1st buffer of the next available | |
4886 | * receive frame. To find the last buffer of the frame look for | |
4887 | * a non-zero status field in the buffer entries. (The status | |
4888 | * field is set by the 16C32 after completing a receive frame. | |
4889 | */ | |
4890 | StartIndex = EndIndex = info->current_rx_buf; | |
4891 | ||
4892 | for ( ;; ) { | |
4893 | desc = &info->rx_buf_list[EndIndex]; | |
4894 | desc_ex = &info->rx_buf_list_ex[EndIndex]; | |
4895 | ||
4896 | if (desc->status == 0xff) | |
4897 | goto Cleanup; /* current desc still in use, no frames available */ | |
4898 | ||
4899 | if (framesize == 0 && info->params.addr_filter != 0xff) | |
4900 | addr_field = desc_ex->virt_addr[0]; | |
4901 | ||
4902 | framesize += desc->length; | |
4903 | ||
4904 | /* Status != 0 means last buffer of frame */ | |
4905 | if (desc->status) | |
4906 | break; | |
4907 | ||
4908 | EndIndex++; | |
4909 | if (EndIndex == info->rx_buf_count) | |
4910 | EndIndex = 0; | |
4911 | ||
4912 | if (EndIndex == info->current_rx_buf) { | |
4913 | /* all buffers have been 'used' but none mark */ | |
4914 | /* the end of a frame. Reset buffers and receiver. */ | |
4915 | if ( info->rx_enabled ){ | |
4916 | spin_lock_irqsave(&info->lock,flags); | |
4917 | rx_start(info); | |
4918 | spin_unlock_irqrestore(&info->lock,flags); | |
4919 | } | |
4920 | goto Cleanup; | |
4921 | } | |
4922 | ||
4923 | } | |
4924 | ||
4925 | /* check status of receive frame */ | |
4926 | ||
4927 | /* frame status is byte stored after frame data | |
4928 | * | |
4929 | * 7 EOM (end of msg), 1 = last buffer of frame | |
4930 | * 6 Short Frame, 1 = short frame | |
4931 | * 5 Abort, 1 = frame aborted | |
4932 | * 4 Residue, 1 = last byte is partial | |
4933 | * 3 Overrun, 1 = overrun occurred during frame reception | |
4934 | * 2 CRC, 1 = CRC error detected | |
4935 | * | |
4936 | */ | |
4937 | status = desc->status; | |
4938 | ||
4939 | /* ignore CRC bit if not using CRC (bit is undefined) */ | |
4940 | /* Note:CRC is not save to data buffer */ | |
4941 | if (info->params.crc_type == HDLC_CRC_NONE) | |
4942 | status &= ~BIT2; | |
4943 | ||
4944 | if (framesize == 0 || | |
4945 | (addr_field != 0xff && addr_field != info->params.addr_filter)) { | |
4946 | /* discard 0 byte frames, this seems to occur sometime | |
4947 | * when remote is idling flags. | |
4948 | */ | |
4949 | rx_free_frame_buffers(info, StartIndex, EndIndex); | |
4950 | goto CheckAgain; | |
4951 | } | |
4952 | ||
4953 | if (framesize < 2) | |
4954 | status |= BIT6; | |
4955 | ||
4956 | if (status & (BIT6+BIT5+BIT3+BIT2)) { | |
4957 | /* received frame has errors, | |
4958 | * update counts and mark frame size as 0 | |
4959 | */ | |
4960 | if (status & BIT6) | |
4961 | info->icount.rxshort++; | |
4962 | else if (status & BIT5) | |
4963 | info->icount.rxabort++; | |
4964 | else if (status & BIT3) | |
4965 | info->icount.rxover++; | |
4966 | else | |
4967 | info->icount.rxcrc++; | |
4968 | ||
4969 | framesize = 0; | |
af69c7f9 | 4970 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
4971 | { |
4972 | struct net_device_stats *stats = hdlc_stats(info->netdev); | |
4973 | stats->rx_errors++; | |
4974 | stats->rx_frame_errors++; | |
4975 | } | |
4976 | #endif | |
4977 | } | |
4978 | ||
4979 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
4980 | printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n", | |
4981 | __FILE__,__LINE__,info->device_name,status,framesize); | |
4982 | ||
4983 | if ( debug_level >= DEBUG_LEVEL_DATA ) | |
4984 | trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr, | |
4985 | min_t(int, framesize,SCABUFSIZE),0); | |
4986 | ||
4987 | if (framesize) { | |
4988 | if (framesize > info->max_frame_size) | |
4989 | info->icount.rxlong++; | |
4990 | else { | |
4991 | /* copy dma buffer(s) to contiguous intermediate buffer */ | |
4992 | int copy_count = framesize; | |
4993 | int index = StartIndex; | |
4994 | unsigned char *ptmp = info->tmp_rx_buf; | |
4995 | info->tmp_rx_buf_count = framesize; | |
4996 | ||
4997 | info->icount.rxok++; | |
4998 | ||
4999 | while(copy_count) { | |
5000 | int partial_count = min(copy_count,SCABUFSIZE); | |
5001 | memcpy( ptmp, | |
5002 | info->rx_buf_list_ex[index].virt_addr, | |
5003 | partial_count ); | |
5004 | ptmp += partial_count; | |
5005 | copy_count -= partial_count; | |
5006 | ||
5007 | if ( ++index == info->rx_buf_count ) | |
5008 | index = 0; | |
5009 | } | |
5010 | ||
af69c7f9 | 5011 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
5012 | if (info->netcount) |
5013 | hdlcdev_rx(info,info->tmp_rx_buf,framesize); | |
5014 | else | |
5015 | #endif | |
5016 | ldisc_receive_buf(tty,info->tmp_rx_buf, | |
5017 | info->flag_buf, framesize); | |
5018 | } | |
5019 | } | |
5020 | /* Free the buffers used by this frame. */ | |
5021 | rx_free_frame_buffers( info, StartIndex, EndIndex ); | |
5022 | ||
5023 | ReturnCode = 1; | |
5024 | ||
5025 | Cleanup: | |
5026 | if ( info->rx_enabled && info->rx_overflow ) { | |
5027 | /* Receiver is enabled, but needs to restarted due to | |
5028 | * rx buffer overflow. If buffers are empty, restart receiver. | |
5029 | */ | |
5030 | if (info->rx_buf_list[EndIndex].status == 0xff) { | |
5031 | spin_lock_irqsave(&info->lock,flags); | |
5032 | rx_start(info); | |
5033 | spin_unlock_irqrestore(&info->lock,flags); | |
5034 | } | |
5035 | } | |
5036 | ||
5037 | return ReturnCode; | |
5038 | } | |
5039 | ||
5040 | /* load the transmit DMA buffer with data | |
5041 | */ | |
5042 | void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count) | |
5043 | { | |
5044 | unsigned short copy_count; | |
5045 | unsigned int i = 0; | |
5046 | SCADESC *desc; | |
5047 | SCADESC_EX *desc_ex; | |
5048 | ||
5049 | if ( debug_level >= DEBUG_LEVEL_DATA ) | |
5050 | trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1); | |
5051 | ||
5052 | /* Copy source buffer to one or more DMA buffers, starting with | |
5053 | * the first transmit dma buffer. | |
5054 | */ | |
5055 | for(i=0;;) | |
5056 | { | |
5057 | copy_count = min_t(unsigned short,count,SCABUFSIZE); | |
5058 | ||
5059 | desc = &info->tx_buf_list[i]; | |
5060 | desc_ex = &info->tx_buf_list_ex[i]; | |
5061 | ||
5062 | load_pci_memory(info, desc_ex->virt_addr,buf,copy_count); | |
5063 | ||
5064 | desc->length = copy_count; | |
5065 | desc->status = 0; | |
5066 | ||
5067 | buf += copy_count; | |
5068 | count -= copy_count; | |
5069 | ||
5070 | if (!count) | |
5071 | break; | |
5072 | ||
5073 | i++; | |
5074 | if (i >= info->tx_buf_count) | |
5075 | i = 0; | |
5076 | } | |
5077 | ||
5078 | info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */ | |
5079 | info->last_tx_buf = ++i; | |
5080 | } | |
5081 | ||
5082 | int register_test(SLMP_INFO *info) | |
5083 | { | |
5084 | static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96}; | |
fe971071 | 5085 | static unsigned int count = ARRAY_SIZE(testval); |
1da177e4 LT |
5086 | unsigned int i; |
5087 | int rc = TRUE; | |
5088 | unsigned long flags; | |
5089 | ||
5090 | spin_lock_irqsave(&info->lock,flags); | |
5091 | reset_port(info); | |
5092 | ||
5093 | /* assume failure */ | |
5094 | info->init_error = DiagStatus_AddressFailure; | |
5095 | ||
5096 | /* Write bit patterns to various registers but do it out of */ | |
5097 | /* sync, then read back and verify values. */ | |
5098 | ||
5099 | for (i = 0 ; i < count ; i++) { | |
5100 | write_reg(info, TMC, testval[i]); | |
5101 | write_reg(info, IDL, testval[(i+1)%count]); | |
5102 | write_reg(info, SA0, testval[(i+2)%count]); | |
5103 | write_reg(info, SA1, testval[(i+3)%count]); | |
5104 | ||
5105 | if ( (read_reg(info, TMC) != testval[i]) || | |
5106 | (read_reg(info, IDL) != testval[(i+1)%count]) || | |
5107 | (read_reg(info, SA0) != testval[(i+2)%count]) || | |
5108 | (read_reg(info, SA1) != testval[(i+3)%count]) ) | |
5109 | { | |
5110 | rc = FALSE; | |
5111 | break; | |
5112 | } | |
5113 | } | |
5114 | ||
5115 | reset_port(info); | |
5116 | spin_unlock_irqrestore(&info->lock,flags); | |
5117 | ||
5118 | return rc; | |
5119 | } | |
5120 | ||
5121 | int irq_test(SLMP_INFO *info) | |
5122 | { | |
5123 | unsigned long timeout; | |
5124 | unsigned long flags; | |
5125 | ||
5126 | unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; | |
5127 | ||
5128 | spin_lock_irqsave(&info->lock,flags); | |
5129 | reset_port(info); | |
5130 | ||
5131 | /* assume failure */ | |
5132 | info->init_error = DiagStatus_IrqFailure; | |
5133 | info->irq_occurred = FALSE; | |
5134 | ||
5135 | /* setup timer0 on SCA0 to interrupt */ | |
5136 | ||
5137 | /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */ | |
5138 | write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); | |
5139 | ||
5140 | write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */ | |
5141 | write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */ | |
5142 | ||
5143 | ||
5144 | /* TMCS, Timer Control/Status Register | |
5145 | * | |
5146 | * 07 CMF, Compare match flag (read only) 1=match | |
5147 | * 06 ECMI, CMF Interrupt Enable: 1=enabled | |
5148 | * 05 Reserved, must be 0 | |
5149 | * 04 TME, Timer Enable | |
5150 | * 03..00 Reserved, must be 0 | |
5151 | * | |
5152 | * 0101 0000 | |
5153 | */ | |
5154 | write_reg(info, (unsigned char)(timer + TMCS), 0x50); | |
5155 | ||
5156 | spin_unlock_irqrestore(&info->lock,flags); | |
5157 | ||
5158 | timeout=100; | |
5159 | while( timeout-- && !info->irq_occurred ) { | |
5160 | msleep_interruptible(10); | |
5161 | } | |
5162 | ||
5163 | spin_lock_irqsave(&info->lock,flags); | |
5164 | reset_port(info); | |
5165 | spin_unlock_irqrestore(&info->lock,flags); | |
5166 | ||
5167 | return info->irq_occurred; | |
5168 | } | |
5169 | ||
5170 | /* initialize individual SCA device (2 ports) | |
5171 | */ | |
5172 | static int sca_init(SLMP_INFO *info) | |
5173 | { | |
5174 | /* set wait controller to single mem partition (low), no wait states */ | |
5175 | write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */ | |
5176 | write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */ | |
5177 | write_reg(info, WCRL, 0); /* wait controller low range */ | |
5178 | write_reg(info, WCRM, 0); /* wait controller mid range */ | |
5179 | write_reg(info, WCRH, 0); /* wait controller high range */ | |
5180 | ||
5181 | /* DPCR, DMA Priority Control | |
5182 | * | |
5183 | * 07..05 Not used, must be 0 | |
5184 | * 04 BRC, bus release condition: 0=all transfers complete | |
5185 | * 03 CCC, channel change condition: 0=every cycle | |
5186 | * 02..00 PR<2..0>, priority 100=round robin | |
5187 | * | |
5188 | * 00000100 = 0x04 | |
5189 | */ | |
5190 | write_reg(info, DPCR, dma_priority); | |
5191 | ||
5192 | /* DMA Master Enable, BIT7: 1=enable all channels */ | |
5193 | write_reg(info, DMER, 0x80); | |
5194 | ||
5195 | /* enable all interrupt classes */ | |
5196 | write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */ | |
5197 | write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */ | |
5198 | write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */ | |
5199 | ||
5200 | /* ITCR, interrupt control register | |
5201 | * 07 IPC, interrupt priority, 0=MSCI->DMA | |
5202 | * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle | |
5203 | * 04 VOS, Vector Output, 0=unmodified vector | |
5204 | * 03..00 Reserved, must be 0 | |
5205 | */ | |
5206 | write_reg(info, ITCR, 0); | |
5207 | ||
5208 | return TRUE; | |
5209 | } | |
5210 | ||
5211 | /* initialize adapter hardware | |
5212 | */ | |
5213 | int init_adapter(SLMP_INFO *info) | |
5214 | { | |
5215 | int i; | |
5216 | ||
5217 | /* Set BIT30 of Local Control Reg 0x50 to reset SCA */ | |
5218 | volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); | |
5219 | u32 readval; | |
5220 | ||
5221 | info->misc_ctrl_value |= BIT30; | |
5222 | *MiscCtrl = info->misc_ctrl_value; | |
5223 | ||
5224 | /* | |
5225 | * Force at least 170ns delay before clearing | |
5226 | * reset bit. Each read from LCR takes at least | |
5227 | * 30ns so 10 times for 300ns to be safe. | |
5228 | */ | |
5229 | for(i=0;i<10;i++) | |
5230 | readval = *MiscCtrl; | |
5231 | ||
5232 | info->misc_ctrl_value &= ~BIT30; | |
5233 | *MiscCtrl = info->misc_ctrl_value; | |
5234 | ||
5235 | /* init control reg (all DTRs off, all clksel=input) */ | |
5236 | info->ctrlreg_value = 0xaa; | |
5237 | write_control_reg(info); | |
5238 | ||
5239 | { | |
5240 | volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c); | |
5241 | lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3); | |
5242 | ||
5243 | switch(read_ahead_count) | |
5244 | { | |
5245 | case 16: | |
5246 | lcr1_brdr_value |= BIT5 + BIT4 + BIT3; | |
5247 | break; | |
5248 | case 8: | |
5249 | lcr1_brdr_value |= BIT5 + BIT4; | |
5250 | break; | |
5251 | case 4: | |
5252 | lcr1_brdr_value |= BIT5 + BIT3; | |
5253 | break; | |
5254 | case 0: | |
5255 | lcr1_brdr_value |= BIT5; | |
5256 | break; | |
5257 | } | |
5258 | ||
5259 | *LCR1BRDR = lcr1_brdr_value; | |
5260 | *MiscCtrl = misc_ctrl_value; | |
5261 | } | |
5262 | ||
5263 | sca_init(info->port_array[0]); | |
5264 | sca_init(info->port_array[2]); | |
5265 | ||
5266 | return TRUE; | |
5267 | } | |
5268 | ||
5269 | /* Loopback an HDLC frame to test the hardware | |
5270 | * interrupt and DMA functions. | |
5271 | */ | |
5272 | int loopback_test(SLMP_INFO *info) | |
5273 | { | |
5274 | #define TESTFRAMESIZE 20 | |
5275 | ||
5276 | unsigned long timeout; | |
5277 | u16 count = TESTFRAMESIZE; | |
5278 | unsigned char buf[TESTFRAMESIZE]; | |
5279 | int rc = FALSE; | |
5280 | unsigned long flags; | |
5281 | ||
5282 | struct tty_struct *oldtty = info->tty; | |
5283 | u32 speed = info->params.clock_speed; | |
5284 | ||
5285 | info->params.clock_speed = 3686400; | |
5286 | info->tty = NULL; | |
5287 | ||
5288 | /* assume failure */ | |
5289 | info->init_error = DiagStatus_DmaFailure; | |
5290 | ||
5291 | /* build and send transmit frame */ | |
5292 | for (count = 0; count < TESTFRAMESIZE;++count) | |
5293 | buf[count] = (unsigned char)count; | |
5294 | ||
5295 | memset(info->tmp_rx_buf,0,TESTFRAMESIZE); | |
5296 | ||
5297 | /* program hardware for HDLC and enabled receiver */ | |
5298 | spin_lock_irqsave(&info->lock,flags); | |
5299 | hdlc_mode(info); | |
5300 | enable_loopback(info,1); | |
5301 | rx_start(info); | |
5302 | info->tx_count = count; | |
5303 | tx_load_dma_buffer(info,buf,count); | |
5304 | tx_start(info); | |
5305 | spin_unlock_irqrestore(&info->lock,flags); | |
5306 | ||
5307 | /* wait for receive complete */ | |
5308 | /* Set a timeout for waiting for interrupt. */ | |
5309 | for ( timeout = 100; timeout; --timeout ) { | |
5310 | msleep_interruptible(10); | |
5311 | ||
5312 | if (rx_get_frame(info)) { | |
5313 | rc = TRUE; | |
5314 | break; | |
5315 | } | |
5316 | } | |
5317 | ||
5318 | /* verify received frame length and contents */ | |
5319 | if (rc == TRUE && | |
5320 | ( info->tmp_rx_buf_count != count || | |
5321 | memcmp(buf, info->tmp_rx_buf,count))) { | |
5322 | rc = FALSE; | |
5323 | } | |
5324 | ||
5325 | spin_lock_irqsave(&info->lock,flags); | |
5326 | reset_adapter(info); | |
5327 | spin_unlock_irqrestore(&info->lock,flags); | |
5328 | ||
5329 | info->params.clock_speed = speed; | |
5330 | info->tty = oldtty; | |
5331 | ||
5332 | return rc; | |
5333 | } | |
5334 | ||
5335 | /* Perform diagnostics on hardware | |
5336 | */ | |
5337 | int adapter_test( SLMP_INFO *info ) | |
5338 | { | |
5339 | unsigned long flags; | |
5340 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
5341 | printk( "%s(%d):Testing device %s\n", | |
5342 | __FILE__,__LINE__,info->device_name ); | |
5343 | ||
5344 | spin_lock_irqsave(&info->lock,flags); | |
5345 | init_adapter(info); | |
5346 | spin_unlock_irqrestore(&info->lock,flags); | |
5347 | ||
5348 | info->port_array[0]->port_count = 0; | |
5349 | ||
5350 | if ( register_test(info->port_array[0]) && | |
5351 | register_test(info->port_array[1])) { | |
5352 | ||
5353 | info->port_array[0]->port_count = 2; | |
5354 | ||
5355 | if ( register_test(info->port_array[2]) && | |
5356 | register_test(info->port_array[3]) ) | |
5357 | info->port_array[0]->port_count += 2; | |
5358 | } | |
5359 | else { | |
5360 | printk( "%s(%d):Register test failure for device %s Addr=%08lX\n", | |
5361 | __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base)); | |
5362 | return -ENODEV; | |
5363 | } | |
5364 | ||
5365 | if ( !irq_test(info->port_array[0]) || | |
5366 | !irq_test(info->port_array[1]) || | |
5367 | (info->port_count == 4 && !irq_test(info->port_array[2])) || | |
5368 | (info->port_count == 4 && !irq_test(info->port_array[3]))) { | |
5369 | printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", | |
5370 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); | |
5371 | return -ENODEV; | |
5372 | } | |
5373 | ||
5374 | if (!loopback_test(info->port_array[0]) || | |
5375 | !loopback_test(info->port_array[1]) || | |
5376 | (info->port_count == 4 && !loopback_test(info->port_array[2])) || | |
5377 | (info->port_count == 4 && !loopback_test(info->port_array[3]))) { | |
5378 | printk( "%s(%d):DMA test failure for device %s\n", | |
5379 | __FILE__,__LINE__,info->device_name); | |
5380 | return -ENODEV; | |
5381 | } | |
5382 | ||
5383 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
5384 | printk( "%s(%d):device %s passed diagnostics\n", | |
5385 | __FILE__,__LINE__,info->device_name ); | |
5386 | ||
5387 | info->port_array[0]->init_error = 0; | |
5388 | info->port_array[1]->init_error = 0; | |
5389 | if ( info->port_count > 2 ) { | |
5390 | info->port_array[2]->init_error = 0; | |
5391 | info->port_array[3]->init_error = 0; | |
5392 | } | |
5393 | ||
5394 | return 0; | |
5395 | } | |
5396 | ||
5397 | /* Test the shared memory on a PCI adapter. | |
5398 | */ | |
5399 | int memory_test(SLMP_INFO *info) | |
5400 | { | |
5401 | static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa, | |
5402 | 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; | |
fe971071 | 5403 | unsigned long count = ARRAY_SIZE(testval); |
1da177e4 LT |
5404 | unsigned long i; |
5405 | unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long); | |
5406 | unsigned long * addr = (unsigned long *)info->memory_base; | |
5407 | ||
5408 | /* Test data lines with test pattern at one location. */ | |
5409 | ||
5410 | for ( i = 0 ; i < count ; i++ ) { | |
5411 | *addr = testval[i]; | |
5412 | if ( *addr != testval[i] ) | |
5413 | return FALSE; | |
5414 | } | |
5415 | ||
5416 | /* Test address lines with incrementing pattern over */ | |
5417 | /* entire address range. */ | |
5418 | ||
5419 | for ( i = 0 ; i < limit ; i++ ) { | |
5420 | *addr = i * 4; | |
5421 | addr++; | |
5422 | } | |
5423 | ||
5424 | addr = (unsigned long *)info->memory_base; | |
5425 | ||
5426 | for ( i = 0 ; i < limit ; i++ ) { | |
5427 | if ( *addr != i * 4 ) | |
5428 | return FALSE; | |
5429 | addr++; | |
5430 | } | |
5431 | ||
5432 | memset( info->memory_base, 0, SCA_MEM_SIZE ); | |
5433 | return TRUE; | |
5434 | } | |
5435 | ||
5436 | /* Load data into PCI adapter shared memory. | |
5437 | * | |
5438 | * The PCI9050 releases control of the local bus | |
5439 | * after completing the current read or write operation. | |
5440 | * | |
5441 | * While the PCI9050 write FIFO not empty, the | |
5442 | * PCI9050 treats all of the writes as a single transaction | |
5443 | * and does not release the bus. This causes DMA latency problems | |
5444 | * at high speeds when copying large data blocks to the shared memory. | |
5445 | * | |
5446 | * This function breaks a write into multiple transations by | |
5447 | * interleaving a read which flushes the write FIFO and 'completes' | |
5448 | * the write transation. This allows any pending DMA request to gain control | |
5449 | * of the local bus in a timely fasion. | |
5450 | */ | |
5451 | void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count) | |
5452 | { | |
5453 | /* A load interval of 16 allows for 4 32-bit writes at */ | |
5454 | /* 136ns each for a maximum latency of 542ns on the local bus.*/ | |
5455 | ||
5456 | unsigned short interval = count / sca_pci_load_interval; | |
5457 | unsigned short i; | |
5458 | ||
5459 | for ( i = 0 ; i < interval ; i++ ) | |
5460 | { | |
5461 | memcpy(dest, src, sca_pci_load_interval); | |
5462 | read_status_reg(info); | |
5463 | dest += sca_pci_load_interval; | |
5464 | src += sca_pci_load_interval; | |
5465 | } | |
5466 | ||
5467 | memcpy(dest, src, count % sca_pci_load_interval); | |
5468 | } | |
5469 | ||
5470 | void trace_block(SLMP_INFO *info,const char* data, int count, int xmit) | |
5471 | { | |
5472 | int i; | |
5473 | int linecount; | |
5474 | if (xmit) | |
5475 | printk("%s tx data:\n",info->device_name); | |
5476 | else | |
5477 | printk("%s rx data:\n",info->device_name); | |
5478 | ||
5479 | while(count) { | |
5480 | if (count > 16) | |
5481 | linecount = 16; | |
5482 | else | |
5483 | linecount = count; | |
5484 | ||
5485 | for(i=0;i<linecount;i++) | |
5486 | printk("%02X ",(unsigned char)data[i]); | |
5487 | for(;i<17;i++) | |
5488 | printk(" "); | |
5489 | for(i=0;i<linecount;i++) { | |
5490 | if (data[i]>=040 && data[i]<=0176) | |
5491 | printk("%c",data[i]); | |
5492 | else | |
5493 | printk("."); | |
5494 | } | |
5495 | printk("\n"); | |
5496 | ||
5497 | data += linecount; | |
5498 | count -= linecount; | |
5499 | } | |
5500 | } /* end of trace_block() */ | |
5501 | ||
5502 | /* called when HDLC frame times out | |
5503 | * update stats and do tx completion processing | |
5504 | */ | |
5505 | void tx_timeout(unsigned long context) | |
5506 | { | |
5507 | SLMP_INFO *info = (SLMP_INFO*)context; | |
5508 | unsigned long flags; | |
5509 | ||
5510 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
5511 | printk( "%s(%d):%s tx_timeout()\n", | |
5512 | __FILE__,__LINE__,info->device_name); | |
5513 | if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { | |
5514 | info->icount.txtimeout++; | |
5515 | } | |
5516 | spin_lock_irqsave(&info->lock,flags); | |
5517 | info->tx_active = 0; | |
5518 | info->tx_count = info->tx_put = info->tx_get = 0; | |
5519 | ||
5520 | spin_unlock_irqrestore(&info->lock,flags); | |
5521 | ||
af69c7f9 | 5522 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
5523 | if (info->netcount) |
5524 | hdlcdev_tx_done(info); | |
5525 | else | |
5526 | #endif | |
5527 | bh_transmit(info); | |
5528 | } | |
5529 | ||
5530 | /* called to periodically check the DSR/RI modem signal input status | |
5531 | */ | |
5532 | void status_timeout(unsigned long context) | |
5533 | { | |
5534 | u16 status = 0; | |
5535 | SLMP_INFO *info = (SLMP_INFO*)context; | |
5536 | unsigned long flags; | |
5537 | unsigned char delta; | |
5538 | ||
5539 | ||
5540 | spin_lock_irqsave(&info->lock,flags); | |
5541 | get_signals(info); | |
5542 | spin_unlock_irqrestore(&info->lock,flags); | |
5543 | ||
5544 | /* check for DSR/RI state change */ | |
5545 | ||
5546 | delta = info->old_signals ^ info->serial_signals; | |
5547 | info->old_signals = info->serial_signals; | |
5548 | ||
5549 | if (delta & SerialSignal_DSR) | |
5550 | status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR); | |
5551 | ||
5552 | if (delta & SerialSignal_RI) | |
5553 | status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI); | |
5554 | ||
5555 | if (delta & SerialSignal_DCD) | |
5556 | status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD); | |
5557 | ||
5558 | if (delta & SerialSignal_CTS) | |
5559 | status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS); | |
5560 | ||
5561 | if (status) | |
5562 | isr_io_pin(info,status); | |
5563 | ||
40565f19 | 5564 | mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); |
1da177e4 LT |
5565 | } |
5566 | ||
5567 | ||
5568 | /* Register Access Routines - | |
5569 | * All registers are memory mapped | |
5570 | */ | |
5571 | #define CALC_REGADDR() \ | |
5572 | unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ | |
5573 | if (info->port_num > 1) \ | |
5574 | RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \ | |
5575 | if ( info->port_num & 1) { \ | |
5576 | if (Addr > 0x7f) \ | |
5577 | RegAddr += 0x40; /* DMA access */ \ | |
5578 | else if (Addr > 0x1f && Addr < 0x60) \ | |
5579 | RegAddr += 0x20; /* MSCI access */ \ | |
5580 | } | |
5581 | ||
5582 | ||
5583 | unsigned char read_reg(SLMP_INFO * info, unsigned char Addr) | |
5584 | { | |
5585 | CALC_REGADDR(); | |
5586 | return *RegAddr; | |
5587 | } | |
5588 | void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) | |
5589 | { | |
5590 | CALC_REGADDR(); | |
5591 | *RegAddr = Value; | |
5592 | } | |
5593 | ||
5594 | u16 read_reg16(SLMP_INFO * info, unsigned char Addr) | |
5595 | { | |
5596 | CALC_REGADDR(); | |
5597 | return *((u16 *)RegAddr); | |
5598 | } | |
5599 | ||
5600 | void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value) | |
5601 | { | |
5602 | CALC_REGADDR(); | |
5603 | *((u16 *)RegAddr) = Value; | |
5604 | } | |
5605 | ||
5606 | unsigned char read_status_reg(SLMP_INFO * info) | |
5607 | { | |
5608 | unsigned char *RegAddr = (unsigned char *)info->statctrl_base; | |
5609 | return *RegAddr; | |
5610 | } | |
5611 | ||
5612 | void write_control_reg(SLMP_INFO * info) | |
5613 | { | |
5614 | unsigned char *RegAddr = (unsigned char *)info->statctrl_base; | |
5615 | *RegAddr = info->port_array[0]->ctrlreg_value; | |
5616 | } | |
5617 | ||
5618 | ||
5619 | static int __devinit synclinkmp_init_one (struct pci_dev *dev, | |
5620 | const struct pci_device_id *ent) | |
5621 | { | |
5622 | if (pci_enable_device(dev)) { | |
5623 | printk("error enabling pci device %p\n", dev); | |
5624 | return -EIO; | |
5625 | } | |
5626 | device_init( ++synclinkmp_adapter_count, dev ); | |
5627 | return 0; | |
5628 | } | |
5629 | ||
5630 | static void __devexit synclinkmp_remove_one (struct pci_dev *dev) | |
5631 | { | |
5632 | } |