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io_edgeport: Fix various bogus returns to the tty layer
[linux-2.6-block.git] / drivers / char / synclinkmp.c
CommitLineData
1da177e4 1/*
7f3edb94 2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
1da177e4
LT		 3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29#if defined(__i386__)
30# define BREAKPOINT() asm(" int $3");
31#else
32# define BREAKPOINT() { }
33#endif
34
35#define MAX_DEVICES 12
36
1da177e4
LT		 37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/sched.h>
41#include <linux/timer.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46#include <linux/serial.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/ptrace.h>
51#include <linux/ioport.h>
52#include <linux/mm.h>
53#include <linux/slab.h>
54#include <linux/netdevice.h>
55#include <linux/vmalloc.h>
56#include <linux/init.h>
1da177e4
LT		 57#include <linux/delay.h>
58#include <linux/ioctl.h>
59
60#include <asm/system.h>
61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/dma.h>
64#include <linux/bitops.h>
65#include <asm/types.h>
66#include <linux/termios.h>
67#include <linux/workqueue.h>
68#include <linux/hdlc.h>
3dd1247f 69#include <linux/synclink.h>
1da177e4 70
af69c7f9
PF		 71#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72#define SYNCLINK_GENERIC_HDLC 1
73#else
74#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 75#endif
76
77#define GET_USER(error,value,addr) error = get_user(value,addr)
78#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79#define PUT_USER(error,value,addr) error = put_user(value,addr)
80#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82#include <asm/uaccess.h>
83
1da177e4
LT		 84static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98};
99
100/* size in bytes of DMA data buffers */
101#define SCABUFSIZE 1024
102#define SCA_MEM_SIZE 0x40000
103#define SCA_BASE_SIZE 512
104#define SCA_REG_SIZE 16
105#define SCA_MAX_PORTS 4
106#define SCAMAXDESC 128
107
108#define BUFFERLISTSIZE 4096
109
110/* SCA-I style DMA buffer descriptor */
111typedef struct _SCADESC
112{
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120} SCADESC, *PSCADESC;
121
122typedef struct _SCADESC_EX
123{
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127} SCADESC_EX, *PSCADESC_EX;
128
129/* The queue of BH actions to be performed */
130
131#define BH_RECEIVE 1
132#define BH_TRANSMIT 2
133#define BH_STATUS 4
134
135#define IO_PIN_SHUTDOWN_LIMIT 100
136
1da177e4
LT		 137struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146};
147
148/*
149 * Device instance data structure
150 */
151typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
8fb06c77 154 struct tty_port port;
1da177e4
LT		 155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
1da177e4
LT		 161 int timeout;
162 int x_char; /* xon/xoff character */
1da177e4
LT		 163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
1da177e4
LT		 172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
0fab6de0 185 bool bh_running; /* Protection from multiple */
1da177e4 186 int isr_overflow;
0fab6de0 187 bool bh_requested;
1da177e4
LT		 188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
0fab6de0
JP		 210 bool rx_enabled;
211 bool rx_overflow;
1da177e4 212
0fab6de0
JP		 213 bool tx_enabled;
214 bool tx_active;
1da177e4
LT		 215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
0fab6de0 235 bool irq_requested; /* true if IRQ requested */
1da177e4
LT		 236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
0fab6de0 241 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
0fab6de0 252 bool sca_base_requested;
1da177e4
LT		 253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
0fab6de0 262 bool sca_statctrl_requested;
1da177e4
LT		 263
264 u32 misc_ctrl_value;
265 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
266 char char_buf[MAX_ASYNC_BUFFER_SIZE];
0fab6de0 267 bool drop_rts_on_tx_done;
1da177e4
LT		 268
269 struct _input_signal_events input_signal_events;
270
271 /* SPPP/Cisco HDLC device parts */
272 int netcount;
273 int dosyncppp;
274 spinlock_t netlock;
275
af69c7f9 276#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 277 struct net_device *netdev;
278#endif
279
280} SLMP_INFO;
281
282#define MGSL_MAGIC 0x5401
283
284/*
285 * define serial signal status change macros
286 */
287#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
288#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
289#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
290#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
291
292/* Common Register macros */
293#define LPR 0x00
294#define PABR0 0x02
295#define PABR1 0x03
296#define WCRL 0x04
297#define WCRM 0x05
298#define WCRH 0x06
299#define DPCR 0x08
300#define DMER 0x09
301#define ISR0 0x10
302#define ISR1 0x11
303#define ISR2 0x12
304#define IER0 0x14
305#define IER1 0x15
306#define IER2 0x16
307#define ITCR 0x18
308#define INTVR 0x1a
309#define IMVR 0x1c
310
311/* MSCI Register macros */
312#define TRB 0x20
313#define TRBL 0x20
314#define TRBH 0x21
315#define SR0 0x22
316#define SR1 0x23
317#define SR2 0x24
318#define SR3 0x25
319#define FST 0x26
320#define IE0 0x28
321#define IE1 0x29
322#define IE2 0x2a
323#define FIE 0x2b
324#define CMD 0x2c
325#define MD0 0x2e
326#define MD1 0x2f
327#define MD2 0x30
328#define CTL 0x31
329#define SA0 0x32
330#define SA1 0x33
331#define IDL 0x34
332#define TMC 0x35
333#define RXS 0x36
334#define TXS 0x37
335#define TRC0 0x38
336#define TRC1 0x39
337#define RRC 0x3a
338#define CST0 0x3c
339#define CST1 0x3d
340
341/* Timer Register Macros */
342#define TCNT 0x60
343#define TCNTL 0x60
344#define TCNTH 0x61
345#define TCONR 0x62
346#define TCONRL 0x62
347#define TCONRH 0x63
348#define TMCS 0x64
349#define TEPR 0x65
350
351/* DMA Controller Register macros */
352#define DARL 0x80
353#define DARH 0x81
354#define DARB 0x82
355#define BAR 0x80
356#define BARL 0x80
357#define BARH 0x81
358#define BARB 0x82
359#define SAR 0x84
360#define SARL 0x84
361#define SARH 0x85
362#define SARB 0x86
363#define CPB 0x86
364#define CDA 0x88
365#define CDAL 0x88
366#define CDAH 0x89
367#define EDA 0x8a
368#define EDAL 0x8a
369#define EDAH 0x8b
370#define BFL 0x8c
371#define BFLL 0x8c
372#define BFLH 0x8d
373#define BCR 0x8e
374#define BCRL 0x8e
375#define BCRH 0x8f
376#define DSR 0x90
377#define DMR 0x91
378#define FCT 0x93
379#define DIR 0x94
380#define DCMD 0x95
381
382/* combine with timer or DMA register address */
383#define TIMER0 0x00
384#define TIMER1 0x08
385#define TIMER2 0x10
386#define TIMER3 0x18
387#define RXDMA 0x00
388#define TXDMA 0x20
389
390/* SCA Command Codes */
391#define NOOP 0x00
392#define TXRESET 0x01
393#define TXENABLE 0x02
394#define TXDISABLE 0x03
395#define TXCRCINIT 0x04
396#define TXCRCEXCL 0x05
397#define TXEOM 0x06
398#define TXABORT 0x07
399#define MPON 0x08
400#define TXBUFCLR 0x09
401#define RXRESET 0x11
402#define RXENABLE 0x12
403#define RXDISABLE 0x13
404#define RXCRCINIT 0x14
405#define RXREJECT 0x15
406#define SEARCHMP 0x16
407#define RXCRCEXCL 0x17
408#define RXCRCCALC 0x18
409#define CHRESET 0x21
410#define HUNT 0x31
411
412/* DMA command codes */
413#define SWABORT 0x01
414#define FEICLEAR 0x02
415
416/* IE0 */
417#define TXINTE BIT7
418#define RXINTE BIT6
419#define TXRDYE BIT1
420#define RXRDYE BIT0
421
422/* IE1 & SR1 */
423#define UDRN BIT7
424#define IDLE BIT6
425#define SYNCD BIT4
426#define FLGD BIT4
427#define CCTS BIT3
428#define CDCD BIT2
429#define BRKD BIT1
430#define ABTD BIT1
431#define GAPD BIT1
432#define BRKE BIT0
433#define IDLD BIT0
434
435/* IE2 & SR2 */
436#define EOM BIT7
437#define PMP BIT6
438#define SHRT BIT6
439#define PE BIT5
440#define ABT BIT5
441#define FRME BIT4
442#define RBIT BIT4
443#define OVRN BIT3
444#define CRCE BIT2
445
446
447/*
448 * Global linked list of SyncLink devices
449 */
450static SLMP_INFO *synclinkmp_device_list = NULL;
451static int synclinkmp_adapter_count = -1;
452static int synclinkmp_device_count = 0;
453
454/*
455 * Set this param to non-zero to load eax with the
456 * .text section address and breakpoint on module load.
457 * This is useful for use with gdb and add-symbol-file command.
458 */
8fb06c77 459static int break_on_load = 0;
1da177e4
LT		 460
461/*
462 * Driver major number, defaults to zero to get auto
463 * assigned major number. May be forced as module parameter.
464 */
8fb06c77 465static int ttymajor = 0;
1da177e4
LT		 466
467/*
468 * Array of user specified options for ISA adapters.
469 */
470static int debug_level = 0;
471static int maxframe[MAX_DEVICES] = {0,};
472static int dosyncppp[MAX_DEVICES] = {0,};
473
474module_param(break_on_load, bool, 0);
475module_param(ttymajor, int, 0);
476module_param(debug_level, int, 0);
477module_param_array(maxframe, int, NULL, 0);
478module_param_array(dosyncppp, int, NULL, 0);
479
480static char *driver_name = "SyncLink MultiPort driver";
7f3edb94 481static char *driver_version = "$Revision: 4.38 $";
1da177e4
LT		 482
483static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
484static void synclinkmp_remove_one(struct pci_dev *dev);
485
486static struct pci_device_id synclinkmp_pci_tbl[] = {
487 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
488 { 0, }, /* terminate list */
489};
490MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
491
492MODULE_LICENSE("GPL");
493
494static struct pci_driver synclinkmp_pci_driver = {
495 .name = "synclinkmp",
496 .id_table = synclinkmp_pci_tbl,
497 .probe = synclinkmp_init_one,
498 .remove = __devexit_p(synclinkmp_remove_one),
499};
500
501
502static struct tty_driver *serial_driver;
503
504/* number of characters left in xmit buffer before we ask for more */
505#define WAKEUP_CHARS 256
506
507
508/* tty callbacks */
509
510static int open(struct tty_struct *tty, struct file * filp);
511static void close(struct tty_struct *tty, struct file * filp);
512static void hangup(struct tty_struct *tty);
606d099c 513static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
1da177e4
LT		 514
515static int write(struct tty_struct *tty, const unsigned char *buf, int count);
55da7789 516static int put_char(struct tty_struct *tty, unsigned char ch);
1da177e4
LT		 517static void send_xchar(struct tty_struct *tty, char ch);
518static void wait_until_sent(struct tty_struct *tty, int timeout);
519static int write_room(struct tty_struct *tty);
520static void flush_chars(struct tty_struct *tty);
521static void flush_buffer(struct tty_struct *tty);
522static void tx_hold(struct tty_struct *tty);
523static void tx_release(struct tty_struct *tty);
524
525static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
526static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
527static int chars_in_buffer(struct tty_struct *tty);
528static void throttle(struct tty_struct * tty);
529static void unthrottle(struct tty_struct * tty);
530static void set_break(struct tty_struct *tty, int break_state);
531
af69c7f9 532#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 533#define dev_to_port(D) (dev_to_hdlc(D)->priv)
534static void hdlcdev_tx_done(SLMP_INFO *info);
535static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
536static int hdlcdev_init(SLMP_INFO *info);
537static void hdlcdev_exit(SLMP_INFO *info);
538#endif
539
540/* ioctl handlers */
541
542static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
543static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
544static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
545static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
546static int set_txidle(SLMP_INFO *info, int idle_mode);
547static int tx_enable(SLMP_INFO *info, int enable);
548static int tx_abort(SLMP_INFO *info);
549static int rx_enable(SLMP_INFO *info, int enable);
1da177e4
LT		 550static int modem_input_wait(SLMP_INFO *info,int arg);
551static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
552static int tiocmget(struct tty_struct *tty, struct file *file);
553static int tiocmset(struct tty_struct *tty, struct file *file,
554 unsigned int set, unsigned int clear);
555static void set_break(struct tty_struct *tty, int break_state);
556
557static void add_device(SLMP_INFO *info);
558static void device_init(int adapter_num, struct pci_dev *pdev);
559static int claim_resources(SLMP_INFO *info);
560static void release_resources(SLMP_INFO *info);
561
562static int startup(SLMP_INFO *info);
563static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
564static void shutdown(SLMP_INFO *info);
565static void program_hw(SLMP_INFO *info);
566static void change_params(SLMP_INFO *info);
567
0fab6de0
JP		 568static bool init_adapter(SLMP_INFO *info);
569static bool register_test(SLMP_INFO *info);
570static bool irq_test(SLMP_INFO *info);
571static bool loopback_test(SLMP_INFO *info);
1da177e4 572static int adapter_test(SLMP_INFO *info);
0fab6de0 573static bool memory_test(SLMP_INFO *info);
1da177e4
LT		 574
575static void reset_adapter(SLMP_INFO *info);
576static void reset_port(SLMP_INFO *info);
577static void async_mode(SLMP_INFO *info);
578static void hdlc_mode(SLMP_INFO *info);
579
580static void rx_stop(SLMP_INFO *info);
581static void rx_start(SLMP_INFO *info);
582static void rx_reset_buffers(SLMP_INFO *info);
583static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
0fab6de0 584static bool rx_get_frame(SLMP_INFO *info);
1da177e4
LT		 585
586static void tx_start(SLMP_INFO *info);
587static void tx_stop(SLMP_INFO *info);
588static void tx_load_fifo(SLMP_INFO *info);
589static void tx_set_idle(SLMP_INFO *info);
590static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
591
592static void get_signals(SLMP_INFO *info);
593static void set_signals(SLMP_INFO *info);
594static void enable_loopback(SLMP_INFO *info, int enable);
595static void set_rate(SLMP_INFO *info, u32 data_rate);
596
597static int bh_action(SLMP_INFO *info);
c4028958 598static void bh_handler(struct work_struct *work);
1da177e4
LT		 599static void bh_receive(SLMP_INFO *info);
600static void bh_transmit(SLMP_INFO *info);
601static void bh_status(SLMP_INFO *info);
602static void isr_timer(SLMP_INFO *info);
603static void isr_rxint(SLMP_INFO *info);
604static void isr_rxrdy(SLMP_INFO *info);
605static void isr_txint(SLMP_INFO *info);
606static void isr_txrdy(SLMP_INFO *info);
607static void isr_rxdmaok(SLMP_INFO *info);
608static void isr_rxdmaerror(SLMP_INFO *info);
609static void isr_txdmaok(SLMP_INFO *info);
610static void isr_txdmaerror(SLMP_INFO *info);
611static void isr_io_pin(SLMP_INFO *info, u16 status);
612
613static int alloc_dma_bufs(SLMP_INFO *info);
614static void free_dma_bufs(SLMP_INFO *info);
615static int alloc_buf_list(SLMP_INFO *info);
616static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
617static int alloc_tmp_rx_buf(SLMP_INFO *info);
618static void free_tmp_rx_buf(SLMP_INFO *info);
619
620static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
621static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
622static void tx_timeout(unsigned long context);
623static void status_timeout(unsigned long context);
624
625static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
626static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
627static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
628static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
629static unsigned char read_status_reg(SLMP_INFO * info);
630static void write_control_reg(SLMP_INFO * info);
631
632
633static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
634static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
635static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
636
637static u32 misc_ctrl_value = 0x007e4040;
761a444d 638static u32 lcr1_brdr_value = 0x00800028;
1da177e4
LT		 639
640static u32 read_ahead_count = 8;
641
642/* DPCR, DMA Priority Control
643 *
644 * 07..05 Not used, must be 0
645 * 04 BRC, bus release condition: 0=all transfers complete
646 * 1=release after 1 xfer on all channels
647 * 03 CCC, channel change condition: 0=every cycle
648 * 1=after each channel completes all xfers
649 * 02..00 PR<2..0>, priority 100=round robin
650 *
651 * 00000100 = 0x00
652 */
653static unsigned char dma_priority = 0x04;
654
655// Number of bytes that can be written to shared RAM
656// in a single write operation
657static u32 sca_pci_load_interval = 64;
658
659/*
660 * 1st function defined in .text section. Calling this function in
661 * init_module() followed by a breakpoint allows a remote debugger
662 * (gdb) to get the .text address for the add-symbol-file command.
663 * This allows remote debugging of dynamically loadable modules.
664 */
665static void* synclinkmp_get_text_ptr(void);
666static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
667
668static inline int sanity_check(SLMP_INFO *info,
669 char *name, const char *routine)
670{
671#ifdef SANITY_CHECK
672 static const char *badmagic =
673 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
674 static const char *badinfo =
675 "Warning: null synclinkmp_struct for (%s) in %s\n";
676
677 if (!info) {
678 printk(badinfo, name, routine);
679 return 1;
680 }
681 if (info->magic != MGSL_MAGIC) {
682 printk(badmagic, name, routine);
683 return 1;
684 }
685#else
686 if (!info)
687 return 1;
688#endif
689 return 0;
690}
691
692/**
693 * line discipline callback wrappers
694 *
695 * The wrappers maintain line discipline references
696 * while calling into the line discipline.
697 *
698 * ldisc_receive_buf - pass receive data to line discipline
699 */
700
701static void ldisc_receive_buf(struct tty_struct *tty,
702 const __u8 *data, char *flags, int count)
703{
704 struct tty_ldisc *ld;
705 if (!tty)
706 return;
707 ld = tty_ldisc_ref(tty);
708 if (ld) {
a352def2
AC		 709 if (ld->ops->receive_buf)
710 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 711 tty_ldisc_deref(ld);
712 }
713}
714
715/* tty callbacks */
716
717/* Called when a port is opened. Init and enable port.
718 */
719static int open(struct tty_struct *tty, struct file *filp)
720{
721 SLMP_INFO *info;
722 int retval, line;
723 unsigned long flags;
724
725 line = tty->index;
726 if ((line < 0) || (line >= synclinkmp_device_count)) {
727 printk("%s(%d): open with invalid line #%d.\n",
728 __FILE__,__LINE__,line);
729 return -ENODEV;
730 }
731
732 info = synclinkmp_device_list;
733 while(info && info->line != line)
734 info = info->next_device;
735 if (sanity_check(info, tty->name, "open"))
736 return -ENODEV;
737 if ( info->init_error ) {
738 printk("%s(%d):%s device is not allocated, init error=%d\n",
739 __FILE__,__LINE__,info->device_name,info->init_error);
740 return -ENODEV;
741 }
742
743 tty->driver_data = info;
8fb06c77 744 info->port.tty = tty;
1da177e4
LT		 745
746 if (debug_level >= DEBUG_LEVEL_INFO)
747 printk("%s(%d):%s open(), old ref count = %d\n",
8fb06c77 748 __FILE__,__LINE__,tty->driver->name, info->port.count);
1da177e4
LT		 749
750 /* If port is closing, signal caller to try again */
8fb06c77
AC		 751 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
752 if (info->port.flags & ASYNC_CLOSING)
753 interruptible_sleep_on(&info->port.close_wait);
754 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 755 -EAGAIN : -ERESTARTSYS);
756 goto cleanup;
757 }
758
8fb06c77 759 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 760
761 spin_lock_irqsave(&info->netlock, flags);
762 if (info->netcount) {
763 retval = -EBUSY;
764 spin_unlock_irqrestore(&info->netlock, flags);
765 goto cleanup;
766 }
8fb06c77 767 info->port.count++;
1da177e4
LT		 768 spin_unlock_irqrestore(&info->netlock, flags);
769
8fb06c77 770 if (info->port.count == 1) {
1da177e4
LT		 771 /* 1st open on this device, init hardware */
772 retval = startup(info);
773 if (retval < 0)
774 goto cleanup;
775 }
776
777 retval = block_til_ready(tty, filp, info);
778 if (retval) {
779 if (debug_level >= DEBUG_LEVEL_INFO)
780 printk("%s(%d):%s block_til_ready() returned %d\n",
781 __FILE__,__LINE__, info->device_name, retval);
782 goto cleanup;
783 }
784
785 if (debug_level >= DEBUG_LEVEL_INFO)
786 printk("%s(%d):%s open() success\n",
787 __FILE__,__LINE__, info->device_name);
788 retval = 0;
789
790cleanup:
791 if (retval) {
792 if (tty->count == 1)
8fb06c77
AC		 793 info->port.tty = NULL; /* tty layer will release tty struct */
794 if(info->port.count)
795 info->port.count--;
1da177e4
LT		 796 }
797
798 return retval;
799}
800
801/* Called when port is closed. Wait for remaining data to be
802 * sent. Disable port and free resources.
803 */
804static void close(struct tty_struct *tty, struct file *filp)
805{
806 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
807
808 if (sanity_check(info, tty->name, "close"))
809 return;
810
811 if (debug_level >= DEBUG_LEVEL_INFO)
812 printk("%s(%d):%s close() entry, count=%d\n",
8fb06c77 813 __FILE__,__LINE__, info->device_name, info->port.count);
1da177e4 814
8fb06c77 815 if (!info->port.count)
1da177e4
LT		 816 return;
817
818 if (tty_hung_up_p(filp))
819 goto cleanup;
820
8fb06c77 821 if ((tty->count == 1) && (info->port.count != 1)) {
1da177e4
LT		 822 /*
823 * tty->count is 1 and the tty structure will be freed.
8fb06c77 824 * info->port.count should be one in this case.
1da177e4
LT		 825 * if it's not, correct it so that the port is shutdown.
826 */
827 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
8fb06c77
AC		 828 "info->port.count is %d\n",
829 __FILE__,__LINE__, info->device_name, info->port.count);
830 info->port.count = 1;
1da177e4
LT		 831 }
832
8fb06c77 833 info->port.count--;
1da177e4
LT		 834
835 /* if at least one open remaining, leave hardware active */
8fb06c77 836 if (info->port.count)
1da177e4
LT		 837 goto cleanup;
838
8fb06c77 839 info->port.flags |= ASYNC_CLOSING;
1da177e4
LT		 840
841 /* set tty->closing to notify line discipline to
842 * only process XON/XOFF characters. Only the N_TTY
843 * discipline appears to use this (ppp does not).
844 */
845 tty->closing = 1;
846
847 /* wait for transmit data to clear all layers */
848
44b7d1b3 849 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
1da177e4
LT		 850 if (debug_level >= DEBUG_LEVEL_INFO)
851 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
852 __FILE__,__LINE__, info->device_name );
44b7d1b3 853 tty_wait_until_sent(tty, info->port.closing_wait);
1da177e4
LT		 854 }
855
8fb06c77 856 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4
LT		 857 wait_until_sent(tty, info->timeout);
858
978e595f 859 flush_buffer(tty);
1da177e4
LT		 860
861 tty_ldisc_flush(tty);
862
863 shutdown(info);
864
865 tty->closing = 0;
8fb06c77 866 info->port.tty = NULL;
1da177e4 867
8fb06c77 868 if (info->port.blocked_open) {
44b7d1b3
AC		 869 if (info->port.close_delay) {
870 msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
1da177e4 871 }
8fb06c77 872 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 873 }
874
8fb06c77 875 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
1da177e4 876
8fb06c77 877 wake_up_interruptible(&info->port.close_wait);
1da177e4
LT		 878
879cleanup:
880 if (debug_level >= DEBUG_LEVEL_INFO)
881 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
8fb06c77 882 tty->driver->name, info->port.count);
1da177e4
LT		 883}
884
885/* Called by tty_hangup() when a hangup is signaled.
886 * This is the same as closing all open descriptors for the port.
887 */
888static void hangup(struct tty_struct *tty)
889{
890 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
891
892 if (debug_level >= DEBUG_LEVEL_INFO)
893 printk("%s(%d):%s hangup()\n",
894 __FILE__,__LINE__, info->device_name );
895
896 if (sanity_check(info, tty->name, "hangup"))
897 return;
898
899 flush_buffer(tty);
900 shutdown(info);
901
8fb06c77
AC		 902 info->port.count = 0;
903 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
904 info->port.tty = NULL;
1da177e4 905
8fb06c77 906 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 907}
908
909/* Set new termios settings
910 */
606d099c 911static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 912{
913 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
914 unsigned long flags;
915
916 if (debug_level >= DEBUG_LEVEL_INFO)
917 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
918 tty->driver->name );
919
1da177e4
LT		 920 change_params(info);
921
922 /* Handle transition to B0 status */
923 if (old_termios->c_cflag & CBAUD &&
924 !(tty->termios->c_cflag & CBAUD)) {
925 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
926 spin_lock_irqsave(&info->lock,flags);
927 set_signals(info);
928 spin_unlock_irqrestore(&info->lock,flags);
929 }
930
931 /* Handle transition away from B0 status */
932 if (!(old_termios->c_cflag & CBAUD) &&
933 tty->termios->c_cflag & CBAUD) {
934 info->serial_signals |= SerialSignal_DTR;
935 if (!(tty->termios->c_cflag & CRTSCTS) ||
936 !test_bit(TTY_THROTTLED, &tty->flags)) {
937 info->serial_signals |= SerialSignal_RTS;
938 }
939 spin_lock_irqsave(&info->lock,flags);
940 set_signals(info);
941 spin_unlock_irqrestore(&info->lock,flags);
942 }
943
944 /* Handle turning off CRTSCTS */
945 if (old_termios->c_cflag & CRTSCTS &&
946 !(tty->termios->c_cflag & CRTSCTS)) {
947 tty->hw_stopped = 0;
948 tx_release(tty);
949 }
950}
951
952/* Send a block of data
953 *
954 * Arguments:
955 *
956 * tty pointer to tty information structure
957 * buf pointer to buffer containing send data
958 * count size of send data in bytes
959 *
960 * Return Value: number of characters written
961 */
962static int write(struct tty_struct *tty,
963 const unsigned char *buf, int count)
964{
965 int c, ret = 0;
966 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
967 unsigned long flags;
968
969 if (debug_level >= DEBUG_LEVEL_INFO)
970 printk("%s(%d):%s write() count=%d\n",
971 __FILE__,__LINE__,info->device_name,count);
972
973 if (sanity_check(info, tty->name, "write"))
974 goto cleanup;
975
326f28e9 976 if (!info->tx_buf)
1da177e4
LT		 977 goto cleanup;
978
979 if (info->params.mode == MGSL_MODE_HDLC) {
980 if (count > info->max_frame_size) {
981 ret = -EIO;
982 goto cleanup;
983 }
984 if (info->tx_active)
985 goto cleanup;
986 if (info->tx_count) {
987 /* send accumulated data from send_char() calls */
988 /* as frame and wait before accepting more data. */
989 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
990 goto start;
991 }
992 ret = info->tx_count = count;
993 tx_load_dma_buffer(info, buf, count);
994 goto start;
995 }
996
997 for (;;) {
998 c = min_t(int, count,
999 min(info->max_frame_size - info->tx_count - 1,
1000 info->max_frame_size - info->tx_put));
1001 if (c <= 0)
1002 break;
1003
1004 memcpy(info->tx_buf + info->tx_put, buf, c);
1005
1006 spin_lock_irqsave(&info->lock,flags);
1007 info->tx_put += c;
1008 if (info->tx_put >= info->max_frame_size)
1009 info->tx_put -= info->max_frame_size;
1010 info->tx_count += c;
1011 spin_unlock_irqrestore(&info->lock,flags);
1012
1013 buf += c;
1014 count -= c;
1015 ret += c;
1016 }
1017
1018 if (info->params.mode == MGSL_MODE_HDLC) {
1019 if (count) {
1020 ret = info->tx_count = 0;
1021 goto cleanup;
1022 }
1023 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1024 }
1025start:
1026 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1027 spin_lock_irqsave(&info->lock,flags);
1028 if (!info->tx_active)
1029 tx_start(info);
1030 spin_unlock_irqrestore(&info->lock,flags);
1031 }
1032
1033cleanup:
1034 if (debug_level >= DEBUG_LEVEL_INFO)
1035 printk( "%s(%d):%s write() returning=%d\n",
1036 __FILE__,__LINE__,info->device_name,ret);
1037 return ret;
1038}
1039
1040/* Add a character to the transmit buffer.
1041 */
55da7789 1042static int put_char(struct tty_struct *tty, unsigned char ch)
1da177e4
LT		 1043{
1044 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1045 unsigned long flags;
55da7789 1046 int ret = 0;
1da177e4
LT		 1047
1048 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1049 printk( "%s(%d):%s put_char(%d)\n",
1050 __FILE__,__LINE__,info->device_name,ch);
1051 }
1052
1053 if (sanity_check(info, tty->name, "put_char"))
55da7789 1054 return 0;
1da177e4 1055
326f28e9 1056 if (!info->tx_buf)
55da7789 1057 return 0;
1da177e4
LT		 1058
1059 spin_lock_irqsave(&info->lock,flags);
1060
1061 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1062 !info->tx_active ) {
1063
1064 if (info->tx_count < info->max_frame_size - 1) {
1065 info->tx_buf[info->tx_put++] = ch;
1066 if (info->tx_put >= info->max_frame_size)
1067 info->tx_put -= info->max_frame_size;
1068 info->tx_count++;
55da7789 1069 ret = 1;
1da177e4
LT		 1070 }
1071 }
1072
1073 spin_unlock_irqrestore(&info->lock,flags);
55da7789 1074 return ret;
1da177e4
LT		 1075}
1076
1077/* Send a high-priority XON/XOFF character
1078 */
1079static void send_xchar(struct tty_struct *tty, char ch)
1080{
1081 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1082 unsigned long flags;
1083
1084 if (debug_level >= DEBUG_LEVEL_INFO)
1085 printk("%s(%d):%s send_xchar(%d)\n",
1086 __FILE__,__LINE__, info->device_name, ch );
1087
1088 if (sanity_check(info, tty->name, "send_xchar"))
1089 return;
1090
1091 info->x_char = ch;
1092 if (ch) {
1093 /* Make sure transmit interrupts are on */
1094 spin_lock_irqsave(&info->lock,flags);
1095 if (!info->tx_enabled)
1096 tx_start(info);
1097 spin_unlock_irqrestore(&info->lock,flags);
1098 }
1099}
1100
1101/* Wait until the transmitter is empty.
1102 */
1103static void wait_until_sent(struct tty_struct *tty, int timeout)
1104{
1105 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1106 unsigned long orig_jiffies, char_time;
1107
1108 if (!info )
1109 return;
1110
1111 if (debug_level >= DEBUG_LEVEL_INFO)
1112 printk("%s(%d):%s wait_until_sent() entry\n",
1113 __FILE__,__LINE__, info->device_name );
1114
1115 if (sanity_check(info, tty->name, "wait_until_sent"))
1116 return;
1117
978e595f
AC		 1118 lock_kernel();
1119
8fb06c77 1120 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 1121 goto exit;
1122
1123 orig_jiffies = jiffies;
1124
1125 /* Set check interval to 1/5 of estimated time to
1126 * send a character, and make it at least 1. The check
1127 * interval should also be less than the timeout.
1128 * Note: use tight timings here to satisfy the NIST-PCTS.
1129 */
1130
1131 if ( info->params.data_rate ) {
1132 char_time = info->timeout/(32 * 5);
1133 if (!char_time)
1134 char_time++;
1135 } else
1136 char_time = 1;
1137
1138 if (timeout)
1139 char_time = min_t(unsigned long, char_time, timeout);
1140
1141 if ( info->params.mode == MGSL_MODE_HDLC ) {
1142 while (info->tx_active) {
1143 msleep_interruptible(jiffies_to_msecs(char_time));
1144 if (signal_pending(current))
1145 break;
1146 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1147 break;
1148 }
1149 } else {
1150 //TODO: determine if there is something similar to USC16C32
1151 // TXSTATUS_ALL_SENT status
1152 while ( info->tx_active && info->tx_enabled) {
1153 msleep_interruptible(jiffies_to_msecs(char_time));
1154 if (signal_pending(current))
1155 break;
1156 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1157 break;
1158 }
1159 }
1160
1161exit:
978e595f 1162 unlock_kernel();
1da177e4
LT		 1163 if (debug_level >= DEBUG_LEVEL_INFO)
1164 printk("%s(%d):%s wait_until_sent() exit\n",
1165 __FILE__,__LINE__, info->device_name );
1166}
1167
1168/* Return the count of free bytes in transmit buffer
1169 */
1170static int write_room(struct tty_struct *tty)
1171{
1172 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1173 int ret;
1174
1175 if (sanity_check(info, tty->name, "write_room"))
1176 return 0;
1177
978e595f 1178 lock_kernel();
1da177e4
LT		 1179 if (info->params.mode == MGSL_MODE_HDLC) {
1180 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1181 } else {
1182 ret = info->max_frame_size - info->tx_count - 1;
1183 if (ret < 0)
1184 ret = 0;
1185 }
978e595f 1186 unlock_kernel();
1da177e4
LT		 1187
1188 if (debug_level >= DEBUG_LEVEL_INFO)
1189 printk("%s(%d):%s write_room()=%d\n",
1190 __FILE__, __LINE__, info->device_name, ret);
1191
1192 return ret;
1193}
1194
1195/* enable transmitter and send remaining buffered characters
1196 */
1197static void flush_chars(struct tty_struct *tty)
1198{
1199 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1200 unsigned long flags;
1201
1202 if ( debug_level >= DEBUG_LEVEL_INFO )
1203 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1204 __FILE__,__LINE__,info->device_name,info->tx_count);
1205
1206 if (sanity_check(info, tty->name, "flush_chars"))
1207 return;
1208
1209 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1210 !info->tx_buf)
1211 return;
1212
1213 if ( debug_level >= DEBUG_LEVEL_INFO )
1214 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1215 __FILE__,__LINE__,info->device_name );
1216
1217 spin_lock_irqsave(&info->lock,flags);
1218
1219 if (!info->tx_active) {
1220 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1221 info->tx_count ) {
1222 /* operating in synchronous (frame oriented) mode */
1223 /* copy data from circular tx_buf to */
1224 /* transmit DMA buffer. */
1225 tx_load_dma_buffer(info,
1226 info->tx_buf,info->tx_count);
1227 }
1228 tx_start(info);
1229 }
1230
1231 spin_unlock_irqrestore(&info->lock,flags);
1232}
1233
1234/* Discard all data in the send buffer
1235 */
1236static void flush_buffer(struct tty_struct *tty)
1237{
1238 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1239 unsigned long flags;
1240
1241 if (debug_level >= DEBUG_LEVEL_INFO)
1242 printk("%s(%d):%s flush_buffer() entry\n",
1243 __FILE__,__LINE__, info->device_name );
1244
1245 if (sanity_check(info, tty->name, "flush_buffer"))
1246 return;
1247
1248 spin_lock_irqsave(&info->lock,flags);
1249 info->tx_count = info->tx_put = info->tx_get = 0;
1250 del_timer(&info->tx_timer);
1251 spin_unlock_irqrestore(&info->lock,flags);
1252
1da177e4
LT		 1253 tty_wakeup(tty);
1254}
1255
1256/* throttle (stop) transmitter
1257 */
1258static void tx_hold(struct tty_struct *tty)
1259{
1260 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1261 unsigned long flags;
1262
1263 if (sanity_check(info, tty->name, "tx_hold"))
1264 return;
1265
1266 if ( debug_level >= DEBUG_LEVEL_INFO )
1267 printk("%s(%d):%s tx_hold()\n",
1268 __FILE__,__LINE__,info->device_name);
1269
1270 spin_lock_irqsave(&info->lock,flags);
1271 if (info->tx_enabled)
1272 tx_stop(info);
1273 spin_unlock_irqrestore(&info->lock,flags);
1274}
1275
1276/* release (start) transmitter
1277 */
1278static void tx_release(struct tty_struct *tty)
1279{
1280 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1281 unsigned long flags;
1282
1283 if (sanity_check(info, tty->name, "tx_release"))
1284 return;
1285
1286 if ( debug_level >= DEBUG_LEVEL_INFO )
1287 printk("%s(%d):%s tx_release()\n",
1288 __FILE__,__LINE__,info->device_name);
1289
1290 spin_lock_irqsave(&info->lock,flags);
1291 if (!info->tx_enabled)
1292 tx_start(info);
1293 spin_unlock_irqrestore(&info->lock,flags);
1294}
1295
1296/* Service an IOCTL request
1297 *
1298 * Arguments:
1299 *
1300 * tty pointer to tty instance data
1301 * file pointer to associated file object for device
1302 * cmd IOCTL command code
1303 * arg command argument/context
1304 *
1305 * Return Value: 0 if success, otherwise error code
1306 */
1f8cabb7 1307static int do_ioctl(struct tty_struct *tty, struct file *file,
1da177e4
LT		 1308 unsigned int cmd, unsigned long arg)
1309{
1310 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1311 int error;
1312 struct mgsl_icount cnow; /* kernel counter temps */
1313 struct serial_icounter_struct __user *p_cuser; /* user space */
1314 unsigned long flags;
1315 void __user *argp = (void __user *)arg;
1316
1317 if (debug_level >= DEBUG_LEVEL_INFO)
1318 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1319 info->device_name, cmd );
1320
1321 if (sanity_check(info, tty->name, "ioctl"))
1322 return -ENODEV;
1323
1324 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1325 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1326 if (tty->flags & (1 << TTY_IO_ERROR))
1327 return -EIO;
1328 }
1329
1330 switch (cmd) {
1331 case MGSL_IOCGPARAMS:
1332 return get_params(info, argp);
1333 case MGSL_IOCSPARAMS:
1334 return set_params(info, argp);
1335 case MGSL_IOCGTXIDLE:
1336 return get_txidle(info, argp);
1337 case MGSL_IOCSTXIDLE:
1338 return set_txidle(info, (int)arg);
1339 case MGSL_IOCTXENABLE:
1340 return tx_enable(info, (int)arg);
1341 case MGSL_IOCRXENABLE:
1342 return rx_enable(info, (int)arg);
1343 case MGSL_IOCTXABORT:
1344 return tx_abort(info);
1345 case MGSL_IOCGSTATS:
1346 return get_stats(info, argp);
1347 case MGSL_IOCWAITEVENT:
1348 return wait_mgsl_event(info, argp);
1349 case MGSL_IOCLOOPTXDONE:
1350 return 0; // TODO: Not supported, need to document
1351 /* Wait for modem input (DCD,RI,DSR,CTS) change
1352 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1353 */
1354 case TIOCMIWAIT:
1355 return modem_input_wait(info,(int)arg);
1356
1357 /*
1358 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1359 * Return: write counters to the user passed counter struct
1360 * NB: both 1->0 and 0->1 transitions are counted except for
1361 * RI where only 0->1 is counted.
1362 */
1363 case TIOCGICOUNT:
1364 spin_lock_irqsave(&info->lock,flags);
1365 cnow = info->icount;
1366 spin_unlock_irqrestore(&info->lock,flags);
1367 p_cuser = argp;
1368 PUT_USER(error,cnow.cts, &p_cuser->cts);
1369 if (error) return error;
1370 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1371 if (error) return error;
1372 PUT_USER(error,cnow.rng, &p_cuser->rng);
1373 if (error) return error;
1374 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1375 if (error) return error;
1376 PUT_USER(error,cnow.rx, &p_cuser->rx);
1377 if (error) return error;
1378 PUT_USER(error,cnow.tx, &p_cuser->tx);
1379 if (error) return error;
1380 PUT_USER(error,cnow.frame, &p_cuser->frame);
1381 if (error) return error;
1382 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1383 if (error) return error;
1384 PUT_USER(error,cnow.parity, &p_cuser->parity);
1385 if (error) return error;
1386 PUT_USER(error,cnow.brk, &p_cuser->brk);
1387 if (error) return error;
1388 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1389 if (error) return error;
1390 return 0;
1391 default:
1392 return -ENOIOCTLCMD;
1393 }
1394 return 0;
1395}
1396
1f8cabb7
AC		 1397static int ioctl(struct tty_struct *tty, struct file *file,
1398 unsigned int cmd, unsigned long arg)
1399{
1400 int ret;
1401 lock_kernel();
1402 ret = do_ioctl(tty, file, cmd, arg);
1403 unlock_kernel();
1404 return ret;
1405}
1406
1da177e4
LT		 1407/*
1408 * /proc fs routines....
1409 */
1410
1411static inline int line_info(char *buf, SLMP_INFO *info)
1412{
1413 char stat_buf[30];
1414 int ret;
1415 unsigned long flags;
1416
1417 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1418 "\tIRQ=%d MaxFrameSize=%u\n",
1419 info->device_name,
1420 info->phys_sca_base,
1421 info->phys_memory_base,
1422 info->phys_statctrl_base,
1423 info->phys_lcr_base,
1424 info->irq_level,
1425 info->max_frame_size );
1426
1427 /* output current serial signal states */
1428 spin_lock_irqsave(&info->lock,flags);
1429 get_signals(info);
1430 spin_unlock_irqrestore(&info->lock,flags);
1431
1432 stat_buf[0] = 0;
1433 stat_buf[1] = 0;
1434 if (info->serial_signals & SerialSignal_RTS)
1435 strcat(stat_buf, "|RTS");
1436 if (info->serial_signals & SerialSignal_CTS)
1437 strcat(stat_buf, "|CTS");
1438 if (info->serial_signals & SerialSignal_DTR)
1439 strcat(stat_buf, "|DTR");
1440 if (info->serial_signals & SerialSignal_DSR)
1441 strcat(stat_buf, "|DSR");
1442 if (info->serial_signals & SerialSignal_DCD)
1443 strcat(stat_buf, "|CD");
1444 if (info->serial_signals & SerialSignal_RI)
1445 strcat(stat_buf, "|RI");
1446
1447 if (info->params.mode == MGSL_MODE_HDLC) {
1448 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1449 info->icount.txok, info->icount.rxok);
1450 if (info->icount.txunder)
1451 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1452 if (info->icount.txabort)
1453 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1454 if (info->icount.rxshort)
1455 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1456 if (info->icount.rxlong)
1457 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1458 if (info->icount.rxover)
1459 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1460 if (info->icount.rxcrc)
1461 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1462 } else {
1463 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1464 info->icount.tx, info->icount.rx);
1465 if (info->icount.frame)
1466 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1467 if (info->icount.parity)
1468 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1469 if (info->icount.brk)
1470 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1471 if (info->icount.overrun)
1472 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1473 }
1474
1475 /* Append serial signal status to end */
1476 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1477
1478 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1479 info->tx_active,info->bh_requested,info->bh_running,
1480 info->pending_bh);
1481
1482 return ret;
1483}
1484
1485/* Called to print information about devices
1486 */
ce9f9f73 1487static int read_proc(char *page, char **start, off_t off, int count,
1da177e4
LT		 1488 int *eof, void *data)
1489{
1490 int len = 0, l;
1491 off_t begin = 0;
1492 SLMP_INFO *info;
1493
1494 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1495
1496 info = synclinkmp_device_list;
1497 while( info ) {
1498 l = line_info(page + len, info);
1499 len += l;
1500 if (len+begin > off+count)
1501 goto done;
1502 if (len+begin < off) {
1503 begin += len;
1504 len = 0;
1505 }
1506 info = info->next_device;
1507 }
1508
1509 *eof = 1;
1510done:
1511 if (off >= len+begin)
1512 return 0;
1513 *start = page + (off-begin);
1514 return ((count < begin+len-off) ? count : begin+len-off);
1515}
1516
1517/* Return the count of bytes in transmit buffer
1518 */
1519static int chars_in_buffer(struct tty_struct *tty)
1520{
1521 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1522
1523 if (sanity_check(info, tty->name, "chars_in_buffer"))
1524 return 0;
1525
1526 if (debug_level >= DEBUG_LEVEL_INFO)
1527 printk("%s(%d):%s chars_in_buffer()=%d\n",
1528 __FILE__, __LINE__, info->device_name, info->tx_count);
1529
1530 return info->tx_count;
1531}
1532
1533/* Signal remote device to throttle send data (our receive data)
1534 */
1535static void throttle(struct tty_struct * tty)
1536{
1537 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1538 unsigned long flags;
1539
1540 if (debug_level >= DEBUG_LEVEL_INFO)
1541 printk("%s(%d):%s throttle() entry\n",
1542 __FILE__,__LINE__, info->device_name );
1543
1544 if (sanity_check(info, tty->name, "throttle"))
1545 return;
1546
1547 if (I_IXOFF(tty))
1548 send_xchar(tty, STOP_CHAR(tty));
1549
1550 if (tty->termios->c_cflag & CRTSCTS) {
1551 spin_lock_irqsave(&info->lock,flags);
1552 info->serial_signals &= ~SerialSignal_RTS;
1553 set_signals(info);
1554 spin_unlock_irqrestore(&info->lock,flags);
1555 }
1556}
1557
1558/* Signal remote device to stop throttling send data (our receive data)
1559 */
1560static void unthrottle(struct tty_struct * tty)
1561{
1562 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1563 unsigned long flags;
1564
1565 if (debug_level >= DEBUG_LEVEL_INFO)
1566 printk("%s(%d):%s unthrottle() entry\n",
1567 __FILE__,__LINE__, info->device_name );
1568
1569 if (sanity_check(info, tty->name, "unthrottle"))
1570 return;
1571
1572 if (I_IXOFF(tty)) {
1573 if (info->x_char)
1574 info->x_char = 0;
1575 else
1576 send_xchar(tty, START_CHAR(tty));
1577 }
1578
1579 if (tty->termios->c_cflag & CRTSCTS) {
1580 spin_lock_irqsave(&info->lock,flags);
1581 info->serial_signals |= SerialSignal_RTS;
1582 set_signals(info);
1583 spin_unlock_irqrestore(&info->lock,flags);
1584 }
1585}
1586
1587/* set or clear transmit break condition
1588 * break_state -1=set break condition, 0=clear
1589 */
1590static void set_break(struct tty_struct *tty, int break_state)
1591{
1592 unsigned char RegValue;
1593 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1594 unsigned long flags;
1595
1596 if (debug_level >= DEBUG_LEVEL_INFO)
1597 printk("%s(%d):%s set_break(%d)\n",
1598 __FILE__,__LINE__, info->device_name, break_state);
1599
1600 if (sanity_check(info, tty->name, "set_break"))
1601 return;
1602
1603 spin_lock_irqsave(&info->lock,flags);
1604 RegValue = read_reg(info, CTL);
1605 if (break_state == -1)
1606 RegValue |= BIT3;
1607 else
1608 RegValue &= ~BIT3;
1609 write_reg(info, CTL, RegValue);
1610 spin_unlock_irqrestore(&info->lock,flags);
1611}
1612
af69c7f9 1613#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 1614
1615/**
1616 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1617 * set encoding and frame check sequence (FCS) options
1618 *
1619 * dev pointer to network device structure
1620 * encoding serial encoding setting
1621 * parity FCS setting
1622 *
1623 * returns 0 if success, otherwise error code
1624 */
1625static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1626 unsigned short parity)
1627{
1628 SLMP_INFO *info = dev_to_port(dev);
1629 unsigned char new_encoding;
1630 unsigned short new_crctype;
1631
1632 /* return error if TTY interface open */
8fb06c77 1633 if (info->port.count)
1da177e4
LT		 1634 return -EBUSY;
1635
1636 switch (encoding)
1637 {
1638 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1639 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1640 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1641 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1642 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1643 default: return -EINVAL;
1644 }
1645
1646 switch (parity)
1647 {
1648 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1649 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1650 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1651 default: return -EINVAL;
1652 }
1653
1654 info->params.encoding = new_encoding;
53b3531b 1655 info->params.crc_type = new_crctype;
1da177e4
LT		 1656
1657 /* if network interface up, reprogram hardware */
1658 if (info->netcount)
1659 program_hw(info);
1660
1661 return 0;
1662}
1663
1664/**
1665 * called by generic HDLC layer to send frame
1666 *
1667 * skb socket buffer containing HDLC frame
1668 * dev pointer to network device structure
1669 *
1670 * returns 0 if success, otherwise error code
1671 */
1672static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1673{
1674 SLMP_INFO *info = dev_to_port(dev);
1da177e4
LT		 1675 unsigned long flags;
1676
1677 if (debug_level >= DEBUG_LEVEL_INFO)
1678 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1679
1680 /* stop sending until this frame completes */
1681 netif_stop_queue(dev);
1682
1683 /* copy data to device buffers */
1684 info->tx_count = skb->len;
1685 tx_load_dma_buffer(info, skb->data, skb->len);
1686
1687 /* update network statistics */
198191c4
KH		 1688 dev->stats.tx_packets++;
1689 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 1690
1691 /* done with socket buffer, so free it */
1692 dev_kfree_skb(skb);
1693
1694 /* save start time for transmit timeout detection */
1695 dev->trans_start = jiffies;
1696
1697 /* start hardware transmitter if necessary */
1698 spin_lock_irqsave(&info->lock,flags);
1699 if (!info->tx_active)
1700 tx_start(info);
1701 spin_unlock_irqrestore(&info->lock,flags);
1702
1703 return 0;
1704}
1705
1706/**
1707 * called by network layer when interface enabled
1708 * claim resources and initialize hardware
1709 *
1710 * dev pointer to network device structure
1711 *
1712 * returns 0 if success, otherwise error code
1713 */
1714static int hdlcdev_open(struct net_device *dev)
1715{
1716 SLMP_INFO *info = dev_to_port(dev);
1717 int rc;
1718 unsigned long flags;
1719
1720 if (debug_level >= DEBUG_LEVEL_INFO)
1721 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1722
1723 /* generic HDLC layer open processing */
1724 if ((rc = hdlc_open(dev)))
1725 return rc;
1726
1727 /* arbitrate between network and tty opens */
1728 spin_lock_irqsave(&info->netlock, flags);
8fb06c77 1729 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 1730 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1731 spin_unlock_irqrestore(&info->netlock, flags);
1732 return -EBUSY;
1733 }
1734 info->netcount=1;
1735 spin_unlock_irqrestore(&info->netlock, flags);
1736
1737 /* claim resources and init adapter */
1738 if ((rc = startup(info)) != 0) {
1739 spin_lock_irqsave(&info->netlock, flags);
1740 info->netcount=0;
1741 spin_unlock_irqrestore(&info->netlock, flags);
1742 return rc;
1743 }
1744
1745 /* assert DTR and RTS, apply hardware settings */
1746 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1747 program_hw(info);
1748
1749 /* enable network layer transmit */
1750 dev->trans_start = jiffies;
1751 netif_start_queue(dev);
1752
1753 /* inform generic HDLC layer of current DCD status */
1754 spin_lock_irqsave(&info->lock, flags);
1755 get_signals(info);
1756 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 1757 if (info->serial_signals & SerialSignal_DCD)
1758 netif_carrier_on(dev);
1759 else
1760 netif_carrier_off(dev);
1da177e4
LT		 1761 return 0;
1762}
1763
1764/**
1765 * called by network layer when interface is disabled
1766 * shutdown hardware and release resources
1767 *
1768 * dev pointer to network device structure
1769 *
1770 * returns 0 if success, otherwise error code
1771 */
1772static int hdlcdev_close(struct net_device *dev)
1773{
1774 SLMP_INFO *info = dev_to_port(dev);
1775 unsigned long flags;
1776
1777 if (debug_level >= DEBUG_LEVEL_INFO)
1778 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1779
1780 netif_stop_queue(dev);
1781
1782 /* shutdown adapter and release resources */
1783 shutdown(info);
1784
1785 hdlc_close(dev);
1786
1787 spin_lock_irqsave(&info->netlock, flags);
1788 info->netcount=0;
1789 spin_unlock_irqrestore(&info->netlock, flags);
1790
1791 return 0;
1792}
1793
1794/**
1795 * called by network layer to process IOCTL call to network device
1796 *
1797 * dev pointer to network device structure
1798 * ifr pointer to network interface request structure
1799 * cmd IOCTL command code
1800 *
1801 * returns 0 if success, otherwise error code
1802 */
1803static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1804{
1805 const size_t size = sizeof(sync_serial_settings);
1806 sync_serial_settings new_line;
1807 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1808 SLMP_INFO *info = dev_to_port(dev);
1809 unsigned int flags;
1810
1811 if (debug_level >= DEBUG_LEVEL_INFO)
1812 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1813
1814 /* return error if TTY interface open */
8fb06c77 1815 if (info->port.count)
1da177e4
LT		 1816 return -EBUSY;
1817
1818 if (cmd != SIOCWANDEV)
1819 return hdlc_ioctl(dev, ifr, cmd);
1820
1821 switch(ifr->ifr_settings.type) {
1822 case IF_GET_IFACE: /* return current sync_serial_settings */
1823
1824 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1825 if (ifr->ifr_settings.size < size) {
1826 ifr->ifr_settings.size = size; /* data size wanted */
1827 return -ENOBUFS;
1828 }
1829
1830 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1831 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1832 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1833 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1834
1835 switch (flags){
1836 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1837 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1838 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1839 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1840 default: new_line.clock_type = CLOCK_DEFAULT;
1841 }
1842
1843 new_line.clock_rate = info->params.clock_speed;
1844 new_line.loopback = info->params.loopback ? 1:0;
1845
1846 if (copy_to_user(line, &new_line, size))
1847 return -EFAULT;
1848 return 0;
1849
1850 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1851
1852 if(!capable(CAP_NET_ADMIN))
1853 return -EPERM;
1854 if (copy_from_user(&new_line, line, size))
1855 return -EFAULT;
1856
1857 switch (new_line.clock_type)
1858 {
1859 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1860 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1861 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1862 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1863 case CLOCK_DEFAULT: flags = info->params.flags &
1864 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1865 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1866 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1867 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1868 default: return -EINVAL;
1869 }
1870
1871 if (new_line.loopback != 0 && new_line.loopback != 1)
1872 return -EINVAL;
1873
1874 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1875 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1876 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1877 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1878 info->params.flags |= flags;
1879
1880 info->params.loopback = new_line.loopback;
1881
1882 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1883 info->params.clock_speed = new_line.clock_rate;
1884 else
1885 info->params.clock_speed = 0;
1886
1887 /* if network interface up, reprogram hardware */
1888 if (info->netcount)
1889 program_hw(info);
1890 return 0;
1891
1892 default:
1893 return hdlc_ioctl(dev, ifr, cmd);
1894 }
1895}
1896
1897/**
1898 * called by network layer when transmit timeout is detected
1899 *
1900 * dev pointer to network device structure
1901 */
1902static void hdlcdev_tx_timeout(struct net_device *dev)
1903{
1904 SLMP_INFO *info = dev_to_port(dev);
1da177e4
LT		 1905 unsigned long flags;
1906
1907 if (debug_level >= DEBUG_LEVEL_INFO)
1908 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1909
198191c4
KH		 1910 dev->stats.tx_errors++;
1911 dev->stats.tx_aborted_errors++;
1da177e4
LT		 1912
1913 spin_lock_irqsave(&info->lock,flags);
1914 tx_stop(info);
1915 spin_unlock_irqrestore(&info->lock,flags);
1916
1917 netif_wake_queue(dev);
1918}
1919
1920/**
1921 * called by device driver when transmit completes
1922 * reenable network layer transmit if stopped
1923 *
1924 * info pointer to device instance information
1925 */
1926static void hdlcdev_tx_done(SLMP_INFO *info)
1927{
1928 if (netif_queue_stopped(info->netdev))
1929 netif_wake_queue(info->netdev);
1930}
1931
1932/**
1933 * called by device driver when frame received
1934 * pass frame to network layer
1935 *
1936 * info pointer to device instance information
1937 * buf pointer to buffer contianing frame data
1938 * size count of data bytes in buf
1939 */
1940static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1941{
1942 struct sk_buff *skb = dev_alloc_skb(size);
1943 struct net_device *dev = info->netdev;
1da177e4
LT		 1944
1945 if (debug_level >= DEBUG_LEVEL_INFO)
1946 printk("hdlcdev_rx(%s)\n",dev->name);
1947
1948 if (skb == NULL) {
198191c4
KH		 1949 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1950 dev->name);
1951 dev->stats.rx_dropped++;
1da177e4
LT		 1952 return;
1953 }
1954
198191c4 1955 memcpy(skb_put(skb, size), buf, size);
1da177e4 1956
198191c4 1957 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 1958
198191c4
KH		 1959 dev->stats.rx_packets++;
1960 dev->stats.rx_bytes += size;
1da177e4
LT		 1961
1962 netif_rx(skb);
1963
198191c4 1964 dev->last_rx = jiffies;
1da177e4
LT		 1965}
1966
1967/**
1968 * called by device driver when adding device instance
1969 * do generic HDLC initialization
1970 *
1971 * info pointer to device instance information
1972 *
1973 * returns 0 if success, otherwise error code
1974 */
1975static int hdlcdev_init(SLMP_INFO *info)
1976{
1977 int rc;
1978 struct net_device *dev;
1979 hdlc_device *hdlc;
1980
1981 /* allocate and initialize network and HDLC layer objects */
1982
1983 if (!(dev = alloc_hdlcdev(info))) {
1984 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1985 return -ENOMEM;
1986 }
1987
1988 /* for network layer reporting purposes only */
1989 dev->mem_start = info->phys_sca_base;
1990 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1991 dev->irq = info->irq_level;
1992
1993 /* network layer callbacks and settings */
1994 dev->do_ioctl = hdlcdev_ioctl;
1995 dev->open = hdlcdev_open;
1996 dev->stop = hdlcdev_close;
1997 dev->tx_timeout = hdlcdev_tx_timeout;
1998 dev->watchdog_timeo = 10*HZ;
1999 dev->tx_queue_len = 50;
2000
2001 /* generic HDLC layer callbacks and settings */
2002 hdlc = dev_to_hdlc(dev);
2003 hdlc->attach = hdlcdev_attach;
2004 hdlc->xmit = hdlcdev_xmit;
2005
2006 /* register objects with HDLC layer */
2007 if ((rc = register_hdlc_device(dev))) {
2008 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2009 free_netdev(dev);
2010 return rc;
2011 }
2012
2013 info->netdev = dev;
2014 return 0;
2015}
2016
2017/**
2018 * called by device driver when removing device instance
2019 * do generic HDLC cleanup
2020 *
2021 * info pointer to device instance information
2022 */
2023static void hdlcdev_exit(SLMP_INFO *info)
2024{
2025 unregister_hdlc_device(info->netdev);
2026 free_netdev(info->netdev);
2027 info->netdev = NULL;
2028}
2029
2030#endif /* CONFIG_HDLC */
2031
2032
2033/* Return next bottom half action to perform.
2034 * Return Value: BH action code or 0 if nothing to do.
2035 */
ce9f9f73 2036static int bh_action(SLMP_INFO *info)
1da177e4
LT		 2037{
2038 unsigned long flags;
2039 int rc = 0;
2040
2041 spin_lock_irqsave(&info->lock,flags);
2042
2043 if (info->pending_bh & BH_RECEIVE) {
2044 info->pending_bh &= ~BH_RECEIVE;
2045 rc = BH_RECEIVE;
2046 } else if (info->pending_bh & BH_TRANSMIT) {
2047 info->pending_bh &= ~BH_TRANSMIT;
2048 rc = BH_TRANSMIT;
2049 } else if (info->pending_bh & BH_STATUS) {
2050 info->pending_bh &= ~BH_STATUS;
2051 rc = BH_STATUS;
2052 }
2053
2054 if (!rc) {
2055 /* Mark BH routine as complete */
0fab6de0
JP		 2056 info->bh_running = false;
2057 info->bh_requested = false;
1da177e4
LT		 2058 }
2059
2060 spin_unlock_irqrestore(&info->lock,flags);
2061
2062 return rc;
2063}
2064
2065/* Perform bottom half processing of work items queued by ISR.
2066 */
ce9f9f73 2067static void bh_handler(struct work_struct *work)
1da177e4 2068{
c4028958 2069 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1da177e4
LT		 2070 int action;
2071
2072 if (!info)
2073 return;
2074
2075 if ( debug_level >= DEBUG_LEVEL_BH )
2076 printk( "%s(%d):%s bh_handler() entry\n",
2077 __FILE__,__LINE__,info->device_name);
2078
0fab6de0 2079 info->bh_running = true;
1da177e4
LT		 2080
2081 while((action = bh_action(info)) != 0) {
2082
2083 /* Process work item */
2084 if ( debug_level >= DEBUG_LEVEL_BH )
2085 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2086 __FILE__,__LINE__,info->device_name, action);
2087
2088 switch (action) {
2089
2090 case BH_RECEIVE:
2091 bh_receive(info);
2092 break;
2093 case BH_TRANSMIT:
2094 bh_transmit(info);
2095 break;
2096 case BH_STATUS:
2097 bh_status(info);
2098 break;
2099 default:
2100 /* unknown work item ID */
2101 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2102 __FILE__,__LINE__,info->device_name,action);
2103 break;
2104 }
2105 }
2106
2107 if ( debug_level >= DEBUG_LEVEL_BH )
2108 printk( "%s(%d):%s bh_handler() exit\n",
2109 __FILE__,__LINE__,info->device_name);
2110}
2111
ce9f9f73 2112static void bh_receive(SLMP_INFO *info)
1da177e4
LT		 2113{
2114 if ( debug_level >= DEBUG_LEVEL_BH )
2115 printk( "%s(%d):%s bh_receive()\n",
2116 __FILE__,__LINE__,info->device_name);
2117
2118 while( rx_get_frame(info) );
2119}
2120
ce9f9f73 2121static void bh_transmit(SLMP_INFO *info)
1da177e4 2122{
8fb06c77 2123 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 2124
2125 if ( debug_level >= DEBUG_LEVEL_BH )
2126 printk( "%s(%d):%s bh_transmit() entry\n",
2127 __FILE__,__LINE__,info->device_name);
2128
b963a844 2129 if (tty)
1da177e4 2130 tty_wakeup(tty);
1da177e4
LT		 2131}
2132
ce9f9f73 2133static void bh_status(SLMP_INFO *info)
1da177e4
LT		 2134{
2135 if ( debug_level >= DEBUG_LEVEL_BH )
2136 printk( "%s(%d):%s bh_status() entry\n",
2137 __FILE__,__LINE__,info->device_name);
2138
2139 info->ri_chkcount = 0;
2140 info->dsr_chkcount = 0;
2141 info->dcd_chkcount = 0;
2142 info->cts_chkcount = 0;
2143}
2144
ce9f9f73 2145static void isr_timer(SLMP_INFO * info)
1da177e4
LT		 2146{
2147 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2148
2149 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2150 write_reg(info, IER2, 0);
2151
2152 /* TMCS, Timer Control/Status Register
2153 *
2154 * 07 CMF, Compare match flag (read only) 1=match
2155 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2156 * 05 Reserved, must be 0
2157 * 04 TME, Timer Enable
2158 * 03..00 Reserved, must be 0
2159 *
2160 * 0000 0000
2161 */
2162 write_reg(info, (unsigned char)(timer + TMCS), 0);
2163
0fab6de0 2164 info->irq_occurred = true;
1da177e4
LT		 2165
2166 if ( debug_level >= DEBUG_LEVEL_ISR )
2167 printk("%s(%d):%s isr_timer()\n",
2168 __FILE__,__LINE__,info->device_name);
2169}
2170
ce9f9f73 2171static void isr_rxint(SLMP_INFO * info)
1da177e4 2172{
8fb06c77 2173 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 2174 struct mgsl_icount *icount = &info->icount;
2175 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2176 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2177
2178 /* clear status bits */
2179 if (status)
2180 write_reg(info, SR1, status);
2181
2182 if (status2)
2183 write_reg(info, SR2, status2);
2184
2185 if ( debug_level >= DEBUG_LEVEL_ISR )
2186 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2187 __FILE__,__LINE__,info->device_name,status,status2);
2188
2189 if (info->params.mode == MGSL_MODE_ASYNC) {
2190 if (status & BRKD) {
2191 icount->brk++;
2192
2193 /* process break detection if tty control
2194 * is not set to ignore it
2195 */
2196 if ( tty ) {
2197 if (!(status & info->ignore_status_mask1)) {
2198 if (info->read_status_mask1 & BRKD) {
33f0f88f 2199 tty_insert_flip_char(tty, 0, TTY_BREAK);
8fb06c77 2200 if (info->port.flags & ASYNC_SAK)
1da177e4
LT		 2201 do_SAK(tty);
2202 }
2203 }
2204 }
2205 }
2206 }
2207 else {
2208 if (status & (FLGD|IDLD)) {
2209 if (status & FLGD)
2210 info->icount.exithunt++;
2211 else if (status & IDLD)
2212 info->icount.rxidle++;
2213 wake_up_interruptible(&info->event_wait_q);
2214 }
2215 }
2216
2217 if (status & CDCD) {
2218 /* simulate a common modem status change interrupt
2219 * for our handler
2220 */
2221 get_signals( info );
2222 isr_io_pin(info,
2223 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2224 }
2225}
2226
2227/*
2228 * handle async rx data interrupts
2229 */
ce9f9f73 2230static void isr_rxrdy(SLMP_INFO * info)
1da177e4
LT		 2231{
2232 u16 status;
2233 unsigned char DataByte;
8fb06c77 2234 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 2235 struct mgsl_icount *icount = &info->icount;
2236
2237 if ( debug_level >= DEBUG_LEVEL_ISR )
2238 printk("%s(%d):%s isr_rxrdy\n",
2239 __FILE__,__LINE__,info->device_name);
2240
2241 while((status = read_reg(info,CST0)) & BIT0)
2242 {
33f0f88f 2243 int flag = 0;
0fab6de0 2244 bool over = false;
1da177e4
LT		 2245 DataByte = read_reg(info,TRB);
2246
1da177e4
LT		 2247 icount->rx++;
2248
2249 if ( status & (PE + FRME + OVRN) ) {
2250 printk("%s(%d):%s rxerr=%04X\n",
2251 __FILE__,__LINE__,info->device_name,status);
2252
2253 /* update error statistics */
2254 if (status & PE)
2255 icount->parity++;
2256 else if (status & FRME)
2257 icount->frame++;
2258 else if (status & OVRN)
2259 icount->overrun++;
2260
2261 /* discard char if tty control flags say so */
2262 if (status & info->ignore_status_mask2)
2263 continue;
2264
2265 status &= info->read_status_mask2;
2266
2267 if ( tty ) {
2268 if (status & PE)
33f0f88f 2269 flag = TTY_PARITY;
1da177e4 2270 else if (status & FRME)
33f0f88f 2271 flag = TTY_FRAME;
1da177e4
LT		 2272 if (status & OVRN) {
2273 /* Overrun is special, since it's
2274 * reported immediately, and doesn't
2275 * affect the current character
2276 */
0fab6de0 2277 over = true;
1da177e4
LT		 2278 }
2279 }
2280 } /* end of if (error) */
2281
2282 if ( tty ) {
33f0f88f
AC		 2283 tty_insert_flip_char(tty, DataByte, flag);
2284 if (over)
2285 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1da177e4
LT		 2286 }
2287 }
2288
2289 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1da177e4
LT		 2290 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2291 __FILE__,__LINE__,info->device_name,
2292 icount->rx,icount->brk,icount->parity,
2293 icount->frame,icount->overrun);
2294 }
2295
33f0f88f 2296 if ( tty )
1da177e4
LT		 2297 tty_flip_buffer_push(tty);
2298}
2299
2300static void isr_txeom(SLMP_INFO * info, unsigned char status)
2301{
2302 if ( debug_level >= DEBUG_LEVEL_ISR )
2303 printk("%s(%d):%s isr_txeom status=%02x\n",
2304 __FILE__,__LINE__,info->device_name,status);
2305
2306 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2307 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2308 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2309
2310 if (status & UDRN) {
2311 write_reg(info, CMD, TXRESET);
2312 write_reg(info, CMD, TXENABLE);
2313 } else
2314 write_reg(info, CMD, TXBUFCLR);
2315
2316 /* disable and clear tx interrupts */
2317 info->ie0_value &= ~TXRDYE;
2318 info->ie1_value &= ~(IDLE + UDRN);
2319 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2320 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2321
2322 if ( info->tx_active ) {
2323 if (info->params.mode != MGSL_MODE_ASYNC) {
2324 if (status & UDRN)
2325 info->icount.txunder++;
2326 else if (status & IDLE)
2327 info->icount.txok++;
2328 }
2329
0fab6de0 2330 info->tx_active = false;
1da177e4
LT		 2331 info->tx_count = info->tx_put = info->tx_get = 0;
2332
2333 del_timer(&info->tx_timer);
2334
2335 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2336 info->serial_signals &= ~SerialSignal_RTS;
0fab6de0 2337 info->drop_rts_on_tx_done = false;
1da177e4
LT		 2338 set_signals(info);
2339 }
2340
af69c7f9 2341#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2342 if (info->netcount)
2343 hdlcdev_tx_done(info);
2344 else
2345#endif
2346 {
8fb06c77 2347 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
1da177e4
LT		 2348 tx_stop(info);
2349 return;
2350 }
2351 info->pending_bh |= BH_TRANSMIT;
2352 }
2353 }
2354}
2355
2356
2357/*
2358 * handle tx status interrupts
2359 */
ce9f9f73 2360static void isr_txint(SLMP_INFO * info)
1da177e4
LT		 2361{
2362 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2363
2364 /* clear status bits */
2365 write_reg(info, SR1, status);
2366
2367 if ( debug_level >= DEBUG_LEVEL_ISR )
2368 printk("%s(%d):%s isr_txint status=%02x\n",
2369 __FILE__,__LINE__,info->device_name,status);
2370
2371 if (status & (UDRN + IDLE))
2372 isr_txeom(info, status);
2373
2374 if (status & CCTS) {
2375 /* simulate a common modem status change interrupt
2376 * for our handler
2377 */
2378 get_signals( info );
2379 isr_io_pin(info,
2380 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2381
2382 }
2383}
2384
2385/*
2386 * handle async tx data interrupts
2387 */
ce9f9f73 2388static void isr_txrdy(SLMP_INFO * info)
1da177e4
LT		 2389{
2390 if ( debug_level >= DEBUG_LEVEL_ISR )
2391 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2392 __FILE__,__LINE__,info->device_name,info->tx_count);
2393
2394 if (info->params.mode != MGSL_MODE_ASYNC) {
2395 /* disable TXRDY IRQ, enable IDLE IRQ */
2396 info->ie0_value &= ~TXRDYE;
2397 info->ie1_value |= IDLE;
2398 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2399 return;
2400 }
2401
8fb06c77 2402 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
1da177e4
LT		 2403 tx_stop(info);
2404 return;
2405 }
2406
2407 if ( info->tx_count )
2408 tx_load_fifo( info );
2409 else {
0fab6de0 2410 info->tx_active = false;
1da177e4
LT		 2411 info->ie0_value &= ~TXRDYE;
2412 write_reg(info, IE0, info->ie0_value);
2413 }
2414
2415 if (info->tx_count < WAKEUP_CHARS)
2416 info->pending_bh |= BH_TRANSMIT;
2417}
2418
ce9f9f73 2419static void isr_rxdmaok(SLMP_INFO * info)
1da177e4
LT		 2420{
2421 /* BIT7 = EOT (end of transfer)
2422 * BIT6 = EOM (end of message/frame)
2423 */
2424 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2425
2426 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2427 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2428
2429 if ( debug_level >= DEBUG_LEVEL_ISR )
2430 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2431 __FILE__,__LINE__,info->device_name,status);
2432
2433 info->pending_bh |= BH_RECEIVE;
2434}
2435
ce9f9f73 2436static void isr_rxdmaerror(SLMP_INFO * info)
1da177e4
LT		 2437{
2438 /* BIT5 = BOF (buffer overflow)
2439 * BIT4 = COF (counter overflow)
2440 */
2441 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2442
2443 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2444 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2445
2446 if ( debug_level >= DEBUG_LEVEL_ISR )
2447 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2448 __FILE__,__LINE__,info->device_name,status);
2449
0fab6de0 2450 info->rx_overflow = true;
1da177e4
LT		 2451 info->pending_bh |= BH_RECEIVE;
2452}
2453
ce9f9f73 2454static void isr_txdmaok(SLMP_INFO * info)
1da177e4
LT		 2455{
2456 unsigned char status_reg1 = read_reg(info, SR1);
2457
2458 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2459 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2460 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2461
2462 if ( debug_level >= DEBUG_LEVEL_ISR )
2463 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2464 __FILE__,__LINE__,info->device_name,status_reg1);
2465
2466 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2467 write_reg16(info, TRC0, 0);
2468 info->ie0_value |= TXRDYE;
2469 write_reg(info, IE0, info->ie0_value);
2470}
2471
ce9f9f73 2472static void isr_txdmaerror(SLMP_INFO * info)
1da177e4
LT		 2473{
2474 /* BIT5 = BOF (buffer overflow)
2475 * BIT4 = COF (counter overflow)
2476 */
2477 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2478
2479 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2480 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2481
2482 if ( debug_level >= DEBUG_LEVEL_ISR )
2483 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2484 __FILE__,__LINE__,info->device_name,status);
2485}
2486
2487/* handle input serial signal changes
2488 */
ce9f9f73 2489static void isr_io_pin( SLMP_INFO *info, u16 status )
1da177e4
LT		 2490{
2491 struct mgsl_icount *icount;
2492
2493 if ( debug_level >= DEBUG_LEVEL_ISR )
2494 printk("%s(%d):isr_io_pin status=%04X\n",
2495 __FILE__,__LINE__,status);
2496
2497 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2498 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2499 icount = &info->icount;
2500 /* update input line counters */
2501 if (status & MISCSTATUS_RI_LATCHED) {
2502 icount->rng++;
2503 if ( status & SerialSignal_RI )
2504 info->input_signal_events.ri_up++;
2505 else
2506 info->input_signal_events.ri_down++;
2507 }
2508 if (status & MISCSTATUS_DSR_LATCHED) {
2509 icount->dsr++;
2510 if ( status & SerialSignal_DSR )
2511 info->input_signal_events.dsr_up++;
2512 else
2513 info->input_signal_events.dsr_down++;
2514 }
2515 if (status & MISCSTATUS_DCD_LATCHED) {
2516 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2517 info->ie1_value &= ~CDCD;
2518 write_reg(info, IE1, info->ie1_value);
2519 }
2520 icount->dcd++;
2521 if (status & SerialSignal_DCD) {
2522 info->input_signal_events.dcd_up++;
2523 } else
2524 info->input_signal_events.dcd_down++;
af69c7f9 2525#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 2526 if (info->netcount) {
2527 if (status & SerialSignal_DCD)
2528 netif_carrier_on(info->netdev);
2529 else
2530 netif_carrier_off(info->netdev);
2531 }
1da177e4
LT		 2532#endif
2533 }
2534 if (status & MISCSTATUS_CTS_LATCHED)
2535 {
2536 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2537 info->ie1_value &= ~CCTS;
2538 write_reg(info, IE1, info->ie1_value);
2539 }
2540 icount->cts++;
2541 if ( status & SerialSignal_CTS )
2542 info->input_signal_events.cts_up++;
2543 else
2544 info->input_signal_events.cts_down++;
2545 }
2546 wake_up_interruptible(&info->status_event_wait_q);
2547 wake_up_interruptible(&info->event_wait_q);
2548
8fb06c77 2549 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1da177e4
LT		 2550 (status & MISCSTATUS_DCD_LATCHED) ) {
2551 if ( debug_level >= DEBUG_LEVEL_ISR )
2552 printk("%s CD now %s...", info->device_name,
2553 (status & SerialSignal_DCD) ? "on" : "off");
2554 if (status & SerialSignal_DCD)
8fb06c77 2555 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 2556 else {
2557 if ( debug_level >= DEBUG_LEVEL_ISR )
2558 printk("doing serial hangup...");
8fb06c77
AC		 2559 if (info->port.tty)
2560 tty_hangup(info->port.tty);
1da177e4
LT		 2561 }
2562 }
2563
8fb06c77 2564 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1da177e4 2565 (status & MISCSTATUS_CTS_LATCHED) ) {
8fb06c77
AC		 2566 if ( info->port.tty ) {
2567 if (info->port.tty->hw_stopped) {
1da177e4
LT		 2568 if (status & SerialSignal_CTS) {
2569 if ( debug_level >= DEBUG_LEVEL_ISR )
2570 printk("CTS tx start...");
8fb06c77 2571 info->port.tty->hw_stopped = 0;
1da177e4
LT		 2572 tx_start(info);
2573 info->pending_bh |= BH_TRANSMIT;
2574 return;
2575 }
2576 } else {
2577 if (!(status & SerialSignal_CTS)) {
2578 if ( debug_level >= DEBUG_LEVEL_ISR )
2579 printk("CTS tx stop...");
8fb06c77 2580 info->port.tty->hw_stopped = 1;
1da177e4
LT		 2581 tx_stop(info);
2582 }
2583 }
2584 }
2585 }
2586 }
2587
2588 info->pending_bh |= BH_STATUS;
2589}
2590
2591/* Interrupt service routine entry point.
2592 *
2593 * Arguments:
2594 * irq interrupt number that caused interrupt
2595 * dev_id device ID supplied during interrupt registration
2596 * regs interrupted processor context
2597 */
a6f97b29 2598static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
1da177e4 2599{
a6f97b29 2600 SLMP_INFO *info = dev_id;
1da177e4
LT		 2601 unsigned char status, status0, status1=0;
2602 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2603 unsigned char timerstatus0, timerstatus1=0;
2604 unsigned char shift;
2605 unsigned int i;
2606 unsigned short tmp;
2607
2608 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 2609 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2610 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 2611
2612 spin_lock(&info->lock);
2613
2614 for(;;) {
2615
2616 /* get status for SCA0 (ports 0-1) */
2617 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2618 status0 = (unsigned char)tmp;
2619 dmastatus0 = (unsigned char)(tmp>>8);
2620 timerstatus0 = read_reg(info, ISR2);
2621
2622 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 2623 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2624 __FILE__, __LINE__, info->device_name,
2625 status0, dmastatus0, timerstatus0);
1da177e4
LT		 2626
2627 if (info->port_count == 4) {
2628 /* get status for SCA1 (ports 2-3) */
2629 tmp = read_reg16(info->port_array[2], ISR0);
2630 status1 = (unsigned char)tmp;
2631 dmastatus1 = (unsigned char)(tmp>>8);
2632 timerstatus1 = read_reg(info->port_array[2], ISR2);
2633
2634 if ( debug_level >= DEBUG_LEVEL_ISR )
2635 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2636 __FILE__,__LINE__,info->device_name,
2637 status1,dmastatus1,timerstatus1);
2638 }
2639
2640 if (!status0 && !dmastatus0 && !timerstatus0 &&
2641 !status1 && !dmastatus1 && !timerstatus1)
2642 break;
2643
2644 for(i=0; i < info->port_count ; i++) {
2645 if (info->port_array[i] == NULL)
2646 continue;
2647 if (i < 2) {
2648 status = status0;
2649 dmastatus = dmastatus0;
2650 } else {
2651 status = status1;
2652 dmastatus = dmastatus1;
2653 }
2654
2655 shift = i & 1 ? 4 :0;
2656
2657 if (status & BIT0 << shift)
2658 isr_rxrdy(info->port_array[i]);
2659 if (status & BIT1 << shift)
2660 isr_txrdy(info->port_array[i]);
2661 if (status & BIT2 << shift)
2662 isr_rxint(info->port_array[i]);
2663 if (status & BIT3 << shift)
2664 isr_txint(info->port_array[i]);
2665
2666 if (dmastatus & BIT0 << shift)
2667 isr_rxdmaerror(info->port_array[i]);
2668 if (dmastatus & BIT1 << shift)
2669 isr_rxdmaok(info->port_array[i]);
2670 if (dmastatus & BIT2 << shift)
2671 isr_txdmaerror(info->port_array[i]);
2672 if (dmastatus & BIT3 << shift)
2673 isr_txdmaok(info->port_array[i]);
2674 }
2675
2676 if (timerstatus0 & (BIT5 | BIT4))
2677 isr_timer(info->port_array[0]);
2678 if (timerstatus0 & (BIT7 | BIT6))
2679 isr_timer(info->port_array[1]);
2680 if (timerstatus1 & (BIT5 | BIT4))
2681 isr_timer(info->port_array[2]);
2682 if (timerstatus1 & (BIT7 | BIT6))
2683 isr_timer(info->port_array[3]);
2684 }
2685
2686 for(i=0; i < info->port_count ; i++) {
2687 SLMP_INFO * port = info->port_array[i];
2688
2689 /* Request bottom half processing if there's something
2690 * for it to do and the bh is not already running.
2691 *
2692 * Note: startup adapter diags require interrupts.
2693 * do not request bottom half processing if the
2694 * device is not open in a normal mode.
2695 */
8fb06c77 2696 if ( port && (port->port.count || port->netcount) &&
1da177e4
LT		 2697 port->pending_bh && !port->bh_running &&
2698 !port->bh_requested ) {
2699 if ( debug_level >= DEBUG_LEVEL_ISR )
2700 printk("%s(%d):%s queueing bh task.\n",
2701 __FILE__,__LINE__,port->device_name);
2702 schedule_work(&port->task);
0fab6de0 2703 port->bh_requested = true;
1da177e4
LT		 2704 }
2705 }
2706
2707 spin_unlock(&info->lock);
2708
2709 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 2710 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2711 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 2712 return IRQ_HANDLED;
2713}
2714
2715/* Initialize and start device.
2716 */
2717static int startup(SLMP_INFO * info)
2718{
2719 if ( debug_level >= DEBUG_LEVEL_INFO )
2720 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2721
8fb06c77 2722 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4
LT		 2723 return 0;
2724
2725 if (!info->tx_buf) {
5cbded58 2726 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
1da177e4
LT		 2727 if (!info->tx_buf) {
2728 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2729 __FILE__,__LINE__,info->device_name);
2730 return -ENOMEM;
2731 }
2732 }
2733
2734 info->pending_bh = 0;
2735
166692e4
PF		 2736 memset(&info->icount, 0, sizeof(info->icount));
2737
1da177e4
LT		 2738 /* program hardware for current parameters */
2739 reset_port(info);
2740
2741 change_params(info);
2742
40565f19 2743 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
1da177e4 2744
8fb06c77
AC		 2745 if (info->port.tty)
2746 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 2747
8fb06c77 2748 info->port.flags |= ASYNC_INITIALIZED;
1da177e4
LT		 2749
2750 return 0;
2751}
2752
2753/* Called by close() and hangup() to shutdown hardware
2754 */
2755static void shutdown(SLMP_INFO * info)
2756{
2757 unsigned long flags;
2758
8fb06c77 2759 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 2760 return;
2761
2762 if (debug_level >= DEBUG_LEVEL_INFO)
2763 printk("%s(%d):%s synclinkmp_shutdown()\n",
2764 __FILE__,__LINE__, info->device_name );
2765
2766 /* clear status wait queue because status changes */
2767 /* can't happen after shutting down the hardware */
2768 wake_up_interruptible(&info->status_event_wait_q);
2769 wake_up_interruptible(&info->event_wait_q);
2770
2771 del_timer(&info->tx_timer);
2772 del_timer(&info->status_timer);
2773
735d5661
JJ		 2774 kfree(info->tx_buf);
2775 info->tx_buf = NULL;
1da177e4
LT		 2776
2777 spin_lock_irqsave(&info->lock,flags);
2778
2779 reset_port(info);
2780
8fb06c77 2781 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1da177e4
LT		 2782 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2783 set_signals(info);
2784 }
2785
2786 spin_unlock_irqrestore(&info->lock,flags);
2787
8fb06c77
AC		 2788 if (info->port.tty)
2789 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 2790
8fb06c77 2791 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 2792}
2793
2794static void program_hw(SLMP_INFO *info)
2795{
2796 unsigned long flags;
2797
2798 spin_lock_irqsave(&info->lock,flags);
2799
2800 rx_stop(info);
2801 tx_stop(info);
2802
2803 info->tx_count = info->tx_put = info->tx_get = 0;
2804
2805 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2806 hdlc_mode(info);
2807 else
2808 async_mode(info);
2809
2810 set_signals(info);
2811
2812 info->dcd_chkcount = 0;
2813 info->cts_chkcount = 0;
2814 info->ri_chkcount = 0;
2815 info->dsr_chkcount = 0;
2816
2817 info->ie1_value |= (CDCD|CCTS);
2818 write_reg(info, IE1, info->ie1_value);
2819
2820 get_signals(info);
2821
8fb06c77 2822 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
1da177e4
LT		 2823 rx_start(info);
2824
2825 spin_unlock_irqrestore(&info->lock,flags);
2826}
2827
2828/* Reconfigure adapter based on new parameters
2829 */
2830static void change_params(SLMP_INFO *info)
2831{
2832 unsigned cflag;
2833 int bits_per_char;
2834
8fb06c77 2835 if (!info->port.tty || !info->port.tty->termios)
1da177e4
LT		 2836 return;
2837
2838 if (debug_level >= DEBUG_LEVEL_INFO)
2839 printk("%s(%d):%s change_params()\n",
2840 __FILE__,__LINE__, info->device_name );
2841
8fb06c77 2842 cflag = info->port.tty->termios->c_cflag;
1da177e4
LT		 2843
2844 /* if B0 rate (hangup) specified then negate DTR and RTS */
2845 /* otherwise assert DTR and RTS */
2846 if (cflag & CBAUD)
2847 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2848 else
2849 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2850
2851 /* byte size and parity */
2852
2853 switch (cflag & CSIZE) {
2854 case CS5: info->params.data_bits = 5; break;
2855 case CS6: info->params.data_bits = 6; break;
2856 case CS7: info->params.data_bits = 7; break;
2857 case CS8: info->params.data_bits = 8; break;
2858 /* Never happens, but GCC is too dumb to figure it out */
2859 default: info->params.data_bits = 7; break;
2860 }
2861
2862 if (cflag & CSTOPB)
2863 info->params.stop_bits = 2;
2864 else
2865 info->params.stop_bits = 1;
2866
2867 info->params.parity = ASYNC_PARITY_NONE;
2868 if (cflag & PARENB) {
2869 if (cflag & PARODD)
2870 info->params.parity = ASYNC_PARITY_ODD;
2871 else
2872 info->params.parity = ASYNC_PARITY_EVEN;
2873#ifdef CMSPAR
2874 if (cflag & CMSPAR)
2875 info->params.parity = ASYNC_PARITY_SPACE;
2876#endif
2877 }
2878
2879 /* calculate number of jiffies to transmit a full
2880 * FIFO (32 bytes) at specified data rate
2881 */
2882 bits_per_char = info->params.data_bits +
2883 info->params.stop_bits + 1;
2884
2885 /* if port data rate is set to 460800 or less then
2886 * allow tty settings to override, otherwise keep the
2887 * current data rate.
2888 */
2889 if (info->params.data_rate <= 460800) {
8fb06c77 2890 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1da177e4
LT		 2891 }
2892
2893 if ( info->params.data_rate ) {
2894 info->timeout = (32*HZ*bits_per_char) /
2895 info->params.data_rate;
2896 }
2897 info->timeout += HZ/50; /* Add .02 seconds of slop */
2898
2899 if (cflag & CRTSCTS)
8fb06c77 2900 info->port.flags |= ASYNC_CTS_FLOW;
1da177e4 2901 else
8fb06c77 2902 info->port.flags &= ~ASYNC_CTS_FLOW;
1da177e4
LT		 2903
2904 if (cflag & CLOCAL)
8fb06c77 2905 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 2906 else
8fb06c77 2907 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 2908
2909 /* process tty input control flags */
2910
2911 info->read_status_mask2 = OVRN;
8fb06c77 2912 if (I_INPCK(info->port.tty))
1da177e4 2913 info->read_status_mask2 |= PE | FRME;
8fb06c77 2914 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1da177e4 2915 info->read_status_mask1 |= BRKD;
8fb06c77 2916 if (I_IGNPAR(info->port.tty))
1da177e4 2917 info->ignore_status_mask2 |= PE | FRME;
8fb06c77 2918 if (I_IGNBRK(info->port.tty)) {
1da177e4
LT		 2919 info->ignore_status_mask1 |= BRKD;
2920 /* If ignoring parity and break indicators, ignore
2921 * overruns too. (For real raw support).
2922 */
8fb06c77 2923 if (I_IGNPAR(info->port.tty))
1da177e4
LT		 2924 info->ignore_status_mask2 |= OVRN;
2925 }
2926
2927 program_hw(info);
2928}
2929
2930static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2931{
2932 int err;
2933
2934 if (debug_level >= DEBUG_LEVEL_INFO)
2935 printk("%s(%d):%s get_params()\n",
2936 __FILE__,__LINE__, info->device_name);
2937
166692e4
PF		 2938 if (!user_icount) {
2939 memset(&info->icount, 0, sizeof(info->icount));
2940 } else {
2941 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2942 if (err)
2943 return -EFAULT;
1da177e4
LT		 2944 }
2945
2946 return 0;
2947}
2948
2949static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2950{
2951 int err;
2952 if (debug_level >= DEBUG_LEVEL_INFO)
2953 printk("%s(%d):%s get_params()\n",
2954 __FILE__,__LINE__, info->device_name);
2955
2956 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2957 if (err) {
2958 if ( debug_level >= DEBUG_LEVEL_INFO )
2959 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2960 __FILE__,__LINE__,info->device_name);
2961 return -EFAULT;
2962 }
2963
2964 return 0;
2965}
2966
2967static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2968{
2969 unsigned long flags;
2970 MGSL_PARAMS tmp_params;
2971 int err;
2972
2973 if (debug_level >= DEBUG_LEVEL_INFO)
2974 printk("%s(%d):%s set_params\n",
2975 __FILE__,__LINE__,info->device_name );
2976 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2977 if (err) {
2978 if ( debug_level >= DEBUG_LEVEL_INFO )
2979 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2980 __FILE__,__LINE__,info->device_name);
2981 return -EFAULT;
2982 }
2983
2984 spin_lock_irqsave(&info->lock,flags);
2985 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2986 spin_unlock_irqrestore(&info->lock,flags);
2987
2988 change_params(info);
2989
2990 return 0;
2991}
2992
2993static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2994{
2995 int err;
2996
2997 if (debug_level >= DEBUG_LEVEL_INFO)
2998 printk("%s(%d):%s get_txidle()=%d\n",
2999 __FILE__,__LINE__, info->device_name, info->idle_mode);
3000
3001 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3002 if (err) {
3003 if ( debug_level >= DEBUG_LEVEL_INFO )
3004 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3005 __FILE__,__LINE__,info->device_name);
3006 return -EFAULT;
3007 }
3008
3009 return 0;
3010}
3011
3012static int set_txidle(SLMP_INFO * info, int idle_mode)
3013{
3014 unsigned long flags;
3015
3016 if (debug_level >= DEBUG_LEVEL_INFO)
3017 printk("%s(%d):%s set_txidle(%d)\n",
3018 __FILE__,__LINE__,info->device_name, idle_mode );
3019
3020 spin_lock_irqsave(&info->lock,flags);
3021 info->idle_mode = idle_mode;
3022 tx_set_idle( info );
3023 spin_unlock_irqrestore(&info->lock,flags);
3024 return 0;
3025}
3026
3027static int tx_enable(SLMP_INFO * info, int enable)
3028{
3029 unsigned long flags;
3030
3031 if (debug_level >= DEBUG_LEVEL_INFO)
3032 printk("%s(%d):%s tx_enable(%d)\n",
3033 __FILE__,__LINE__,info->device_name, enable);
3034
3035 spin_lock_irqsave(&info->lock,flags);
3036 if ( enable ) {
3037 if ( !info->tx_enabled ) {
3038 tx_start(info);
3039 }
3040 } else {
3041 if ( info->tx_enabled )
3042 tx_stop(info);
3043 }
3044 spin_unlock_irqrestore(&info->lock,flags);
3045 return 0;
3046}
3047
3048/* abort send HDLC frame
3049 */
3050static int tx_abort(SLMP_INFO * info)
3051{
3052 unsigned long flags;
3053
3054 if (debug_level >= DEBUG_LEVEL_INFO)
3055 printk("%s(%d):%s tx_abort()\n",
3056 __FILE__,__LINE__,info->device_name);
3057
3058 spin_lock_irqsave(&info->lock,flags);
3059 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3060 info->ie1_value &= ~UDRN;
3061 info->ie1_value |= IDLE;
3062 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3063 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3064
3065 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3066 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3067
3068 write_reg(info, CMD, TXABORT);
3069 }
3070 spin_unlock_irqrestore(&info->lock,flags);
3071 return 0;
3072}
3073
3074static int rx_enable(SLMP_INFO * info, int enable)
3075{
3076 unsigned long flags;
3077
3078 if (debug_level >= DEBUG_LEVEL_INFO)
3079 printk("%s(%d):%s rx_enable(%d)\n",
3080 __FILE__,__LINE__,info->device_name,enable);
3081
3082 spin_lock_irqsave(&info->lock,flags);
3083 if ( enable ) {
3084 if ( !info->rx_enabled )
3085 rx_start(info);
3086 } else {
3087 if ( info->rx_enabled )
3088 rx_stop(info);
3089 }
3090 spin_unlock_irqrestore(&info->lock,flags);
3091 return 0;
3092}
3093
1da177e4
LT		 3094/* wait for specified event to occur
3095 */
3096static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3097{
3098 unsigned long flags;
3099 int s;
3100 int rc=0;
3101 struct mgsl_icount cprev, cnow;
3102 int events;
3103 int mask;
3104 struct _input_signal_events oldsigs, newsigs;
3105 DECLARE_WAITQUEUE(wait, current);
3106
3107 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3108 if (rc) {
3109 return -EFAULT;
3110 }
3111
3112 if (debug_level >= DEBUG_LEVEL_INFO)
3113 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3114 __FILE__,__LINE__,info->device_name,mask);
3115
3116 spin_lock_irqsave(&info->lock,flags);
3117
3118 /* return immediately if state matches requested events */
3119 get_signals(info);
7f3edb94 3120 s = info->serial_signals;
1da177e4
LT		 3121
3122 events = mask &
3123 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3124 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3125 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3126 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3127 if (events) {
3128 spin_unlock_irqrestore(&info->lock,flags);
3129 goto exit;
3130 }
3131
3132 /* save current irq counts */
3133 cprev = info->icount;
3134 oldsigs = info->input_signal_events;
3135
3136 /* enable hunt and idle irqs if needed */
3137 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3138 unsigned char oldval = info->ie1_value;
3139 unsigned char newval = oldval +
3140 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3141 (mask & MgslEvent_IdleReceived ? IDLD:0);
3142 if ( oldval != newval ) {
3143 info->ie1_value = newval;
3144 write_reg(info, IE1, info->ie1_value);
3145 }
3146 }
3147
3148 set_current_state(TASK_INTERRUPTIBLE);
3149 add_wait_queue(&info->event_wait_q, &wait);
3150
3151 spin_unlock_irqrestore(&info->lock,flags);
3152
3153 for(;;) {
3154 schedule();
3155 if (signal_pending(current)) {
3156 rc = -ERESTARTSYS;
3157 break;
3158 }
3159
3160 /* get current irq counts */
3161 spin_lock_irqsave(&info->lock,flags);
3162 cnow = info->icount;
3163 newsigs = info->input_signal_events;
3164 set_current_state(TASK_INTERRUPTIBLE);
3165 spin_unlock_irqrestore(&info->lock,flags);
3166
3167 /* if no change, wait aborted for some reason */
3168 if (newsigs.dsr_up == oldsigs.dsr_up &&
3169 newsigs.dsr_down == oldsigs.dsr_down &&
3170 newsigs.dcd_up == oldsigs.dcd_up &&
3171 newsigs.dcd_down == oldsigs.dcd_down &&
3172 newsigs.cts_up == oldsigs.cts_up &&
3173 newsigs.cts_down == oldsigs.cts_down &&
3174 newsigs.ri_up == oldsigs.ri_up &&
3175 newsigs.ri_down == oldsigs.ri_down &&
3176 cnow.exithunt == cprev.exithunt &&
3177 cnow.rxidle == cprev.rxidle) {
3178 rc = -EIO;
3179 break;
3180 }
3181
3182 events = mask &
3183 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3184 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3185 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3186 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3187 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3188 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3189 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3190 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3191 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3192 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3193 if (events)
3194 break;
3195
3196 cprev = cnow;
3197 oldsigs = newsigs;
3198 }
3199
3200 remove_wait_queue(&info->event_wait_q, &wait);
3201 set_current_state(TASK_RUNNING);
3202
3203
3204 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3205 spin_lock_irqsave(&info->lock,flags);
3206 if (!waitqueue_active(&info->event_wait_q)) {
3207 /* disable enable exit hunt mode/idle rcvd IRQs */
3208 info->ie1_value &= ~(FLGD|IDLD);
3209 write_reg(info, IE1, info->ie1_value);
3210 }
3211 spin_unlock_irqrestore(&info->lock,flags);
3212 }
3213exit:
3214 if ( rc == 0 )
3215 PUT_USER(rc, events, mask_ptr);
3216
3217 return rc;
3218}
3219
3220static int modem_input_wait(SLMP_INFO *info,int arg)
3221{
3222 unsigned long flags;
3223 int rc;
3224 struct mgsl_icount cprev, cnow;
3225 DECLARE_WAITQUEUE(wait, current);
3226
3227 /* save current irq counts */
3228 spin_lock_irqsave(&info->lock,flags);
3229 cprev = info->icount;
3230 add_wait_queue(&info->status_event_wait_q, &wait);
3231 set_current_state(TASK_INTERRUPTIBLE);
3232 spin_unlock_irqrestore(&info->lock,flags);
3233
3234 for(;;) {
3235 schedule();
3236 if (signal_pending(current)) {
3237 rc = -ERESTARTSYS;
3238 break;
3239 }
3240
3241 /* get new irq counts */
3242 spin_lock_irqsave(&info->lock,flags);
3243 cnow = info->icount;
3244 set_current_state(TASK_INTERRUPTIBLE);
3245 spin_unlock_irqrestore(&info->lock,flags);
3246
3247 /* if no change, wait aborted for some reason */
3248 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3249 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3250 rc = -EIO;
3251 break;
3252 }
3253
3254 /* check for change in caller specified modem input */
3255 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3256 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3257 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3258 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3259 rc = 0;
3260 break;
3261 }
3262
3263 cprev = cnow;
3264 }
3265 remove_wait_queue(&info->status_event_wait_q, &wait);
3266 set_current_state(TASK_RUNNING);
3267 return rc;
3268}
3269
3270/* return the state of the serial control and status signals
3271 */
3272static int tiocmget(struct tty_struct *tty, struct file *file)
3273{
3274 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3275 unsigned int result;
3276 unsigned long flags;
3277
3278 spin_lock_irqsave(&info->lock,flags);
3279 get_signals(info);
3280 spin_unlock_irqrestore(&info->lock,flags);
3281
3282 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3283 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3284 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3285 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3286 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3287 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3288
3289 if (debug_level >= DEBUG_LEVEL_INFO)
3290 printk("%s(%d):%s tiocmget() value=%08X\n",
3291 __FILE__,__LINE__, info->device_name, result );
3292 return result;
3293}
3294
3295/* set modem control signals (DTR/RTS)
3296 */
3297static int tiocmset(struct tty_struct *tty, struct file *file,
3298 unsigned int set, unsigned int clear)
3299{
3300 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3301 unsigned long flags;
3302
3303 if (debug_level >= DEBUG_LEVEL_INFO)
3304 printk("%s(%d):%s tiocmset(%x,%x)\n",
3305 __FILE__,__LINE__,info->device_name, set, clear);
3306
3307 if (set & TIOCM_RTS)
3308 info->serial_signals |= SerialSignal_RTS;
3309 if (set & TIOCM_DTR)
3310 info->serial_signals |= SerialSignal_DTR;
3311 if (clear & TIOCM_RTS)
3312 info->serial_signals &= ~SerialSignal_RTS;
3313 if (clear & TIOCM_DTR)
3314 info->serial_signals &= ~SerialSignal_DTR;
3315
3316 spin_lock_irqsave(&info->lock,flags);
3317 set_signals(info);
3318 spin_unlock_irqrestore(&info->lock,flags);
3319
3320 return 0;
3321}
3322
3323
3324
3325/* Block the current process until the specified port is ready to open.
3326 */
3327static int block_til_ready(struct tty_struct *tty, struct file *filp,
3328 SLMP_INFO *info)
3329{
3330 DECLARE_WAITQUEUE(wait, current);
3331 int retval;
0fab6de0
JP		 3332 bool do_clocal = false;
3333 bool extra_count = false;
1da177e4
LT		 3334 unsigned long flags;
3335
3336 if (debug_level >= DEBUG_LEVEL_INFO)
3337 printk("%s(%d):%s block_til_ready()\n",
3338 __FILE__,__LINE__, tty->driver->name );
3339
3340 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3341 /* nonblock mode is set or port is not enabled */
3342 /* just verify that callout device is not active */
8fb06c77 3343 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3344 return 0;
3345 }
3346
3347 if (tty->termios->c_cflag & CLOCAL)
0fab6de0 3348 do_clocal = true;
1da177e4
LT		 3349
3350 /* Wait for carrier detect and the line to become
3351 * free (i.e., not in use by the callout). While we are in
8fb06c77 3352 * this loop, info->port.count is dropped by one, so that
1da177e4
LT		 3353 * close() knows when to free things. We restore it upon
3354 * exit, either normal or abnormal.
3355 */
3356
3357 retval = 0;
8fb06c77 3358 add_wait_queue(&info->port.open_wait, &wait);
1da177e4
LT		 3359
3360 if (debug_level >= DEBUG_LEVEL_INFO)
3361 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
8fb06c77 3362 __FILE__,__LINE__, tty->driver->name, info->port.count );
1da177e4
LT		 3363
3364 spin_lock_irqsave(&info->lock, flags);
3365 if (!tty_hung_up_p(filp)) {
0fab6de0 3366 extra_count = true;
8fb06c77 3367 info->port.count--;
1da177e4
LT		 3368 }
3369 spin_unlock_irqrestore(&info->lock, flags);
8fb06c77 3370 info->port.blocked_open++;
1da177e4
LT		 3371
3372 while (1) {
3373 if ((tty->termios->c_cflag & CBAUD)) {
3374 spin_lock_irqsave(&info->lock,flags);
3375 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3376 set_signals(info);
3377 spin_unlock_irqrestore(&info->lock,flags);
3378 }
3379
3380 set_current_state(TASK_INTERRUPTIBLE);
3381
8fb06c77
AC		 3382 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3383 retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 3384 -EAGAIN : -ERESTARTSYS;
3385 break;
3386 }
3387
3388 spin_lock_irqsave(&info->lock,flags);
3389 get_signals(info);
3390 spin_unlock_irqrestore(&info->lock,flags);
3391
8fb06c77 3392 if (!(info->port.flags & ASYNC_CLOSING) &&
1da177e4
LT		 3393 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3394 break;
3395 }
3396
3397 if (signal_pending(current)) {
3398 retval = -ERESTARTSYS;
3399 break;
3400 }
3401
3402 if (debug_level >= DEBUG_LEVEL_INFO)
3403 printk("%s(%d):%s block_til_ready() count=%d\n",
8fb06c77 3404 __FILE__,__LINE__, tty->driver->name, info->port.count );
1da177e4
LT		 3405
3406 schedule();
3407 }
3408
3409 set_current_state(TASK_RUNNING);
8fb06c77 3410 remove_wait_queue(&info->port.open_wait, &wait);
1da177e4
LT		 3411
3412 if (extra_count)
8fb06c77
AC		 3413 info->port.count++;
3414 info->port.blocked_open--;
1da177e4
LT		 3415
3416 if (debug_level >= DEBUG_LEVEL_INFO)
3417 printk("%s(%d):%s block_til_ready() after, count=%d\n",
8fb06c77 3418 __FILE__,__LINE__, tty->driver->name, info->port.count );
1da177e4
LT		 3419
3420 if (!retval)
8fb06c77 3421 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3422
3423 return retval;
3424}
3425
ce9f9f73 3426static int alloc_dma_bufs(SLMP_INFO *info)
1da177e4
LT		 3427{
3428 unsigned short BuffersPerFrame;
3429 unsigned short BufferCount;
3430
3431 // Force allocation to start at 64K boundary for each port.
3432 // This is necessary because *all* buffer descriptors for a port
3433 // *must* be in the same 64K block. All descriptors on a port
3434 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3435 // into the CBP register.
3436 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3437
3438 /* Calculate the number of DMA buffers necessary to hold the */
3439 /* largest allowable frame size. Note: If the max frame size is */
3440 /* not an even multiple of the DMA buffer size then we need to */
3441 /* round the buffer count per frame up one. */
3442
3443 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3444 if ( info->max_frame_size % SCABUFSIZE )
3445 BuffersPerFrame++;
3446
3447 /* calculate total number of data buffers (SCABUFSIZE) possible
3448 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3449 * for the descriptor list (BUFFERLISTSIZE).
3450 */
3451 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3452
3453 /* limit number of buffers to maximum amount of descriptors */
3454 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3455 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3456
3457 /* use enough buffers to transmit one max size frame */
3458 info->tx_buf_count = BuffersPerFrame + 1;
3459
3460 /* never use more than half the available buffers for transmit */
3461 if (info->tx_buf_count > (BufferCount/2))
3462 info->tx_buf_count = BufferCount/2;
3463
3464 if (info->tx_buf_count > SCAMAXDESC)
3465 info->tx_buf_count = SCAMAXDESC;
3466
3467 /* use remaining buffers for receive */
3468 info->rx_buf_count = BufferCount - info->tx_buf_count;
3469
3470 if (info->rx_buf_count > SCAMAXDESC)
3471 info->rx_buf_count = SCAMAXDESC;
3472
3473 if ( debug_level >= DEBUG_LEVEL_INFO )
3474 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3475 __FILE__,__LINE__, info->device_name,
3476 info->tx_buf_count,info->rx_buf_count);
3477
3478 if ( alloc_buf_list( info ) < 0 ||
3479 alloc_frame_bufs(info,
3480 info->rx_buf_list,
3481 info->rx_buf_list_ex,
3482 info->rx_buf_count) < 0 ||
3483 alloc_frame_bufs(info,
3484 info->tx_buf_list,
3485 info->tx_buf_list_ex,
3486 info->tx_buf_count) < 0 ||
3487 alloc_tmp_rx_buf(info) < 0 ) {
3488 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3489 __FILE__,__LINE__, info->device_name);
3490 return -ENOMEM;
3491 }
3492
3493 rx_reset_buffers( info );
3494
3495 return 0;
3496}
3497
3498/* Allocate DMA buffers for the transmit and receive descriptor lists.
3499 */
ce9f9f73 3500static int alloc_buf_list(SLMP_INFO *info)
1da177e4
LT		 3501{
3502 unsigned int i;
3503
3504 /* build list in adapter shared memory */
3505 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3506 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3507 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3508
3509 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3510
3511 /* Save virtual address pointers to the receive and */
3512 /* transmit buffer lists. (Receive 1st). These pointers will */
3513 /* be used by the processor to access the lists. */
3514 info->rx_buf_list = (SCADESC *)info->buffer_list;
3515
3516 info->tx_buf_list = (SCADESC *)info->buffer_list;
3517 info->tx_buf_list += info->rx_buf_count;
3518
3519 /* Build links for circular buffer entry lists (tx and rx)
3520 *
3521 * Note: links are physical addresses read by the SCA device
3522 * to determine the next buffer entry to use.
3523 */
3524
3525 for ( i = 0; i < info->rx_buf_count; i++ ) {
3526 /* calculate and store physical address of this buffer entry */
3527 info->rx_buf_list_ex[i].phys_entry =
3528 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3529
3530 /* calculate and store physical address of */
3531 /* next entry in cirular list of entries */
3532 info->rx_buf_list[i].next = info->buffer_list_phys;
3533 if ( i < info->rx_buf_count - 1 )
3534 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3535
3536 info->rx_buf_list[i].length = SCABUFSIZE;
3537 }
3538
3539 for ( i = 0; i < info->tx_buf_count; i++ ) {
3540 /* calculate and store physical address of this buffer entry */
3541 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3542 ((info->rx_buf_count + i) * sizeof(SCADESC));
3543
3544 /* calculate and store physical address of */
3545 /* next entry in cirular list of entries */
3546
3547 info->tx_buf_list[i].next = info->buffer_list_phys +
3548 info->rx_buf_count * sizeof(SCADESC);
3549
3550 if ( i < info->tx_buf_count - 1 )
3551 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3552 }
3553
3554 return 0;
3555}
3556
3557/* Allocate the frame DMA buffers used by the specified buffer list.
3558 */
ce9f9f73 3559static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
1da177e4
LT		 3560{
3561 int i;
3562 unsigned long phys_addr;
3563
3564 for ( i = 0; i < count; i++ ) {
3565 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3566 phys_addr = info->port_array[0]->last_mem_alloc;
3567 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3568
3569 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3570 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3571 }
3572
3573 return 0;
3574}
3575
ce9f9f73 3576static void free_dma_bufs(SLMP_INFO *info)
1da177e4
LT		 3577{
3578 info->buffer_list = NULL;
3579 info->rx_buf_list = NULL;
3580 info->tx_buf_list = NULL;
3581}
3582
3583/* allocate buffer large enough to hold max_frame_size.
3584 * This buffer is used to pass an assembled frame to the line discipline.
3585 */
ce9f9f73 3586static int alloc_tmp_rx_buf(SLMP_INFO *info)
1da177e4
LT		 3587{
3588 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3589 if (info->tmp_rx_buf == NULL)
3590 return -ENOMEM;
3591 return 0;
3592}
3593
ce9f9f73 3594static void free_tmp_rx_buf(SLMP_INFO *info)
1da177e4 3595{
735d5661 3596 kfree(info->tmp_rx_buf);
1da177e4
LT		 3597 info->tmp_rx_buf = NULL;
3598}
3599
ce9f9f73 3600static int claim_resources(SLMP_INFO *info)
1da177e4
LT		 3601{
3602 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3603 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3604 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3605 info->init_error = DiagStatus_AddressConflict;
3606 goto errout;
3607 }
3608 else
0fab6de0 3609 info->shared_mem_requested = true;
1da177e4
LT		 3610
3611 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3612 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3613 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3614 info->init_error = DiagStatus_AddressConflict;
3615 goto errout;
3616 }
3617 else
0fab6de0 3618 info->lcr_mem_requested = true;
1da177e4
LT		 3619
3620 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3621 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3622 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3623 info->init_error = DiagStatus_AddressConflict;
3624 goto errout;
3625 }
3626 else
0fab6de0 3627 info->sca_base_requested = true;
1da177e4
LT		 3628
3629 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3630 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3631 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3632 info->init_error = DiagStatus_AddressConflict;
3633 goto errout;
3634 }
3635 else
0fab6de0 3636 info->sca_statctrl_requested = true;
1da177e4 3637
24cb2335
AC		 3638 info->memory_base = ioremap_nocache(info->phys_memory_base,
3639 SCA_MEM_SIZE);
1da177e4
LT		 3640 if (!info->memory_base) {
3641 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3642 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3643 info->init_error = DiagStatus_CantAssignPciResources;
3644 goto errout;
3645 }
3646
24cb2335 3647 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
1da177e4
LT		 3648 if (!info->lcr_base) {
3649 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3650 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3651 info->init_error = DiagStatus_CantAssignPciResources;
3652 goto errout;
3653 }
3654 info->lcr_base += info->lcr_offset;
3655
24cb2335 3656 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
1da177e4
LT		 3657 if (!info->sca_base) {
3658 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3659 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3660 info->init_error = DiagStatus_CantAssignPciResources;
3661 goto errout;
3662 }
3663 info->sca_base += info->sca_offset;
3664
24cb2335
AC		 3665 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3666 PAGE_SIZE);
1da177e4
LT		 3667 if (!info->statctrl_base) {
3668 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3669 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3670 info->init_error = DiagStatus_CantAssignPciResources;
3671 goto errout;
3672 }
3673 info->statctrl_base += info->statctrl_offset;
3674
3675 if ( !memory_test(info) ) {
3676 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3677 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3678 info->init_error = DiagStatus_MemoryError;
3679 goto errout;
3680 }
3681
3682 return 0;
3683
3684errout:
3685 release_resources( info );
3686 return -ENODEV;
3687}
3688
ce9f9f73 3689static void release_resources(SLMP_INFO *info)
1da177e4
LT		 3690{
3691 if ( debug_level >= DEBUG_LEVEL_INFO )
3692 printk( "%s(%d):%s release_resources() entry\n",
3693 __FILE__,__LINE__,info->device_name );
3694
3695 if ( info->irq_requested ) {
3696 free_irq(info->irq_level, info);
0fab6de0 3697 info->irq_requested = false;
1da177e4
LT		 3698 }
3699
3700 if ( info->shared_mem_requested ) {
3701 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
0fab6de0 3702 info->shared_mem_requested = false;
1da177e4
LT		 3703 }
3704 if ( info->lcr_mem_requested ) {
3705 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
0fab6de0 3706 info->lcr_mem_requested = false;
1da177e4
LT		 3707 }
3708 if ( info->sca_base_requested ) {
3709 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
0fab6de0 3710 info->sca_base_requested = false;
1da177e4
LT		 3711 }
3712 if ( info->sca_statctrl_requested ) {
3713 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
0fab6de0 3714 info->sca_statctrl_requested = false;
1da177e4
LT		 3715 }
3716
3717 if (info->memory_base){
3718 iounmap(info->memory_base);
3719 info->memory_base = NULL;
3720 }
3721
3722 if (info->sca_base) {
3723 iounmap(info->sca_base - info->sca_offset);
3724 info->sca_base=NULL;
3725 }
3726
3727 if (info->statctrl_base) {
3728 iounmap(info->statctrl_base - info->statctrl_offset);
3729 info->statctrl_base=NULL;
3730 }
3731
3732 if (info->lcr_base){
3733 iounmap(info->lcr_base - info->lcr_offset);
3734 info->lcr_base = NULL;
3735 }
3736
3737 if ( debug_level >= DEBUG_LEVEL_INFO )
3738 printk( "%s(%d):%s release_resources() exit\n",
3739 __FILE__,__LINE__,info->device_name );
3740}
3741
3742/* Add the specified device instance data structure to the
3743 * global linked list of devices and increment the device count.
3744 */
ce9f9f73 3745static void add_device(SLMP_INFO *info)
1da177e4
LT		 3746{
3747 info->next_device = NULL;
3748 info->line = synclinkmp_device_count;
3749 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3750
3751 if (info->line < MAX_DEVICES) {
3752 if (maxframe[info->line])
3753 info->max_frame_size = maxframe[info->line];
3754 info->dosyncppp = dosyncppp[info->line];
3755 }
3756
3757 synclinkmp_device_count++;
3758
3759 if ( !synclinkmp_device_list )
3760 synclinkmp_device_list = info;
3761 else {
3762 SLMP_INFO *current_dev = synclinkmp_device_list;
3763 while( current_dev->next_device )
3764 current_dev = current_dev->next_device;
3765 current_dev->next_device = info;
3766 }
3767
3768 if ( info->max_frame_size < 4096 )
3769 info->max_frame_size = 4096;
3770 else if ( info->max_frame_size > 65535 )
3771 info->max_frame_size = 65535;
3772
3773 printk( "SyncLink MultiPort %s: "
3774 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3775 info->device_name,
3776 info->phys_sca_base,
3777 info->phys_memory_base,
3778 info->phys_statctrl_base,
3779 info->phys_lcr_base,
3780 info->irq_level,
3781 info->max_frame_size );
3782
af69c7f9 3783#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3784 hdlcdev_init(info);
3785#endif
3786}
3787
3788/* Allocate and initialize a device instance structure
3789 *
3790 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3791 */
3792static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3793{
3794 SLMP_INFO *info;
3795
dd00cc48 3796 info = kzalloc(sizeof(SLMP_INFO),
1da177e4
LT		 3797 GFP_KERNEL);
3798
3799 if (!info) {
3800 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3801 __FILE__,__LINE__, adapter_num, port_num);
3802 } else {
44b7d1b3 3803 tty_port_init(&info->port);
1da177e4 3804 info->magic = MGSL_MAGIC;
c4028958 3805 INIT_WORK(&info->task, bh_handler);
1da177e4 3806 info->max_frame_size = 4096;
44b7d1b3
AC		 3807 info->port.close_delay = 5*HZ/10;
3808 info->port.closing_wait = 30*HZ;
1da177e4
LT		 3809 init_waitqueue_head(&info->status_event_wait_q);
3810 init_waitqueue_head(&info->event_wait_q);
3811 spin_lock_init(&info->netlock);
3812 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3813 info->idle_mode = HDLC_TXIDLE_FLAGS;
3814 info->adapter_num = adapter_num;
3815 info->port_num = port_num;
3816
3817 /* Copy configuration info to device instance data */
3818 info->irq_level = pdev->irq;
3819 info->phys_lcr_base = pci_resource_start(pdev,0);
3820 info->phys_sca_base = pci_resource_start(pdev,2);
3821 info->phys_memory_base = pci_resource_start(pdev,3);
3822 info->phys_statctrl_base = pci_resource_start(pdev,4);
3823
3824 /* Because veremap only works on page boundaries we must map
3825 * a larger area than is actually implemented for the LCR
3826 * memory range. We map a full page starting at the page boundary.
3827 */
3828 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3829 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3830
3831 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3832 info->phys_sca_base &= ~(PAGE_SIZE-1);
3833
3834 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3835 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3836
3837 info->bus_type = MGSL_BUS_TYPE_PCI;
0f2ed4c6 3838 info->irq_flags = IRQF_SHARED;
1da177e4 3839
40565f19
JS		 3840 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3841 setup_timer(&info->status_timer, status_timeout,
3842 (unsigned long)info);
1da177e4
LT		 3843
3844 /* Store the PCI9050 misc control register value because a flaw
3845 * in the PCI9050 prevents LCR registers from being read if
3846 * BIOS assigns an LCR base address with bit 7 set.
3847 *
3848 * Only the misc control register is accessed for which only
3849 * write access is needed, so set an initial value and change
3850 * bits to the device instance data as we write the value
3851 * to the actual misc control register.
3852 */
3853 info->misc_ctrl_value = 0x087e4546;
3854
3855 /* initial port state is unknown - if startup errors
3856 * occur, init_error will be set to indicate the
3857 * problem. Once the port is fully initialized,
3858 * this value will be set to 0 to indicate the
3859 * port is available.
3860 */
3861 info->init_error = -1;
3862 }
3863
3864 return info;
3865}
3866
ce9f9f73 3867static void device_init(int adapter_num, struct pci_dev *pdev)
1da177e4
LT		 3868{
3869 SLMP_INFO *port_array[SCA_MAX_PORTS];
3870 int port;
3871
3872 /* allocate device instances for up to SCA_MAX_PORTS devices */
3873 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3874 port_array[port] = alloc_dev(adapter_num,port,pdev);
3875 if( port_array[port] == NULL ) {
3876 for ( --port; port >= 0; --port )
3877 kfree(port_array[port]);
3878 return;
3879 }
3880 }
3881
3882 /* give copy of port_array to all ports and add to device list */
3883 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3884 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3885 add_device( port_array[port] );
3886 spin_lock_init(&port_array[port]->lock);
3887 }
3888
3889 /* Allocate and claim adapter resources */
3890 if ( !claim_resources(port_array[0]) ) {
3891
3892 alloc_dma_bufs(port_array[0]);
3893
3894 /* copy resource information from first port to others */
3895 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3896 port_array[port]->lock = port_array[0]->lock;
3897 port_array[port]->irq_level = port_array[0]->irq_level;
3898 port_array[port]->memory_base = port_array[0]->memory_base;
3899 port_array[port]->sca_base = port_array[0]->sca_base;
3900 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3901 port_array[port]->lcr_base = port_array[0]->lcr_base;
3902 alloc_dma_bufs(port_array[port]);
3903 }
3904
3905 if ( request_irq(port_array[0]->irq_level,
3906 synclinkmp_interrupt,
3907 port_array[0]->irq_flags,
3908 port_array[0]->device_name,
3909 port_array[0]) < 0 ) {
3910 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3911 __FILE__,__LINE__,
3912 port_array[0]->device_name,
3913 port_array[0]->irq_level );
3914 }
3915 else {
0fab6de0 3916 port_array[0]->irq_requested = true;
1da177e4
LT		 3917 adapter_test(port_array[0]);
3918 }
3919 }
3920}
3921
b68e31d0 3922static const struct tty_operations ops = {
1da177e4
LT		 3923 .open = open,
3924 .close = close,
3925 .write = write,
3926 .put_char = put_char,
3927 .flush_chars = flush_chars,
3928 .write_room = write_room,
3929 .chars_in_buffer = chars_in_buffer,
3930 .flush_buffer = flush_buffer,
3931 .ioctl = ioctl,
3932 .throttle = throttle,
3933 .unthrottle = unthrottle,
3934 .send_xchar = send_xchar,
3935 .break_ctl = set_break,
3936 .wait_until_sent = wait_until_sent,
3937 .read_proc = read_proc,
3938 .set_termios = set_termios,
3939 .stop = tx_hold,
3940 .start = tx_release,
3941 .hangup = hangup,
3942 .tiocmget = tiocmget,
3943 .tiocmset = tiocmset,
3944};
3945
3946static void synclinkmp_cleanup(void)
3947{
3948 int rc;
3949 SLMP_INFO *info;
3950 SLMP_INFO *tmp;
3951
3952 printk("Unloading %s %s\n", driver_name, driver_version);
3953
3954 if (serial_driver) {
3955 if ((rc = tty_unregister_driver(serial_driver)))
3956 printk("%s(%d) failed to unregister tty driver err=%d\n",
3957 __FILE__,__LINE__,rc);
3958 put_tty_driver(serial_driver);
3959 }
3960
3961 /* reset devices */
3962 info = synclinkmp_device_list;
3963 while(info) {
3964 reset_port(info);
3965 info = info->next_device;
3966 }
3967
3968 /* release devices */
3969 info = synclinkmp_device_list;
3970 while(info) {
af69c7f9 3971#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3972 hdlcdev_exit(info);
3973#endif
3974 free_dma_bufs(info);
3975 free_tmp_rx_buf(info);
3976 if ( info->port_num == 0 ) {
3977 if (info->sca_base)
3978 write_reg(info, LPR, 1); /* set low power mode */
3979 release_resources(info);
3980 }
3981 tmp = info;
3982 info = info->next_device;
3983 kfree(tmp);
3984 }
3985
3986 pci_unregister_driver(&synclinkmp_pci_driver);
3987}
3988
3989/* Driver initialization entry point.
3990 */
3991
3992static int __init synclinkmp_init(void)
3993{
3994 int rc;
3995
3996 if (break_on_load) {
3997 synclinkmp_get_text_ptr();
3998 BREAKPOINT();
3999 }
4000
4001 printk("%s %s\n", driver_name, driver_version);
4002
4003 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4004 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4005 return rc;
4006 }
4007
4008 serial_driver = alloc_tty_driver(128);
4009 if (!serial_driver) {
4010 rc = -ENOMEM;
4011 goto error;
4012 }
4013
4014 /* Initialize the tty_driver structure */
4015
4016 serial_driver->owner = THIS_MODULE;
4017 serial_driver->driver_name = "synclinkmp";
4018 serial_driver->name = "ttySLM";
4019 serial_driver->major = ttymajor;
4020 serial_driver->minor_start = 64;
4021 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4022 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4023 serial_driver->init_termios = tty_std_termios;
4024 serial_driver->init_termios.c_cflag =
4025 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 4026 serial_driver->init_termios.c_ispeed = 9600;
4027 serial_driver->init_termios.c_ospeed = 9600;
1da177e4
LT		 4028 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4029 tty_set_operations(serial_driver, &ops);
4030 if ((rc = tty_register_driver(serial_driver)) < 0) {
4031 printk("%s(%d):Couldn't register serial driver\n",
4032 __FILE__,__LINE__);
4033 put_tty_driver(serial_driver);
4034 serial_driver = NULL;
4035 goto error;
4036 }
4037
4038 printk("%s %s, tty major#%d\n",
4039 driver_name, driver_version,
4040 serial_driver->major);
4041
4042 return 0;
4043
4044error:
4045 synclinkmp_cleanup();
4046 return rc;
4047}
4048
4049static void __exit synclinkmp_exit(void)
4050{
4051 synclinkmp_cleanup();
4052}
4053
4054module_init(synclinkmp_init);
4055module_exit(synclinkmp_exit);
4056
4057/* Set the port for internal loopback mode.
4058 * The TxCLK and RxCLK signals are generated from the BRG and
4059 * the TxD is looped back to the RxD internally.
4060 */
ce9f9f73 4061static void enable_loopback(SLMP_INFO *info, int enable)
1da177e4
LT		 4062{
4063 if (enable) {
4064 /* MD2 (Mode Register 2)
4065 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4066 */
4067 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4068
4069 /* degate external TxC clock source */
4070 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4071 write_control_reg(info);
4072
4073 /* RXS/TXS (Rx/Tx clock source)
4074 * 07 Reserved, must be 0
4075 * 06..04 Clock Source, 100=BRG
4076 * 03..00 Clock Divisor, 0000=1
4077 */
4078 write_reg(info, RXS, 0x40);
4079 write_reg(info, TXS, 0x40);
4080
4081 } else {
4082 /* MD2 (Mode Register 2)
4083 * 01..00 CNCT<1..0> Channel connection, 0=normal
4084 */
4085 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4086
4087 /* RXS/TXS (Rx/Tx clock source)
4088 * 07 Reserved, must be 0
4089 * 06..04 Clock Source, 000=RxC/TxC Pin
4090 * 03..00 Clock Divisor, 0000=1
4091 */
4092 write_reg(info, RXS, 0x00);
4093 write_reg(info, TXS, 0x00);
4094 }
4095
4096 /* set LinkSpeed if available, otherwise default to 2Mbps */
4097 if (info->params.clock_speed)
4098 set_rate(info, info->params.clock_speed);
4099 else
4100 set_rate(info, 3686400);
4101}
4102
4103/* Set the baud rate register to the desired speed
4104 *
4105 * data_rate data rate of clock in bits per second
4106 * A data rate of 0 disables the AUX clock.
4107 */
ce9f9f73 4108static void set_rate( SLMP_INFO *info, u32 data_rate )
1da177e4
LT		 4109{
4110 u32 TMCValue;
4111 unsigned char BRValue;
4112 u32 Divisor=0;
4113
4114 /* fBRG = fCLK/(TMC * 2^BR)
4115 */
4116 if (data_rate != 0) {
4117 Divisor = 14745600/data_rate;
4118 if (!Divisor)
4119 Divisor = 1;
4120
4121 TMCValue = Divisor;
4122
4123 BRValue = 0;
4124 if (TMCValue != 1 && TMCValue != 2) {
4125 /* BRValue of 0 provides 50/50 duty cycle *only* when
4126 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4127 * 50/50 duty cycle.
4128 */
4129 BRValue = 1;
4130 TMCValue >>= 1;
4131 }
4132
4133 /* while TMCValue is too big for TMC register, divide
4134 * by 2 and increment BR exponent.
4135 */
4136 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4137 TMCValue >>= 1;
4138
4139 write_reg(info, TXS,
4140 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4141 write_reg(info, RXS,
4142 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4143 write_reg(info, TMC, (unsigned char)TMCValue);
4144 }
4145 else {
4146 write_reg(info, TXS,0);
4147 write_reg(info, RXS,0);
4148 write_reg(info, TMC, 0);
4149 }
4150}
4151
4152/* Disable receiver
4153 */
ce9f9f73 4154static void rx_stop(SLMP_INFO *info)
1da177e4
LT		 4155{
4156 if (debug_level >= DEBUG_LEVEL_ISR)
4157 printk("%s(%d):%s rx_stop()\n",
4158 __FILE__,__LINE__, info->device_name );
4159
4160 write_reg(info, CMD, RXRESET);
4161
4162 info->ie0_value &= ~RXRDYE;
4163 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4164
4165 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4166 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4167 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4168
0fab6de0
JP		 4169 info->rx_enabled = false;
4170 info->rx_overflow = false;
1da177e4
LT		 4171}
4172
4173/* enable the receiver
4174 */
ce9f9f73 4175static void rx_start(SLMP_INFO *info)
1da177e4
LT		 4176{
4177 int i;
4178
4179 if (debug_level >= DEBUG_LEVEL_ISR)
4180 printk("%s(%d):%s rx_start()\n",
4181 __FILE__,__LINE__, info->device_name );
4182
4183 write_reg(info, CMD, RXRESET);
4184
4185 if ( info->params.mode == MGSL_MODE_HDLC ) {
4186 /* HDLC, disabe IRQ on rxdata */
4187 info->ie0_value &= ~RXRDYE;
4188 write_reg(info, IE0, info->ie0_value);
4189
4190 /* Reset all Rx DMA buffers and program rx dma */
4191 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4192 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4193
4194 for (i = 0; i < info->rx_buf_count; i++) {
4195 info->rx_buf_list[i].status = 0xff;
4196
4197 // throttle to 4 shared memory writes at a time to prevent
4198 // hogging local bus (keep latency time for DMA requests low).
4199 if (!(i % 4))
4200 read_status_reg(info);
4201 }
4202 info->current_rx_buf = 0;
4203
4204 /* set current/1st descriptor address */
4205 write_reg16(info, RXDMA + CDA,
4206 info->rx_buf_list_ex[0].phys_entry);
4207
4208 /* set new last rx descriptor address */
4209 write_reg16(info, RXDMA + EDA,
4210 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4211
4212 /* set buffer length (shared by all rx dma data buffers) */
4213 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4214
4215 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4216 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4217 } else {
4218 /* async, enable IRQ on rxdata */
4219 info->ie0_value |= RXRDYE;
4220 write_reg(info, IE0, info->ie0_value);
4221 }
4222
4223 write_reg(info, CMD, RXENABLE);
4224
0fab6de0
JP		 4225 info->rx_overflow = false;
4226 info->rx_enabled = true;
1da177e4
LT		 4227}
4228
4229/* Enable the transmitter and send a transmit frame if
4230 * one is loaded in the DMA buffers.
4231 */
ce9f9f73 4232static void tx_start(SLMP_INFO *info)
1da177e4
LT		 4233{
4234 if (debug_level >= DEBUG_LEVEL_ISR)
4235 printk("%s(%d):%s tx_start() tx_count=%d\n",
4236 __FILE__,__LINE__, info->device_name,info->tx_count );
4237
4238 if (!info->tx_enabled ) {
4239 write_reg(info, CMD, TXRESET);
4240 write_reg(info, CMD, TXENABLE);
0fab6de0 4241 info->tx_enabled = true;
1da177e4
LT		 4242 }
4243
4244 if ( info->tx_count ) {
4245
4246 /* If auto RTS enabled and RTS is inactive, then assert */
4247 /* RTS and set a flag indicating that the driver should */
4248 /* negate RTS when the transmission completes. */
4249
0fab6de0 4250 info->drop_rts_on_tx_done = false;
1da177e4
LT		 4251
4252 if (info->params.mode != MGSL_MODE_ASYNC) {
4253
4254 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4255 get_signals( info );
4256 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4257 info->serial_signals |= SerialSignal_RTS;
4258 set_signals( info );
0fab6de0 4259 info->drop_rts_on_tx_done = true;
1da177e4
LT		 4260 }
4261 }
4262
4263 write_reg16(info, TRC0,
4264 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4265
4266 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4267 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4268
4269 /* set TX CDA (current descriptor address) */
4270 write_reg16(info, TXDMA + CDA,
4271 info->tx_buf_list_ex[0].phys_entry);
4272
4273 /* set TX EDA (last descriptor address) */
4274 write_reg16(info, TXDMA + EDA,
4275 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4276
4277 /* enable underrun IRQ */
4278 info->ie1_value &= ~IDLE;
4279 info->ie1_value |= UDRN;
4280 write_reg(info, IE1, info->ie1_value);
4281 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4282
4283 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4284 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4285
40565f19
JS		 4286 mod_timer(&info->tx_timer, jiffies +
4287 msecs_to_jiffies(5000));
1da177e4
LT		 4288 }
4289 else {
4290 tx_load_fifo(info);
4291 /* async, enable IRQ on txdata */
4292 info->ie0_value |= TXRDYE;
4293 write_reg(info, IE0, info->ie0_value);
4294 }
4295
0fab6de0 4296 info->tx_active = true;
1da177e4
LT		 4297 }
4298}
4299
4300/* stop the transmitter and DMA
4301 */
ce9f9f73 4302static void tx_stop( SLMP_INFO *info )
1da177e4
LT		 4303{
4304 if (debug_level >= DEBUG_LEVEL_ISR)
4305 printk("%s(%d):%s tx_stop()\n",
4306 __FILE__,__LINE__, info->device_name );
4307
4308 del_timer(&info->tx_timer);
4309
4310 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4311 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4312
4313 write_reg(info, CMD, TXRESET);
4314
4315 info->ie1_value &= ~(UDRN + IDLE);
4316 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4317 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4318
4319 info->ie0_value &= ~TXRDYE;
4320 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4321
0fab6de0
JP		 4322 info->tx_enabled = false;
4323 info->tx_active = false;
1da177e4
LT		 4324}
4325
4326/* Fill the transmit FIFO until the FIFO is full or
4327 * there is no more data to load.
4328 */
ce9f9f73 4329static void tx_load_fifo(SLMP_INFO *info)
1da177e4
LT		 4330{
4331 u8 TwoBytes[2];
4332
4333 /* do nothing is now tx data available and no XON/XOFF pending */
4334
4335 if ( !info->tx_count && !info->x_char )
4336 return;
4337
4338 /* load the Transmit FIFO until FIFOs full or all data sent */
4339
4340 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4341
4342 /* there is more space in the transmit FIFO and */
4343 /* there is more data in transmit buffer */
4344
4345 if ( (info->tx_count > 1) && !info->x_char ) {
4346 /* write 16-bits */
4347 TwoBytes[0] = info->tx_buf[info->tx_get++];
4348 if (info->tx_get >= info->max_frame_size)
4349 info->tx_get -= info->max_frame_size;
4350 TwoBytes[1] = info->tx_buf[info->tx_get++];
4351 if (info->tx_get >= info->max_frame_size)
4352 info->tx_get -= info->max_frame_size;
4353
4354 write_reg16(info, TRB, *((u16 *)TwoBytes));
4355
4356 info->tx_count -= 2;
4357 info->icount.tx += 2;
4358 } else {
4359 /* only 1 byte left to transmit or 1 FIFO slot left */
4360
4361 if (info->x_char) {
4362 /* transmit pending high priority char */
4363 write_reg(info, TRB, info->x_char);
4364 info->x_char = 0;
4365 } else {
4366 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4367 if (info->tx_get >= info->max_frame_size)
4368 info->tx_get -= info->max_frame_size;
4369 info->tx_count--;
4370 }
4371 info->icount.tx++;
4372 }
4373 }
4374}
4375
4376/* Reset a port to a known state
4377 */
ce9f9f73 4378static void reset_port(SLMP_INFO *info)
1da177e4
LT		 4379{
4380 if (info->sca_base) {
4381
4382 tx_stop(info);
4383 rx_stop(info);
4384
4385 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4386 set_signals(info);
4387
4388 /* disable all port interrupts */
4389 info->ie0_value = 0;
4390 info->ie1_value = 0;
4391 info->ie2_value = 0;
4392 write_reg(info, IE0, info->ie0_value);
4393 write_reg(info, IE1, info->ie1_value);
4394 write_reg(info, IE2, info->ie2_value);
4395
4396 write_reg(info, CMD, CHRESET);
4397 }
4398}
4399
4400/* Reset all the ports to a known state.
4401 */
ce9f9f73 4402static void reset_adapter(SLMP_INFO *info)
1da177e4
LT		 4403{
4404 int i;
4405
4406 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4407 if (info->port_array[i])
4408 reset_port(info->port_array[i]);
4409 }
4410}
4411
4412/* Program port for asynchronous communications.
4413 */
ce9f9f73 4414static void async_mode(SLMP_INFO *info)
1da177e4
LT		 4415{
4416
4417 unsigned char RegValue;
4418
4419 tx_stop(info);
4420 rx_stop(info);
4421
4422 /* MD0, Mode Register 0
4423 *
4424 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4425 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4426 * 03 Reserved, must be 0
4427 * 02 CRCCC, CRC Calculation, 0=disabled
4428 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4429 *
4430 * 0000 0000
4431 */
4432 RegValue = 0x00;
4433 if (info->params.stop_bits != 1)
4434 RegValue |= BIT1;
4435 write_reg(info, MD0, RegValue);
4436
4437 /* MD1, Mode Register 1
4438 *
4439 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4440 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4441 * 03..02 RXCHR<1..0>, rx char size
4442 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4443 *
4444 * 0100 0000
4445 */
4446 RegValue = 0x40;
4447 switch (info->params.data_bits) {
4448 case 7: RegValue |= BIT4 + BIT2; break;
4449 case 6: RegValue |= BIT5 + BIT3; break;
4450 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4451 }
4452 if (info->params.parity != ASYNC_PARITY_NONE) {
4453 RegValue |= BIT1;
4454 if (info->params.parity == ASYNC_PARITY_ODD)
4455 RegValue |= BIT0;
4456 }
4457 write_reg(info, MD1, RegValue);
4458
4459 /* MD2, Mode Register 2
4460 *
4461 * 07..02 Reserved, must be 0
6e8dcee3 4462 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
1da177e4
LT		 4463 *
4464 * 0000 0000
4465 */
4466 RegValue = 0x00;
6e8dcee3
PF		 4467 if (info->params.loopback)
4468 RegValue |= (BIT1 + BIT0);
1da177e4
LT		 4469 write_reg(info, MD2, RegValue);
4470
4471 /* RXS, Receive clock source
4472 *
4473 * 07 Reserved, must be 0
4474 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4475 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4476 */
4477 RegValue=BIT6;
4478 write_reg(info, RXS, RegValue);
4479
4480 /* TXS, Transmit clock source
4481 *
4482 * 07 Reserved, must be 0
4483 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4484 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4485 */
4486 RegValue=BIT6;
4487 write_reg(info, TXS, RegValue);
4488
4489 /* Control Register
4490 *
4491 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4492 */
4493 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4494 write_control_reg(info);
4495
4496 tx_set_idle(info);
4497
4498 /* RRC Receive Ready Control 0
4499 *
4500 * 07..05 Reserved, must be 0
4501 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4502 */
4503 write_reg(info, RRC, 0x00);
4504
4505 /* TRC0 Transmit Ready Control 0
4506 *
4507 * 07..05 Reserved, must be 0
4508 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4509 */
4510 write_reg(info, TRC0, 0x10);
4511
4512 /* TRC1 Transmit Ready Control 1
4513 *
4514 * 07..05 Reserved, must be 0
4515 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4516 */
4517 write_reg(info, TRC1, 0x1e);
4518
4519 /* CTL, MSCI control register
4520 *
4521 * 07..06 Reserved, set to 0
4522 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4523 * 04 IDLC, idle control, 0=mark 1=idle register
4524 * 03 BRK, break, 0=off 1 =on (async)
4525 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4526 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4527 * 00 RTS, RTS output control, 0=active 1=inactive
4528 *
4529 * 0001 0001
4530 */
4531 RegValue = 0x10;
4532 if (!(info->serial_signals & SerialSignal_RTS))
4533 RegValue |= 0x01;
4534 write_reg(info, CTL, RegValue);
4535
4536 /* enable status interrupts */
4537 info->ie0_value |= TXINTE + RXINTE;
4538 write_reg(info, IE0, info->ie0_value);
4539
4540 /* enable break detect interrupt */
4541 info->ie1_value = BRKD;
4542 write_reg(info, IE1, info->ie1_value);
4543
4544 /* enable rx overrun interrupt */
4545 info->ie2_value = OVRN;
4546 write_reg(info, IE2, info->ie2_value);
4547
4548 set_rate( info, info->params.data_rate * 16 );
1da177e4
LT		 4549}
4550
4551/* Program the SCA for HDLC communications.
4552 */
ce9f9f73 4553static void hdlc_mode(SLMP_INFO *info)
1da177e4
LT		 4554{
4555 unsigned char RegValue;
4556 u32 DpllDivisor;
4557
4558 // Can't use DPLL because SCA outputs recovered clock on RxC when
4559 // DPLL mode selected. This causes output contention with RxC receiver.
4560 // Use of DPLL would require external hardware to disable RxC receiver
4561 // when DPLL mode selected.
4562 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4563
4564 /* disable DMA interrupts */
4565 write_reg(info, TXDMA + DIR, 0);
4566 write_reg(info, RXDMA + DIR, 0);
4567
4568 /* MD0, Mode Register 0
4569 *
4570 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4571 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4572 * 03 Reserved, must be 0
4573 * 02 CRCCC, CRC Calculation, 1=enabled
4574 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4575 * 00 CRC0, CRC initial value, 1 = all 1s
4576 *
4577 * 1000 0001
4578 */
4579 RegValue = 0x81;
4580 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4581 RegValue |= BIT4;
4582 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4583 RegValue |= BIT4;
4584 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4585 RegValue |= BIT2 + BIT1;
4586 write_reg(info, MD0, RegValue);
4587
4588 /* MD1, Mode Register 1
4589 *
4590 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4591 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4592 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4593 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4594 *
4595 * 0000 0000
4596 */
4597 RegValue = 0x00;
4598 write_reg(info, MD1, RegValue);
4599
4600 /* MD2, Mode Register 2
4601 *
4602 * 07 NRZFM, 0=NRZ, 1=FM
4603 * 06..05 CODE<1..0> Encoding, 00=NRZ
4604 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4605 * 02 Reserved, must be 0
4606 * 01..00 CNCT<1..0> Channel connection, 0=normal
4607 *
4608 * 0000 0000
4609 */
4610 RegValue = 0x00;
4611 switch(info->params.encoding) {
4612 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4613 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4614 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4615 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4616#if 0
4617 case HDLC_ENCODING_NRZB: /* not supported */
4618 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4619 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4620#endif
4621 }
4622 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4623 DpllDivisor = 16;
4624 RegValue |= BIT3;
4625 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4626 DpllDivisor = 8;
4627 } else {
4628 DpllDivisor = 32;
4629 RegValue |= BIT4;
4630 }
4631 write_reg(info, MD2, RegValue);
4632
4633
4634 /* RXS, Receive clock source
4635 *
4636 * 07 Reserved, must be 0
4637 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4638 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4639 */
4640 RegValue=0;
4641 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4642 RegValue |= BIT6;
4643 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4644 RegValue |= BIT6 + BIT5;
4645 write_reg(info, RXS, RegValue);
4646
4647 /* TXS, Transmit clock source
4648 *
4649 * 07 Reserved, must be 0
4650 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4651 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4652 */
4653 RegValue=0;
4654 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4655 RegValue |= BIT6;
4656 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4657 RegValue |= BIT6 + BIT5;
4658 write_reg(info, TXS, RegValue);
4659
4660 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4661 set_rate(info, info->params.clock_speed * DpllDivisor);
4662 else
4663 set_rate(info, info->params.clock_speed);
4664
4665 /* GPDATA (General Purpose I/O Data Register)
4666 *
4667 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4668 */
4669 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4670 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4671 else
4672 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4673 write_control_reg(info);
4674
4675 /* RRC Receive Ready Control 0
4676 *
4677 * 07..05 Reserved, must be 0
4678 * 04..00 RRC<4..0> Rx FIFO trigger active
4679 */
4680 write_reg(info, RRC, rx_active_fifo_level);
4681
4682 /* TRC0 Transmit Ready Control 0
4683 *
4684 * 07..05 Reserved, must be 0
4685 * 04..00 TRC<4..0> Tx FIFO trigger active
4686 */
4687 write_reg(info, TRC0, tx_active_fifo_level);
4688
4689 /* TRC1 Transmit Ready Control 1
4690 *
4691 * 07..05 Reserved, must be 0
4692 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4693 */
4694 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4695
4696 /* DMR, DMA Mode Register
4697 *
4698 * 07..05 Reserved, must be 0
4699 * 04 TMOD, Transfer Mode: 1=chained-block
4700 * 03 Reserved, must be 0
4701 * 02 NF, Number of Frames: 1=multi-frame
4702 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4703 * 00 Reserved, must be 0
4704 *
4705 * 0001 0100
4706 */
4707 write_reg(info, TXDMA + DMR, 0x14);
4708 write_reg(info, RXDMA + DMR, 0x14);
4709
4710 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4711 write_reg(info, RXDMA + CPB,
4712 (unsigned char)(info->buffer_list_phys >> 16));
4713
4714 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4715 write_reg(info, TXDMA + CPB,
4716 (unsigned char)(info->buffer_list_phys >> 16));
4717
4718 /* enable status interrupts. other code enables/disables
4719 * the individual sources for these two interrupt classes.
4720 */
4721 info->ie0_value |= TXINTE + RXINTE;
4722 write_reg(info, IE0, info->ie0_value);
4723
4724 /* CTL, MSCI control register
4725 *
4726 * 07..06 Reserved, set to 0
4727 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4728 * 04 IDLC, idle control, 0=mark 1=idle register
4729 * 03 BRK, break, 0=off 1 =on (async)
4730 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4731 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4732 * 00 RTS, RTS output control, 0=active 1=inactive
4733 *
4734 * 0001 0001
4735 */
4736 RegValue = 0x10;
4737 if (!(info->serial_signals & SerialSignal_RTS))
4738 RegValue |= 0x01;
4739 write_reg(info, CTL, RegValue);
4740
4741 /* preamble not supported ! */
4742
4743 tx_set_idle(info);
4744 tx_stop(info);
4745 rx_stop(info);
4746
4747 set_rate(info, info->params.clock_speed);
4748
4749 if (info->params.loopback)
4750 enable_loopback(info,1);
4751}
4752
4753/* Set the transmit HDLC idle mode
4754 */
ce9f9f73 4755static void tx_set_idle(SLMP_INFO *info)
1da177e4
LT		 4756{
4757 unsigned char RegValue = 0xff;
4758
4759 /* Map API idle mode to SCA register bits */
4760 switch(info->idle_mode) {
4761 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4762 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4763 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4764 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4765 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4766 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4767 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4768 }
4769
4770 write_reg(info, IDL, RegValue);
4771}
4772
4773/* Query the adapter for the state of the V24 status (input) signals.
4774 */
ce9f9f73 4775static void get_signals(SLMP_INFO *info)
1da177e4
LT		 4776{
4777 u16 status = read_reg(info, SR3);
4778 u16 gpstatus = read_status_reg(info);
4779 u16 testbit;
4780
4781 /* clear all serial signals except DTR and RTS */
4782 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4783
4784 /* set serial signal bits to reflect MISR */
4785
4786 if (!(status & BIT3))
4787 info->serial_signals |= SerialSignal_CTS;
4788
4789 if ( !(status & BIT2))
4790 info->serial_signals |= SerialSignal_DCD;
4791
4792 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4793 if (!(gpstatus & testbit))
4794 info->serial_signals |= SerialSignal_RI;
4795
4796 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4797 if (!(gpstatus & testbit))
4798 info->serial_signals |= SerialSignal_DSR;
4799}
4800
4801/* Set the state of DTR and RTS based on contents of
4802 * serial_signals member of device context.
4803 */
ce9f9f73 4804static void set_signals(SLMP_INFO *info)
1da177e4
LT		 4805{
4806 unsigned char RegValue;
4807 u16 EnableBit;
4808
4809 RegValue = read_reg(info, CTL);
4810 if (info->serial_signals & SerialSignal_RTS)
4811 RegValue &= ~BIT0;
4812 else
4813 RegValue |= BIT0;
4814 write_reg(info, CTL, RegValue);
4815
4816 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4817 EnableBit = BIT1 << (info->port_num*2);
4818 if (info->serial_signals & SerialSignal_DTR)
4819 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4820 else
4821 info->port_array[0]->ctrlreg_value |= EnableBit;
4822 write_control_reg(info);
4823}
4824
4825/*******************/
4826/* DMA Buffer Code */
4827/*******************/
4828
4829/* Set the count for all receive buffers to SCABUFSIZE
4830 * and set the current buffer to the first buffer. This effectively
4831 * makes all buffers free and discards any data in buffers.
4832 */
ce9f9f73 4833static void rx_reset_buffers(SLMP_INFO *info)
1da177e4
LT		 4834{
4835 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4836}
4837
4838/* Free the buffers used by a received frame
4839 *
4840 * info pointer to device instance data
4841 * first index of 1st receive buffer of frame
4842 * last index of last receive buffer of frame
4843 */
ce9f9f73 4844static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
1da177e4 4845{
0fab6de0 4846 bool done = false;
1da177e4
LT		 4847
4848 while(!done) {
4849 /* reset current buffer for reuse */
4850 info->rx_buf_list[first].status = 0xff;
4851
4852 if (first == last) {
0fab6de0 4853 done = true;
1da177e4
LT		 4854 /* set new last rx descriptor address */
4855 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4856 }
4857
4858 first++;
4859 if (first == info->rx_buf_count)
4860 first = 0;
4861 }
4862
4863 /* set current buffer to next buffer after last buffer of frame */
4864 info->current_rx_buf = first;
4865}
4866
4867/* Return a received frame from the receive DMA buffers.
4868 * Only frames received without errors are returned.
4869 *
0fab6de0 4870 * Return Value: true if frame returned, otherwise false
1da177e4 4871 */
ce9f9f73 4872static bool rx_get_frame(SLMP_INFO *info)
1da177e4
LT		 4873{
4874 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4875 unsigned short status;
4876 unsigned int framesize = 0;
0fab6de0 4877 bool ReturnCode = false;
1da177e4 4878 unsigned long flags;
8fb06c77 4879 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 4880 unsigned char addr_field = 0xff;
4881 SCADESC *desc;
4882 SCADESC_EX *desc_ex;
4883
4884CheckAgain:
4885 /* assume no frame returned, set zero length */
4886 framesize = 0;
4887 addr_field = 0xff;
4888
4889 /*
4890 * current_rx_buf points to the 1st buffer of the next available
4891 * receive frame. To find the last buffer of the frame look for
4892 * a non-zero status field in the buffer entries. (The status
4893 * field is set by the 16C32 after completing a receive frame.
4894 */
4895 StartIndex = EndIndex = info->current_rx_buf;
4896
4897 for ( ;; ) {
4898 desc = &info->rx_buf_list[EndIndex];
4899 desc_ex = &info->rx_buf_list_ex[EndIndex];
4900
4901 if (desc->status == 0xff)
4902 goto Cleanup; /* current desc still in use, no frames available */
4903
4904 if (framesize == 0 && info->params.addr_filter != 0xff)
4905 addr_field = desc_ex->virt_addr[0];
4906
4907 framesize += desc->length;
4908
4909 /* Status != 0 means last buffer of frame */
4910 if (desc->status)
4911 break;
4912
4913 EndIndex++;
4914 if (EndIndex == info->rx_buf_count)
4915 EndIndex = 0;
4916
4917 if (EndIndex == info->current_rx_buf) {
4918 /* all buffers have been 'used' but none mark */
4919 /* the end of a frame. Reset buffers and receiver. */
4920 if ( info->rx_enabled ){
4921 spin_lock_irqsave(&info->lock,flags);
4922 rx_start(info);
4923 spin_unlock_irqrestore(&info->lock,flags);
4924 }
4925 goto Cleanup;
4926 }
4927
4928 }
4929
4930 /* check status of receive frame */
4931
4932 /* frame status is byte stored after frame data
4933 *
4934 * 7 EOM (end of msg), 1 = last buffer of frame
4935 * 6 Short Frame, 1 = short frame
4936 * 5 Abort, 1 = frame aborted
4937 * 4 Residue, 1 = last byte is partial
4938 * 3 Overrun, 1 = overrun occurred during frame reception
4939 * 2 CRC, 1 = CRC error detected
4940 *
4941 */
4942 status = desc->status;
4943
4944 /* ignore CRC bit if not using CRC (bit is undefined) */
4945 /* Note:CRC is not save to data buffer */
4946 if (info->params.crc_type == HDLC_CRC_NONE)
4947 status &= ~BIT2;
4948
4949 if (framesize == 0 ||
4950 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4951 /* discard 0 byte frames, this seems to occur sometime
4952 * when remote is idling flags.
4953 */
4954 rx_free_frame_buffers(info, StartIndex, EndIndex);
4955 goto CheckAgain;
4956 }
4957
4958 if (framesize < 2)
4959 status |= BIT6;
4960
4961 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4962 /* received frame has errors,
4963 * update counts and mark frame size as 0
4964 */
4965 if (status & BIT6)
4966 info->icount.rxshort++;
4967 else if (status & BIT5)
4968 info->icount.rxabort++;
4969 else if (status & BIT3)
4970 info->icount.rxover++;
4971 else
4972 info->icount.rxcrc++;
4973
4974 framesize = 0;
af69c7f9 4975#if SYNCLINK_GENERIC_HDLC
1da177e4 4976 {
198191c4
KH		 4977 info->netdev->stats.rx_errors++;
4978 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 4979 }
4980#endif
4981 }
4982
4983 if ( debug_level >= DEBUG_LEVEL_BH )
4984 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4985 __FILE__,__LINE__,info->device_name,status,framesize);
4986
4987 if ( debug_level >= DEBUG_LEVEL_DATA )
4988 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4989 min_t(int, framesize,SCABUFSIZE),0);
4990
4991 if (framesize) {
4992 if (framesize > info->max_frame_size)
4993 info->icount.rxlong++;
4994 else {
4995 /* copy dma buffer(s) to contiguous intermediate buffer */
4996 int copy_count = framesize;
4997 int index = StartIndex;
4998 unsigned char *ptmp = info->tmp_rx_buf;
4999 info->tmp_rx_buf_count = framesize;
5000
5001 info->icount.rxok++;
5002
5003 while(copy_count) {
5004 int partial_count = min(copy_count,SCABUFSIZE);
5005 memcpy( ptmp,
5006 info->rx_buf_list_ex[index].virt_addr,
5007 partial_count );
5008 ptmp += partial_count;
5009 copy_count -= partial_count;
5010
5011 if ( ++index == info->rx_buf_count )
5012 index = 0;
5013 }
5014
af69c7f9 5015#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 5016 if (info->netcount)
5017 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5018 else
5019#endif
5020 ldisc_receive_buf(tty,info->tmp_rx_buf,
5021 info->flag_buf, framesize);
5022 }
5023 }
5024 /* Free the buffers used by this frame. */
5025 rx_free_frame_buffers( info, StartIndex, EndIndex );
5026
0fab6de0 5027 ReturnCode = true;
1da177e4
LT		 5028
5029Cleanup:
5030 if ( info->rx_enabled && info->rx_overflow ) {
5031 /* Receiver is enabled, but needs to restarted due to
5032 * rx buffer overflow. If buffers are empty, restart receiver.
5033 */
5034 if (info->rx_buf_list[EndIndex].status == 0xff) {
5035 spin_lock_irqsave(&info->lock,flags);
5036 rx_start(info);
5037 spin_unlock_irqrestore(&info->lock,flags);
5038 }
5039 }
5040
5041 return ReturnCode;
5042}
5043
5044/* load the transmit DMA buffer with data
5045 */
ce9f9f73 5046static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
1da177e4
LT		 5047{
5048 unsigned short copy_count;
5049 unsigned int i = 0;
5050 SCADESC *desc;
5051 SCADESC_EX *desc_ex;
5052
5053 if ( debug_level >= DEBUG_LEVEL_DATA )
5054 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5055
5056 /* Copy source buffer to one or more DMA buffers, starting with
5057 * the first transmit dma buffer.
5058 */
5059 for(i=0;;)
5060 {
5061 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5062
5063 desc = &info->tx_buf_list[i];
5064 desc_ex = &info->tx_buf_list_ex[i];
5065
5066 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5067
5068 desc->length = copy_count;
5069 desc->status = 0;
5070
5071 buf += copy_count;
5072 count -= copy_count;
5073
5074 if (!count)
5075 break;
5076
5077 i++;
5078 if (i >= info->tx_buf_count)
5079 i = 0;
5080 }
5081
5082 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5083 info->last_tx_buf = ++i;
5084}
5085
ce9f9f73 5086static bool register_test(SLMP_INFO *info)
1da177e4
LT		 5087{
5088 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
fe971071 5089 static unsigned int count = ARRAY_SIZE(testval);
1da177e4 5090 unsigned int i;
0fab6de0 5091 bool rc = true;
1da177e4
LT		 5092 unsigned long flags;
5093
5094 spin_lock_irqsave(&info->lock,flags);
5095 reset_port(info);
5096
5097 /* assume failure */
5098 info->init_error = DiagStatus_AddressFailure;
5099
5100 /* Write bit patterns to various registers but do it out of */
5101 /* sync, then read back and verify values. */
5102
5103 for (i = 0 ; i < count ; i++) {
5104 write_reg(info, TMC, testval[i]);
5105 write_reg(info, IDL, testval[(i+1)%count]);
5106 write_reg(info, SA0, testval[(i+2)%count]);
5107 write_reg(info, SA1, testval[(i+3)%count]);
5108
5109 if ( (read_reg(info, TMC) != testval[i]) ||
5110 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5111 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5112 (read_reg(info, SA1) != testval[(i+3)%count]) )
5113 {
0fab6de0 5114 rc = false;
1da177e4
LT		 5115 break;
5116 }
5117 }
5118
5119 reset_port(info);
5120 spin_unlock_irqrestore(&info->lock,flags);
5121
5122 return rc;
5123}
5124
ce9f9f73 5125static bool irq_test(SLMP_INFO *info)
1da177e4
LT		 5126{
5127 unsigned long timeout;
5128 unsigned long flags;
5129
5130 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5131
5132 spin_lock_irqsave(&info->lock,flags);
5133 reset_port(info);
5134
5135 /* assume failure */
5136 info->init_error = DiagStatus_IrqFailure;
0fab6de0 5137 info->irq_occurred = false;
1da177e4
LT		 5138
5139 /* setup timer0 on SCA0 to interrupt */
5140
5141 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5142 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5143
5144 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5145 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5146
5147
5148 /* TMCS, Timer Control/Status Register
5149 *
5150 * 07 CMF, Compare match flag (read only) 1=match
5151 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5152 * 05 Reserved, must be 0
5153 * 04 TME, Timer Enable
5154 * 03..00 Reserved, must be 0
5155 *
5156 * 0101 0000
5157 */
5158 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5159
5160 spin_unlock_irqrestore(&info->lock,flags);
5161
5162 timeout=100;
5163 while( timeout-- && !info->irq_occurred ) {
5164 msleep_interruptible(10);
5165 }
5166
5167 spin_lock_irqsave(&info->lock,flags);
5168 reset_port(info);
5169 spin_unlock_irqrestore(&info->lock,flags);
5170
5171 return info->irq_occurred;
5172}
5173
5174/* initialize individual SCA device (2 ports)
5175 */
0fab6de0 5176static bool sca_init(SLMP_INFO *info)
1da177e4
LT		 5177{
5178 /* set wait controller to single mem partition (low), no wait states */
5179 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5180 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5181 write_reg(info, WCRL, 0); /* wait controller low range */
5182 write_reg(info, WCRM, 0); /* wait controller mid range */
5183 write_reg(info, WCRH, 0); /* wait controller high range */
5184
5185 /* DPCR, DMA Priority Control
5186 *
5187 * 07..05 Not used, must be 0
5188 * 04 BRC, bus release condition: 0=all transfers complete
5189 * 03 CCC, channel change condition: 0=every cycle
5190 * 02..00 PR<2..0>, priority 100=round robin
5191 *
5192 * 00000100 = 0x04
5193 */
5194 write_reg(info, DPCR, dma_priority);
5195
5196 /* DMA Master Enable, BIT7: 1=enable all channels */
5197 write_reg(info, DMER, 0x80);
5198
5199 /* enable all interrupt classes */
5200 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5201 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5202 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5203
5204 /* ITCR, interrupt control register
5205 * 07 IPC, interrupt priority, 0=MSCI->DMA
5206 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5207 * 04 VOS, Vector Output, 0=unmodified vector
5208 * 03..00 Reserved, must be 0
5209 */
5210 write_reg(info, ITCR, 0);
5211
0fab6de0 5212 return true;
1da177e4
LT		 5213}
5214
5215/* initialize adapter hardware
5216 */
ce9f9f73 5217static bool init_adapter(SLMP_INFO *info)
1da177e4
LT		 5218{
5219 int i;
5220
5221 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5222 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5223 u32 readval;
5224
5225 info->misc_ctrl_value |= BIT30;
5226 *MiscCtrl = info->misc_ctrl_value;
5227
5228 /*
5229 * Force at least 170ns delay before clearing
5230 * reset bit. Each read from LCR takes at least
5231 * 30ns so 10 times for 300ns to be safe.
5232 */
5233 for(i=0;i<10;i++)
5234 readval = *MiscCtrl;
5235
5236 info->misc_ctrl_value &= ~BIT30;
5237 *MiscCtrl = info->misc_ctrl_value;
5238
5239 /* init control reg (all DTRs off, all clksel=input) */
5240 info->ctrlreg_value = 0xaa;
5241 write_control_reg(info);
5242
5243 {
5244 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5245 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5246
5247 switch(read_ahead_count)
5248 {
5249 case 16:
5250 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5251 break;
5252 case 8:
5253 lcr1_brdr_value |= BIT5 + BIT4;
5254 break;
5255 case 4:
5256 lcr1_brdr_value |= BIT5 + BIT3;
5257 break;
5258 case 0:
5259 lcr1_brdr_value |= BIT5;
5260 break;
5261 }
5262
5263 *LCR1BRDR = lcr1_brdr_value;
5264 *MiscCtrl = misc_ctrl_value;
5265 }
5266
5267 sca_init(info->port_array[0]);
5268 sca_init(info->port_array[2]);
5269
0fab6de0 5270 return true;
1da177e4
LT		 5271}
5272
5273/* Loopback an HDLC frame to test the hardware
5274 * interrupt and DMA functions.
5275 */
ce9f9f73 5276static bool loopback_test(SLMP_INFO *info)
1da177e4
LT		 5277{
5278#define TESTFRAMESIZE 20
5279
5280 unsigned long timeout;
5281 u16 count = TESTFRAMESIZE;
5282 unsigned char buf[TESTFRAMESIZE];
0fab6de0 5283 bool rc = false;
1da177e4
LT		 5284 unsigned long flags;
5285
8fb06c77 5286 struct tty_struct *oldtty = info->port.tty;
1da177e4
LT		 5287 u32 speed = info->params.clock_speed;
5288
5289 info->params.clock_speed = 3686400;
8fb06c77 5290 info->port.tty = NULL;
1da177e4
LT		 5291
5292 /* assume failure */
5293 info->init_error = DiagStatus_DmaFailure;
5294
5295 /* build and send transmit frame */
5296 for (count = 0; count < TESTFRAMESIZE;++count)
5297 buf[count] = (unsigned char)count;
5298
5299 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5300
5301 /* program hardware for HDLC and enabled receiver */
5302 spin_lock_irqsave(&info->lock,flags);
5303 hdlc_mode(info);
5304 enable_loopback(info,1);
5305 rx_start(info);
5306 info->tx_count = count;
5307 tx_load_dma_buffer(info,buf,count);
5308 tx_start(info);
5309 spin_unlock_irqrestore(&info->lock,flags);
5310
5311 /* wait for receive complete */
5312 /* Set a timeout for waiting for interrupt. */
5313 for ( timeout = 100; timeout; --timeout ) {
5314 msleep_interruptible(10);
5315
5316 if (rx_get_frame(info)) {
0fab6de0 5317 rc = true;
1da177e4
LT		 5318 break;
5319 }
5320 }
5321
5322 /* verify received frame length and contents */
0fab6de0
JP		 5323 if (rc &&
5324 ( info->tmp_rx_buf_count != count ||
5325 memcmp(buf, info->tmp_rx_buf,count))) {
5326 rc = false;
1da177e4
LT		 5327 }
5328
5329 spin_lock_irqsave(&info->lock,flags);
5330 reset_adapter(info);
5331 spin_unlock_irqrestore(&info->lock,flags);
5332
5333 info->params.clock_speed = speed;
8fb06c77 5334 info->port.tty = oldtty;
1da177e4
LT		 5335
5336 return rc;
5337}
5338
5339/* Perform diagnostics on hardware
5340 */
ce9f9f73 5341static int adapter_test( SLMP_INFO *info )
1da177e4
LT		 5342{
5343 unsigned long flags;
5344 if ( debug_level >= DEBUG_LEVEL_INFO )
5345 printk( "%s(%d):Testing device %s\n",
5346 __FILE__,__LINE__,info->device_name );
5347
5348 spin_lock_irqsave(&info->lock,flags);
5349 init_adapter(info);
5350 spin_unlock_irqrestore(&info->lock,flags);
5351
5352 info->port_array[0]->port_count = 0;
5353
5354 if ( register_test(info->port_array[0]) &&
5355 register_test(info->port_array[1])) {
5356
5357 info->port_array[0]->port_count = 2;
5358
5359 if ( register_test(info->port_array[2]) &&
5360 register_test(info->port_array[3]) )
5361 info->port_array[0]->port_count += 2;
5362 }
5363 else {
5364 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5365 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5366 return -ENODEV;
5367 }
5368
5369 if ( !irq_test(info->port_array[0]) ||
5370 !irq_test(info->port_array[1]) ||
5371 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5372 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5373 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5374 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5375 return -ENODEV;
5376 }
5377
5378 if (!loopback_test(info->port_array[0]) ||
5379 !loopback_test(info->port_array[1]) ||
5380 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5381 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5382 printk( "%s(%d):DMA test failure for device %s\n",
5383 __FILE__,__LINE__,info->device_name);
5384 return -ENODEV;
5385 }
5386
5387 if ( debug_level >= DEBUG_LEVEL_INFO )
5388 printk( "%s(%d):device %s passed diagnostics\n",
5389 __FILE__,__LINE__,info->device_name );
5390
5391 info->port_array[0]->init_error = 0;
5392 info->port_array[1]->init_error = 0;
5393 if ( info->port_count > 2 ) {
5394 info->port_array[2]->init_error = 0;
5395 info->port_array[3]->init_error = 0;
5396 }
5397
5398 return 0;
5399}
5400
5401/* Test the shared memory on a PCI adapter.
5402 */
ce9f9f73 5403static bool memory_test(SLMP_INFO *info)
1da177e4
LT		 5404{
5405 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5406 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
fe971071 5407 unsigned long count = ARRAY_SIZE(testval);
1da177e4
LT		 5408 unsigned long i;
5409 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5410 unsigned long * addr = (unsigned long *)info->memory_base;
5411
5412 /* Test data lines with test pattern at one location. */
5413
5414 for ( i = 0 ; i < count ; i++ ) {
5415 *addr = testval[i];
5416 if ( *addr != testval[i] )
0fab6de0 5417 return false;
1da177e4
LT		 5418 }
5419
5420 /* Test address lines with incrementing pattern over */
5421 /* entire address range. */
5422
5423 for ( i = 0 ; i < limit ; i++ ) {
5424 *addr = i * 4;
5425 addr++;
5426 }
5427
5428 addr = (unsigned long *)info->memory_base;
5429
5430 for ( i = 0 ; i < limit ; i++ ) {
5431 if ( *addr != i * 4 )
0fab6de0 5432 return false;
1da177e4
LT		 5433 addr++;
5434 }
5435
5436 memset( info->memory_base, 0, SCA_MEM_SIZE );
0fab6de0 5437 return true;
1da177e4
LT		 5438}
5439
5440/* Load data into PCI adapter shared memory.
5441 *
5442 * The PCI9050 releases control of the local bus
5443 * after completing the current read or write operation.
5444 *
5445 * While the PCI9050 write FIFO not empty, the
5446 * PCI9050 treats all of the writes as a single transaction
5447 * and does not release the bus. This causes DMA latency problems
5448 * at high speeds when copying large data blocks to the shared memory.
5449 *
5450 * This function breaks a write into multiple transations by
5451 * interleaving a read which flushes the write FIFO and 'completes'
5452 * the write transation. This allows any pending DMA request to gain control
5453 * of the local bus in a timely fasion.
5454 */
ce9f9f73 5455static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
1da177e4
LT		 5456{
5457 /* A load interval of 16 allows for 4 32-bit writes at */
5458 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5459
5460 unsigned short interval = count / sca_pci_load_interval;
5461 unsigned short i;
5462
5463 for ( i = 0 ; i < interval ; i++ )
5464 {
5465 memcpy(dest, src, sca_pci_load_interval);
5466 read_status_reg(info);
5467 dest += sca_pci_load_interval;
5468 src += sca_pci_load_interval;
5469 }
5470
5471 memcpy(dest, src, count % sca_pci_load_interval);
5472}
5473
ce9f9f73 5474static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
1da177e4
LT		 5475{
5476 int i;
5477 int linecount;
5478 if (xmit)
5479 printk("%s tx data:\n",info->device_name);
5480 else
5481 printk("%s rx data:\n",info->device_name);
5482
5483 while(count) {
5484 if (count > 16)
5485 linecount = 16;
5486 else
5487 linecount = count;
5488
5489 for(i=0;i<linecount;i++)
5490 printk("%02X ",(unsigned char)data[i]);
5491 for(;i<17;i++)
5492 printk(" ");
5493 for(i=0;i<linecount;i++) {
5494 if (data[i]>=040 && data[i]<=0176)
5495 printk("%c",data[i]);
5496 else
5497 printk(".");
5498 }
5499 printk("\n");
5500
5501 data += linecount;
5502 count -= linecount;
5503 }
5504} /* end of trace_block() */
5505
5506/* called when HDLC frame times out
5507 * update stats and do tx completion processing
5508 */
ce9f9f73 5509static void tx_timeout(unsigned long context)
1da177e4
LT		 5510{
5511 SLMP_INFO *info = (SLMP_INFO*)context;
5512 unsigned long flags;
5513
5514 if ( debug_level >= DEBUG_LEVEL_INFO )
5515 printk( "%s(%d):%s tx_timeout()\n",
5516 __FILE__,__LINE__,info->device_name);
5517 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5518 info->icount.txtimeout++;
5519 }
5520 spin_lock_irqsave(&info->lock,flags);
0fab6de0 5521 info->tx_active = false;
1da177e4
LT		 5522 info->tx_count = info->tx_put = info->tx_get = 0;
5523
5524 spin_unlock_irqrestore(&info->lock,flags);
5525
af69c7f9 5526#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 5527 if (info->netcount)
5528 hdlcdev_tx_done(info);
5529 else
5530#endif
5531 bh_transmit(info);
5532}
5533
5534/* called to periodically check the DSR/RI modem signal input status
5535 */
ce9f9f73 5536static void status_timeout(unsigned long context)
1da177e4
LT		 5537{
5538 u16 status = 0;
5539 SLMP_INFO *info = (SLMP_INFO*)context;
5540 unsigned long flags;
5541 unsigned char delta;
5542
5543
5544 spin_lock_irqsave(&info->lock,flags);
5545 get_signals(info);
5546 spin_unlock_irqrestore(&info->lock,flags);
5547
5548 /* check for DSR/RI state change */
5549
5550 delta = info->old_signals ^ info->serial_signals;
5551 info->old_signals = info->serial_signals;
5552
5553 if (delta & SerialSignal_DSR)
5554 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5555
5556 if (delta & SerialSignal_RI)
5557 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5558
5559 if (delta & SerialSignal_DCD)
5560 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5561
5562 if (delta & SerialSignal_CTS)
5563 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5564
5565 if (status)
5566 isr_io_pin(info,status);
5567
40565f19 5568 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
1da177e4
LT		 5569}
5570
5571
5572/* Register Access Routines -
5573 * All registers are memory mapped
5574 */
5575#define CALC_REGADDR() \
5576 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5577 if (info->port_num > 1) \
5578 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5579 if ( info->port_num & 1) { \
5580 if (Addr > 0x7f) \
5581 RegAddr += 0x40; /* DMA access */ \
5582 else if (Addr > 0x1f && Addr < 0x60) \
5583 RegAddr += 0x20; /* MSCI access */ \
5584 }
5585
5586
ce9f9f73 5587static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
1da177e4
LT		 5588{
5589 CALC_REGADDR();
5590 return *RegAddr;
5591}
ce9f9f73 5592static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
1da177e4
LT		 5593{
5594 CALC_REGADDR();
5595 *RegAddr = Value;
5596}
5597
ce9f9f73 5598static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
1da177e4
LT		 5599{
5600 CALC_REGADDR();
5601 return *((u16 *)RegAddr);
5602}
5603
ce9f9f73 5604static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
1da177e4
LT		 5605{
5606 CALC_REGADDR();
5607 *((u16 *)RegAddr) = Value;
5608}
5609
ce9f9f73 5610static unsigned char read_status_reg(SLMP_INFO * info)
1da177e4
LT		 5611{
5612 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5613 return *RegAddr;
5614}
5615
ce9f9f73 5616static void write_control_reg(SLMP_INFO * info)
1da177e4
LT		 5617{
5618 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5619 *RegAddr = info->port_array[0]->ctrlreg_value;
5620}
5621
5622
5623static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5624 const struct pci_device_id *ent)
5625{
5626 if (pci_enable_device(dev)) {
5627 printk("error enabling pci device %p\n", dev);
5628 return -EIO;
5629 }
5630 device_init( ++synclinkmp_adapter_count, dev );
5631 return 0;
5632}
5633
5634static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5635{
5636}
Linux 6.x block layer and io_uring tree(s)