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[PATCH] kfree cleanup: drivers/mtd
[linux-block.git] / drivers / char / synclink.c
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1da177e4
LT		 1/*
2 * linux/drivers/char/synclink.c
3 *
4a918bc2 4 * $Id: synclink.c,v 4.37 2005/09/07 13:13:19 paulkf Exp $
1da177e4
LT		 5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56#if defined(__i386__)
57# define BREAKPOINT() asm(" int $3");
58#else
59# define BREAKPOINT() { }
60#endif
61
62#define MAX_ISA_DEVICES 10
63#define MAX_PCI_DEVICES 10
64#define MAX_TOTAL_DEVICES 20
65
66#include <linux/config.h>
67#include <linux/module.h>
68#include <linux/errno.h>
69#include <linux/signal.h>
70#include <linux/sched.h>
71#include <linux/timer.h>
72#include <linux/interrupt.h>
73#include <linux/pci.h>
74#include <linux/tty.h>
75#include <linux/tty_flip.h>
76#include <linux/serial.h>
77#include <linux/major.h>
78#include <linux/string.h>
79#include <linux/fcntl.h>
80#include <linux/ptrace.h>
81#include <linux/ioport.h>
82#include <linux/mm.h>
83#include <linux/slab.h>
84#include <linux/delay.h>
85
86#include <linux/netdevice.h>
87
88#include <linux/vmalloc.h>
89#include <linux/init.h>
90#include <asm/serial.h>
91
92#include <linux/delay.h>
93#include <linux/ioctl.h>
94
95#include <asm/system.h>
96#include <asm/io.h>
97#include <asm/irq.h>
98#include <asm/dma.h>
99#include <linux/bitops.h>
100#include <asm/types.h>
101#include <linux/termios.h>
102#include <linux/workqueue.h>
103#include <linux/hdlc.h>
104
105#ifdef CONFIG_HDLC_MODULE
106#define CONFIG_HDLC 1
107#endif
108
109#define GET_USER(error,value,addr) error = get_user(value,addr)
110#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
111#define PUT_USER(error,value,addr) error = put_user(value,addr)
112#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
113
114#include <asm/uaccess.h>
115
116#include "linux/synclink.h"
117
118#define RCLRVALUE 0xffff
119
120static MGSL_PARAMS default_params = {
121 MGSL_MODE_HDLC, /* unsigned long mode */
122 0, /* unsigned char loopback; */
123 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
124 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
125 0, /* unsigned long clock_speed; */
126 0xff, /* unsigned char addr_filter; */
127 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
128 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
129 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
130 9600, /* unsigned long data_rate; */
131 8, /* unsigned char data_bits; */
132 1, /* unsigned char stop_bits; */
133 ASYNC_PARITY_NONE /* unsigned char parity; */
134};
135
136#define SHARED_MEM_ADDRESS_SIZE 0x40000
137#define BUFFERLISTSIZE (PAGE_SIZE)
138#define DMABUFFERSIZE (PAGE_SIZE)
139#define MAXRXFRAMES 7
140
141typedef struct _DMABUFFERENTRY
142{
143 u32 phys_addr; /* 32-bit flat physical address of data buffer */
4a918bc2
PF		 144 volatile u16 count; /* buffer size/data count */
145 volatile u16 status; /* Control/status field */
146 volatile u16 rcc; /* character count field */
1da177e4
LT		 147 u16 reserved; /* padding required by 16C32 */
148 u32 link; /* 32-bit flat link to next buffer entry */
149 char *virt_addr; /* virtual address of data buffer */
150 u32 phys_entry; /* physical address of this buffer entry */
151} DMABUFFERENTRY, *DMAPBUFFERENTRY;
152
153/* The queue of BH actions to be performed */
154
155#define BH_RECEIVE 1
156#define BH_TRANSMIT 2
157#define BH_STATUS 4
158
159#define IO_PIN_SHUTDOWN_LIMIT 100
160
161#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
162
163struct _input_signal_events {
164 int ri_up;
165 int ri_down;
166 int dsr_up;
167 int dsr_down;
168 int dcd_up;
169 int dcd_down;
170 int cts_up;
171 int cts_down;
172};
173
174/* transmit holding buffer definitions*/
175#define MAX_TX_HOLDING_BUFFERS 5
176struct tx_holding_buffer {
177 int buffer_size;
178 unsigned char * buffer;
179};
180
181
182/*
183 * Device instance data structure
184 */
185
186struct mgsl_struct {
187 int magic;
188 int flags;
189 int count; /* count of opens */
190 int line;
191 int hw_version;
192 unsigned short close_delay;
193 unsigned short closing_wait; /* time to wait before closing */
194
195 struct mgsl_icount icount;
196
197 struct tty_struct *tty;
198 int timeout;
199 int x_char; /* xon/xoff character */
200 int blocked_open; /* # of blocked opens */
201 u16 read_status_mask;
202 u16 ignore_status_mask;
203 unsigned char *xmit_buf;
204 int xmit_head;
205 int xmit_tail;
206 int xmit_cnt;
207
208 wait_queue_head_t open_wait;
209 wait_queue_head_t close_wait;
210
211 wait_queue_head_t status_event_wait_q;
212 wait_queue_head_t event_wait_q;
213 struct timer_list tx_timer; /* HDLC transmit timeout timer */
214 struct mgsl_struct *next_device; /* device list link */
215
216 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
217 struct work_struct task; /* task structure for scheduling bh */
218
219 u32 EventMask; /* event trigger mask */
220 u32 RecordedEvents; /* pending events */
221
222 u32 max_frame_size; /* as set by device config */
223
224 u32 pending_bh;
225
226 int bh_running; /* Protection from multiple */
227 int isr_overflow;
228 int bh_requested;
229
230 int dcd_chkcount; /* check counts to prevent */
231 int cts_chkcount; /* too many IRQs if a signal */
232 int dsr_chkcount; /* is floating */
233 int ri_chkcount;
234
235 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
236 unsigned long buffer_list_phys;
237
238 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
239 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
240 unsigned int current_rx_buffer;
241
242 int num_tx_dma_buffers; /* number of tx dma frames required */
243 int tx_dma_buffers_used;
244 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
245 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
246 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
247 int current_tx_buffer; /* next tx dma buffer to be loaded */
248
249 unsigned char *intermediate_rxbuffer;
250
251 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
252 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
253 int put_tx_holding_index; /* next tx holding buffer to store user request */
254 int tx_holding_count; /* number of tx holding buffers waiting */
255 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
256
257 int rx_enabled;
258 int rx_overflow;
259 int rx_rcc_underrun;
260
261 int tx_enabled;
262 int tx_active;
263 u32 idle_mode;
264
265 u16 cmr_value;
266 u16 tcsr_value;
267
268 char device_name[25]; /* device instance name */
269
270 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
271 unsigned char bus; /* expansion bus number (zero based) */
272 unsigned char function; /* PCI device number */
273
274 unsigned int io_base; /* base I/O address of adapter */
275 unsigned int io_addr_size; /* size of the I/O address range */
276 int io_addr_requested; /* nonzero if I/O address requested */
277
278 unsigned int irq_level; /* interrupt level */
279 unsigned long irq_flags;
280 int irq_requested; /* nonzero if IRQ requested */
281
282 unsigned int dma_level; /* DMA channel */
283 int dma_requested; /* nonzero if dma channel requested */
284
285 u16 mbre_bit;
286 u16 loopback_bits;
287 u16 usc_idle_mode;
288
289 MGSL_PARAMS params; /* communications parameters */
290
291 unsigned char serial_signals; /* current serial signal states */
292
293 int irq_occurred; /* for diagnostics use */
294 unsigned int init_error; /* Initialization startup error (DIAGS) */
295 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
296
297 u32 last_mem_alloc;
298 unsigned char* memory_base; /* shared memory address (PCI only) */
299 u32 phys_memory_base;
300 int shared_mem_requested;
301
302 unsigned char* lcr_base; /* local config registers (PCI only) */
303 u32 phys_lcr_base;
304 u32 lcr_offset;
305 int lcr_mem_requested;
306
307 u32 misc_ctrl_value;
308 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
309 char char_buf[MAX_ASYNC_BUFFER_SIZE];
310 BOOLEAN drop_rts_on_tx_done;
311
312 BOOLEAN loopmode_insert_requested;
313 BOOLEAN loopmode_send_done_requested;
314
315 struct _input_signal_events input_signal_events;
316
317 /* generic HDLC device parts */
318 int netcount;
319 int dosyncppp;
320 spinlock_t netlock;
321
322#ifdef CONFIG_HDLC
323 struct net_device *netdev;
324#endif
325};
326
327#define MGSL_MAGIC 0x5401
328
329/*
330 * The size of the serial xmit buffer is 1 page, or 4096 bytes
331 */
332#ifndef SERIAL_XMIT_SIZE
333#define SERIAL_XMIT_SIZE 4096
334#endif
335
336/*
337 * These macros define the offsets used in calculating the
338 * I/O address of the specified USC registers.
339 */
340
341
342#define DCPIN 2 /* Bit 1 of I/O address */
343#define SDPIN 4 /* Bit 2 of I/O address */
344
345#define DCAR 0 /* DMA command/address register */
346#define CCAR SDPIN /* channel command/address register */
347#define DATAREG DCPIN + SDPIN /* serial data register */
348#define MSBONLY 0x41
349#define LSBONLY 0x40
350
351/*
352 * These macros define the register address (ordinal number)
353 * used for writing address/value pairs to the USC.
354 */
355
356#define CMR 0x02 /* Channel mode Register */
357#define CCSR 0x04 /* Channel Command/status Register */
358#define CCR 0x06 /* Channel Control Register */
359#define PSR 0x08 /* Port status Register */
360#define PCR 0x0a /* Port Control Register */
361#define TMDR 0x0c /* Test mode Data Register */
362#define TMCR 0x0e /* Test mode Control Register */
363#define CMCR 0x10 /* Clock mode Control Register */
364#define HCR 0x12 /* Hardware Configuration Register */
365#define IVR 0x14 /* Interrupt Vector Register */
366#define IOCR 0x16 /* Input/Output Control Register */
367#define ICR 0x18 /* Interrupt Control Register */
368#define DCCR 0x1a /* Daisy Chain Control Register */
369#define MISR 0x1c /* Misc Interrupt status Register */
370#define SICR 0x1e /* status Interrupt Control Register */
371#define RDR 0x20 /* Receive Data Register */
372#define RMR 0x22 /* Receive mode Register */
373#define RCSR 0x24 /* Receive Command/status Register */
374#define RICR 0x26 /* Receive Interrupt Control Register */
375#define RSR 0x28 /* Receive Sync Register */
376#define RCLR 0x2a /* Receive count Limit Register */
377#define RCCR 0x2c /* Receive Character count Register */
378#define TC0R 0x2e /* Time Constant 0 Register */
379#define TDR 0x30 /* Transmit Data Register */
380#define TMR 0x32 /* Transmit mode Register */
381#define TCSR 0x34 /* Transmit Command/status Register */
382#define TICR 0x36 /* Transmit Interrupt Control Register */
383#define TSR 0x38 /* Transmit Sync Register */
384#define TCLR 0x3a /* Transmit count Limit Register */
385#define TCCR 0x3c /* Transmit Character count Register */
386#define TC1R 0x3e /* Time Constant 1 Register */
387
388
389/*
390 * MACRO DEFINITIONS FOR DMA REGISTERS
391 */
392
393#define DCR 0x06 /* DMA Control Register (shared) */
394#define DACR 0x08 /* DMA Array count Register (shared) */
395#define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
396#define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
397#define DICR 0x18 /* DMA Interrupt Control Register (shared) */
398#define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
399#define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
400
401#define TDMR 0x02 /* Transmit DMA mode Register */
402#define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
403#define TBCR 0x2a /* Transmit Byte count Register */
404#define TARL 0x2c /* Transmit Address Register (low) */
405#define TARU 0x2e /* Transmit Address Register (high) */
406#define NTBCR 0x3a /* Next Transmit Byte count Register */
407#define NTARL 0x3c /* Next Transmit Address Register (low) */
408#define NTARU 0x3e /* Next Transmit Address Register (high) */
409
410#define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
411#define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
412#define RBCR 0xaa /* Receive Byte count Register */
413#define RARL 0xac /* Receive Address Register (low) */
414#define RARU 0xae /* Receive Address Register (high) */
415#define NRBCR 0xba /* Next Receive Byte count Register */
416#define NRARL 0xbc /* Next Receive Address Register (low) */
417#define NRARU 0xbe /* Next Receive Address Register (high) */
418
419
420/*
421 * MACRO DEFINITIONS FOR MODEM STATUS BITS
422 */
423
424#define MODEMSTATUS_DTR 0x80
425#define MODEMSTATUS_DSR 0x40
426#define MODEMSTATUS_RTS 0x20
427#define MODEMSTATUS_CTS 0x10
428#define MODEMSTATUS_RI 0x04
429#define MODEMSTATUS_DCD 0x01
430
431
432/*
433 * Channel Command/Address Register (CCAR) Command Codes
434 */
435
436#define RTCmd_Null 0x0000
437#define RTCmd_ResetHighestIus 0x1000
438#define RTCmd_TriggerChannelLoadDma 0x2000
439#define RTCmd_TriggerRxDma 0x2800
440#define RTCmd_TriggerTxDma 0x3000
441#define RTCmd_TriggerRxAndTxDma 0x3800
442#define RTCmd_PurgeRxFifo 0x4800
443#define RTCmd_PurgeTxFifo 0x5000
444#define RTCmd_PurgeRxAndTxFifo 0x5800
445#define RTCmd_LoadRcc 0x6800
446#define RTCmd_LoadTcc 0x7000
447#define RTCmd_LoadRccAndTcc 0x7800
448#define RTCmd_LoadTC0 0x8800
449#define RTCmd_LoadTC1 0x9000
450#define RTCmd_LoadTC0AndTC1 0x9800
451#define RTCmd_SerialDataLSBFirst 0xa000
452#define RTCmd_SerialDataMSBFirst 0xa800
453#define RTCmd_SelectBigEndian 0xb000
454#define RTCmd_SelectLittleEndian 0xb800
455
456
457/*
458 * DMA Command/Address Register (DCAR) Command Codes
459 */
460
461#define DmaCmd_Null 0x0000
462#define DmaCmd_ResetTxChannel 0x1000
463#define DmaCmd_ResetRxChannel 0x1200
464#define DmaCmd_StartTxChannel 0x2000
465#define DmaCmd_StartRxChannel 0x2200
466#define DmaCmd_ContinueTxChannel 0x3000
467#define DmaCmd_ContinueRxChannel 0x3200
468#define DmaCmd_PauseTxChannel 0x4000
469#define DmaCmd_PauseRxChannel 0x4200
470#define DmaCmd_AbortTxChannel 0x5000
471#define DmaCmd_AbortRxChannel 0x5200
472#define DmaCmd_InitTxChannel 0x7000
473#define DmaCmd_InitRxChannel 0x7200
474#define DmaCmd_ResetHighestDmaIus 0x8000
475#define DmaCmd_ResetAllChannels 0x9000
476#define DmaCmd_StartAllChannels 0xa000
477#define DmaCmd_ContinueAllChannels 0xb000
478#define DmaCmd_PauseAllChannels 0xc000
479#define DmaCmd_AbortAllChannels 0xd000
480#define DmaCmd_InitAllChannels 0xf000
481
482#define TCmd_Null 0x0000
483#define TCmd_ClearTxCRC 0x2000
484#define TCmd_SelectTicrTtsaData 0x4000
485#define TCmd_SelectTicrTxFifostatus 0x5000
486#define TCmd_SelectTicrIntLevel 0x6000
487#define TCmd_SelectTicrdma_level 0x7000
488#define TCmd_SendFrame 0x8000
489#define TCmd_SendAbort 0x9000
490#define TCmd_EnableDleInsertion 0xc000
491#define TCmd_DisableDleInsertion 0xd000
492#define TCmd_ClearEofEom 0xe000
493#define TCmd_SetEofEom 0xf000
494
495#define RCmd_Null 0x0000
496#define RCmd_ClearRxCRC 0x2000
497#define RCmd_EnterHuntmode 0x3000
498#define RCmd_SelectRicrRtsaData 0x4000
499#define RCmd_SelectRicrRxFifostatus 0x5000
500#define RCmd_SelectRicrIntLevel 0x6000
501#define RCmd_SelectRicrdma_level 0x7000
502
503/*
504 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
505 */
506
507#define RECEIVE_STATUS BIT5
508#define RECEIVE_DATA BIT4
509#define TRANSMIT_STATUS BIT3
510#define TRANSMIT_DATA BIT2
511#define IO_PIN BIT1
512#define MISC BIT0
513
514
515/*
516 * Receive status Bits in Receive Command/status Register RCSR
517 */
518
519#define RXSTATUS_SHORT_FRAME BIT8
520#define RXSTATUS_CODE_VIOLATION BIT8
521#define RXSTATUS_EXITED_HUNT BIT7
522#define RXSTATUS_IDLE_RECEIVED BIT6
523#define RXSTATUS_BREAK_RECEIVED BIT5
524#define RXSTATUS_ABORT_RECEIVED BIT5
525#define RXSTATUS_RXBOUND BIT4
526#define RXSTATUS_CRC_ERROR BIT3
527#define RXSTATUS_FRAMING_ERROR BIT3
528#define RXSTATUS_ABORT BIT2
529#define RXSTATUS_PARITY_ERROR BIT2
530#define RXSTATUS_OVERRUN BIT1
531#define RXSTATUS_DATA_AVAILABLE BIT0
532#define RXSTATUS_ALL 0x01f6
533#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
534
535/*
536 * Values for setting transmit idle mode in
537 * Transmit Control/status Register (TCSR)
538 */
539#define IDLEMODE_FLAGS 0x0000
540#define IDLEMODE_ALT_ONE_ZERO 0x0100
541#define IDLEMODE_ZERO 0x0200
542#define IDLEMODE_ONE 0x0300
543#define IDLEMODE_ALT_MARK_SPACE 0x0500
544#define IDLEMODE_SPACE 0x0600
545#define IDLEMODE_MARK 0x0700
546#define IDLEMODE_MASK 0x0700
547
548/*
549 * IUSC revision identifiers
550 */
551#define IUSC_SL1660 0x4d44
552#define IUSC_PRE_SL1660 0x4553
553
554/*
555 * Transmit status Bits in Transmit Command/status Register (TCSR)
556 */
557
558#define TCSR_PRESERVE 0x0F00
559
560#define TCSR_UNDERWAIT BIT11
561#define TXSTATUS_PREAMBLE_SENT BIT7
562#define TXSTATUS_IDLE_SENT BIT6
563#define TXSTATUS_ABORT_SENT BIT5
564#define TXSTATUS_EOF_SENT BIT4
565#define TXSTATUS_EOM_SENT BIT4
566#define TXSTATUS_CRC_SENT BIT3
567#define TXSTATUS_ALL_SENT BIT2
568#define TXSTATUS_UNDERRUN BIT1
569#define TXSTATUS_FIFO_EMPTY BIT0
570#define TXSTATUS_ALL 0x00fa
571#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
572
573
574#define MISCSTATUS_RXC_LATCHED BIT15
575#define MISCSTATUS_RXC BIT14
576#define MISCSTATUS_TXC_LATCHED BIT13
577#define MISCSTATUS_TXC BIT12
578#define MISCSTATUS_RI_LATCHED BIT11
579#define MISCSTATUS_RI BIT10
580#define MISCSTATUS_DSR_LATCHED BIT9
581#define MISCSTATUS_DSR BIT8
582#define MISCSTATUS_DCD_LATCHED BIT7
583#define MISCSTATUS_DCD BIT6
584#define MISCSTATUS_CTS_LATCHED BIT5
585#define MISCSTATUS_CTS BIT4
586#define MISCSTATUS_RCC_UNDERRUN BIT3
587#define MISCSTATUS_DPLL_NO_SYNC BIT2
588#define MISCSTATUS_BRG1_ZERO BIT1
589#define MISCSTATUS_BRG0_ZERO BIT0
590
591#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
592#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
593
594#define SICR_RXC_ACTIVE BIT15
595#define SICR_RXC_INACTIVE BIT14
596#define SICR_RXC (BIT15+BIT14)
597#define SICR_TXC_ACTIVE BIT13
598#define SICR_TXC_INACTIVE BIT12
599#define SICR_TXC (BIT13+BIT12)
600#define SICR_RI_ACTIVE BIT11
601#define SICR_RI_INACTIVE BIT10
602#define SICR_RI (BIT11+BIT10)
603#define SICR_DSR_ACTIVE BIT9
604#define SICR_DSR_INACTIVE BIT8
605#define SICR_DSR (BIT9+BIT8)
606#define SICR_DCD_ACTIVE BIT7
607#define SICR_DCD_INACTIVE BIT6
608#define SICR_DCD (BIT7+BIT6)
609#define SICR_CTS_ACTIVE BIT5
610#define SICR_CTS_INACTIVE BIT4
611#define SICR_CTS (BIT5+BIT4)
612#define SICR_RCC_UNDERFLOW BIT3
613#define SICR_DPLL_NO_SYNC BIT2
614#define SICR_BRG1_ZERO BIT1
615#define SICR_BRG0_ZERO BIT0
616
617void usc_DisableMasterIrqBit( struct mgsl_struct *info );
618void usc_EnableMasterIrqBit( struct mgsl_struct *info );
619void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
620void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
621void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
622
623#define usc_EnableInterrupts( a, b ) \
624 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
625
626#define usc_DisableInterrupts( a, b ) \
627 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
628
629#define usc_EnableMasterIrqBit(a) \
630 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
631
632#define usc_DisableMasterIrqBit(a) \
633 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
634
635#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
636
637/*
638 * Transmit status Bits in Transmit Control status Register (TCSR)
639 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
640 */
641
642#define TXSTATUS_PREAMBLE_SENT BIT7
643#define TXSTATUS_IDLE_SENT BIT6
644#define TXSTATUS_ABORT_SENT BIT5
645#define TXSTATUS_EOF BIT4
646#define TXSTATUS_CRC_SENT BIT3
647#define TXSTATUS_ALL_SENT BIT2
648#define TXSTATUS_UNDERRUN BIT1
649#define TXSTATUS_FIFO_EMPTY BIT0
650
651#define DICR_MASTER BIT15
652#define DICR_TRANSMIT BIT0
653#define DICR_RECEIVE BIT1
654
655#define usc_EnableDmaInterrupts(a,b) \
656 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
657
658#define usc_DisableDmaInterrupts(a,b) \
659 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
660
661#define usc_EnableStatusIrqs(a,b) \
662 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
663
664#define usc_DisablestatusIrqs(a,b) \
665 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
666
667/* Transmit status Bits in Transmit Control status Register (TCSR) */
668/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
669
670
671#define DISABLE_UNCONDITIONAL 0
672#define DISABLE_END_OF_FRAME 1
673#define ENABLE_UNCONDITIONAL 2
674#define ENABLE_AUTO_CTS 3
675#define ENABLE_AUTO_DCD 3
676#define usc_EnableTransmitter(a,b) \
677 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
678#define usc_EnableReceiver(a,b) \
679 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
680
681static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
682static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
683static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
684
685static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
686static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
687static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
688void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
689void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
690
691#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
692#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
693
694#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
695
696static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
697static void usc_start_receiver( struct mgsl_struct *info );
698static void usc_stop_receiver( struct mgsl_struct *info );
699
700static void usc_start_transmitter( struct mgsl_struct *info );
701static void usc_stop_transmitter( struct mgsl_struct *info );
702static void usc_set_txidle( struct mgsl_struct *info );
703static void usc_load_txfifo( struct mgsl_struct *info );
704
705static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
706static void usc_enable_loopback( struct mgsl_struct *info, int enable );
707
708static void usc_get_serial_signals( struct mgsl_struct *info );
709static void usc_set_serial_signals( struct mgsl_struct *info );
710
711static void usc_reset( struct mgsl_struct *info );
712
713static void usc_set_sync_mode( struct mgsl_struct *info );
714static void usc_set_sdlc_mode( struct mgsl_struct *info );
715static void usc_set_async_mode( struct mgsl_struct *info );
716static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
717
718static void usc_loopback_frame( struct mgsl_struct *info );
719
720static void mgsl_tx_timeout(unsigned long context);
721
722
723static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
724static void usc_loopmode_insert_request( struct mgsl_struct * info );
725static int usc_loopmode_active( struct mgsl_struct * info);
726static void usc_loopmode_send_done( struct mgsl_struct * info );
727
728static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
729
730#ifdef CONFIG_HDLC
731#define dev_to_port(D) (dev_to_hdlc(D)->priv)
732static void hdlcdev_tx_done(struct mgsl_struct *info);
733static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
734static int hdlcdev_init(struct mgsl_struct *info);
735static void hdlcdev_exit(struct mgsl_struct *info);
736#endif
737
738/*
739 * Defines a BUS descriptor value for the PCI adapter
740 * local bus address ranges.
741 */
742
743#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
744(0x00400020 + \
745((WrHold) << 30) + \
746((WrDly) << 28) + \
747((RdDly) << 26) + \
748((Nwdd) << 20) + \
749((Nwad) << 15) + \
750((Nxda) << 13) + \
751((Nrdd) << 11) + \
752((Nrad) << 6) )
753
754static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
755
756/*
757 * Adapter diagnostic routines
758 */
759static BOOLEAN mgsl_register_test( struct mgsl_struct *info );
760static BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
761static BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
762static BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
763static int mgsl_adapter_test( struct mgsl_struct *info );
764
765/*
766 * device and resource management routines
767 */
768static int mgsl_claim_resources(struct mgsl_struct *info);
769static void mgsl_release_resources(struct mgsl_struct *info);
770static void mgsl_add_device(struct mgsl_struct *info);
771static struct mgsl_struct* mgsl_allocate_device(void);
772
773/*
774 * DMA buffer manupulation functions.
775 */
776static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
777static int mgsl_get_rx_frame( struct mgsl_struct *info );
778static int mgsl_get_raw_rx_frame( struct mgsl_struct *info );
779static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
780static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
781static int num_free_tx_dma_buffers(struct mgsl_struct *info);
782static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
783static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
784
785/*
786 * DMA and Shared Memory buffer allocation and formatting
787 */
788static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
789static void mgsl_free_dma_buffers(struct mgsl_struct *info);
790static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
791static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
792static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
793static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
794static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
795static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
796static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
797static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
798static int load_next_tx_holding_buffer(struct mgsl_struct *info);
799static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
800
801/*
802 * Bottom half interrupt handlers
803 */
804static void mgsl_bh_handler(void* Context);
805static void mgsl_bh_receive(struct mgsl_struct *info);
806static void mgsl_bh_transmit(struct mgsl_struct *info);
807static void mgsl_bh_status(struct mgsl_struct *info);
808
809/*
810 * Interrupt handler routines and dispatch table.
811 */
812static void mgsl_isr_null( struct mgsl_struct *info );
813static void mgsl_isr_transmit_data( struct mgsl_struct *info );
814static void mgsl_isr_receive_data( struct mgsl_struct *info );
815static void mgsl_isr_receive_status( struct mgsl_struct *info );
816static void mgsl_isr_transmit_status( struct mgsl_struct *info );
817static void mgsl_isr_io_pin( struct mgsl_struct *info );
818static void mgsl_isr_misc( struct mgsl_struct *info );
819static void mgsl_isr_receive_dma( struct mgsl_struct *info );
820static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
821
822typedef void (*isr_dispatch_func)(struct mgsl_struct *);
823
824static isr_dispatch_func UscIsrTable[7] =
825{
826 mgsl_isr_null,
827 mgsl_isr_misc,
828 mgsl_isr_io_pin,
829 mgsl_isr_transmit_data,
830 mgsl_isr_transmit_status,
831 mgsl_isr_receive_data,
832 mgsl_isr_receive_status
833};
834
835/*
836 * ioctl call handlers
837 */
838static int tiocmget(struct tty_struct *tty, struct file *file);
839static int tiocmset(struct tty_struct *tty, struct file *file,
840 unsigned int set, unsigned int clear);
841static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
842 __user *user_icount);
843static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
844static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
845static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
846static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
847static int mgsl_txenable(struct mgsl_struct * info, int enable);
848static int mgsl_txabort(struct mgsl_struct * info);
849static int mgsl_rxenable(struct mgsl_struct * info, int enable);
850static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
851static int mgsl_loopmode_send_done( struct mgsl_struct * info );
852
853/* set non-zero on successful registration with PCI subsystem */
854static int pci_registered;
855
856/*
857 * Global linked list of SyncLink devices
858 */
859static struct mgsl_struct *mgsl_device_list;
860static int mgsl_device_count;
861
862/*
863 * Set this param to non-zero to load eax with the
864 * .text section address and breakpoint on module load.
865 * This is useful for use with gdb and add-symbol-file command.
866 */
867static int break_on_load;
868
869/*
870 * Driver major number, defaults to zero to get auto
871 * assigned major number. May be forced as module parameter.
872 */
873static int ttymajor;
874
875/*
876 * Array of user specified options for ISA adapters.
877 */
878static int io[MAX_ISA_DEVICES];
879static int irq[MAX_ISA_DEVICES];
880static int dma[MAX_ISA_DEVICES];
881static int debug_level;
882static int maxframe[MAX_TOTAL_DEVICES];
883static int dosyncppp[MAX_TOTAL_DEVICES];
884static int txdmabufs[MAX_TOTAL_DEVICES];
885static int txholdbufs[MAX_TOTAL_DEVICES];
886
887module_param(break_on_load, bool, 0);
888module_param(ttymajor, int, 0);
889module_param_array(io, int, NULL, 0);
890module_param_array(irq, int, NULL, 0);
891module_param_array(dma, int, NULL, 0);
892module_param(debug_level, int, 0);
893module_param_array(maxframe, int, NULL, 0);
894module_param_array(dosyncppp, int, NULL, 0);
895module_param_array(txdmabufs, int, NULL, 0);
896module_param_array(txholdbufs, int, NULL, 0);
897
898static char *driver_name = "SyncLink serial driver";
4a918bc2 899static char *driver_version = "$Revision: 4.37 $";
1da177e4
LT		 900
901static int synclink_init_one (struct pci_dev *dev,
902 const struct pci_device_id *ent);
903static void synclink_remove_one (struct pci_dev *dev);
904
905static struct pci_device_id synclink_pci_tbl[] = {
906 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
907 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
908 { 0, }, /* terminate list */
909};
910MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
911
912MODULE_LICENSE("GPL");
913
914static struct pci_driver synclink_pci_driver = {
413a42e2 915 .owner = THIS_MODULE,
1da177e4
LT		 916 .name = "synclink",
917 .id_table = synclink_pci_tbl,
918 .probe = synclink_init_one,
919 .remove = __devexit_p(synclink_remove_one),
920};
921
922static struct tty_driver *serial_driver;
923
924/* number of characters left in xmit buffer before we ask for more */
925#define WAKEUP_CHARS 256
926
927
928static void mgsl_change_params(struct mgsl_struct *info);
929static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
930
931/*
932 * 1st function defined in .text section. Calling this function in
933 * init_module() followed by a breakpoint allows a remote debugger
934 * (gdb) to get the .text address for the add-symbol-file command.
935 * This allows remote debugging of dynamically loadable modules.
936 */
937static void* mgsl_get_text_ptr(void)
938{
939 return mgsl_get_text_ptr;
940}
941
942/*
943 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
944 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
945 * and some other program tries to do a serial write at the same time.
946 * Since the lock will only come under contention when the system is
947 * swapping and available memory is low, it makes sense to share one
948 * buffer across all the serial ioports, since it significantly saves
949 * memory if large numbers of serial ports are open.
950 */
951static unsigned char *tmp_buf;
952static DECLARE_MUTEX(tmp_buf_sem);
953
954static inline int mgsl_paranoia_check(struct mgsl_struct *info,
955 char *name, const char *routine)
956{
957#ifdef MGSL_PARANOIA_CHECK
958 static const char *badmagic =
959 "Warning: bad magic number for mgsl struct (%s) in %s\n";
960 static const char *badinfo =
961 "Warning: null mgsl_struct for (%s) in %s\n";
962
963 if (!info) {
964 printk(badinfo, name, routine);
965 return 1;
966 }
967 if (info->magic != MGSL_MAGIC) {
968 printk(badmagic, name, routine);
969 return 1;
970 }
971#else
972 if (!info)
973 return 1;
974#endif
975 return 0;
976}
977
978/**
979 * line discipline callback wrappers
980 *
981 * The wrappers maintain line discipline references
982 * while calling into the line discipline.
983 *
984 * ldisc_receive_buf - pass receive data to line discipline
985 */
986
987static void ldisc_receive_buf(struct tty_struct *tty,
988 const __u8 *data, char *flags, int count)
989{
990 struct tty_ldisc *ld;
991 if (!tty)
992 return;
993 ld = tty_ldisc_ref(tty);
994 if (ld) {
995 if (ld->receive_buf)
996 ld->receive_buf(tty, data, flags, count);
997 tty_ldisc_deref(ld);
998 }
999}
1000
1001/* mgsl_stop() throttle (stop) transmitter
1002 *
1003 * Arguments: tty pointer to tty info structure
1004 * Return Value: None
1005 */
1006static void mgsl_stop(struct tty_struct *tty)
1007{
1008 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1009 unsigned long flags;
1010
1011 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
1012 return;
1013
1014 if ( debug_level >= DEBUG_LEVEL_INFO )
1015 printk("mgsl_stop(%s)\n",info->device_name);
1016
1017 spin_lock_irqsave(&info->irq_spinlock,flags);
1018 if (info->tx_enabled)
1019 usc_stop_transmitter(info);
1020 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1021
1022} /* end of mgsl_stop() */
1023
1024/* mgsl_start() release (start) transmitter
1025 *
1026 * Arguments: tty pointer to tty info structure
1027 * Return Value: None
1028 */
1029static void mgsl_start(struct tty_struct *tty)
1030{
1031 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1032 unsigned long flags;
1033
1034 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1035 return;
1036
1037 if ( debug_level >= DEBUG_LEVEL_INFO )
1038 printk("mgsl_start(%s)\n",info->device_name);
1039
1040 spin_lock_irqsave(&info->irq_spinlock,flags);
1041 if (!info->tx_enabled)
1042 usc_start_transmitter(info);
1043 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1044
1045} /* end of mgsl_start() */
1046
1047/*
1048 * Bottom half work queue access functions
1049 */
1050
1051/* mgsl_bh_action() Return next bottom half action to perform.
1052 * Return Value: BH action code or 0 if nothing to do.
1053 */
1054static int mgsl_bh_action(struct mgsl_struct *info)
1055{
1056 unsigned long flags;
1057 int rc = 0;
1058
1059 spin_lock_irqsave(&info->irq_spinlock,flags);
1060
1061 if (info->pending_bh & BH_RECEIVE) {
1062 info->pending_bh &= ~BH_RECEIVE;
1063 rc = BH_RECEIVE;
1064 } else if (info->pending_bh & BH_TRANSMIT) {
1065 info->pending_bh &= ~BH_TRANSMIT;
1066 rc = BH_TRANSMIT;
1067 } else if (info->pending_bh & BH_STATUS) {
1068 info->pending_bh &= ~BH_STATUS;
1069 rc = BH_STATUS;
1070 }
1071
1072 if (!rc) {
1073 /* Mark BH routine as complete */
1074 info->bh_running = 0;
1075 info->bh_requested = 0;
1076 }
1077
1078 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1079
1080 return rc;
1081}
1082
1083/*
1084 * Perform bottom half processing of work items queued by ISR.
1085 */
1086static void mgsl_bh_handler(void* Context)
1087{
1088 struct mgsl_struct *info = (struct mgsl_struct*)Context;
1089 int action;
1090
1091 if (!info)
1092 return;
1093
1094 if ( debug_level >= DEBUG_LEVEL_BH )
1095 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1096 __FILE__,__LINE__,info->device_name);
1097
1098 info->bh_running = 1;
1099
1100 while((action = mgsl_bh_action(info)) != 0) {
1101
1102 /* Process work item */
1103 if ( debug_level >= DEBUG_LEVEL_BH )
1104 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1105 __FILE__,__LINE__,action);
1106
1107 switch (action) {
1108
1109 case BH_RECEIVE:
1110 mgsl_bh_receive(info);
1111 break;
1112 case BH_TRANSMIT:
1113 mgsl_bh_transmit(info);
1114 break;
1115 case BH_STATUS:
1116 mgsl_bh_status(info);
1117 break;
1118 default:
1119 /* unknown work item ID */
1120 printk("Unknown work item ID=%08X!\n", action);
1121 break;
1122 }
1123 }
1124
1125 if ( debug_level >= DEBUG_LEVEL_BH )
1126 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1127 __FILE__,__LINE__,info->device_name);
1128}
1129
1130static void mgsl_bh_receive(struct mgsl_struct *info)
1131{
1132 int (*get_rx_frame)(struct mgsl_struct *info) =
1133 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1134
1135 if ( debug_level >= DEBUG_LEVEL_BH )
1136 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1137 __FILE__,__LINE__,info->device_name);
1138
1139 do
1140 {
1141 if (info->rx_rcc_underrun) {
1142 unsigned long flags;
1143 spin_lock_irqsave(&info->irq_spinlock,flags);
1144 usc_start_receiver(info);
1145 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1146 return;
1147 }
1148 } while(get_rx_frame(info));
1149}
1150
1151static void mgsl_bh_transmit(struct mgsl_struct *info)
1152{
1153 struct tty_struct *tty = info->tty;
1154 unsigned long flags;
1155
1156 if ( debug_level >= DEBUG_LEVEL_BH )
1157 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1158 __FILE__,__LINE__,info->device_name);
1159
1160 if (tty) {
1161 tty_wakeup(tty);
1162 wake_up_interruptible(&tty->write_wait);
1163 }
1164
1165 /* if transmitter idle and loopmode_send_done_requested
1166 * then start echoing RxD to TxD
1167 */
1168 spin_lock_irqsave(&info->irq_spinlock,flags);
1169 if ( !info->tx_active && info->loopmode_send_done_requested )
1170 usc_loopmode_send_done( info );
1171 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1172}
1173
1174static void mgsl_bh_status(struct mgsl_struct *info)
1175{
1176 if ( debug_level >= DEBUG_LEVEL_BH )
1177 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1178 __FILE__,__LINE__,info->device_name);
1179
1180 info->ri_chkcount = 0;
1181 info->dsr_chkcount = 0;
1182 info->dcd_chkcount = 0;
1183 info->cts_chkcount = 0;
1184}
1185
1186/* mgsl_isr_receive_status()
1187 *
1188 * Service a receive status interrupt. The type of status
1189 * interrupt is indicated by the state of the RCSR.
1190 * This is only used for HDLC mode.
1191 *
1192 * Arguments: info pointer to device instance data
1193 * Return Value: None
1194 */
1195static void mgsl_isr_receive_status( struct mgsl_struct *info )
1196{
1197 u16 status = usc_InReg( info, RCSR );
1198
1199 if ( debug_level >= DEBUG_LEVEL_ISR )
1200 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1201 __FILE__,__LINE__,status);
1202
1203 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1204 info->loopmode_insert_requested &&
1205 usc_loopmode_active(info) )
1206 {
1207 ++info->icount.rxabort;
1208 info->loopmode_insert_requested = FALSE;
1209
1210 /* clear CMR:13 to start echoing RxD to TxD */
1211 info->cmr_value &= ~BIT13;
1212 usc_OutReg(info, CMR, info->cmr_value);
1213
1214 /* disable received abort irq (no longer required) */
1215 usc_OutReg(info, RICR,
1216 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1217 }
1218
1219 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1220 if (status & RXSTATUS_EXITED_HUNT)
1221 info->icount.exithunt++;
1222 if (status & RXSTATUS_IDLE_RECEIVED)
1223 info->icount.rxidle++;
1224 wake_up_interruptible(&info->event_wait_q);
1225 }
1226
1227 if (status & RXSTATUS_OVERRUN){
1228 info->icount.rxover++;
1229 usc_process_rxoverrun_sync( info );
1230 }
1231
1232 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1233 usc_UnlatchRxstatusBits( info, status );
1234
1235} /* end of mgsl_isr_receive_status() */
1236
1237/* mgsl_isr_transmit_status()
1238 *
1239 * Service a transmit status interrupt
1240 * HDLC mode :end of transmit frame
1241 * Async mode:all data is sent
1242 * transmit status is indicated by bits in the TCSR.
1243 *
1244 * Arguments: info pointer to device instance data
1245 * Return Value: None
1246 */
1247static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1248{
1249 u16 status = usc_InReg( info, TCSR );
1250
1251 if ( debug_level >= DEBUG_LEVEL_ISR )
1252 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1253 __FILE__,__LINE__,status);
1254
1255 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1256 usc_UnlatchTxstatusBits( info, status );
1257
1258 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1259 {
1260 /* finished sending HDLC abort. This may leave */
1261 /* the TxFifo with data from the aborted frame */
1262 /* so purge the TxFifo. Also shutdown the DMA */
1263 /* channel in case there is data remaining in */
1264 /* the DMA buffer */
1265 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1266 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1267 }
1268
1269 if ( status & TXSTATUS_EOF_SENT )
1270 info->icount.txok++;
1271 else if ( status & TXSTATUS_UNDERRUN )
1272 info->icount.txunder++;
1273 else if ( status & TXSTATUS_ABORT_SENT )
1274 info->icount.txabort++;
1275 else
1276 info->icount.txunder++;
1277
1278 info->tx_active = 0;
1279 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1280 del_timer(&info->tx_timer);
1281
1282 if ( info->drop_rts_on_tx_done ) {
1283 usc_get_serial_signals( info );
1284 if ( info->serial_signals & SerialSignal_RTS ) {
1285 info->serial_signals &= ~SerialSignal_RTS;
1286 usc_set_serial_signals( info );
1287 }
1288 info->drop_rts_on_tx_done = 0;
1289 }
1290
1291#ifdef CONFIG_HDLC
1292 if (info->netcount)
1293 hdlcdev_tx_done(info);
1294 else
1295#endif
1296 {
1297 if (info->tty->stopped || info->tty->hw_stopped) {
1298 usc_stop_transmitter(info);
1299 return;
1300 }
1301 info->pending_bh |= BH_TRANSMIT;
1302 }
1303
1304} /* end of mgsl_isr_transmit_status() */
1305
1306/* mgsl_isr_io_pin()
1307 *
1308 * Service an Input/Output pin interrupt. The type of
1309 * interrupt is indicated by bits in the MISR
1310 *
1311 * Arguments: info pointer to device instance data
1312 * Return Value: None
1313 */
1314static void mgsl_isr_io_pin( struct mgsl_struct *info )
1315{
1316 struct mgsl_icount *icount;
1317 u16 status = usc_InReg( info, MISR );
1318
1319 if ( debug_level >= DEBUG_LEVEL_ISR )
1320 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1321 __FILE__,__LINE__,status);
1322
1323 usc_ClearIrqPendingBits( info, IO_PIN );
1324 usc_UnlatchIostatusBits( info, status );
1325
1326 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1327 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1328 icount = &info->icount;
1329 /* update input line counters */
1330 if (status & MISCSTATUS_RI_LATCHED) {
1331 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1332 usc_DisablestatusIrqs(info,SICR_RI);
1333 icount->rng++;
1334 if ( status & MISCSTATUS_RI )
1335 info->input_signal_events.ri_up++;
1336 else
1337 info->input_signal_events.ri_down++;
1338 }
1339 if (status & MISCSTATUS_DSR_LATCHED) {
1340 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1341 usc_DisablestatusIrqs(info,SICR_DSR);
1342 icount->dsr++;
1343 if ( status & MISCSTATUS_DSR )
1344 info->input_signal_events.dsr_up++;
1345 else
1346 info->input_signal_events.dsr_down++;
1347 }
1348 if (status & MISCSTATUS_DCD_LATCHED) {
1349 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1350 usc_DisablestatusIrqs(info,SICR_DCD);
1351 icount->dcd++;
1352 if (status & MISCSTATUS_DCD) {
1353 info->input_signal_events.dcd_up++;
1354 } else
1355 info->input_signal_events.dcd_down++;
1356#ifdef CONFIG_HDLC
1357 if (info->netcount)
1358 hdlc_set_carrier(status & MISCSTATUS_DCD, info->netdev);
1359#endif
1360 }
1361 if (status & MISCSTATUS_CTS_LATCHED)
1362 {
1363 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1364 usc_DisablestatusIrqs(info,SICR_CTS);
1365 icount->cts++;
1366 if ( status & MISCSTATUS_CTS )
1367 info->input_signal_events.cts_up++;
1368 else
1369 info->input_signal_events.cts_down++;
1370 }
1371 wake_up_interruptible(&info->status_event_wait_q);
1372 wake_up_interruptible(&info->event_wait_q);
1373
1374 if ( (info->flags & ASYNC_CHECK_CD) &&
1375 (status & MISCSTATUS_DCD_LATCHED) ) {
1376 if ( debug_level >= DEBUG_LEVEL_ISR )
1377 printk("%s CD now %s...", info->device_name,
1378 (status & MISCSTATUS_DCD) ? "on" : "off");
1379 if (status & MISCSTATUS_DCD)
1380 wake_up_interruptible(&info->open_wait);
1381 else {
1382 if ( debug_level >= DEBUG_LEVEL_ISR )
1383 printk("doing serial hangup...");
1384 if (info->tty)
1385 tty_hangup(info->tty);
1386 }
1387 }
1388
1389 if ( (info->flags & ASYNC_CTS_FLOW) &&
1390 (status & MISCSTATUS_CTS_LATCHED) ) {
1391 if (info->tty->hw_stopped) {
1392 if (status & MISCSTATUS_CTS) {
1393 if ( debug_level >= DEBUG_LEVEL_ISR )
1394 printk("CTS tx start...");
1395 if (info->tty)
1396 info->tty->hw_stopped = 0;
1397 usc_start_transmitter(info);
1398 info->pending_bh |= BH_TRANSMIT;
1399 return;
1400 }
1401 } else {
1402 if (!(status & MISCSTATUS_CTS)) {
1403 if ( debug_level >= DEBUG_LEVEL_ISR )
1404 printk("CTS tx stop...");
1405 if (info->tty)
1406 info->tty->hw_stopped = 1;
1407 usc_stop_transmitter(info);
1408 }
1409 }
1410 }
1411 }
1412
1413 info->pending_bh |= BH_STATUS;
1414
1415 /* for diagnostics set IRQ flag */
1416 if ( status & MISCSTATUS_TXC_LATCHED ){
1417 usc_OutReg( info, SICR,
1418 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1419 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1420 info->irq_occurred = 1;
1421 }
1422
1423} /* end of mgsl_isr_io_pin() */
1424
1425/* mgsl_isr_transmit_data()
1426 *
1427 * Service a transmit data interrupt (async mode only).
1428 *
1429 * Arguments: info pointer to device instance data
1430 * Return Value: None
1431 */
1432static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1433{
1434 if ( debug_level >= DEBUG_LEVEL_ISR )
1435 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1436 __FILE__,__LINE__,info->xmit_cnt);
1437
1438 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1439
1440 if (info->tty->stopped || info->tty->hw_stopped) {
1441 usc_stop_transmitter(info);
1442 return;
1443 }
1444
1445 if ( info->xmit_cnt )
1446 usc_load_txfifo( info );
1447 else
1448 info->tx_active = 0;
1449
1450 if (info->xmit_cnt < WAKEUP_CHARS)
1451 info->pending_bh |= BH_TRANSMIT;
1452
1453} /* end of mgsl_isr_transmit_data() */
1454
1455/* mgsl_isr_receive_data()
1456 *
1457 * Service a receive data interrupt. This occurs
1458 * when operating in asynchronous interrupt transfer mode.
1459 * The receive data FIFO is flushed to the receive data buffers.
1460 *
1461 * Arguments: info pointer to device instance data
1462 * Return Value: None
1463 */
1464static void mgsl_isr_receive_data( struct mgsl_struct *info )
1465{
1466 int Fifocount;
1467 u16 status;
1468 unsigned char DataByte;
1469 struct tty_struct *tty = info->tty;
1470 struct mgsl_icount *icount = &info->icount;
1471
1472 if ( debug_level >= DEBUG_LEVEL_ISR )
1473 printk("%s(%d):mgsl_isr_receive_data\n",
1474 __FILE__,__LINE__);
1475
1476 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1477
1478 /* select FIFO status for RICR readback */
1479 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1480
1481 /* clear the Wordstatus bit so that status readback */
1482 /* only reflects the status of this byte */
1483 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1484
1485 /* flush the receive FIFO */
1486
1487 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1488 /* read one byte from RxFIFO */
1489 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1490 info->io_base + CCAR );
1491 DataByte = inb( info->io_base + CCAR );
1492
1493 /* get the status of the received byte */
1494 status = usc_InReg(info, RCSR);
1495 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1496 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1497 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1498
1499 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1500 continue;
1501
1502 *tty->flip.char_buf_ptr = DataByte;
1503 icount->rx++;
1504
1505 *tty->flip.flag_buf_ptr = 0;
1506 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1507 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1508 printk("rxerr=%04X\n",status);
1509 /* update error statistics */
1510 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1511 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1512 icount->brk++;
1513 } else if (status & RXSTATUS_PARITY_ERROR)
1514 icount->parity++;
1515 else if (status & RXSTATUS_FRAMING_ERROR)
1516 icount->frame++;
1517 else if (status & RXSTATUS_OVERRUN) {
1518 /* must issue purge fifo cmd before */
1519 /* 16C32 accepts more receive chars */
1520 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1521 icount->overrun++;
1522 }
1523
1524 /* discard char if tty control flags say so */
1525 if (status & info->ignore_status_mask)
1526 continue;
1527
1528 status &= info->read_status_mask;
1529
1530 if (status & RXSTATUS_BREAK_RECEIVED) {
1531 *tty->flip.flag_buf_ptr = TTY_BREAK;
1532 if (info->flags & ASYNC_SAK)
1533 do_SAK(tty);
1534 } else if (status & RXSTATUS_PARITY_ERROR)
1535 *tty->flip.flag_buf_ptr = TTY_PARITY;
1536 else if (status & RXSTATUS_FRAMING_ERROR)
1537 *tty->flip.flag_buf_ptr = TTY_FRAME;
1538 if (status & RXSTATUS_OVERRUN) {
1539 /* Overrun is special, since it's
1540 * reported immediately, and doesn't
1541 * affect the current character
1542 */
1543 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
1544 tty->flip.count++;
1545 tty->flip.flag_buf_ptr++;
1546 tty->flip.char_buf_ptr++;
1547 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
1548 }
1549 }
1550 } /* end of if (error) */
1551
1552 tty->flip.flag_buf_ptr++;
1553 tty->flip.char_buf_ptr++;
1554 tty->flip.count++;
1555 }
1556
1557 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1558 printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1559 __FILE__,__LINE__,tty->flip.count);
1560 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1561 __FILE__,__LINE__,icount->rx,icount->brk,
1562 icount->parity,icount->frame,icount->overrun);
1563 }
1564
1565 if ( tty->flip.count )
1566 tty_flip_buffer_push(tty);
1567}
1568
1569/* mgsl_isr_misc()
1570 *
1571 * Service a miscellaneos interrupt source.
1572 *
1573 * Arguments: info pointer to device extension (instance data)
1574 * Return Value: None
1575 */
1576static void mgsl_isr_misc( struct mgsl_struct *info )
1577{
1578 u16 status = usc_InReg( info, MISR );
1579
1580 if ( debug_level >= DEBUG_LEVEL_ISR )
1581 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1582 __FILE__,__LINE__,status);
1583
1584 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1585 (info->params.mode == MGSL_MODE_HDLC)) {
1586
1587 /* turn off receiver and rx DMA */
1588 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1589 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1590 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1591 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1592 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1593
1594 /* schedule BH handler to restart receiver */
1595 info->pending_bh |= BH_RECEIVE;
1596 info->rx_rcc_underrun = 1;
1597 }
1598
1599 usc_ClearIrqPendingBits( info, MISC );
1600 usc_UnlatchMiscstatusBits( info, status );
1601
1602} /* end of mgsl_isr_misc() */
1603
1604/* mgsl_isr_null()
1605 *
1606 * Services undefined interrupt vectors from the
1607 * USC. (hence this function SHOULD never be called)
1608 *
1609 * Arguments: info pointer to device extension (instance data)
1610 * Return Value: None
1611 */
1612static void mgsl_isr_null( struct mgsl_struct *info )
1613{
1614
1615} /* end of mgsl_isr_null() */
1616
1617/* mgsl_isr_receive_dma()
1618 *
1619 * Service a receive DMA channel interrupt.
1620 * For this driver there are two sources of receive DMA interrupts
1621 * as identified in the Receive DMA mode Register (RDMR):
1622 *
1623 * BIT3 EOA/EOL End of List, all receive buffers in receive
1624 * buffer list have been filled (no more free buffers
1625 * available). The DMA controller has shut down.
1626 *
1627 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1628 * DMA buffer is terminated in response to completion
1629 * of a good frame or a frame with errors. The status
1630 * of the frame is stored in the buffer entry in the
1631 * list of receive buffer entries.
1632 *
1633 * Arguments: info pointer to device instance data
1634 * Return Value: None
1635 */
1636static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1637{
1638 u16 status;
1639
1640 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1641 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1642
1643 /* Read the receive DMA status to identify interrupt type. */
1644 /* This also clears the status bits. */
1645 status = usc_InDmaReg( info, RDMR );
1646
1647 if ( debug_level >= DEBUG_LEVEL_ISR )
1648 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1649 __FILE__,__LINE__,info->device_name,status);
1650
1651 info->pending_bh |= BH_RECEIVE;
1652
1653 if ( status & BIT3 ) {
1654 info->rx_overflow = 1;
1655 info->icount.buf_overrun++;
1656 }
1657
1658} /* end of mgsl_isr_receive_dma() */
1659
1660/* mgsl_isr_transmit_dma()
1661 *
1662 * This function services a transmit DMA channel interrupt.
1663 *
1664 * For this driver there is one source of transmit DMA interrupts
1665 * as identified in the Transmit DMA Mode Register (TDMR):
1666 *
1667 * BIT2 EOB End of Buffer. This interrupt occurs when a
1668 * transmit DMA buffer has been emptied.
1669 *
1670 * The driver maintains enough transmit DMA buffers to hold at least
1671 * one max frame size transmit frame. When operating in a buffered
1672 * transmit mode, there may be enough transmit DMA buffers to hold at
1673 * least two or more max frame size frames. On an EOB condition,
1674 * determine if there are any queued transmit buffers and copy into
1675 * transmit DMA buffers if we have room.
1676 *
1677 * Arguments: info pointer to device instance data
1678 * Return Value: None
1679 */
1680static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1681{
1682 u16 status;
1683
1684 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1685 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1686
1687 /* Read the transmit DMA status to identify interrupt type. */
1688 /* This also clears the status bits. */
1689
1690 status = usc_InDmaReg( info, TDMR );
1691
1692 if ( debug_level >= DEBUG_LEVEL_ISR )
1693 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1694 __FILE__,__LINE__,info->device_name,status);
1695
1696 if ( status & BIT2 ) {
1697 --info->tx_dma_buffers_used;
1698
1699 /* if there are transmit frames queued,
1700 * try to load the next one
1701 */
1702 if ( load_next_tx_holding_buffer(info) ) {
1703 /* if call returns non-zero value, we have
1704 * at least one free tx holding buffer
1705 */
1706 info->pending_bh |= BH_TRANSMIT;
1707 }
1708 }
1709
1710} /* end of mgsl_isr_transmit_dma() */
1711
1712/* mgsl_interrupt()
1713 *
1714 * Interrupt service routine entry point.
1715 *
1716 * Arguments:
1717 *
1718 * irq interrupt number that caused interrupt
1719 * dev_id device ID supplied during interrupt registration
1720 * regs interrupted processor context
1721 *
1722 * Return Value: None
1723 */
1724static irqreturn_t mgsl_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1725{
1726 struct mgsl_struct * info;
1727 u16 UscVector;
1728 u16 DmaVector;
1729
1730 if ( debug_level >= DEBUG_LEVEL_ISR )
1731 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1732 __FILE__,__LINE__,irq);
1733
1734 info = (struct mgsl_struct *)dev_id;
1735 if (!info)
1736 return IRQ_NONE;
1737
1738 spin_lock(&info->irq_spinlock);
1739
1740 for(;;) {
1741 /* Read the interrupt vectors from hardware. */
1742 UscVector = usc_InReg(info, IVR) >> 9;
1743 DmaVector = usc_InDmaReg(info, DIVR);
1744
1745 if ( debug_level >= DEBUG_LEVEL_ISR )
1746 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1747 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1748
1749 if ( !UscVector && !DmaVector )
1750 break;
1751
1752 /* Dispatch interrupt vector */
1753 if ( UscVector )
1754 (*UscIsrTable[UscVector])(info);
1755 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1756 mgsl_isr_transmit_dma(info);
1757 else
1758 mgsl_isr_receive_dma(info);
1759
1760 if ( info->isr_overflow ) {
1761 printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
1762 __FILE__,__LINE__,info->device_name, irq);
1763 usc_DisableMasterIrqBit(info);
1764 usc_DisableDmaInterrupts(info,DICR_MASTER);
1765 break;
1766 }
1767 }
1768
1769 /* Request bottom half processing if there's something
1770 * for it to do and the bh is not already running
1771 */
1772
1773 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1774 if ( debug_level >= DEBUG_LEVEL_ISR )
1775 printk("%s(%d):%s queueing bh task.\n",
1776 __FILE__,__LINE__,info->device_name);
1777 schedule_work(&info->task);
1778 info->bh_requested = 1;
1779 }
1780
1781 spin_unlock(&info->irq_spinlock);
1782
1783 if ( debug_level >= DEBUG_LEVEL_ISR )
1784 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1785 __FILE__,__LINE__,irq);
1786 return IRQ_HANDLED;
1787} /* end of mgsl_interrupt() */
1788
1789/* startup()
1790 *
1791 * Initialize and start device.
1792 *
1793 * Arguments: info pointer to device instance data
1794 * Return Value: 0 if success, otherwise error code
1795 */
1796static int startup(struct mgsl_struct * info)
1797{
1798 int retval = 0;
1799
1800 if ( debug_level >= DEBUG_LEVEL_INFO )
1801 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1802
1803 if (info->flags & ASYNC_INITIALIZED)
1804 return 0;
1805
1806 if (!info->xmit_buf) {
1807 /* allocate a page of memory for a transmit buffer */
1808 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1809 if (!info->xmit_buf) {
1810 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1811 __FILE__,__LINE__,info->device_name);
1812 return -ENOMEM;
1813 }
1814 }
1815
1816 info->pending_bh = 0;
1817
9661239f
PF		 1818 memset(&info->icount, 0, sizeof(info->icount));
1819
1da177e4
LT		 1820 init_timer(&info->tx_timer);
1821 info->tx_timer.data = (unsigned long)info;
1822 info->tx_timer.function = mgsl_tx_timeout;
1823
1824 /* Allocate and claim adapter resources */
1825 retval = mgsl_claim_resources(info);
1826
1827 /* perform existence check and diagnostics */
1828 if ( !retval )
1829 retval = mgsl_adapter_test(info);
1830
1831 if ( retval ) {
1832 if (capable(CAP_SYS_ADMIN) && info->tty)
1833 set_bit(TTY_IO_ERROR, &info->tty->flags);
1834 mgsl_release_resources(info);
1835 return retval;
1836 }
1837
1838 /* program hardware for current parameters */
1839 mgsl_change_params(info);
1840
1841 if (info->tty)
1842 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1843
1844 info->flags |= ASYNC_INITIALIZED;
1845
1846 return 0;
1847
1848} /* end of startup() */
1849
1850/* shutdown()
1851 *
1852 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1853 *
1854 * Arguments: info pointer to device instance data
1855 * Return Value: None
1856 */
1857static void shutdown(struct mgsl_struct * info)
1858{
1859 unsigned long flags;
1860
1861 if (!(info->flags & ASYNC_INITIALIZED))
1862 return;
1863
1864 if (debug_level >= DEBUG_LEVEL_INFO)
1865 printk("%s(%d):mgsl_shutdown(%s)\n",
1866 __FILE__,__LINE__, info->device_name );
1867
1868 /* clear status wait queue because status changes */
1869 /* can't happen after shutting down the hardware */
1870 wake_up_interruptible(&info->status_event_wait_q);
1871 wake_up_interruptible(&info->event_wait_q);
1872
1873 del_timer(&info->tx_timer);
1874
1875 if (info->xmit_buf) {
1876 free_page((unsigned long) info->xmit_buf);
1877 info->xmit_buf = NULL;
1878 }
1879
1880 spin_lock_irqsave(&info->irq_spinlock,flags);
1881 usc_DisableMasterIrqBit(info);
1882 usc_stop_receiver(info);
1883 usc_stop_transmitter(info);
1884 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1885 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1886 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1887
1888 /* Disable DMAEN (Port 7, Bit 14) */
1889 /* This disconnects the DMA request signal from the ISA bus */
1890 /* on the ISA adapter. This has no effect for the PCI adapter */
1891 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1892
1893 /* Disable INTEN (Port 6, Bit12) */
1894 /* This disconnects the IRQ request signal to the ISA bus */
1895 /* on the ISA adapter. This has no effect for the PCI adapter */
1896 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1897
1898 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1899 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1900 usc_set_serial_signals(info);
1901 }
1902
1903 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1904
1905 mgsl_release_resources(info);
1906
1907 if (info->tty)
1908 set_bit(TTY_IO_ERROR, &info->tty->flags);
1909
1910 info->flags &= ~ASYNC_INITIALIZED;
1911
1912} /* end of shutdown() */
1913
1914static void mgsl_program_hw(struct mgsl_struct *info)
1915{
1916 unsigned long flags;
1917
1918 spin_lock_irqsave(&info->irq_spinlock,flags);
1919
1920 usc_stop_receiver(info);
1921 usc_stop_transmitter(info);
1922 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1923
1924 if (info->params.mode == MGSL_MODE_HDLC ||
1925 info->params.mode == MGSL_MODE_RAW ||
1926 info->netcount)
1927 usc_set_sync_mode(info);
1928 else
1929 usc_set_async_mode(info);
1930
1931 usc_set_serial_signals(info);
1932
1933 info->dcd_chkcount = 0;
1934 info->cts_chkcount = 0;
1935 info->ri_chkcount = 0;
1936 info->dsr_chkcount = 0;
1937
1938 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1939 usc_EnableInterrupts(info, IO_PIN);
1940 usc_get_serial_signals(info);
1941
1942 if (info->netcount || info->tty->termios->c_cflag & CREAD)
1943 usc_start_receiver(info);
1944
1945 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1946}
1947
1948/* Reconfigure adapter based on new parameters
1949 */
1950static void mgsl_change_params(struct mgsl_struct *info)
1951{
1952 unsigned cflag;
1953 int bits_per_char;
1954
1955 if (!info->tty || !info->tty->termios)
1956 return;
1957
1958 if (debug_level >= DEBUG_LEVEL_INFO)
1959 printk("%s(%d):mgsl_change_params(%s)\n",
1960 __FILE__,__LINE__, info->device_name );
1961
1962 cflag = info->tty->termios->c_cflag;
1963
1964 /* if B0 rate (hangup) specified then negate DTR and RTS */
1965 /* otherwise assert DTR and RTS */
1966 if (cflag & CBAUD)
1967 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1968 else
1969 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1970
1971 /* byte size and parity */
1972
1973 switch (cflag & CSIZE) {
1974 case CS5: info->params.data_bits = 5; break;
1975 case CS6: info->params.data_bits = 6; break;
1976 case CS7: info->params.data_bits = 7; break;
1977 case CS8: info->params.data_bits = 8; break;
1978 /* Never happens, but GCC is too dumb to figure it out */
1979 default: info->params.data_bits = 7; break;
1980 }
1981
1982 if (cflag & CSTOPB)
1983 info->params.stop_bits = 2;
1984 else
1985 info->params.stop_bits = 1;
1986
1987 info->params.parity = ASYNC_PARITY_NONE;
1988 if (cflag & PARENB) {
1989 if (cflag & PARODD)
1990 info->params.parity = ASYNC_PARITY_ODD;
1991 else
1992 info->params.parity = ASYNC_PARITY_EVEN;
1993#ifdef CMSPAR
1994 if (cflag & CMSPAR)
1995 info->params.parity = ASYNC_PARITY_SPACE;
1996#endif
1997 }
1998
1999 /* calculate number of jiffies to transmit a full
2000 * FIFO (32 bytes) at specified data rate
2001 */
2002 bits_per_char = info->params.data_bits +
2003 info->params.stop_bits + 1;
2004
2005 /* if port data rate is set to 460800 or less then
2006 * allow tty settings to override, otherwise keep the
2007 * current data rate.
2008 */
2009 if (info->params.data_rate <= 460800)
2010 info->params.data_rate = tty_get_baud_rate(info->tty);
2011
2012 if ( info->params.data_rate ) {
2013 info->timeout = (32*HZ*bits_per_char) /
2014 info->params.data_rate;
2015 }
2016 info->timeout += HZ/50; /* Add .02 seconds of slop */
2017
2018 if (cflag & CRTSCTS)
2019 info->flags |= ASYNC_CTS_FLOW;
2020 else
2021 info->flags &= ~ASYNC_CTS_FLOW;
2022
2023 if (cflag & CLOCAL)
2024 info->flags &= ~ASYNC_CHECK_CD;
2025 else
2026 info->flags |= ASYNC_CHECK_CD;
2027
2028 /* process tty input control flags */
2029
2030 info->read_status_mask = RXSTATUS_OVERRUN;
2031 if (I_INPCK(info->tty))
2032 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2033 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2034 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
2035
2036 if (I_IGNPAR(info->tty))
2037 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2038 if (I_IGNBRK(info->tty)) {
2039 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2040 /* If ignoring parity and break indicators, ignore
2041 * overruns too. (For real raw support).
2042 */
2043 if (I_IGNPAR(info->tty))
2044 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2045 }
2046
2047 mgsl_program_hw(info);
2048
2049} /* end of mgsl_change_params() */
2050
2051/* mgsl_put_char()
2052 *
2053 * Add a character to the transmit buffer.
2054 *
2055 * Arguments: tty pointer to tty information structure
2056 * ch character to add to transmit buffer
2057 *
2058 * Return Value: None
2059 */
2060static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2061{
2062 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2063 unsigned long flags;
2064
2065 if ( debug_level >= DEBUG_LEVEL_INFO ) {
2066 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2067 __FILE__,__LINE__,ch,info->device_name);
2068 }
2069
2070 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2071 return;
2072
2073 if (!tty || !info->xmit_buf)
2074 return;
2075
2076 spin_lock_irqsave(&info->irq_spinlock,flags);
2077
2078 if ( (info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active ) {
2079
2080 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2081 info->xmit_buf[info->xmit_head++] = ch;
2082 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2083 info->xmit_cnt++;
2084 }
2085 }
2086
2087 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2088
2089} /* end of mgsl_put_char() */
2090
2091/* mgsl_flush_chars()
2092 *
2093 * Enable transmitter so remaining characters in the
2094 * transmit buffer are sent.
2095 *
2096 * Arguments: tty pointer to tty information structure
2097 * Return Value: None
2098 */
2099static void mgsl_flush_chars(struct tty_struct *tty)
2100{
2101 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2102 unsigned long flags;
2103
2104 if ( debug_level >= DEBUG_LEVEL_INFO )
2105 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2106 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2107
2108 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2109 return;
2110
2111 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2112 !info->xmit_buf)
2113 return;
2114
2115 if ( debug_level >= DEBUG_LEVEL_INFO )
2116 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2117 __FILE__,__LINE__,info->device_name );
2118
2119 spin_lock_irqsave(&info->irq_spinlock,flags);
2120
2121 if (!info->tx_active) {
2122 if ( (info->params.mode == MGSL_MODE_HDLC ||
2123 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2124 /* operating in synchronous (frame oriented) mode */
2125 /* copy data from circular xmit_buf to */
2126 /* transmit DMA buffer. */
2127 mgsl_load_tx_dma_buffer(info,
2128 info->xmit_buf,info->xmit_cnt);
2129 }
2130 usc_start_transmitter(info);
2131 }
2132
2133 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2134
2135} /* end of mgsl_flush_chars() */
2136
2137/* mgsl_write()
2138 *
2139 * Send a block of data
2140 *
2141 * Arguments:
2142 *
2143 * tty pointer to tty information structure
2144 * buf pointer to buffer containing send data
2145 * count size of send data in bytes
2146 *
2147 * Return Value: number of characters written
2148 */
2149static int mgsl_write(struct tty_struct * tty,
2150 const unsigned char *buf, int count)
2151{
2152 int c, ret = 0;
2153 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2154 unsigned long flags;
2155
2156 if ( debug_level >= DEBUG_LEVEL_INFO )
2157 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2158 __FILE__,__LINE__,info->device_name,count);
2159
2160 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2161 goto cleanup;
2162
2163 if (!tty || !info->xmit_buf || !tmp_buf)
2164 goto cleanup;
2165
2166 if ( info->params.mode == MGSL_MODE_HDLC ||
2167 info->params.mode == MGSL_MODE_RAW ) {
2168 /* operating in synchronous (frame oriented) mode */
2169 /* operating in synchronous (frame oriented) mode */
2170 if (info->tx_active) {
2171
2172 if ( info->params.mode == MGSL_MODE_HDLC ) {
2173 ret = 0;
2174 goto cleanup;
2175 }
2176 /* transmitter is actively sending data -
2177 * if we have multiple transmit dma and
2178 * holding buffers, attempt to queue this
2179 * frame for transmission at a later time.
2180 */
2181 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2182 /* no tx holding buffers available */
2183 ret = 0;
2184 goto cleanup;
2185 }
2186
2187 /* queue transmit frame request */
2188 ret = count;
2189 save_tx_buffer_request(info,buf,count);
2190
2191 /* if we have sufficient tx dma buffers,
2192 * load the next buffered tx request
2193 */
2194 spin_lock_irqsave(&info->irq_spinlock,flags);
2195 load_next_tx_holding_buffer(info);
2196 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2197 goto cleanup;
2198 }
2199
2200 /* if operating in HDLC LoopMode and the adapter */
2201 /* has yet to be inserted into the loop, we can't */
2202 /* transmit */
2203
2204 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2205 !usc_loopmode_active(info) )
2206 {
2207 ret = 0;
2208 goto cleanup;
2209 }
2210
2211 if ( info->xmit_cnt ) {
2212 /* Send accumulated from send_char() calls */
2213 /* as frame and wait before accepting more data. */
2214 ret = 0;
2215
2216 /* copy data from circular xmit_buf to */
2217 /* transmit DMA buffer. */
2218 mgsl_load_tx_dma_buffer(info,
2219 info->xmit_buf,info->xmit_cnt);
2220 if ( debug_level >= DEBUG_LEVEL_INFO )
2221 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2222 __FILE__,__LINE__,info->device_name);
2223 } else {
2224 if ( debug_level >= DEBUG_LEVEL_INFO )
2225 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2226 __FILE__,__LINE__,info->device_name);
2227 ret = count;
2228 info->xmit_cnt = count;
2229 mgsl_load_tx_dma_buffer(info,buf,count);
2230 }
2231 } else {
2232 while (1) {
2233 spin_lock_irqsave(&info->irq_spinlock,flags);
2234 c = min_t(int, count,
2235 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2236 SERIAL_XMIT_SIZE - info->xmit_head));
2237 if (c <= 0) {
2238 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2239 break;
2240 }
2241 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2242 info->xmit_head = ((info->xmit_head + c) &
2243 (SERIAL_XMIT_SIZE-1));
2244 info->xmit_cnt += c;
2245 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2246 buf += c;
2247 count -= c;
2248 ret += c;
2249 }
2250 }
2251
2252 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2253 spin_lock_irqsave(&info->irq_spinlock,flags);
2254 if (!info->tx_active)
2255 usc_start_transmitter(info);
2256 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2257 }
2258cleanup:
2259 if ( debug_level >= DEBUG_LEVEL_INFO )
2260 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2261 __FILE__,__LINE__,info->device_name,ret);
2262
2263 return ret;
2264
2265} /* end of mgsl_write() */
2266
2267/* mgsl_write_room()
2268 *
2269 * Return the count of free bytes in transmit buffer
2270 *
2271 * Arguments: tty pointer to tty info structure
2272 * Return Value: None
2273 */
2274static int mgsl_write_room(struct tty_struct *tty)
2275{
2276 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2277 int ret;
2278
2279 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2280 return 0;
2281 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2282 if (ret < 0)
2283 ret = 0;
2284
2285 if (debug_level >= DEBUG_LEVEL_INFO)
2286 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2287 __FILE__,__LINE__, info->device_name,ret );
2288
2289 if ( info->params.mode == MGSL_MODE_HDLC ||
2290 info->params.mode == MGSL_MODE_RAW ) {
2291 /* operating in synchronous (frame oriented) mode */
2292 if ( info->tx_active )
2293 return 0;
2294 else
2295 return HDLC_MAX_FRAME_SIZE;
2296 }
2297
2298 return ret;
2299
2300} /* end of mgsl_write_room() */
2301
2302/* mgsl_chars_in_buffer()
2303 *
2304 * Return the count of bytes in transmit buffer
2305 *
2306 * Arguments: tty pointer to tty info structure
2307 * Return Value: None
2308 */
2309static int mgsl_chars_in_buffer(struct tty_struct *tty)
2310{
2311 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2312
2313 if (debug_level >= DEBUG_LEVEL_INFO)
2314 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2315 __FILE__,__LINE__, info->device_name );
2316
2317 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2318 return 0;
2319
2320 if (debug_level >= DEBUG_LEVEL_INFO)
2321 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2322 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2323
2324 if ( info->params.mode == MGSL_MODE_HDLC ||
2325 info->params.mode == MGSL_MODE_RAW ) {
2326 /* operating in synchronous (frame oriented) mode */
2327 if ( info->tx_active )
2328 return info->max_frame_size;
2329 else
2330 return 0;
2331 }
2332
2333 return info->xmit_cnt;
2334} /* end of mgsl_chars_in_buffer() */
2335
2336/* mgsl_flush_buffer()
2337 *
2338 * Discard all data in the send buffer
2339 *
2340 * Arguments: tty pointer to tty info structure
2341 * Return Value: None
2342 */
2343static void mgsl_flush_buffer(struct tty_struct *tty)
2344{
2345 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2346 unsigned long flags;
2347
2348 if (debug_level >= DEBUG_LEVEL_INFO)
2349 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2350 __FILE__,__LINE__, info->device_name );
2351
2352 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2353 return;
2354
2355 spin_lock_irqsave(&info->irq_spinlock,flags);
2356 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2357 del_timer(&info->tx_timer);
2358 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2359
2360 wake_up_interruptible(&tty->write_wait);
2361 tty_wakeup(tty);
2362}
2363
2364/* mgsl_send_xchar()
2365 *
2366 * Send a high-priority XON/XOFF character
2367 *
2368 * Arguments: tty pointer to tty info structure
2369 * ch character to send
2370 * Return Value: None
2371 */
2372static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2373{
2374 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2375 unsigned long flags;
2376
2377 if (debug_level >= DEBUG_LEVEL_INFO)
2378 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2379 __FILE__,__LINE__, info->device_name, ch );
2380
2381 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2382 return;
2383
2384 info->x_char = ch;
2385 if (ch) {
2386 /* Make sure transmit interrupts are on */
2387 spin_lock_irqsave(&info->irq_spinlock,flags);
2388 if (!info->tx_enabled)
2389 usc_start_transmitter(info);
2390 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2391 }
2392} /* end of mgsl_send_xchar() */
2393
2394/* mgsl_throttle()
2395 *
2396 * Signal remote device to throttle send data (our receive data)
2397 *
2398 * Arguments: tty pointer to tty info structure
2399 * Return Value: None
2400 */
2401static void mgsl_throttle(struct tty_struct * tty)
2402{
2403 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2404 unsigned long flags;
2405
2406 if (debug_level >= DEBUG_LEVEL_INFO)
2407 printk("%s(%d):mgsl_throttle(%s) entry\n",
2408 __FILE__,__LINE__, info->device_name );
2409
2410 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2411 return;
2412
2413 if (I_IXOFF(tty))
2414 mgsl_send_xchar(tty, STOP_CHAR(tty));
2415
2416 if (tty->termios->c_cflag & CRTSCTS) {
2417 spin_lock_irqsave(&info->irq_spinlock,flags);
2418 info->serial_signals &= ~SerialSignal_RTS;
2419 usc_set_serial_signals(info);
2420 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2421 }
2422} /* end of mgsl_throttle() */
2423
2424/* mgsl_unthrottle()
2425 *
2426 * Signal remote device to stop throttling send data (our receive data)
2427 *
2428 * Arguments: tty pointer to tty info structure
2429 * Return Value: None
2430 */
2431static void mgsl_unthrottle(struct tty_struct * tty)
2432{
2433 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2434 unsigned long flags;
2435
2436 if (debug_level >= DEBUG_LEVEL_INFO)
2437 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2438 __FILE__,__LINE__, info->device_name );
2439
2440 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2441 return;
2442
2443 if (I_IXOFF(tty)) {
2444 if (info->x_char)
2445 info->x_char = 0;
2446 else
2447 mgsl_send_xchar(tty, START_CHAR(tty));
2448 }
2449
2450 if (tty->termios->c_cflag & CRTSCTS) {
2451 spin_lock_irqsave(&info->irq_spinlock,flags);
2452 info->serial_signals |= SerialSignal_RTS;
2453 usc_set_serial_signals(info);
2454 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2455 }
2456
2457} /* end of mgsl_unthrottle() */
2458
2459/* mgsl_get_stats()
2460 *
2461 * get the current serial parameters information
2462 *
2463 * Arguments: info pointer to device instance data
2464 * user_icount pointer to buffer to hold returned stats
2465 *
2466 * Return Value: 0 if success, otherwise error code
2467 */
2468static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2469{
2470 int err;
2471
2472 if (debug_level >= DEBUG_LEVEL_INFO)
2473 printk("%s(%d):mgsl_get_params(%s)\n",
2474 __FILE__,__LINE__, info->device_name);
2475
9661239f
PF		 2476 if (!user_icount) {
2477 memset(&info->icount, 0, sizeof(info->icount));
2478 } else {
2479 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2480 if (err)
2481 return -EFAULT;
1da177e4
LT		 2482 }
2483
2484 return 0;
2485
2486} /* end of mgsl_get_stats() */
2487
2488/* mgsl_get_params()
2489 *
2490 * get the current serial parameters information
2491 *
2492 * Arguments: info pointer to device instance data
2493 * user_params pointer to buffer to hold returned params
2494 *
2495 * Return Value: 0 if success, otherwise error code
2496 */
2497static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2498{
2499 int err;
2500 if (debug_level >= DEBUG_LEVEL_INFO)
2501 printk("%s(%d):mgsl_get_params(%s)\n",
2502 __FILE__,__LINE__, info->device_name);
2503
2504 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2505 if (err) {
2506 if ( debug_level >= DEBUG_LEVEL_INFO )
2507 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2508 __FILE__,__LINE__,info->device_name);
2509 return -EFAULT;
2510 }
2511
2512 return 0;
2513
2514} /* end of mgsl_get_params() */
2515
2516/* mgsl_set_params()
2517 *
2518 * set the serial parameters
2519 *
2520 * Arguments:
2521 *
2522 * info pointer to device instance data
2523 * new_params user buffer containing new serial params
2524 *
2525 * Return Value: 0 if success, otherwise error code
2526 */
2527static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2528{
2529 unsigned long flags;
2530 MGSL_PARAMS tmp_params;
2531 int err;
2532
2533 if (debug_level >= DEBUG_LEVEL_INFO)
2534 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2535 info->device_name );
2536 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2537 if (err) {
2538 if ( debug_level >= DEBUG_LEVEL_INFO )
2539 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2540 __FILE__,__LINE__,info->device_name);
2541 return -EFAULT;
2542 }
2543
2544 spin_lock_irqsave(&info->irq_spinlock,flags);
2545 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2546 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2547
2548 mgsl_change_params(info);
2549
2550 return 0;
2551
2552} /* end of mgsl_set_params() */
2553
2554/* mgsl_get_txidle()
2555 *
2556 * get the current transmit idle mode
2557 *
2558 * Arguments: info pointer to device instance data
2559 * idle_mode pointer to buffer to hold returned idle mode
2560 *
2561 * Return Value: 0 if success, otherwise error code
2562 */
2563static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2564{
2565 int err;
2566
2567 if (debug_level >= DEBUG_LEVEL_INFO)
2568 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2569 __FILE__,__LINE__, info->device_name, info->idle_mode);
2570
2571 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2572 if (err) {
2573 if ( debug_level >= DEBUG_LEVEL_INFO )
2574 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2575 __FILE__,__LINE__,info->device_name);
2576 return -EFAULT;
2577 }
2578
2579 return 0;
2580
2581} /* end of mgsl_get_txidle() */
2582
2583/* mgsl_set_txidle() service ioctl to set transmit idle mode
2584 *
2585 * Arguments: info pointer to device instance data
2586 * idle_mode new idle mode
2587 *
2588 * Return Value: 0 if success, otherwise error code
2589 */
2590static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2591{
2592 unsigned long flags;
2593
2594 if (debug_level >= DEBUG_LEVEL_INFO)
2595 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2596 info->device_name, idle_mode );
2597
2598 spin_lock_irqsave(&info->irq_spinlock,flags);
2599 info->idle_mode = idle_mode;
2600 usc_set_txidle( info );
2601 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2602 return 0;
2603
2604} /* end of mgsl_set_txidle() */
2605
2606/* mgsl_txenable()
2607 *
2608 * enable or disable the transmitter
2609 *
2610 * Arguments:
2611 *
2612 * info pointer to device instance data
2613 * enable 1 = enable, 0 = disable
2614 *
2615 * Return Value: 0 if success, otherwise error code
2616 */
2617static int mgsl_txenable(struct mgsl_struct * info, int enable)
2618{
2619 unsigned long flags;
2620
2621 if (debug_level >= DEBUG_LEVEL_INFO)
2622 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2623 info->device_name, enable);
2624
2625 spin_lock_irqsave(&info->irq_spinlock,flags);
2626 if ( enable ) {
2627 if ( !info->tx_enabled ) {
2628
2629 usc_start_transmitter(info);
2630 /*--------------------------------------------------
2631 * if HDLC/SDLC Loop mode, attempt to insert the
2632 * station in the 'loop' by setting CMR:13. Upon
2633 * receipt of the next GoAhead (RxAbort) sequence,
2634 * the OnLoop indicator (CCSR:7) should go active
2635 * to indicate that we are on the loop
2636 *--------------------------------------------------*/
2637 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2638 usc_loopmode_insert_request( info );
2639 }
2640 } else {
2641 if ( info->tx_enabled )
2642 usc_stop_transmitter(info);
2643 }
2644 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2645 return 0;
2646
2647} /* end of mgsl_txenable() */
2648
2649/* mgsl_txabort() abort send HDLC frame
2650 *
2651 * Arguments: info pointer to device instance data
2652 * Return Value: 0 if success, otherwise error code
2653 */
2654static int mgsl_txabort(struct mgsl_struct * info)
2655{
2656 unsigned long flags;
2657
2658 if (debug_level >= DEBUG_LEVEL_INFO)
2659 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2660 info->device_name);
2661
2662 spin_lock_irqsave(&info->irq_spinlock,flags);
2663 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2664 {
2665 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2666 usc_loopmode_cancel_transmit( info );
2667 else
2668 usc_TCmd(info,TCmd_SendAbort);
2669 }
2670 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2671 return 0;
2672
2673} /* end of mgsl_txabort() */
2674
2675/* mgsl_rxenable() enable or disable the receiver
2676 *
2677 * Arguments: info pointer to device instance data
2678 * enable 1 = enable, 0 = disable
2679 * Return Value: 0 if success, otherwise error code
2680 */
2681static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2682{
2683 unsigned long flags;
2684
2685 if (debug_level >= DEBUG_LEVEL_INFO)
2686 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2687 info->device_name, enable);
2688
2689 spin_lock_irqsave(&info->irq_spinlock,flags);
2690 if ( enable ) {
2691 if ( !info->rx_enabled )
2692 usc_start_receiver(info);
2693 } else {
2694 if ( info->rx_enabled )
2695 usc_stop_receiver(info);
2696 }
2697 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2698 return 0;
2699
2700} /* end of mgsl_rxenable() */
2701
2702/* mgsl_wait_event() wait for specified event to occur
2703 *
2704 * Arguments: info pointer to device instance data
2705 * mask pointer to bitmask of events to wait for
2706 * Return Value: 0 if successful and bit mask updated with
2707 * of events triggerred,
2708 * otherwise error code
2709 */
2710static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2711{
2712 unsigned long flags;
2713 int s;
2714 int rc=0;
2715 struct mgsl_icount cprev, cnow;
2716 int events;
2717 int mask;
2718 struct _input_signal_events oldsigs, newsigs;
2719 DECLARE_WAITQUEUE(wait, current);
2720
2721 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2722 if (rc) {
2723 return -EFAULT;
2724 }
2725
2726 if (debug_level >= DEBUG_LEVEL_INFO)
2727 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2728 info->device_name, mask);
2729
2730 spin_lock_irqsave(&info->irq_spinlock,flags);
2731
2732 /* return immediately if state matches requested events */
2733 usc_get_serial_signals(info);
2734 s = info->serial_signals;
2735 events = mask &
2736 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2737 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2738 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2739 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2740 if (events) {
2741 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2742 goto exit;
2743 }
2744
2745 /* save current irq counts */
2746 cprev = info->icount;
2747 oldsigs = info->input_signal_events;
2748
2749 /* enable hunt and idle irqs if needed */
2750 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2751 u16 oldreg = usc_InReg(info,RICR);
2752 u16 newreg = oldreg +
2753 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2754 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2755 if (oldreg != newreg)
2756 usc_OutReg(info, RICR, newreg);
2757 }
2758
2759 set_current_state(TASK_INTERRUPTIBLE);
2760 add_wait_queue(&info->event_wait_q, &wait);
2761
2762 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2763
2764
2765 for(;;) {
2766 schedule();
2767 if (signal_pending(current)) {
2768 rc = -ERESTARTSYS;
2769 break;
2770 }
2771
2772 /* get current irq counts */
2773 spin_lock_irqsave(&info->irq_spinlock,flags);
2774 cnow = info->icount;
2775 newsigs = info->input_signal_events;
2776 set_current_state(TASK_INTERRUPTIBLE);
2777 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2778
2779 /* if no change, wait aborted for some reason */
2780 if (newsigs.dsr_up == oldsigs.dsr_up &&
2781 newsigs.dsr_down == oldsigs.dsr_down &&
2782 newsigs.dcd_up == oldsigs.dcd_up &&
2783 newsigs.dcd_down == oldsigs.dcd_down &&
2784 newsigs.cts_up == oldsigs.cts_up &&
2785 newsigs.cts_down == oldsigs.cts_down &&
2786 newsigs.ri_up == oldsigs.ri_up &&
2787 newsigs.ri_down == oldsigs.ri_down &&
2788 cnow.exithunt == cprev.exithunt &&
2789 cnow.rxidle == cprev.rxidle) {
2790 rc = -EIO;
2791 break;
2792 }
2793
2794 events = mask &
2795 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2796 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2797 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2798 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2799 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2800 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2801 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2802 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2803 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2804 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2805 if (events)
2806 break;
2807
2808 cprev = cnow;
2809 oldsigs = newsigs;
2810 }
2811
2812 remove_wait_queue(&info->event_wait_q, &wait);
2813 set_current_state(TASK_RUNNING);
2814
2815 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2816 spin_lock_irqsave(&info->irq_spinlock,flags);
2817 if (!waitqueue_active(&info->event_wait_q)) {
2818 /* disable enable exit hunt mode/idle rcvd IRQs */
2819 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2820 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2821 }
2822 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2823 }
2824exit:
2825 if ( rc == 0 )
2826 PUT_USER(rc, events, mask_ptr);
2827
2828 return rc;
2829
2830} /* end of mgsl_wait_event() */
2831
2832static int modem_input_wait(struct mgsl_struct *info,int arg)
2833{
2834 unsigned long flags;
2835 int rc;
2836 struct mgsl_icount cprev, cnow;
2837 DECLARE_WAITQUEUE(wait, current);
2838
2839 /* save current irq counts */
2840 spin_lock_irqsave(&info->irq_spinlock,flags);
2841 cprev = info->icount;
2842 add_wait_queue(&info->status_event_wait_q, &wait);
2843 set_current_state(TASK_INTERRUPTIBLE);
2844 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2845
2846 for(;;) {
2847 schedule();
2848 if (signal_pending(current)) {
2849 rc = -ERESTARTSYS;
2850 break;
2851 }
2852
2853 /* get new irq counts */
2854 spin_lock_irqsave(&info->irq_spinlock,flags);
2855 cnow = info->icount;
2856 set_current_state(TASK_INTERRUPTIBLE);
2857 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2858
2859 /* if no change, wait aborted for some reason */
2860 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2861 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2862 rc = -EIO;
2863 break;
2864 }
2865
2866 /* check for change in caller specified modem input */
2867 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2868 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2869 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2870 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2871 rc = 0;
2872 break;
2873 }
2874
2875 cprev = cnow;
2876 }
2877 remove_wait_queue(&info->status_event_wait_q, &wait);
2878 set_current_state(TASK_RUNNING);
2879 return rc;
2880}
2881
2882/* return the state of the serial control and status signals
2883 */
2884static int tiocmget(struct tty_struct *tty, struct file *file)
2885{
2886 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2887 unsigned int result;
2888 unsigned long flags;
2889
2890 spin_lock_irqsave(&info->irq_spinlock,flags);
2891 usc_get_serial_signals(info);
2892 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2893
2894 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2895 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2896 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2897 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2898 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2899 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2900
2901 if (debug_level >= DEBUG_LEVEL_INFO)
2902 printk("%s(%d):%s tiocmget() value=%08X\n",
2903 __FILE__,__LINE__, info->device_name, result );
2904 return result;
2905}
2906
2907/* set modem control signals (DTR/RTS)
2908 */
2909static int tiocmset(struct tty_struct *tty, struct file *file,
2910 unsigned int set, unsigned int clear)
2911{
2912 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2913 unsigned long flags;
2914
2915 if (debug_level >= DEBUG_LEVEL_INFO)
2916 printk("%s(%d):%s tiocmset(%x,%x)\n",
2917 __FILE__,__LINE__,info->device_name, set, clear);
2918
2919 if (set & TIOCM_RTS)
2920 info->serial_signals |= SerialSignal_RTS;
2921 if (set & TIOCM_DTR)
2922 info->serial_signals |= SerialSignal_DTR;
2923 if (clear & TIOCM_RTS)
2924 info->serial_signals &= ~SerialSignal_RTS;
2925 if (clear & TIOCM_DTR)
2926 info->serial_signals &= ~SerialSignal_DTR;
2927
2928 spin_lock_irqsave(&info->irq_spinlock,flags);
2929 usc_set_serial_signals(info);
2930 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2931
2932 return 0;
2933}
2934
2935/* mgsl_break() Set or clear transmit break condition
2936 *
2937 * Arguments: tty pointer to tty instance data
2938 * break_state -1=set break condition, 0=clear
2939 * Return Value: None
2940 */
2941static void mgsl_break(struct tty_struct *tty, int break_state)
2942{
2943 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2944 unsigned long flags;
2945
2946 if (debug_level >= DEBUG_LEVEL_INFO)
2947 printk("%s(%d):mgsl_break(%s,%d)\n",
2948 __FILE__,__LINE__, info->device_name, break_state);
2949
2950 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2951 return;
2952
2953 spin_lock_irqsave(&info->irq_spinlock,flags);
2954 if (break_state == -1)
2955 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2956 else
2957 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2958 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2959
2960} /* end of mgsl_break() */
2961
2962/* mgsl_ioctl() Service an IOCTL request
2963 *
2964 * Arguments:
2965 *
2966 * tty pointer to tty instance data
2967 * file pointer to associated file object for device
2968 * cmd IOCTL command code
2969 * arg command argument/context
2970 *
2971 * Return Value: 0 if success, otherwise error code
2972 */
2973static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2974 unsigned int cmd, unsigned long arg)
2975{
2976 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2977
2978 if (debug_level >= DEBUG_LEVEL_INFO)
2979 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2980 info->device_name, cmd );
2981
2982 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2983 return -ENODEV;
2984
2985 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2986 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2987 if (tty->flags & (1 << TTY_IO_ERROR))
2988 return -EIO;
2989 }
2990
2991 return mgsl_ioctl_common(info, cmd, arg);
2992}
2993
2994static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2995{
2996 int error;
2997 struct mgsl_icount cnow; /* kernel counter temps */
2998 void __user *argp = (void __user *)arg;
2999 struct serial_icounter_struct __user *p_cuser; /* user space */
3000 unsigned long flags;
3001
3002 switch (cmd) {
3003 case MGSL_IOCGPARAMS:
3004 return mgsl_get_params(info, argp);
3005 case MGSL_IOCSPARAMS:
3006 return mgsl_set_params(info, argp);
3007 case MGSL_IOCGTXIDLE:
3008 return mgsl_get_txidle(info, argp);
3009 case MGSL_IOCSTXIDLE:
3010 return mgsl_set_txidle(info,(int)arg);
3011 case MGSL_IOCTXENABLE:
3012 return mgsl_txenable(info,(int)arg);
3013 case MGSL_IOCRXENABLE:
3014 return mgsl_rxenable(info,(int)arg);
3015 case MGSL_IOCTXABORT:
3016 return mgsl_txabort(info);
3017 case MGSL_IOCGSTATS:
3018 return mgsl_get_stats(info, argp);
3019 case MGSL_IOCWAITEVENT:
3020 return mgsl_wait_event(info, argp);
3021 case MGSL_IOCLOOPTXDONE:
3022 return mgsl_loopmode_send_done(info);
3023 /* Wait for modem input (DCD,RI,DSR,CTS) change
3024 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3025 */
3026 case TIOCMIWAIT:
3027 return modem_input_wait(info,(int)arg);
3028
3029 /*
3030 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3031 * Return: write counters to the user passed counter struct
3032 * NB: both 1->0 and 0->1 transitions are counted except for
3033 * RI where only 0->1 is counted.
3034 */
3035 case TIOCGICOUNT:
3036 spin_lock_irqsave(&info->irq_spinlock,flags);
3037 cnow = info->icount;
3038 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3039 p_cuser = argp;
3040 PUT_USER(error,cnow.cts, &p_cuser->cts);
3041 if (error) return error;
3042 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3043 if (error) return error;
3044 PUT_USER(error,cnow.rng, &p_cuser->rng);
3045 if (error) return error;
3046 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3047 if (error) return error;
3048 PUT_USER(error,cnow.rx, &p_cuser->rx);
3049 if (error) return error;
3050 PUT_USER(error,cnow.tx, &p_cuser->tx);
3051 if (error) return error;
3052 PUT_USER(error,cnow.frame, &p_cuser->frame);
3053 if (error) return error;
3054 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3055 if (error) return error;
3056 PUT_USER(error,cnow.parity, &p_cuser->parity);
3057 if (error) return error;
3058 PUT_USER(error,cnow.brk, &p_cuser->brk);
3059 if (error) return error;
3060 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3061 if (error) return error;
3062 return 0;
3063 default:
3064 return -ENOIOCTLCMD;
3065 }
3066 return 0;
3067}
3068
3069/* mgsl_set_termios()
3070 *
3071 * Set new termios settings
3072 *
3073 * Arguments:
3074 *
3075 * tty pointer to tty structure
3076 * termios pointer to buffer to hold returned old termios
3077 *
3078 * Return Value: None
3079 */
3080static void mgsl_set_termios(struct tty_struct *tty, struct termios *old_termios)
3081{
3082 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3083 unsigned long flags;
3084
3085 if (debug_level >= DEBUG_LEVEL_INFO)
3086 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3087 tty->driver->name );
3088
3089 /* just return if nothing has changed */
3090 if ((tty->termios->c_cflag == old_termios->c_cflag)
3091 && (RELEVANT_IFLAG(tty->termios->c_iflag)
3092 == RELEVANT_IFLAG(old_termios->c_iflag)))
3093 return;
3094
3095 mgsl_change_params(info);
3096
3097 /* Handle transition to B0 status */
3098 if (old_termios->c_cflag & CBAUD &&
3099 !(tty->termios->c_cflag & CBAUD)) {
3100 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3101 spin_lock_irqsave(&info->irq_spinlock,flags);
3102 usc_set_serial_signals(info);
3103 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3104 }
3105
3106 /* Handle transition away from B0 status */
3107 if (!(old_termios->c_cflag & CBAUD) &&
3108 tty->termios->c_cflag & CBAUD) {
3109 info->serial_signals |= SerialSignal_DTR;
3110 if (!(tty->termios->c_cflag & CRTSCTS) ||
3111 !test_bit(TTY_THROTTLED, &tty->flags)) {
3112 info->serial_signals |= SerialSignal_RTS;
3113 }
3114 spin_lock_irqsave(&info->irq_spinlock,flags);
3115 usc_set_serial_signals(info);
3116 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3117 }
3118
3119 /* Handle turning off CRTSCTS */
3120 if (old_termios->c_cflag & CRTSCTS &&
3121 !(tty->termios->c_cflag & CRTSCTS)) {
3122 tty->hw_stopped = 0;
3123 mgsl_start(tty);
3124 }
3125
3126} /* end of mgsl_set_termios() */
3127
3128/* mgsl_close()
3129 *
3130 * Called when port is closed. Wait for remaining data to be
3131 * sent. Disable port and free resources.
3132 *
3133 * Arguments:
3134 *
3135 * tty pointer to open tty structure
3136 * filp pointer to open file object
3137 *
3138 * Return Value: None
3139 */
3140static void mgsl_close(struct tty_struct *tty, struct file * filp)
3141{
3142 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3143
3144 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3145 return;
3146
3147 if (debug_level >= DEBUG_LEVEL_INFO)
3148 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3149 __FILE__,__LINE__, info->device_name, info->count);
3150
3151 if (!info->count)
3152 return;
3153
3154 if (tty_hung_up_p(filp))
3155 goto cleanup;
3156
3157 if ((tty->count == 1) && (info->count != 1)) {
3158 /*
3159 * tty->count is 1 and the tty structure will be freed.
3160 * info->count should be one in this case.
3161 * if it's not, correct it so that the port is shutdown.
3162 */
3163 printk("mgsl_close: bad refcount; tty->count is 1, "
3164 "info->count is %d\n", info->count);
3165 info->count = 1;
3166 }
3167
3168 info->count--;
3169
3170 /* if at least one open remaining, leave hardware active */
3171 if (info->count)
3172 goto cleanup;
3173
3174 info->flags |= ASYNC_CLOSING;
3175
3176 /* set tty->closing to notify line discipline to
3177 * only process XON/XOFF characters. Only the N_TTY
3178 * discipline appears to use this (ppp does not).
3179 */
3180 tty->closing = 1;
3181
3182 /* wait for transmit data to clear all layers */
3183
3184 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3185 if (debug_level >= DEBUG_LEVEL_INFO)
3186 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3187 __FILE__,__LINE__, info->device_name );
3188 tty_wait_until_sent(tty, info->closing_wait);
3189 }
3190
3191 if (info->flags & ASYNC_INITIALIZED)
3192 mgsl_wait_until_sent(tty, info->timeout);
3193
3194 if (tty->driver->flush_buffer)
3195 tty->driver->flush_buffer(tty);
3196
3197 tty_ldisc_flush(tty);
3198
3199 shutdown(info);
3200
3201 tty->closing = 0;
3202 info->tty = NULL;
3203
3204 if (info->blocked_open) {
3205 if (info->close_delay) {
3206 msleep_interruptible(jiffies_to_msecs(info->close_delay));
3207 }
3208 wake_up_interruptible(&info->open_wait);
3209 }
3210
3211 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3212
3213 wake_up_interruptible(&info->close_wait);
3214
3215cleanup:
3216 if (debug_level >= DEBUG_LEVEL_INFO)
3217 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3218 tty->driver->name, info->count);
3219
3220} /* end of mgsl_close() */
3221
3222/* mgsl_wait_until_sent()
3223 *
3224 * Wait until the transmitter is empty.
3225 *
3226 * Arguments:
3227 *
3228 * tty pointer to tty info structure
3229 * timeout time to wait for send completion
3230 *
3231 * Return Value: None
3232 */
3233static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3234{
3235 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3236 unsigned long orig_jiffies, char_time;
3237
3238 if (!info )
3239 return;
3240
3241 if (debug_level >= DEBUG_LEVEL_INFO)
3242 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3243 __FILE__,__LINE__, info->device_name );
3244
3245 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3246 return;
3247
3248 if (!(info->flags & ASYNC_INITIALIZED))
3249 goto exit;
3250
3251 orig_jiffies = jiffies;
3252
3253 /* Set check interval to 1/5 of estimated time to
3254 * send a character, and make it at least 1. The check
3255 * interval should also be less than the timeout.
3256 * Note: use tight timings here to satisfy the NIST-PCTS.
3257 */
3258
3259 if ( info->params.data_rate ) {
3260 char_time = info->timeout/(32 * 5);
3261 if (!char_time)
3262 char_time++;
3263 } else
3264 char_time = 1;
3265
3266 if (timeout)
3267 char_time = min_t(unsigned long, char_time, timeout);
3268
3269 if ( info->params.mode == MGSL_MODE_HDLC ||
3270 info->params.mode == MGSL_MODE_RAW ) {
3271 while (info->tx_active) {
3272 msleep_interruptible(jiffies_to_msecs(char_time));
3273 if (signal_pending(current))
3274 break;
3275 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3276 break;
3277 }
3278 } else {
3279 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3280 info->tx_enabled) {
3281 msleep_interruptible(jiffies_to_msecs(char_time));
3282 if (signal_pending(current))
3283 break;
3284 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3285 break;
3286 }
3287 }
3288
3289exit:
3290 if (debug_level >= DEBUG_LEVEL_INFO)
3291 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3292 __FILE__,__LINE__, info->device_name );
3293
3294} /* end of mgsl_wait_until_sent() */
3295
3296/* mgsl_hangup()
3297 *
3298 * Called by tty_hangup() when a hangup is signaled.
3299 * This is the same as to closing all open files for the port.
3300 *
3301 * Arguments: tty pointer to associated tty object
3302 * Return Value: None
3303 */
3304static void mgsl_hangup(struct tty_struct *tty)
3305{
3306 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3307
3308 if (debug_level >= DEBUG_LEVEL_INFO)
3309 printk("%s(%d):mgsl_hangup(%s)\n",
3310 __FILE__,__LINE__, info->device_name );
3311
3312 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3313 return;
3314
3315 mgsl_flush_buffer(tty);
3316 shutdown(info);
3317
3318 info->count = 0;
3319 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3320 info->tty = NULL;
3321
3322 wake_up_interruptible(&info->open_wait);
3323
3324} /* end of mgsl_hangup() */
3325
3326/* block_til_ready()
3327 *
3328 * Block the current process until the specified port
3329 * is ready to be opened.
3330 *
3331 * Arguments:
3332 *
3333 * tty pointer to tty info structure
3334 * filp pointer to open file object
3335 * info pointer to device instance data
3336 *
3337 * Return Value: 0 if success, otherwise error code
3338 */
3339static int block_til_ready(struct tty_struct *tty, struct file * filp,
3340 struct mgsl_struct *info)
3341{
3342 DECLARE_WAITQUEUE(wait, current);
3343 int retval;
3344 int do_clocal = 0, extra_count = 0;
3345 unsigned long flags;
3346
3347 if (debug_level >= DEBUG_LEVEL_INFO)
3348 printk("%s(%d):block_til_ready on %s\n",
3349 __FILE__,__LINE__, tty->driver->name );
3350
3351 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3352 /* nonblock mode is set or port is not enabled */
3353 info->flags |= ASYNC_NORMAL_ACTIVE;
3354 return 0;
3355 }
3356
3357 if (tty->termios->c_cflag & CLOCAL)
3358 do_clocal = 1;
3359
3360 /* Wait for carrier detect and the line to become
3361 * free (i.e., not in use by the callout). While we are in
3362 * this loop, info->count is dropped by one, so that
3363 * mgsl_close() knows when to free things. We restore it upon
3364 * exit, either normal or abnormal.
3365 */
3366
3367 retval = 0;
3368 add_wait_queue(&info->open_wait, &wait);
3369
3370 if (debug_level >= DEBUG_LEVEL_INFO)
3371 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3372 __FILE__,__LINE__, tty->driver->name, info->count );
3373
3374 spin_lock_irqsave(&info->irq_spinlock, flags);
3375 if (!tty_hung_up_p(filp)) {
3376 extra_count = 1;
3377 info->count--;
3378 }
3379 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3380 info->blocked_open++;
3381
3382 while (1) {
3383 if (tty->termios->c_cflag & CBAUD) {
3384 spin_lock_irqsave(&info->irq_spinlock,flags);
3385 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3386 usc_set_serial_signals(info);
3387 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3388 }
3389
3390 set_current_state(TASK_INTERRUPTIBLE);
3391
3392 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3393 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3394 -EAGAIN : -ERESTARTSYS;
3395 break;
3396 }
3397
3398 spin_lock_irqsave(&info->irq_spinlock,flags);
3399 usc_get_serial_signals(info);
3400 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3401
3402 if (!(info->flags & ASYNC_CLOSING) &&
3403 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3404 break;
3405 }
3406
3407 if (signal_pending(current)) {
3408 retval = -ERESTARTSYS;
3409 break;
3410 }
3411
3412 if (debug_level >= DEBUG_LEVEL_INFO)
3413 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3414 __FILE__,__LINE__, tty->driver->name, info->count );
3415
3416 schedule();
3417 }
3418
3419 set_current_state(TASK_RUNNING);
3420 remove_wait_queue(&info->open_wait, &wait);
3421
3422 if (extra_count)
3423 info->count++;
3424 info->blocked_open--;
3425
3426 if (debug_level >= DEBUG_LEVEL_INFO)
3427 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3428 __FILE__,__LINE__, tty->driver->name, info->count );
3429
3430 if (!retval)
3431 info->flags |= ASYNC_NORMAL_ACTIVE;
3432
3433 return retval;
3434
3435} /* end of block_til_ready() */
3436
3437/* mgsl_open()
3438 *
3439 * Called when a port is opened. Init and enable port.
3440 * Perform serial-specific initialization for the tty structure.
3441 *
3442 * Arguments: tty pointer to tty info structure
3443 * filp associated file pointer
3444 *
3445 * Return Value: 0 if success, otherwise error code
3446 */
3447static int mgsl_open(struct tty_struct *tty, struct file * filp)
3448{
3449 struct mgsl_struct *info;
3450 int retval, line;
3451 unsigned long page;
3452 unsigned long flags;
3453
3454 /* verify range of specified line number */
3455 line = tty->index;
3456 if ((line < 0) || (line >= mgsl_device_count)) {
3457 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3458 __FILE__,__LINE__,line);
3459 return -ENODEV;
3460 }
3461
3462 /* find the info structure for the specified line */
3463 info = mgsl_device_list;
3464 while(info && info->line != line)
3465 info = info->next_device;
3466 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3467 return -ENODEV;
3468
3469 tty->driver_data = info;
3470 info->tty = tty;
3471
3472 if (debug_level >= DEBUG_LEVEL_INFO)
3473 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3474 __FILE__,__LINE__,tty->driver->name, info->count);
3475
3476 /* If port is closing, signal caller to try again */
3477 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
3478 if (info->flags & ASYNC_CLOSING)
3479 interruptible_sleep_on(&info->close_wait);
3480 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
3481 -EAGAIN : -ERESTARTSYS);
3482 goto cleanup;
3483 }
3484
3485 if (!tmp_buf) {
3486 page = get_zeroed_page(GFP_KERNEL);
3487 if (!page) {
3488 retval = -ENOMEM;
3489 goto cleanup;
3490 }
3491 if (tmp_buf)
3492 free_page(page);
3493 else
3494 tmp_buf = (unsigned char *) page;
3495 }
3496
3497 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3498
3499 spin_lock_irqsave(&info->netlock, flags);
3500 if (info->netcount) {
3501 retval = -EBUSY;
3502 spin_unlock_irqrestore(&info->netlock, flags);
3503 goto cleanup;
3504 }
3505 info->count++;
3506 spin_unlock_irqrestore(&info->netlock, flags);
3507
3508 if (info->count == 1) {
3509 /* 1st open on this device, init hardware */
3510 retval = startup(info);
3511 if (retval < 0)
3512 goto cleanup;
3513 }
3514
3515 retval = block_til_ready(tty, filp, info);
3516 if (retval) {
3517 if (debug_level >= DEBUG_LEVEL_INFO)
3518 printk("%s(%d):block_til_ready(%s) returned %d\n",
3519 __FILE__,__LINE__, info->device_name, retval);
3520 goto cleanup;
3521 }
3522
3523 if (debug_level >= DEBUG_LEVEL_INFO)
3524 printk("%s(%d):mgsl_open(%s) success\n",
3525 __FILE__,__LINE__, info->device_name);
3526 retval = 0;
3527
3528cleanup:
3529 if (retval) {
3530 if (tty->count == 1)
3531 info->tty = NULL; /* tty layer will release tty struct */
3532 if(info->count)
3533 info->count--;
3534 }
3535
3536 return retval;
3537
3538} /* end of mgsl_open() */
3539
3540/*
3541 * /proc fs routines....
3542 */
3543
3544static inline int line_info(char *buf, struct mgsl_struct *info)
3545{
3546 char stat_buf[30];
3547 int ret;
3548 unsigned long flags;
3549
3550 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3551 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3552 info->device_name, info->io_base, info->irq_level,
3553 info->phys_memory_base, info->phys_lcr_base);
3554 } else {
3555 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3556 info->device_name, info->io_base,
3557 info->irq_level, info->dma_level);
3558 }
3559
3560 /* output current serial signal states */
3561 spin_lock_irqsave(&info->irq_spinlock,flags);
3562 usc_get_serial_signals(info);
3563 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3564
3565 stat_buf[0] = 0;
3566 stat_buf[1] = 0;
3567 if (info->serial_signals & SerialSignal_RTS)
3568 strcat(stat_buf, "|RTS");
3569 if (info->serial_signals & SerialSignal_CTS)
3570 strcat(stat_buf, "|CTS");
3571 if (info->serial_signals & SerialSignal_DTR)
3572 strcat(stat_buf, "|DTR");
3573 if (info->serial_signals & SerialSignal_DSR)
3574 strcat(stat_buf, "|DSR");
3575 if (info->serial_signals & SerialSignal_DCD)
3576 strcat(stat_buf, "|CD");
3577 if (info->serial_signals & SerialSignal_RI)
3578 strcat(stat_buf, "|RI");
3579
3580 if (info->params.mode == MGSL_MODE_HDLC ||
3581 info->params.mode == MGSL_MODE_RAW ) {
3582 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3583 info->icount.txok, info->icount.rxok);
3584 if (info->icount.txunder)
3585 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3586 if (info->icount.txabort)
3587 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3588 if (info->icount.rxshort)
3589 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3590 if (info->icount.rxlong)
3591 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3592 if (info->icount.rxover)
3593 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3594 if (info->icount.rxcrc)
3595 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
3596 } else {
3597 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3598 info->icount.tx, info->icount.rx);
3599 if (info->icount.frame)
3600 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3601 if (info->icount.parity)
3602 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3603 if (info->icount.brk)
3604 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3605 if (info->icount.overrun)
3606 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3607 }
3608
3609 /* Append serial signal status to end */
3610 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3611
3612 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3613 info->tx_active,info->bh_requested,info->bh_running,
3614 info->pending_bh);
3615
3616 spin_lock_irqsave(&info->irq_spinlock,flags);
3617 {
3618 u16 Tcsr = usc_InReg( info, TCSR );
3619 u16 Tdmr = usc_InDmaReg( info, TDMR );
3620 u16 Ticr = usc_InReg( info, TICR );
3621 u16 Rscr = usc_InReg( info, RCSR );
3622 u16 Rdmr = usc_InDmaReg( info, RDMR );
3623 u16 Ricr = usc_InReg( info, RICR );
3624 u16 Icr = usc_InReg( info, ICR );
3625 u16 Dccr = usc_InReg( info, DCCR );
3626 u16 Tmr = usc_InReg( info, TMR );
3627 u16 Tccr = usc_InReg( info, TCCR );
3628 u16 Ccar = inw( info->io_base + CCAR );
3629 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3630 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3631 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3632 }
3633 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3634
3635 return ret;
3636
3637} /* end of line_info() */
3638
3639/* mgsl_read_proc()
3640 *
3641 * Called to print information about devices
3642 *
3643 * Arguments:
3644 * page page of memory to hold returned info
3645 * start
3646 * off
3647 * count
3648 * eof
3649 * data
3650 *
3651 * Return Value:
3652 */
3653static int mgsl_read_proc(char *page, char **start, off_t off, int count,
3654 int *eof, void *data)
3655{
3656 int len = 0, l;
3657 off_t begin = 0;
3658 struct mgsl_struct *info;
3659
3660 len += sprintf(page, "synclink driver:%s\n", driver_version);
3661
3662 info = mgsl_device_list;
3663 while( info ) {
3664 l = line_info(page + len, info);
3665 len += l;
3666 if (len+begin > off+count)
3667 goto done;
3668 if (len+begin < off) {
3669 begin += len;
3670 len = 0;
3671 }
3672 info = info->next_device;
3673 }
3674
3675 *eof = 1;
3676done:
3677 if (off >= len+begin)
3678 return 0;
3679 *start = page + (off-begin);
3680 return ((count < begin+len-off) ? count : begin+len-off);
3681
3682} /* end of mgsl_read_proc() */
3683
3684/* mgsl_allocate_dma_buffers()
3685 *
3686 * Allocate and format DMA buffers (ISA adapter)
3687 * or format shared memory buffers (PCI adapter).
3688 *
3689 * Arguments: info pointer to device instance data
3690 * Return Value: 0 if success, otherwise error
3691 */
3692static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3693{
3694 unsigned short BuffersPerFrame;
3695
3696 info->last_mem_alloc = 0;
3697
3698 /* Calculate the number of DMA buffers necessary to hold the */
3699 /* largest allowable frame size. Note: If the max frame size is */
3700 /* not an even multiple of the DMA buffer size then we need to */
3701 /* round the buffer count per frame up one. */
3702
3703 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3704 if ( info->max_frame_size % DMABUFFERSIZE )
3705 BuffersPerFrame++;
3706
3707 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3708 /*
3709 * The PCI adapter has 256KBytes of shared memory to use.
3710 * This is 64 PAGE_SIZE buffers.
3711 *
3712 * The first page is used for padding at this time so the
3713 * buffer list does not begin at offset 0 of the PCI
3714 * adapter's shared memory.
3715 *
3716 * The 2nd page is used for the buffer list. A 4K buffer
3717 * list can hold 128 DMA_BUFFER structures at 32 bytes
3718 * each.
3719 *
3720 * This leaves 62 4K pages.
3721 *
3722 * The next N pages are used for transmit frame(s). We
3723 * reserve enough 4K page blocks to hold the required
3724 * number of transmit dma buffers (num_tx_dma_buffers),
3725 * each of MaxFrameSize size.
3726 *
3727 * Of the remaining pages (62-N), determine how many can
3728 * be used to receive full MaxFrameSize inbound frames
3729 */
3730 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3731 info->rx_buffer_count = 62 - info->tx_buffer_count;
3732 } else {
3733 /* Calculate the number of PAGE_SIZE buffers needed for */
3734 /* receive and transmit DMA buffers. */
3735
3736
3737 /* Calculate the number of DMA buffers necessary to */
3738 /* hold 7 max size receive frames and one max size transmit frame. */
3739 /* The receive buffer count is bumped by one so we avoid an */
3740 /* End of List condition if all receive buffers are used when */
3741 /* using linked list DMA buffers. */
3742
3743 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3744 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3745
3746 /*
3747 * limit total TxBuffers & RxBuffers to 62 4K total
3748 * (ala PCI Allocation)
3749 */
3750
3751 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3752 info->rx_buffer_count = 62 - info->tx_buffer_count;
3753
3754 }
3755
3756 if ( debug_level >= DEBUG_LEVEL_INFO )
3757 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3758 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3759
3760 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3761 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3762 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3763 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3764 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3765 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3766 return -ENOMEM;
3767 }
3768
3769 mgsl_reset_rx_dma_buffers( info );
3770 mgsl_reset_tx_dma_buffers( info );
3771
3772 return 0;
3773
3774} /* end of mgsl_allocate_dma_buffers() */
3775
3776/*
3777 * mgsl_alloc_buffer_list_memory()
3778 *
3779 * Allocate a common DMA buffer for use as the
3780 * receive and transmit buffer lists.
3781 *
3782 * A buffer list is a set of buffer entries where each entry contains
3783 * a pointer to an actual buffer and a pointer to the next buffer entry
3784 * (plus some other info about the buffer).
3785 *
3786 * The buffer entries for a list are built to form a circular list so
3787 * that when the entire list has been traversed you start back at the
3788 * beginning.
3789 *
3790 * This function allocates memory for just the buffer entries.
3791 * The links (pointer to next entry) are filled in with the physical
3792 * address of the next entry so the adapter can navigate the list
3793 * using bus master DMA. The pointers to the actual buffers are filled
3794 * out later when the actual buffers are allocated.
3795 *
3796 * Arguments: info pointer to device instance data
3797 * Return Value: 0 if success, otherwise error
3798 */
3799static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3800{
3801 unsigned int i;
3802
3803 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3804 /* PCI adapter uses shared memory. */
3805 info->buffer_list = info->memory_base + info->last_mem_alloc;
3806 info->buffer_list_phys = info->last_mem_alloc;
3807 info->last_mem_alloc += BUFFERLISTSIZE;
3808 } else {
3809 /* ISA adapter uses system memory. */
3810 /* The buffer lists are allocated as a common buffer that both */
3811 /* the processor and adapter can access. This allows the driver to */
3812 /* inspect portions of the buffer while other portions are being */
3813 /* updated by the adapter using Bus Master DMA. */
3814
3815 info->buffer_list = kmalloc(BUFFERLISTSIZE, GFP_KERNEL | GFP_DMA);
3816 if ( info->buffer_list == NULL )
3817 return -ENOMEM;
3818
3819 info->buffer_list_phys = isa_virt_to_bus(info->buffer_list);
3820 }
3821
3822 /* We got the memory for the buffer entry lists. */
3823 /* Initialize the memory block to all zeros. */
3824 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3825
3826 /* Save virtual address pointers to the receive and */
3827 /* transmit buffer lists. (Receive 1st). These pointers will */
3828 /* be used by the processor to access the lists. */
3829 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3830 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3831 info->tx_buffer_list += info->rx_buffer_count;
3832
3833 /*
3834 * Build the links for the buffer entry lists such that
3835 * two circular lists are built. (Transmit and Receive).
3836 *
3837 * Note: the links are physical addresses
3838 * which are read by the adapter to determine the next
3839 * buffer entry to use.
3840 */
3841
3842 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3843 /* calculate and store physical address of this buffer entry */
3844 info->rx_buffer_list[i].phys_entry =
3845 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3846
3847 /* calculate and store physical address of */
3848 /* next entry in cirular list of entries */
3849
3850 info->rx_buffer_list[i].link = info->buffer_list_phys;
3851
3852 if ( i < info->rx_buffer_count - 1 )
3853 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3854 }
3855
3856 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3857 /* calculate and store physical address of this buffer entry */
3858 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3859 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3860
3861 /* calculate and store physical address of */
3862 /* next entry in cirular list of entries */
3863
3864 info->tx_buffer_list[i].link = info->buffer_list_phys +
3865 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3866
3867 if ( i < info->tx_buffer_count - 1 )
3868 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3869 }
3870
3871 return 0;
3872
3873} /* end of mgsl_alloc_buffer_list_memory() */
3874
3875/* Free DMA buffers allocated for use as the
3876 * receive and transmit buffer lists.
3877 * Warning:
3878 *
3879 * The data transfer buffers associated with the buffer list
3880 * MUST be freed before freeing the buffer list itself because
3881 * the buffer list contains the information necessary to free
3882 * the individual buffers!
3883 */
3884static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3885{
3886 if ( info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI )
3887 kfree(info->buffer_list);
3888
3889 info->buffer_list = NULL;
3890 info->rx_buffer_list = NULL;
3891 info->tx_buffer_list = NULL;
3892
3893} /* end of mgsl_free_buffer_list_memory() */
3894
3895/*
3896 * mgsl_alloc_frame_memory()
3897 *
3898 * Allocate the frame DMA buffers used by the specified buffer list.
3899 * Each DMA buffer will be one memory page in size. This is necessary
3900 * because memory can fragment enough that it may be impossible
3901 * contiguous pages.
3902 *
3903 * Arguments:
3904 *
3905 * info pointer to device instance data
3906 * BufferList pointer to list of buffer entries
3907 * Buffercount count of buffer entries in buffer list
3908 *
3909 * Return Value: 0 if success, otherwise -ENOMEM
3910 */
3911static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3912{
3913 int i;
3914 unsigned long phys_addr;
3915
3916 /* Allocate page sized buffers for the receive buffer list */
3917
3918 for ( i = 0; i < Buffercount; i++ ) {
3919 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3920 /* PCI adapter uses shared memory buffers. */
3921 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3922 phys_addr = info->last_mem_alloc;
3923 info->last_mem_alloc += DMABUFFERSIZE;
3924 } else {
3925 /* ISA adapter uses system memory. */
3926 BufferList[i].virt_addr =
3927 kmalloc(DMABUFFERSIZE, GFP_KERNEL | GFP_DMA);
3928 if ( BufferList[i].virt_addr == NULL )
3929 return -ENOMEM;
3930 phys_addr = isa_virt_to_bus(BufferList[i].virt_addr);
3931 }
3932 BufferList[i].phys_addr = phys_addr;
3933 }
3934
3935 return 0;
3936
3937} /* end of mgsl_alloc_frame_memory() */
3938
3939/*
3940 * mgsl_free_frame_memory()
3941 *
3942 * Free the buffers associated with
3943 * each buffer entry of a buffer list.
3944 *
3945 * Arguments:
3946 *
3947 * info pointer to device instance data
3948 * BufferList pointer to list of buffer entries
3949 * Buffercount count of buffer entries in buffer list
3950 *
3951 * Return Value: None
3952 */
3953static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3954{
3955 int i;
3956
3957 if ( BufferList ) {
3958 for ( i = 0 ; i < Buffercount ; i++ ) {
3959 if ( BufferList[i].virt_addr ) {
3960 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3961 kfree(BufferList[i].virt_addr);
3962 BufferList[i].virt_addr = NULL;
3963 }
3964 }
3965 }
3966
3967} /* end of mgsl_free_frame_memory() */
3968
3969/* mgsl_free_dma_buffers()
3970 *
3971 * Free DMA buffers
3972 *
3973 * Arguments: info pointer to device instance data
3974 * Return Value: None
3975 */
3976static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3977{
3978 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3979 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3980 mgsl_free_buffer_list_memory( info );
3981
3982} /* end of mgsl_free_dma_buffers() */
3983
3984
3985/*
3986 * mgsl_alloc_intermediate_rxbuffer_memory()
3987 *
3988 * Allocate a buffer large enough to hold max_frame_size. This buffer
3989 * is used to pass an assembled frame to the line discipline.
3990 *
3991 * Arguments:
3992 *
3993 * info pointer to device instance data
3994 *
3995 * Return Value: 0 if success, otherwise -ENOMEM
3996 */
3997static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3998{
3999 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
4000 if ( info->intermediate_rxbuffer == NULL )
4001 return -ENOMEM;
4002
4003 return 0;
4004
4005} /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
4006
4007/*
4008 * mgsl_free_intermediate_rxbuffer_memory()
4009 *
4010 *
4011 * Arguments:
4012 *
4013 * info pointer to device instance data
4014 *
4015 * Return Value: None
4016 */
4017static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
4018{
4019 if ( info->intermediate_rxbuffer )
4020 kfree(info->intermediate_rxbuffer);
4021
4022 info->intermediate_rxbuffer = NULL;
4023
4024} /* end of mgsl_free_intermediate_rxbuffer_memory() */
4025
4026/*
4027 * mgsl_alloc_intermediate_txbuffer_memory()
4028 *
4029 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
4030 * This buffer is used to load transmit frames into the adapter's dma transfer
4031 * buffers when there is sufficient space.
4032 *
4033 * Arguments:
4034 *
4035 * info pointer to device instance data
4036 *
4037 * Return Value: 0 if success, otherwise -ENOMEM
4038 */
4039static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
4040{
4041 int i;
4042
4043 if ( debug_level >= DEBUG_LEVEL_INFO )
4044 printk("%s %s(%d) allocating %d tx holding buffers\n",
4045 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
4046
4047 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
4048
4049 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
4050 info->tx_holding_buffers[i].buffer =
4051 kmalloc(info->max_frame_size, GFP_KERNEL);
4052 if ( info->tx_holding_buffers[i].buffer == NULL )
4053 return -ENOMEM;
4054 }
4055
4056 return 0;
4057
4058} /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4059
4060/*
4061 * mgsl_free_intermediate_txbuffer_memory()
4062 *
4063 *
4064 * Arguments:
4065 *
4066 * info pointer to device instance data
4067 *
4068 * Return Value: None
4069 */
4070static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4071{
4072 int i;
4073
4074 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4075 if ( info->tx_holding_buffers[i].buffer ) {
4076 kfree(info->tx_holding_buffers[i].buffer);
4077 info->tx_holding_buffers[i].buffer=NULL;
4078 }
4079 }
4080
4081 info->get_tx_holding_index = 0;
4082 info->put_tx_holding_index = 0;
4083 info->tx_holding_count = 0;
4084
4085} /* end of mgsl_free_intermediate_txbuffer_memory() */
4086
4087
4088/*
4089 * load_next_tx_holding_buffer()
4090 *
4091 * attempts to load the next buffered tx request into the
4092 * tx dma buffers
4093 *
4094 * Arguments:
4095 *
4096 * info pointer to device instance data
4097 *
4098 * Return Value: 1 if next buffered tx request loaded
4099 * into adapter's tx dma buffer,
4100 * 0 otherwise
4101 */
4102static int load_next_tx_holding_buffer(struct mgsl_struct *info)
4103{
4104 int ret = 0;
4105
4106 if ( info->tx_holding_count ) {
4107 /* determine if we have enough tx dma buffers
4108 * to accommodate the next tx frame
4109 */
4110 struct tx_holding_buffer *ptx =
4111 &info->tx_holding_buffers[info->get_tx_holding_index];
4112 int num_free = num_free_tx_dma_buffers(info);
4113 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4114 if ( ptx->buffer_size % DMABUFFERSIZE )
4115 ++num_needed;
4116
4117 if (num_needed <= num_free) {
4118 info->xmit_cnt = ptx->buffer_size;
4119 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4120
4121 --info->tx_holding_count;
4122 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4123 info->get_tx_holding_index=0;
4124
4125 /* restart transmit timer */
4126 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4127
4128 ret = 1;
4129 }
4130 }
4131
4132 return ret;
4133}
4134
4135/*
4136 * save_tx_buffer_request()
4137 *
4138 * attempt to store transmit frame request for later transmission
4139 *
4140 * Arguments:
4141 *
4142 * info pointer to device instance data
4143 * Buffer pointer to buffer containing frame to load
4144 * BufferSize size in bytes of frame in Buffer
4145 *
4146 * Return Value: 1 if able to store, 0 otherwise
4147 */
4148static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4149{
4150 struct tx_holding_buffer *ptx;
4151
4152 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4153 return 0; /* all buffers in use */
4154 }
4155
4156 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4157 ptx->buffer_size = BufferSize;
4158 memcpy( ptx->buffer, Buffer, BufferSize);
4159
4160 ++info->tx_holding_count;
4161 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4162 info->put_tx_holding_index=0;
4163
4164 return 1;
4165}
4166
4167static int mgsl_claim_resources(struct mgsl_struct *info)
4168{
4169 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4170 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4171 __FILE__,__LINE__,info->device_name, info->io_base);
4172 return -ENODEV;
4173 }
4174 info->io_addr_requested = 1;
4175
4176 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4177 info->device_name, info ) < 0 ) {
4178 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4179 __FILE__,__LINE__,info->device_name, info->irq_level );
4180 goto errout;
4181 }
4182 info->irq_requested = 1;
4183
4184 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4185 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4186 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4187 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4188 goto errout;
4189 }
4190 info->shared_mem_requested = 1;
4191 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4192 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4193 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4194 goto errout;
4195 }
4196 info->lcr_mem_requested = 1;
4197
4198 info->memory_base = ioremap(info->phys_memory_base,0x40000);
4199 if (!info->memory_base) {
4200 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4201 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4202 goto errout;
4203 }
4204
4205 if ( !mgsl_memory_test(info) ) {
4206 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4207 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4208 goto errout;
4209 }
4210
4211 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
4212 if (!info->lcr_base) {
4213 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4214 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4215 goto errout;
4216 }
4217
4218 } else {
4219 /* claim DMA channel */
4220
4221 if (request_dma(info->dma_level,info->device_name) < 0){
4222 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4223 __FILE__,__LINE__,info->device_name, info->dma_level );
4224 mgsl_release_resources( info );
4225 return -ENODEV;
4226 }
4227 info->dma_requested = 1;
4228
4229 /* ISA adapter uses bus master DMA */
4230 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4231 enable_dma(info->dma_level);
4232 }
4233
4234 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4235 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4236 __FILE__,__LINE__,info->device_name, info->dma_level );
4237 goto errout;
4238 }
4239
4240 return 0;
4241errout:
4242 mgsl_release_resources(info);
4243 return -ENODEV;
4244
4245} /* end of mgsl_claim_resources() */
4246
4247static void mgsl_release_resources(struct mgsl_struct *info)
4248{
4249 if ( debug_level >= DEBUG_LEVEL_INFO )
4250 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4251 __FILE__,__LINE__,info->device_name );
4252
4253 if ( info->irq_requested ) {
4254 free_irq(info->irq_level, info);
4255 info->irq_requested = 0;
4256 }
4257 if ( info->dma_requested ) {
4258 disable_dma(info->dma_level);
4259 free_dma(info->dma_level);
4260 info->dma_requested = 0;
4261 }
4262 mgsl_free_dma_buffers(info);
4263 mgsl_free_intermediate_rxbuffer_memory(info);
4264 mgsl_free_intermediate_txbuffer_memory(info);
4265
4266 if ( info->io_addr_requested ) {
4267 release_region(info->io_base,info->io_addr_size);
4268 info->io_addr_requested = 0;
4269 }
4270 if ( info->shared_mem_requested ) {
4271 release_mem_region(info->phys_memory_base,0x40000);
4272 info->shared_mem_requested = 0;
4273 }
4274 if ( info->lcr_mem_requested ) {
4275 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4276 info->lcr_mem_requested = 0;
4277 }
4278 if (info->memory_base){
4279 iounmap(info->memory_base);
4280 info->memory_base = NULL;
4281 }
4282 if (info->lcr_base){
4283 iounmap(info->lcr_base - info->lcr_offset);
4284 info->lcr_base = NULL;
4285 }
4286
4287 if ( debug_level >= DEBUG_LEVEL_INFO )
4288 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4289 __FILE__,__LINE__,info->device_name );
4290
4291} /* end of mgsl_release_resources() */
4292
4293/* mgsl_add_device()
4294 *
4295 * Add the specified device instance data structure to the
4296 * global linked list of devices and increment the device count.
4297 *
4298 * Arguments: info pointer to device instance data
4299 * Return Value: None
4300 */
4301static void mgsl_add_device( struct mgsl_struct *info )
4302{
4303 info->next_device = NULL;
4304 info->line = mgsl_device_count;
4305 sprintf(info->device_name,"ttySL%d",info->line);
4306
4307 if (info->line < MAX_TOTAL_DEVICES) {
4308 if (maxframe[info->line])
4309 info->max_frame_size = maxframe[info->line];
4310 info->dosyncppp = dosyncppp[info->line];
4311
4312 if (txdmabufs[info->line]) {
4313 info->num_tx_dma_buffers = txdmabufs[info->line];
4314 if (info->num_tx_dma_buffers < 1)
4315 info->num_tx_dma_buffers = 1;
4316 }
4317
4318 if (txholdbufs[info->line]) {
4319 info->num_tx_holding_buffers = txholdbufs[info->line];
4320 if (info->num_tx_holding_buffers < 1)
4321 info->num_tx_holding_buffers = 1;
4322 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4323 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4324 }
4325 }
4326
4327 mgsl_device_count++;
4328
4329 if ( !mgsl_device_list )
4330 mgsl_device_list = info;
4331 else {
4332 struct mgsl_struct *current_dev = mgsl_device_list;
4333 while( current_dev->next_device )
4334 current_dev = current_dev->next_device;
4335 current_dev->next_device = info;
4336 }
4337
4338 if ( info->max_frame_size < 4096 )
4339 info->max_frame_size = 4096;
4340 else if ( info->max_frame_size > 65535 )
4341 info->max_frame_size = 65535;
4342
4343 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4344 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4345 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4346 info->phys_memory_base, info->phys_lcr_base,
4347 info->max_frame_size );
4348 } else {
4349 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4350 info->device_name, info->io_base, info->irq_level, info->dma_level,
4351 info->max_frame_size );
4352 }
4353
4354#ifdef CONFIG_HDLC
4355 hdlcdev_init(info);
4356#endif
4357
4358} /* end of mgsl_add_device() */
4359
4360/* mgsl_allocate_device()
4361 *
4362 * Allocate and initialize a device instance structure
4363 *
4364 * Arguments: none
4365 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4366 */
4367static struct mgsl_struct* mgsl_allocate_device(void)
4368{
4369 struct mgsl_struct *info;
4370
4371 info = (struct mgsl_struct *)kmalloc(sizeof(struct mgsl_struct),
4372 GFP_KERNEL);
4373
4374 if (!info) {
4375 printk("Error can't allocate device instance data\n");
4376 } else {
4377 memset(info, 0, sizeof(struct mgsl_struct));
4378 info->magic = MGSL_MAGIC;
4379 INIT_WORK(&info->task, mgsl_bh_handler, info);
4380 info->max_frame_size = 4096;
4381 info->close_delay = 5*HZ/10;
4382 info->closing_wait = 30*HZ;
4383 init_waitqueue_head(&info->open_wait);
4384 init_waitqueue_head(&info->close_wait);
4385 init_waitqueue_head(&info->status_event_wait_q);
4386 init_waitqueue_head(&info->event_wait_q);
4387 spin_lock_init(&info->irq_spinlock);
4388 spin_lock_init(&info->netlock);
4389 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4390 info->idle_mode = HDLC_TXIDLE_FLAGS;
4391 info->num_tx_dma_buffers = 1;
4392 info->num_tx_holding_buffers = 0;
4393 }
4394
4395 return info;
4396
4397} /* end of mgsl_allocate_device()*/
4398
4399static struct tty_operations mgsl_ops = {
4400 .open = mgsl_open,
4401 .close = mgsl_close,
4402 .write = mgsl_write,
4403 .put_char = mgsl_put_char,
4404 .flush_chars = mgsl_flush_chars,
4405 .write_room = mgsl_write_room,
4406 .chars_in_buffer = mgsl_chars_in_buffer,
4407 .flush_buffer = mgsl_flush_buffer,
4408 .ioctl = mgsl_ioctl,
4409 .throttle = mgsl_throttle,
4410 .unthrottle = mgsl_unthrottle,
4411 .send_xchar = mgsl_send_xchar,
4412 .break_ctl = mgsl_break,
4413 .wait_until_sent = mgsl_wait_until_sent,
4414 .read_proc = mgsl_read_proc,
4415 .set_termios = mgsl_set_termios,
4416 .stop = mgsl_stop,
4417 .start = mgsl_start,
4418 .hangup = mgsl_hangup,
4419 .tiocmget = tiocmget,
4420 .tiocmset = tiocmset,
4421};
4422
4423/*
4424 * perform tty device initialization
4425 */
4426static int mgsl_init_tty(void)
4427{
4428 int rc;
4429
4430 serial_driver = alloc_tty_driver(128);
4431 if (!serial_driver)
4432 return -ENOMEM;
4433
4434 serial_driver->owner = THIS_MODULE;
4435 serial_driver->driver_name = "synclink";
4436 serial_driver->name = "ttySL";
4437 serial_driver->major = ttymajor;
4438 serial_driver->minor_start = 64;
4439 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4440 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4441 serial_driver->init_termios = tty_std_termios;
4442 serial_driver->init_termios.c_cflag =
4443 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4444 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4445 tty_set_operations(serial_driver, &mgsl_ops);
4446 if ((rc = tty_register_driver(serial_driver)) < 0) {
4447 printk("%s(%d):Couldn't register serial driver\n",
4448 __FILE__,__LINE__);
4449 put_tty_driver(serial_driver);
4450 serial_driver = NULL;
4451 return rc;
4452 }
4453
4454 printk("%s %s, tty major#%d\n",
4455 driver_name, driver_version,
4456 serial_driver->major);
4457 return 0;
4458}
4459
4460/* enumerate user specified ISA adapters
4461 */
4462static void mgsl_enum_isa_devices(void)
4463{
4464 struct mgsl_struct *info;
4465 int i;
4466
4467 /* Check for user specified ISA devices */
4468
4469 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4470 if ( debug_level >= DEBUG_LEVEL_INFO )
4471 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4472 io[i], irq[i], dma[i] );
4473
4474 info = mgsl_allocate_device();
4475 if ( !info ) {
4476 /* error allocating device instance data */
4477 if ( debug_level >= DEBUG_LEVEL_ERROR )
4478 printk( "can't allocate device instance data.\n");
4479 continue;
4480 }
4481
4482 /* Copy user configuration info to device instance data */
4483 info->io_base = (unsigned int)io[i];
4484 info->irq_level = (unsigned int)irq[i];
4485 info->irq_level = irq_canonicalize(info->irq_level);
4486 info->dma_level = (unsigned int)dma[i];
4487 info->bus_type = MGSL_BUS_TYPE_ISA;
4488 info->io_addr_size = 16;
4489 info->irq_flags = 0;
4490
4491 mgsl_add_device( info );
4492 }
4493}
4494
4495static void synclink_cleanup(void)
4496{
4497 int rc;
4498 struct mgsl_struct *info;
4499 struct mgsl_struct *tmp;
4500
4501 printk("Unloading %s: %s\n", driver_name, driver_version);
4502
4503 if (serial_driver) {
4504 if ((rc = tty_unregister_driver(serial_driver)))
4505 printk("%s(%d) failed to unregister tty driver err=%d\n",
4506 __FILE__,__LINE__,rc);
4507 put_tty_driver(serial_driver);
4508 }
4509
4510 info = mgsl_device_list;
4511 while(info) {
4512#ifdef CONFIG_HDLC
4513 hdlcdev_exit(info);
4514#endif
4515 mgsl_release_resources(info);
4516 tmp = info;
4517 info = info->next_device;
4518 kfree(tmp);
4519 }
4520
4521 if (tmp_buf) {
4522 free_page((unsigned long) tmp_buf);
4523 tmp_buf = NULL;
4524 }
4525
4526 if (pci_registered)
4527 pci_unregister_driver(&synclink_pci_driver);
4528}
4529
4530static int __init synclink_init(void)
4531{
4532 int rc;
4533
4534 if (break_on_load) {
4535 mgsl_get_text_ptr();
4536 BREAKPOINT();
4537 }
4538
4539 printk("%s %s\n", driver_name, driver_version);
4540
4541 mgsl_enum_isa_devices();
4542 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4543 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4544 else
4545 pci_registered = 1;
4546
4547 if ((rc = mgsl_init_tty()) < 0)
4548 goto error;
4549
4550 return 0;
4551
4552error:
4553 synclink_cleanup();
4554 return rc;
4555}
4556
4557static void __exit synclink_exit(void)
4558{
4559 synclink_cleanup();
4560}
4561
4562module_init(synclink_init);
4563module_exit(synclink_exit);
4564
4565/*
4566 * usc_RTCmd()
4567 *
4568 * Issue a USC Receive/Transmit command to the
4569 * Channel Command/Address Register (CCAR).
4570 *
4571 * Notes:
4572 *
4573 * The command is encoded in the most significant 5 bits <15..11>
4574 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4575 * and Bits <6..0> must be written as zeros.
4576 *
4577 * Arguments:
4578 *
4579 * info pointer to device information structure
4580 * Cmd command mask (use symbolic macros)
4581 *
4582 * Return Value:
4583 *
4584 * None
4585 */
4586static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4587{
4588 /* output command to CCAR in bits <15..11> */
4589 /* preserve bits <10..7>, bits <6..0> must be zero */
4590
4591 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4592
4593 /* Read to flush write to CCAR */
4594 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4595 inw( info->io_base + CCAR );
4596
4597} /* end of usc_RTCmd() */
4598
4599/*
4600 * usc_DmaCmd()
4601 *
4602 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4603 *
4604 * Arguments:
4605 *
4606 * info pointer to device information structure
4607 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4608 *
4609 * Return Value:
4610 *
4611 * None
4612 */
4613static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4614{
4615 /* write command mask to DCAR */
4616 outw( Cmd + info->mbre_bit, info->io_base );
4617
4618 /* Read to flush write to DCAR */
4619 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4620 inw( info->io_base );
4621
4622} /* end of usc_DmaCmd() */
4623
4624/*
4625 * usc_OutDmaReg()
4626 *
4627 * Write a 16-bit value to a USC DMA register
4628 *
4629 * Arguments:
4630 *
4631 * info pointer to device info structure
4632 * RegAddr register address (number) for write
4633 * RegValue 16-bit value to write to register
4634 *
4635 * Return Value:
4636 *
4637 * None
4638 *
4639 */
4640static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4641{
4642 /* Note: The DCAR is located at the adapter base address */
4643 /* Note: must preserve state of BIT8 in DCAR */
4644
4645 outw( RegAddr + info->mbre_bit, info->io_base );
4646 outw( RegValue, info->io_base );
4647
4648 /* Read to flush write to DCAR */
4649 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4650 inw( info->io_base );
4651
4652} /* end of usc_OutDmaReg() */
4653
4654/*
4655 * usc_InDmaReg()
4656 *
4657 * Read a 16-bit value from a DMA register
4658 *
4659 * Arguments:
4660 *
4661 * info pointer to device info structure
4662 * RegAddr register address (number) to read from
4663 *
4664 * Return Value:
4665 *
4666 * The 16-bit value read from register
4667 *
4668 */
4669static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4670{
4671 /* Note: The DCAR is located at the adapter base address */
4672 /* Note: must preserve state of BIT8 in DCAR */
4673
4674 outw( RegAddr + info->mbre_bit, info->io_base );
4675 return inw( info->io_base );
4676
4677} /* end of usc_InDmaReg() */
4678
4679/*
4680 *
4681 * usc_OutReg()
4682 *
4683 * Write a 16-bit value to a USC serial channel register
4684 *
4685 * Arguments:
4686 *
4687 * info pointer to device info structure
4688 * RegAddr register address (number) to write to
4689 * RegValue 16-bit value to write to register
4690 *
4691 * Return Value:
4692 *
4693 * None
4694 *
4695 */
4696static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4697{
4698 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4699 outw( RegValue, info->io_base + CCAR );
4700
4701 /* Read to flush write to CCAR */
4702 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4703 inw( info->io_base + CCAR );
4704
4705} /* end of usc_OutReg() */
4706
4707/*
4708 * usc_InReg()
4709 *
4710 * Reads a 16-bit value from a USC serial channel register
4711 *
4712 * Arguments:
4713 *
4714 * info pointer to device extension
4715 * RegAddr register address (number) to read from
4716 *
4717 * Return Value:
4718 *
4719 * 16-bit value read from register
4720 */
4721static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4722{
4723 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4724 return inw( info->io_base + CCAR );
4725
4726} /* end of usc_InReg() */
4727
4728/* usc_set_sdlc_mode()
4729 *
4730 * Set up the adapter for SDLC DMA communications.
4731 *
4732 * Arguments: info pointer to device instance data
4733 * Return Value: NONE
4734 */
4735static void usc_set_sdlc_mode( struct mgsl_struct *info )
4736{
4737 u16 RegValue;
4738 int PreSL1660;
4739
4740 /*
4741 * determine if the IUSC on the adapter is pre-SL1660. If
4742 * not, take advantage of the UnderWait feature of more
4743 * modern chips. If an underrun occurs and this bit is set,
4744 * the transmitter will idle the programmed idle pattern
4745 * until the driver has time to service the underrun. Otherwise,
4746 * the dma controller may get the cycles previously requested
4747 * and begin transmitting queued tx data.
4748 */
4749 usc_OutReg(info,TMCR,0x1f);
4750 RegValue=usc_InReg(info,TMDR);
4751 if ( RegValue == IUSC_PRE_SL1660 )
4752 PreSL1660 = 1;
4753 else
4754 PreSL1660 = 0;
4755
4756
4757 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4758 {
4759 /*
4760 ** Channel Mode Register (CMR)
4761 **
4762 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4763 ** <13> 0 0 = Transmit Disabled (initially)
4764 ** <12> 0 1 = Consecutive Idles share common 0
4765 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4766 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4767 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4768 **
4769 ** 1000 1110 0000 0110 = 0x8e06
4770 */
4771 RegValue = 0x8e06;
4772
4773 /*--------------------------------------------------
4774 * ignore user options for UnderRun Actions and
4775 * preambles
4776 *--------------------------------------------------*/
4777 }
4778 else
4779 {
4780 /* Channel mode Register (CMR)
4781 *
4782 * <15..14> 00 Tx Sub modes, Underrun Action
4783 * <13> 0 1 = Send Preamble before opening flag
4784 * <12> 0 1 = Consecutive Idles share common 0
4785 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4786 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4787 * <3..0> 0110 Receiver mode = HDLC/SDLC
4788 *
4789 * 0000 0110 0000 0110 = 0x0606
4790 */
4791 if (info->params.mode == MGSL_MODE_RAW) {
4792 RegValue = 0x0001; /* Set Receive mode = external sync */
4793
4794 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4795 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4796
4797 /*
4798 * TxSubMode:
4799 * CMR <15> 0 Don't send CRC on Tx Underrun
4800 * CMR <14> x undefined
4801 * CMR <13> 0 Send preamble before openning sync
4802 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4803 *
4804 * TxMode:
4805 * CMR <11-8) 0100 MonoSync
4806 *
4807 * 0x00 0100 xxxx xxxx 04xx
4808 */
4809 RegValue |= 0x0400;
4810 }
4811 else {
4812
4813 RegValue = 0x0606;
4814
4815 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4816 RegValue |= BIT14;
4817 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4818 RegValue |= BIT15;
4819 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4820 RegValue |= BIT15 + BIT14;
4821 }
4822
4823 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4824 RegValue |= BIT13;
4825 }
4826
4827 if ( info->params.mode == MGSL_MODE_HDLC &&
4828 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4829 RegValue |= BIT12;
4830
4831 if ( info->params.addr_filter != 0xff )
4832 {
4833 /* set up receive address filtering */
4834 usc_OutReg( info, RSR, info->params.addr_filter );
4835 RegValue |= BIT4;
4836 }
4837
4838 usc_OutReg( info, CMR, RegValue );
4839 info->cmr_value = RegValue;
4840
4841 /* Receiver mode Register (RMR)
4842 *
4843 * <15..13> 000 encoding
4844 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4845 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4846 * <9> 0 1 = Include Receive chars in CRC
4847 * <8> 1 1 = Use Abort/PE bit as abort indicator
4848 * <7..6> 00 Even parity
4849 * <5> 0 parity disabled
4850 * <4..2> 000 Receive Char Length = 8 bits
4851 * <1..0> 00 Disable Receiver
4852 *
4853 * 0000 0101 0000 0000 = 0x0500
4854 */
4855
4856 RegValue = 0x0500;
4857
4858 switch ( info->params.encoding ) {
4859 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4860 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4861 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4862 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4863 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4864 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4865 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4866 }
4867
4868 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4869 RegValue |= BIT9;
4870 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4871 RegValue |= ( BIT12 | BIT10 | BIT9 );
4872
4873 usc_OutReg( info, RMR, RegValue );
4874
4875 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4876 /* When an opening flag of an SDLC frame is recognized the */
4877 /* Receive Character count (RCC) is loaded with the value in */
4878 /* RCLR. The RCC is decremented for each received byte. The */
4879 /* value of RCC is stored after the closing flag of the frame */
4880 /* allowing the frame size to be computed. */
4881
4882 usc_OutReg( info, RCLR, RCLRVALUE );
4883
4884 usc_RCmd( info, RCmd_SelectRicrdma_level );
4885
4886 /* Receive Interrupt Control Register (RICR)
4887 *
4888 * <15..8> ? RxFIFO DMA Request Level
4889 * <7> 0 Exited Hunt IA (Interrupt Arm)
4890 * <6> 0 Idle Received IA
4891 * <5> 0 Break/Abort IA
4892 * <4> 0 Rx Bound IA
4893 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4894 * <2> 0 Abort/PE IA
4895 * <1> 1 Rx Overrun IA
4896 * <0> 0 Select TC0 value for readback
4897 *
4898 * 0000 0000 0000 1000 = 0x000a
4899 */
4900
4901 /* Carry over the Exit Hunt and Idle Received bits */
4902 /* in case they have been armed by usc_ArmEvents. */
4903
4904 RegValue = usc_InReg( info, RICR ) & 0xc0;
4905
4906 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4907 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4908 else
4909 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4910
4911 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4912
4913 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4914 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4915
4916 /* Transmit mode Register (TMR)
4917 *
4918 * <15..13> 000 encoding
4919 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4920 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4921 * <9> 0 1 = Tx CRC Enabled
4922 * <8> 0 1 = Append CRC to end of transmit frame
4923 * <7..6> 00 Transmit parity Even
4924 * <5> 0 Transmit parity Disabled
4925 * <4..2> 000 Tx Char Length = 8 bits
4926 * <1..0> 00 Disable Transmitter
4927 *
4928 * 0000 0100 0000 0000 = 0x0400
4929 */
4930
4931 RegValue = 0x0400;
4932
4933 switch ( info->params.encoding ) {
4934 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4935 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4936 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4937 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4938 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4939 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4940 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4941 }
4942
4943 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4944 RegValue |= BIT9 + BIT8;
4945 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4946 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4947
4948 usc_OutReg( info, TMR, RegValue );
4949
4950 usc_set_txidle( info );
4951
4952
4953 usc_TCmd( info, TCmd_SelectTicrdma_level );
4954
4955 /* Transmit Interrupt Control Register (TICR)
4956 *
4957 * <15..8> ? Transmit FIFO DMA Level
4958 * <7> 0 Present IA (Interrupt Arm)
4959 * <6> 0 Idle Sent IA
4960 * <5> 1 Abort Sent IA
4961 * <4> 1 EOF/EOM Sent IA
4962 * <3> 0 CRC Sent IA
4963 * <2> 1 1 = Wait for SW Trigger to Start Frame
4964 * <1> 1 Tx Underrun IA
4965 * <0> 0 TC0 constant on read back
4966 *
4967 * 0000 0000 0011 0110 = 0x0036
4968 */
4969
4970 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4971 usc_OutReg( info, TICR, 0x0736 );
4972 else
4973 usc_OutReg( info, TICR, 0x1436 );
4974
4975 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4976 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4977
4978 /*
4979 ** Transmit Command/Status Register (TCSR)
4980 **
4981 ** <15..12> 0000 TCmd
4982 ** <11> 0/1 UnderWait
4983 ** <10..08> 000 TxIdle
4984 ** <7> x PreSent
4985 ** <6> x IdleSent
4986 ** <5> x AbortSent
4987 ** <4> x EOF/EOM Sent
4988 ** <3> x CRC Sent
4989 ** <2> x All Sent
4990 ** <1> x TxUnder
4991 ** <0> x TxEmpty
4992 **
4993 ** 0000 0000 0000 0000 = 0x0000
4994 */
4995 info->tcsr_value = 0;
4996
4997 if ( !PreSL1660 )
4998 info->tcsr_value |= TCSR_UNDERWAIT;
4999
5000 usc_OutReg( info, TCSR, info->tcsr_value );
5001
5002 /* Clock mode Control Register (CMCR)
5003 *
5004 * <15..14> 00 counter 1 Source = Disabled
5005 * <13..12> 00 counter 0 Source = Disabled
5006 * <11..10> 11 BRG1 Input is TxC Pin
5007 * <9..8> 11 BRG0 Input is TxC Pin
5008 * <7..6> 01 DPLL Input is BRG1 Output
5009 * <5..3> XXX TxCLK comes from Port 0
5010 * <2..0> XXX RxCLK comes from Port 1
5011 *
5012 * 0000 1111 0111 0111 = 0x0f77
5013 */
5014
5015 RegValue = 0x0f40;
5016
5017 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
5018 RegValue |= 0x0003; /* RxCLK from DPLL */
5019 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
5020 RegValue |= 0x0004; /* RxCLK from BRG0 */
5021 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
5022 RegValue |= 0x0006; /* RxCLK from TXC Input */
5023 else
5024 RegValue |= 0x0007; /* RxCLK from Port1 */
5025
5026 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
5027 RegValue |= 0x0018; /* TxCLK from DPLL */
5028 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
5029 RegValue |= 0x0020; /* TxCLK from BRG0 */
5030 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
5031 RegValue |= 0x0038; /* RxCLK from TXC Input */
5032 else
5033 RegValue |= 0x0030; /* TxCLK from Port0 */
5034
5035 usc_OutReg( info, CMCR, RegValue );
5036
5037
5038 /* Hardware Configuration Register (HCR)
5039 *
5040 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5041 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5042 * <12> 0 CVOK:0=report code violation in biphase
5043 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5044 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5045 * <7..6> 00 reserved
5046 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5047 * <4> X BRG1 Enable
5048 * <3..2> 00 reserved
5049 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5050 * <0> 0 BRG0 Enable
5051 */
5052
5053 RegValue = 0x0000;
5054
5055 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
5056 u32 XtalSpeed;
5057 u32 DpllDivisor;
5058 u16 Tc;
5059
5060 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5061 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5062
5063 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5064 XtalSpeed = 11059200;
5065 else
5066 XtalSpeed = 14745600;
5067
5068 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5069 DpllDivisor = 16;
5070 RegValue |= BIT10;
5071 }
5072 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5073 DpllDivisor = 8;
5074 RegValue |= BIT11;
5075 }
5076 else
5077 DpllDivisor = 32;
5078
5079 /* Tc = (Xtal/Speed) - 1 */
5080 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5081 /* then rounding up gives a more precise time constant. Instead */
5082 /* of rounding up and then subtracting 1 we just don't subtract */
5083 /* the one in this case. */
5084
5085 /*--------------------------------------------------
5086 * ejz: for DPLL mode, application should use the
5087 * same clock speed as the partner system, even
5088 * though clocking is derived from the input RxData.
5089 * In case the user uses a 0 for the clock speed,
5090 * default to 0xffffffff and don't try to divide by
5091 * zero
5092 *--------------------------------------------------*/
5093 if ( info->params.clock_speed )
5094 {
5095 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5096 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5097 / info->params.clock_speed) )
5098 Tc--;
5099 }
5100 else
5101 Tc = -1;
5102
5103
5104 /* Write 16-bit Time Constant for BRG1 */
5105 usc_OutReg( info, TC1R, Tc );
5106
5107 RegValue |= BIT4; /* enable BRG1 */
5108
5109 switch ( info->params.encoding ) {
5110 case HDLC_ENCODING_NRZ:
5111 case HDLC_ENCODING_NRZB:
5112 case HDLC_ENCODING_NRZI_MARK:
5113 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5114 case HDLC_ENCODING_BIPHASE_MARK:
5115 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5116 case HDLC_ENCODING_BIPHASE_LEVEL:
5117 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5118 }
5119 }
5120
5121 usc_OutReg( info, HCR, RegValue );
5122
5123
5124 /* Channel Control/status Register (CCSR)
5125 *
5126 * <15> X RCC FIFO Overflow status (RO)
5127 * <14> X RCC FIFO Not Empty status (RO)
5128 * <13> 0 1 = Clear RCC FIFO (WO)
5129 * <12> X DPLL Sync (RW)
5130 * <11> X DPLL 2 Missed Clocks status (RO)
5131 * <10> X DPLL 1 Missed Clock status (RO)
5132 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5133 * <7> X SDLC Loop On status (RO)
5134 * <6> X SDLC Loop Send status (RO)
5135 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5136 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5137 * <1..0> 00 reserved
5138 *
5139 * 0000 0000 0010 0000 = 0x0020
5140 */
5141
5142 usc_OutReg( info, CCSR, 0x1020 );
5143
5144
5145 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5146 usc_OutReg( info, SICR,
5147 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5148 }
5149
5150
5151 /* enable Master Interrupt Enable bit (MIE) */
5152 usc_EnableMasterIrqBit( info );
5153
5154 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5155 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5156
5157 /* arm RCC underflow interrupt */
5158 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5159 usc_EnableInterrupts(info, MISC);
5160
5161 info->mbre_bit = 0;
5162 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5163 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5164 info->mbre_bit = BIT8;
5165 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5166
5167 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5168 /* Enable DMAEN (Port 7, Bit 14) */
5169 /* This connects the DMA request signal to the ISA bus */
5170 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5171 }
5172
5173 /* DMA Control Register (DCR)
5174 *
5175 * <15..14> 10 Priority mode = Alternating Tx/Rx
5176 * 01 Rx has priority
5177 * 00 Tx has priority
5178 *
5179 * <13> 1 Enable Priority Preempt per DCR<15..14>
5180 * (WARNING DCR<11..10> must be 00 when this is 1)
5181 * 0 Choose activate channel per DCR<11..10>
5182 *
5183 * <12> 0 Little Endian for Array/List
5184 * <11..10> 00 Both Channels can use each bus grant
5185 * <9..6> 0000 reserved
5186 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5187 * <4> 0 1 = drive D/C and S/D pins
5188 * <3> 1 1 = Add one wait state to all DMA cycles.
5189 * <2> 0 1 = Strobe /UAS on every transfer.
5190 * <1..0> 11 Addr incrementing only affects LS24 bits
5191 *
5192 * 0110 0000 0000 1011 = 0x600b
5193 */
5194
5195 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5196 /* PCI adapter does not need DMA wait state */
5197 usc_OutDmaReg( info, DCR, 0xa00b );
5198 }
5199 else
5200 usc_OutDmaReg( info, DCR, 0x800b );
5201
5202
5203 /* Receive DMA mode Register (RDMR)
5204 *
5205 * <15..14> 11 DMA mode = Linked List Buffer mode
5206 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5207 * <12> 1 Clear count of List Entry after fetching
5208 * <11..10> 00 Address mode = Increment
5209 * <9> 1 Terminate Buffer on RxBound
5210 * <8> 0 Bus Width = 16bits
5211 * <7..0> ? status Bits (write as 0s)
5212 *
5213 * 1111 0010 0000 0000 = 0xf200
5214 */
5215
5216 usc_OutDmaReg( info, RDMR, 0xf200 );
5217
5218
5219 /* Transmit DMA mode Register (TDMR)
5220 *
5221 * <15..14> 11 DMA mode = Linked List Buffer mode
5222 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5223 * <12> 1 Clear count of List Entry after fetching
5224 * <11..10> 00 Address mode = Increment
5225 * <9> 1 Terminate Buffer on end of frame
5226 * <8> 0 Bus Width = 16bits
5227 * <7..0> ? status Bits (Read Only so write as 0)
5228 *
5229 * 1111 0010 0000 0000 = 0xf200
5230 */
5231
5232 usc_OutDmaReg( info, TDMR, 0xf200 );
5233
5234
5235 /* DMA Interrupt Control Register (DICR)
5236 *
5237 * <15> 1 DMA Interrupt Enable
5238 * <14> 0 1 = Disable IEO from USC
5239 * <13> 0 1 = Don't provide vector during IntAck
5240 * <12> 1 1 = Include status in Vector
5241 * <10..2> 0 reserved, Must be 0s
5242 * <1> 0 1 = Rx DMA Interrupt Enabled
5243 * <0> 0 1 = Tx DMA Interrupt Enabled
5244 *
5245 * 1001 0000 0000 0000 = 0x9000
5246 */
5247
5248 usc_OutDmaReg( info, DICR, 0x9000 );
5249
5250 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5251 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5252 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5253
5254 /* Channel Control Register (CCR)
5255 *
5256 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5257 * <13> 0 Trigger Tx on SW Command Disabled
5258 * <12> 0 Flag Preamble Disabled
5259 * <11..10> 00 Preamble Length
5260 * <9..8> 00 Preamble Pattern
5261 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5262 * <5> 0 Trigger Rx on SW Command Disabled
5263 * <4..0> 0 reserved
5264 *
5265 * 1000 0000 1000 0000 = 0x8080
5266 */
5267
5268 RegValue = 0x8080;
5269
5270 switch ( info->params.preamble_length ) {
5271 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5272 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5273 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5274 }
5275
5276 switch ( info->params.preamble ) {
5277 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5278 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5279 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5280 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5281 }
5282
5283 usc_OutReg( info, CCR, RegValue );
5284
5285
5286 /*
5287 * Burst/Dwell Control Register
5288 *
5289 * <15..8> 0x20 Maximum number of transfers per bus grant
5290 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5291 */
5292
5293 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5294 /* don't limit bus occupancy on PCI adapter */
5295 usc_OutDmaReg( info, BDCR, 0x0000 );
5296 }
5297 else
5298 usc_OutDmaReg( info, BDCR, 0x2000 );
5299
5300 usc_stop_transmitter(info);
5301 usc_stop_receiver(info);
5302
5303} /* end of usc_set_sdlc_mode() */
5304
5305/* usc_enable_loopback()
5306 *
5307 * Set the 16C32 for internal loopback mode.
5308 * The TxCLK and RxCLK signals are generated from the BRG0 and
5309 * the TxD is looped back to the RxD internally.
5310 *
5311 * Arguments: info pointer to device instance data
5312 * enable 1 = enable loopback, 0 = disable
5313 * Return Value: None
5314 */
5315static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5316{
5317 if (enable) {
5318 /* blank external TXD output */
5319 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5320
5321 /* Clock mode Control Register (CMCR)
5322 *
5323 * <15..14> 00 counter 1 Disabled
5324 * <13..12> 00 counter 0 Disabled
5325 * <11..10> 11 BRG1 Input is TxC Pin
5326 * <9..8> 11 BRG0 Input is TxC Pin
5327 * <7..6> 01 DPLL Input is BRG1 Output
5328 * <5..3> 100 TxCLK comes from BRG0
5329 * <2..0> 100 RxCLK comes from BRG0
5330 *
5331 * 0000 1111 0110 0100 = 0x0f64
5332 */
5333
5334 usc_OutReg( info, CMCR, 0x0f64 );
5335
5336 /* Write 16-bit Time Constant for BRG0 */
5337 /* use clock speed if available, otherwise use 8 for diagnostics */
5338 if (info->params.clock_speed) {
5339 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5340 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5341 else
5342 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5343 } else
5344 usc_OutReg(info, TC0R, (u16)8);
5345
5346 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5347 mode = Continuous Set Bit 0 to enable BRG0. */
5348 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5349
5350 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5351 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5352
5353 /* set Internal Data loopback mode */
5354 info->loopback_bits = 0x300;
5355 outw( 0x0300, info->io_base + CCAR );
5356 } else {
5357 /* enable external TXD output */
5358 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5359
5360 /* clear Internal Data loopback mode */
5361 info->loopback_bits = 0;
5362 outw( 0,info->io_base + CCAR );
5363 }
5364
5365} /* end of usc_enable_loopback() */
5366
5367/* usc_enable_aux_clock()
5368 *
5369 * Enabled the AUX clock output at the specified frequency.
5370 *
5371 * Arguments:
5372 *
5373 * info pointer to device extension
5374 * data_rate data rate of clock in bits per second
5375 * A data rate of 0 disables the AUX clock.
5376 *
5377 * Return Value: None
5378 */
5379static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5380{
5381 u32 XtalSpeed;
5382 u16 Tc;
5383
5384 if ( data_rate ) {
5385 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5386 XtalSpeed = 11059200;
5387 else
5388 XtalSpeed = 14745600;
5389
5390
5391 /* Tc = (Xtal/Speed) - 1 */
5392 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5393 /* then rounding up gives a more precise time constant. Instead */
5394 /* of rounding up and then subtracting 1 we just don't subtract */
5395 /* the one in this case. */
5396
5397
5398 Tc = (u16)(XtalSpeed/data_rate);
5399 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5400 Tc--;
5401
5402 /* Write 16-bit Time Constant for BRG0 */
5403 usc_OutReg( info, TC0R, Tc );
5404
5405 /*
5406 * Hardware Configuration Register (HCR)
5407 * Clear Bit 1, BRG0 mode = Continuous
5408 * Set Bit 0 to enable BRG0.
5409 */
5410
5411 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5412
5413 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5414 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5415 } else {
5416 /* data rate == 0 so turn off BRG0 */
5417 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5418 }
5419
5420} /* end of usc_enable_aux_clock() */
5421
5422/*
5423 *
5424 * usc_process_rxoverrun_sync()
5425 *
5426 * This function processes a receive overrun by resetting the
5427 * receive DMA buffers and issuing a Purge Rx FIFO command
5428 * to allow the receiver to continue receiving.
5429 *
5430 * Arguments:
5431 *
5432 * info pointer to device extension
5433 *
5434 * Return Value: None
5435 */
5436static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5437{
5438 int start_index;
5439 int end_index;
5440 int frame_start_index;
5441 int start_of_frame_found = FALSE;
5442 int end_of_frame_found = FALSE;
5443 int reprogram_dma = FALSE;
5444
5445 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5446 u32 phys_addr;
5447
5448 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5449 usc_RCmd( info, RCmd_EnterHuntmode );
5450 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5451
5452 /* CurrentRxBuffer points to the 1st buffer of the next */
5453 /* possibly available receive frame. */
5454
5455 frame_start_index = start_index = end_index = info->current_rx_buffer;
5456
5457 /* Search for an unfinished string of buffers. This means */
5458 /* that a receive frame started (at least one buffer with */
5459 /* count set to zero) but there is no terminiting buffer */
5460 /* (status set to non-zero). */
5461
5462 while( !buffer_list[end_index].count )
5463 {
5464 /* Count field has been reset to zero by 16C32. */
5465 /* This buffer is currently in use. */
5466
5467 if ( !start_of_frame_found )
5468 {
5469 start_of_frame_found = TRUE;
5470 frame_start_index = end_index;
5471 end_of_frame_found = FALSE;
5472 }
5473
5474 if ( buffer_list[end_index].status )
5475 {
5476 /* Status field has been set by 16C32. */
5477 /* This is the last buffer of a received frame. */
5478
5479 /* We want to leave the buffers for this frame intact. */
5480 /* Move on to next possible frame. */
5481
5482 start_of_frame_found = FALSE;
5483 end_of_frame_found = TRUE;
5484 }
5485
5486 /* advance to next buffer entry in linked list */
5487 end_index++;
5488 if ( end_index == info->rx_buffer_count )
5489 end_index = 0;
5490
5491 if ( start_index == end_index )
5492 {
5493 /* The entire list has been searched with all Counts == 0 and */
5494 /* all Status == 0. The receive buffers are */
5495 /* completely screwed, reset all receive buffers! */
5496 mgsl_reset_rx_dma_buffers( info );
5497 frame_start_index = 0;
5498 start_of_frame_found = FALSE;
5499 reprogram_dma = TRUE;
5500 break;
5501 }
5502 }
5503
5504 if ( start_of_frame_found && !end_of_frame_found )
5505 {
5506 /* There is an unfinished string of receive DMA buffers */
5507 /* as a result of the receiver overrun. */
5508
5509 /* Reset the buffers for the unfinished frame */
5510 /* and reprogram the receive DMA controller to start */
5511 /* at the 1st buffer of unfinished frame. */
5512
5513 start_index = frame_start_index;
5514
5515 do
5516 {
5517 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5518
5519 /* Adjust index for wrap around. */
5520 if ( start_index == info->rx_buffer_count )
5521 start_index = 0;
5522
5523 } while( start_index != end_index );
5524
5525 reprogram_dma = TRUE;
5526 }
5527
5528 if ( reprogram_dma )
5529 {
5530 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5531 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5532 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5533
5534 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5535
5536 /* This empties the receive FIFO and loads the RCC with RCLR */
5537 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5538
5539 /* program 16C32 with physical address of 1st DMA buffer entry */
5540 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5541 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5542 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5543
5544 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5545 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5546 usc_EnableInterrupts( info, RECEIVE_STATUS );
5547
5548 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5549 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5550
5551 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5552 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5553 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5554 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5555 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5556 else
5557 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5558 }
5559 else
5560 {
5561 /* This empties the receive FIFO and loads the RCC with RCLR */
5562 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5563 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5564 }
5565
5566} /* end of usc_process_rxoverrun_sync() */
5567
5568/* usc_stop_receiver()
5569 *
5570 * Disable USC receiver
5571 *
5572 * Arguments: info pointer to device instance data
5573 * Return Value: None
5574 */
5575static void usc_stop_receiver( struct mgsl_struct *info )
5576{
5577 if (debug_level >= DEBUG_LEVEL_ISR)
5578 printk("%s(%d):usc_stop_receiver(%s)\n",
5579 __FILE__,__LINE__, info->device_name );
5580
5581 /* Disable receive DMA channel. */
5582 /* This also disables receive DMA channel interrupts */
5583 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5584
5585 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5586 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5587 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5588
5589 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5590
5591 /* This empties the receive FIFO and loads the RCC with RCLR */
5592 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5593 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5594
5595 info->rx_enabled = 0;
5596 info->rx_overflow = 0;
5597 info->rx_rcc_underrun = 0;
5598
5599} /* end of stop_receiver() */
5600
5601/* usc_start_receiver()
5602 *
5603 * Enable the USC receiver
5604 *
5605 * Arguments: info pointer to device instance data
5606 * Return Value: None
5607 */
5608static void usc_start_receiver( struct mgsl_struct *info )
5609{
5610 u32 phys_addr;
5611
5612 if (debug_level >= DEBUG_LEVEL_ISR)
5613 printk("%s(%d):usc_start_receiver(%s)\n",
5614 __FILE__,__LINE__, info->device_name );
5615
5616 mgsl_reset_rx_dma_buffers( info );
5617 usc_stop_receiver( info );
5618
5619 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5620 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5621
5622 if ( info->params.mode == MGSL_MODE_HDLC ||
5623 info->params.mode == MGSL_MODE_RAW ) {
5624 /* DMA mode Transfers */
5625 /* Program the DMA controller. */
5626 /* Enable the DMA controller end of buffer interrupt. */
5627
5628 /* program 16C32 with physical address of 1st DMA buffer entry */
5629 phys_addr = info->rx_buffer_list[0].phys_entry;
5630 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5631 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5632
5633 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5634 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5635 usc_EnableInterrupts( info, RECEIVE_STATUS );
5636
5637 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5638 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5639
5640 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5641 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5642 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5643 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5644 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5645 else
5646 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5647 } else {
5648 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5649 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5650 usc_EnableInterrupts(info, RECEIVE_DATA);
5651
5652 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5653 usc_RCmd( info, RCmd_EnterHuntmode );
5654
5655 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5656 }
5657
5658 usc_OutReg( info, CCSR, 0x1020 );
5659
5660 info->rx_enabled = 1;
5661
5662} /* end of usc_start_receiver() */
5663
5664/* usc_start_transmitter()
5665 *
5666 * Enable the USC transmitter and send a transmit frame if
5667 * one is loaded in the DMA buffers.
5668 *
5669 * Arguments: info pointer to device instance data
5670 * Return Value: None
5671 */
5672static void usc_start_transmitter( struct mgsl_struct *info )
5673{
5674 u32 phys_addr;
5675 unsigned int FrameSize;
5676
5677 if (debug_level >= DEBUG_LEVEL_ISR)
5678 printk("%s(%d):usc_start_transmitter(%s)\n",
5679 __FILE__,__LINE__, info->device_name );
5680
5681 if ( info->xmit_cnt ) {
5682
5683 /* If auto RTS enabled and RTS is inactive, then assert */
5684 /* RTS and set a flag indicating that the driver should */
5685 /* negate RTS when the transmission completes. */
5686
5687 info->drop_rts_on_tx_done = 0;
5688
5689 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5690 usc_get_serial_signals( info );
5691 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5692 info->serial_signals |= SerialSignal_RTS;
5693 usc_set_serial_signals( info );
5694 info->drop_rts_on_tx_done = 1;
5695 }
5696 }
5697
5698
5699 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5700 if ( !info->tx_active ) {
5701 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5702 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5703 usc_EnableInterrupts(info, TRANSMIT_DATA);
5704 usc_load_txfifo(info);
5705 }
5706 } else {
5707 /* Disable transmit DMA controller while programming. */
5708 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5709
5710 /* Transmit DMA buffer is loaded, so program USC */
5711 /* to send the frame contained in the buffers. */
5712
5713 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5714
5715 /* if operating in Raw sync mode, reset the rcc component
5716 * of the tx dma buffer entry, otherwise, the serial controller
5717 * will send a closing sync char after this count.
5718 */
5719 if ( info->params.mode == MGSL_MODE_RAW )
5720 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5721
5722 /* Program the Transmit Character Length Register (TCLR) */
5723 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5724 usc_OutReg( info, TCLR, (u16)FrameSize );
5725
5726 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5727
5728 /* Program the address of the 1st DMA Buffer Entry in linked list */
5729 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5730 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5731 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5732
5733 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5734 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5735 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5736
5737 if ( info->params.mode == MGSL_MODE_RAW &&
5738 info->num_tx_dma_buffers > 1 ) {
5739 /* When running external sync mode, attempt to 'stream' transmit */
5740 /* by filling tx dma buffers as they become available. To do this */
5741 /* we need to enable Tx DMA EOB Status interrupts : */
5742 /* */
5743 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5744 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5745
5746 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5747 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5748 }
5749
5750 /* Initialize Transmit DMA Channel */
5751 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5752
5753 usc_TCmd( info, TCmd_SendFrame );
5754
5755 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
5756 add_timer(&info->tx_timer);
5757 }
5758 info->tx_active = 1;
5759 }
5760
5761 if ( !info->tx_enabled ) {
5762 info->tx_enabled = 1;
5763 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5764 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5765 else
5766 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5767 }
5768
5769} /* end of usc_start_transmitter() */
5770
5771/* usc_stop_transmitter()
5772 *
5773 * Stops the transmitter and DMA
5774 *
5775 * Arguments: info pointer to device isntance data
5776 * Return Value: None
5777 */
5778static void usc_stop_transmitter( struct mgsl_struct *info )
5779{
5780 if (debug_level >= DEBUG_LEVEL_ISR)
5781 printk("%s(%d):usc_stop_transmitter(%s)\n",
5782 __FILE__,__LINE__, info->device_name );
5783
5784 del_timer(&info->tx_timer);
5785
5786 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5787 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5788 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5789
5790 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5791 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5792 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5793
5794 info->tx_enabled = 0;
5795 info->tx_active = 0;
5796
5797} /* end of usc_stop_transmitter() */
5798
5799/* usc_load_txfifo()
5800 *
5801 * Fill the transmit FIFO until the FIFO is full or
5802 * there is no more data to load.
5803 *
5804 * Arguments: info pointer to device extension (instance data)
5805 * Return Value: None
5806 */
5807static void usc_load_txfifo( struct mgsl_struct *info )
5808{
5809 int Fifocount;
5810 u8 TwoBytes[2];
5811
5812 if ( !info->xmit_cnt && !info->x_char )
5813 return;
5814
5815 /* Select transmit FIFO status readback in TICR */
5816 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5817
5818 /* load the Transmit FIFO until FIFOs full or all data sent */
5819
5820 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5821 /* there is more space in the transmit FIFO and */
5822 /* there is more data in transmit buffer */
5823
5824 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5825 /* write a 16-bit word from transmit buffer to 16C32 */
5826
5827 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5828 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5829 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5830 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5831
5832 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5833
5834 info->xmit_cnt -= 2;
5835 info->icount.tx += 2;
5836 } else {
5837 /* only 1 byte left to transmit or 1 FIFO slot left */
5838
5839 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5840 info->io_base + CCAR );
5841
5842 if (info->x_char) {
5843 /* transmit pending high priority char */
5844 outw( info->x_char,info->io_base + CCAR );
5845 info->x_char = 0;
5846 } else {
5847 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5848 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5849 info->xmit_cnt--;
5850 }
5851 info->icount.tx++;
5852 }
5853 }
5854
5855} /* end of usc_load_txfifo() */
5856
5857/* usc_reset()
5858 *
5859 * Reset the adapter to a known state and prepare it for further use.
5860 *
5861 * Arguments: info pointer to device instance data
5862 * Return Value: None
5863 */
5864static void usc_reset( struct mgsl_struct *info )
5865{
5866 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5867 int i;
5868 u32 readval;
5869
5870 /* Set BIT30 of Misc Control Register */
5871 /* (Local Control Register 0x50) to force reset of USC. */
5872
5873 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5874 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5875
5876 info->misc_ctrl_value |= BIT30;
5877 *MiscCtrl = info->misc_ctrl_value;
5878
5879 /*
5880 * Force at least 170ns delay before clearing
5881 * reset bit. Each read from LCR takes at least
5882 * 30ns so 10 times for 300ns to be safe.
5883 */
5884 for(i=0;i<10;i++)
5885 readval = *MiscCtrl;
5886
5887 info->misc_ctrl_value &= ~BIT30;
5888 *MiscCtrl = info->misc_ctrl_value;
5889
5890 *LCR0BRDR = BUS_DESCRIPTOR(
5891 1, // Write Strobe Hold (0-3)
5892 2, // Write Strobe Delay (0-3)
5893 2, // Read Strobe Delay (0-3)
5894 0, // NWDD (Write data-data) (0-3)
5895 4, // NWAD (Write Addr-data) (0-31)
5896 0, // NXDA (Read/Write Data-Addr) (0-3)
5897 0, // NRDD (Read Data-Data) (0-3)
5898 5 // NRAD (Read Addr-Data) (0-31)
5899 );
5900 } else {
5901 /* do HW reset */
5902 outb( 0,info->io_base + 8 );
5903 }
5904
5905 info->mbre_bit = 0;
5906 info->loopback_bits = 0;
5907 info->usc_idle_mode = 0;
5908
5909 /*
5910 * Program the Bus Configuration Register (BCR)
5911 *
5912 * <15> 0 Don't use separate address
5913 * <14..6> 0 reserved
5914 * <5..4> 00 IAckmode = Default, don't care
5915 * <3> 1 Bus Request Totem Pole output
5916 * <2> 1 Use 16 Bit data bus
5917 * <1> 0 IRQ Totem Pole output
5918 * <0> 0 Don't Shift Right Addr
5919 *
5920 * 0000 0000 0000 1100 = 0x000c
5921 *
5922 * By writing to io_base + SDPIN the Wait/Ack pin is
5923 * programmed to work as a Wait pin.
5924 */
5925
5926 outw( 0x000c,info->io_base + SDPIN );
5927
5928
5929 outw( 0,info->io_base );
5930 outw( 0,info->io_base + CCAR );
5931
5932 /* select little endian byte ordering */
5933 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5934
5935
5936 /* Port Control Register (PCR)
5937 *
5938 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5939 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5940 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5941 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5942 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5943 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5944 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5945 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5946 *
5947 * 1111 0000 1111 0101 = 0xf0f5
5948 */
5949
5950 usc_OutReg( info, PCR, 0xf0f5 );
5951
5952
5953 /*
5954 * Input/Output Control Register
5955 *
5956 * <15..14> 00 CTS is active low input
5957 * <13..12> 00 DCD is active low input
5958 * <11..10> 00 TxREQ pin is input (DSR)
5959 * <9..8> 00 RxREQ pin is input (RI)
5960 * <7..6> 00 TxD is output (Transmit Data)
5961 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5962 * <2..0> 100 RxC is Output (drive with BRG0)
5963 *
5964 * 0000 0000 0000 0100 = 0x0004
5965 */
5966
5967 usc_OutReg( info, IOCR, 0x0004 );
5968
5969} /* end of usc_reset() */
5970
5971/* usc_set_async_mode()
5972 *
5973 * Program adapter for asynchronous communications.
5974 *
5975 * Arguments: info pointer to device instance data
5976 * Return Value: None
5977 */
5978static void usc_set_async_mode( struct mgsl_struct *info )
5979{
5980 u16 RegValue;
5981
5982 /* disable interrupts while programming USC */
5983 usc_DisableMasterIrqBit( info );
5984
5985 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5986 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5987
5988 usc_loopback_frame( info );
5989
5990 /* Channel mode Register (CMR)
5991 *
5992 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5993 * <13..12> 00 00 = 16X Clock
5994 * <11..8> 0000 Transmitter mode = Asynchronous
5995 * <7..6> 00 reserved?
5996 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5997 * <3..0> 0000 Receiver mode = Asynchronous
5998 *
5999 * 0000 0000 0000 0000 = 0x0
6000 */
6001
6002 RegValue = 0;
6003 if ( info->params.stop_bits != 1 )
6004 RegValue |= BIT14;
6005 usc_OutReg( info, CMR, RegValue );
6006
6007
6008 /* Receiver mode Register (RMR)
6009 *
6010 * <15..13> 000 encoding = None
6011 * <12..08> 00000 reserved (Sync Only)
6012 * <7..6> 00 Even parity
6013 * <5> 0 parity disabled
6014 * <4..2> 000 Receive Char Length = 8 bits
6015 * <1..0> 00 Disable Receiver
6016 *
6017 * 0000 0000 0000 0000 = 0x0
6018 */
6019
6020 RegValue = 0;
6021
6022 if ( info->params.data_bits != 8 )
6023 RegValue |= BIT4+BIT3+BIT2;
6024
6025 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6026 RegValue |= BIT5;
6027 if ( info->params.parity != ASYNC_PARITY_ODD )
6028 RegValue |= BIT6;
6029 }
6030
6031 usc_OutReg( info, RMR, RegValue );
6032
6033
6034 /* Set IRQ trigger level */
6035
6036 usc_RCmd( info, RCmd_SelectRicrIntLevel );
6037
6038
6039 /* Receive Interrupt Control Register (RICR)
6040 *
6041 * <15..8> ? RxFIFO IRQ Request Level
6042 *
6043 * Note: For async mode the receive FIFO level must be set
6044 * to 0 to aviod the situation where the FIFO contains fewer bytes
6045 * than the trigger level and no more data is expected.
6046 *
6047 * <7> 0 Exited Hunt IA (Interrupt Arm)
6048 * <6> 0 Idle Received IA
6049 * <5> 0 Break/Abort IA
6050 * <4> 0 Rx Bound IA
6051 * <3> 0 Queued status reflects oldest byte in FIFO
6052 * <2> 0 Abort/PE IA
6053 * <1> 0 Rx Overrun IA
6054 * <0> 0 Select TC0 value for readback
6055 *
6056 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6057 */
6058
6059 usc_OutReg( info, RICR, 0x0000 );
6060
6061 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
6062 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6063
6064
6065 /* Transmit mode Register (TMR)
6066 *
6067 * <15..13> 000 encoding = None
6068 * <12..08> 00000 reserved (Sync Only)
6069 * <7..6> 00 Transmit parity Even
6070 * <5> 0 Transmit parity Disabled
6071 * <4..2> 000 Tx Char Length = 8 bits
6072 * <1..0> 00 Disable Transmitter
6073 *
6074 * 0000 0000 0000 0000 = 0x0
6075 */
6076
6077 RegValue = 0;
6078
6079 if ( info->params.data_bits != 8 )
6080 RegValue |= BIT4+BIT3+BIT2;
6081
6082 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6083 RegValue |= BIT5;
6084 if ( info->params.parity != ASYNC_PARITY_ODD )
6085 RegValue |= BIT6;
6086 }
6087
6088 usc_OutReg( info, TMR, RegValue );
6089
6090 usc_set_txidle( info );
6091
6092
6093 /* Set IRQ trigger level */
6094
6095 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6096
6097
6098 /* Transmit Interrupt Control Register (TICR)
6099 *
6100 * <15..8> ? Transmit FIFO IRQ Level
6101 * <7> 0 Present IA (Interrupt Arm)
6102 * <6> 1 Idle Sent IA
6103 * <5> 0 Abort Sent IA
6104 * <4> 0 EOF/EOM Sent IA
6105 * <3> 0 CRC Sent IA
6106 * <2> 0 1 = Wait for SW Trigger to Start Frame
6107 * <1> 0 Tx Underrun IA
6108 * <0> 0 TC0 constant on read back
6109 *
6110 * 0000 0000 0100 0000 = 0x0040
6111 */
6112
6113 usc_OutReg( info, TICR, 0x1f40 );
6114
6115 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6116 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6117
6118 usc_enable_async_clock( info, info->params.data_rate );
6119
6120
6121 /* Channel Control/status Register (CCSR)
6122 *
6123 * <15> X RCC FIFO Overflow status (RO)
6124 * <14> X RCC FIFO Not Empty status (RO)
6125 * <13> 0 1 = Clear RCC FIFO (WO)
6126 * <12> X DPLL in Sync status (RO)
6127 * <11> X DPLL 2 Missed Clocks status (RO)
6128 * <10> X DPLL 1 Missed Clock status (RO)
6129 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6130 * <7> X SDLC Loop On status (RO)
6131 * <6> X SDLC Loop Send status (RO)
6132 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6133 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6134 * <1..0> 00 reserved
6135 *
6136 * 0000 0000 0010 0000 = 0x0020
6137 */
6138
6139 usc_OutReg( info, CCSR, 0x0020 );
6140
6141 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6142 RECEIVE_DATA + RECEIVE_STATUS );
6143
6144 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6145 RECEIVE_DATA + RECEIVE_STATUS );
6146
6147 usc_EnableMasterIrqBit( info );
6148
6149 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6150 /* Enable INTEN (Port 6, Bit12) */
6151 /* This connects the IRQ request signal to the ISA bus */
6152 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6153 }
6154
7c1fff58
PF		 6155 if (info->params.loopback) {
6156 info->loopback_bits = 0x300;
6157 outw(0x0300, info->io_base + CCAR);
6158 }
6159
1da177e4
LT		 6160} /* end of usc_set_async_mode() */
6161
6162/* usc_loopback_frame()
6163 *
6164 * Loop back a small (2 byte) dummy SDLC frame.
6165 * Interrupts and DMA are NOT used. The purpose of this is to
6166 * clear any 'stale' status info left over from running in async mode.
6167 *
6168 * The 16C32 shows the strange behaviour of marking the 1st
6169 * received SDLC frame with a CRC error even when there is no
6170 * CRC error. To get around this a small dummy from of 2 bytes
6171 * is looped back when switching from async to sync mode.
6172 *
6173 * Arguments: info pointer to device instance data
6174 * Return Value: None
6175 */
6176static void usc_loopback_frame( struct mgsl_struct *info )
6177{
6178 int i;
6179 unsigned long oldmode = info->params.mode;
6180
6181 info->params.mode = MGSL_MODE_HDLC;
6182
6183 usc_DisableMasterIrqBit( info );
6184
6185 usc_set_sdlc_mode( info );
6186 usc_enable_loopback( info, 1 );
6187
6188 /* Write 16-bit Time Constant for BRG0 */
6189 usc_OutReg( info, TC0R, 0 );
6190
6191 /* Channel Control Register (CCR)
6192 *
6193 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6194 * <13> 0 Trigger Tx on SW Command Disabled
6195 * <12> 0 Flag Preamble Disabled
6196 * <11..10> 00 Preamble Length = 8-Bits
6197 * <9..8> 01 Preamble Pattern = flags
6198 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6199 * <5> 0 Trigger Rx on SW Command Disabled
6200 * <4..0> 0 reserved
6201 *
6202 * 0000 0001 0000 0000 = 0x0100
6203 */
6204
6205 usc_OutReg( info, CCR, 0x0100 );
6206
6207 /* SETUP RECEIVER */
6208 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6209 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6210
6211 /* SETUP TRANSMITTER */
6212 /* Program the Transmit Character Length Register (TCLR) */
6213 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6214 usc_OutReg( info, TCLR, 2 );
6215 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6216
6217 /* unlatch Tx status bits, and start transmit channel. */
6218 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6219 outw(0,info->io_base + DATAREG);
6220
6221 /* ENABLE TRANSMITTER */
6222 usc_TCmd( info, TCmd_SendFrame );
6223 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6224
6225 /* WAIT FOR RECEIVE COMPLETE */
6226 for (i=0 ; i<1000 ; i++)
6227 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6228 break;
6229
6230 /* clear Internal Data loopback mode */
6231 usc_enable_loopback(info, 0);
6232
6233 usc_EnableMasterIrqBit(info);
6234
6235 info->params.mode = oldmode;
6236
6237} /* end of usc_loopback_frame() */
6238
6239/* usc_set_sync_mode() Programs the USC for SDLC communications.
6240 *
6241 * Arguments: info pointer to adapter info structure
6242 * Return Value: None
6243 */
6244static void usc_set_sync_mode( struct mgsl_struct *info )
6245{
6246 usc_loopback_frame( info );
6247 usc_set_sdlc_mode( info );
6248
6249 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6250 /* Enable INTEN (Port 6, Bit12) */
6251 /* This connects the IRQ request signal to the ISA bus */
6252 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6253 }
6254
6255 usc_enable_aux_clock(info, info->params.clock_speed);
6256
6257 if (info->params.loopback)
6258 usc_enable_loopback(info,1);
6259
6260} /* end of mgsl_set_sync_mode() */
6261
6262/* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6263 *
6264 * Arguments: info pointer to device instance data
6265 * Return Value: None
6266 */
6267static void usc_set_txidle( struct mgsl_struct *info )
6268{
6269 u16 usc_idle_mode = IDLEMODE_FLAGS;
6270
6271 /* Map API idle mode to USC register bits */
6272
6273 switch( info->idle_mode ){
6274 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6275 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6276 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6277 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6278 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6279 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6280 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6281 }
6282
6283 info->usc_idle_mode = usc_idle_mode;
6284 //usc_OutReg(info, TCSR, usc_idle_mode);
6285 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6286 info->tcsr_value += usc_idle_mode;
6287 usc_OutReg(info, TCSR, info->tcsr_value);
6288
6289 /*
6290 * if SyncLink WAN adapter is running in external sync mode, the
6291 * transmitter has been set to Monosync in order to try to mimic
6292 * a true raw outbound bit stream. Monosync still sends an open/close
6293 * sync char at the start/end of a frame. Try to match those sync
6294 * patterns to the idle mode set here
6295 */
6296 if ( info->params.mode == MGSL_MODE_RAW ) {
6297 unsigned char syncpat = 0;
6298 switch( info->idle_mode ) {
6299 case HDLC_TXIDLE_FLAGS:
6300 syncpat = 0x7e;
6301 break;
6302 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6303 syncpat = 0x55;
6304 break;
6305 case HDLC_TXIDLE_ZEROS:
6306 case HDLC_TXIDLE_SPACE:
6307 syncpat = 0x00;
6308 break;
6309 case HDLC_TXIDLE_ONES:
6310 case HDLC_TXIDLE_MARK:
6311 syncpat = 0xff;
6312 break;
6313 case HDLC_TXIDLE_ALT_MARK_SPACE:
6314 syncpat = 0xaa;
6315 break;
6316 }
6317
6318 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6319 }
6320
6321} /* end of usc_set_txidle() */
6322
6323/* usc_get_serial_signals()
6324 *
6325 * Query the adapter for the state of the V24 status (input) signals.
6326 *
6327 * Arguments: info pointer to device instance data
6328 * Return Value: None
6329 */
6330static void usc_get_serial_signals( struct mgsl_struct *info )
6331{
6332 u16 status;
6333
6334 /* clear all serial signals except DTR and RTS */
6335 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6336
6337 /* Read the Misc Interrupt status Register (MISR) to get */
6338 /* the V24 status signals. */
6339
6340 status = usc_InReg( info, MISR );
6341
6342 /* set serial signal bits to reflect MISR */
6343
6344 if ( status & MISCSTATUS_CTS )
6345 info->serial_signals |= SerialSignal_CTS;
6346
6347 if ( status & MISCSTATUS_DCD )
6348 info->serial_signals |= SerialSignal_DCD;
6349
6350 if ( status & MISCSTATUS_RI )
6351 info->serial_signals |= SerialSignal_RI;
6352
6353 if ( status & MISCSTATUS_DSR )
6354 info->serial_signals |= SerialSignal_DSR;
6355
6356} /* end of usc_get_serial_signals() */
6357
6358/* usc_set_serial_signals()
6359 *
6360 * Set the state of DTR and RTS based on contents of
6361 * serial_signals member of device extension.
6362 *
6363 * Arguments: info pointer to device instance data
6364 * Return Value: None
6365 */
6366static void usc_set_serial_signals( struct mgsl_struct *info )
6367{
6368 u16 Control;
6369 unsigned char V24Out = info->serial_signals;
6370
6371 /* get the current value of the Port Control Register (PCR) */
6372
6373 Control = usc_InReg( info, PCR );
6374
6375 if ( V24Out & SerialSignal_RTS )
6376 Control &= ~(BIT6);
6377 else
6378 Control |= BIT6;
6379
6380 if ( V24Out & SerialSignal_DTR )
6381 Control &= ~(BIT4);
6382 else
6383 Control |= BIT4;
6384
6385 usc_OutReg( info, PCR, Control );
6386
6387} /* end of usc_set_serial_signals() */
6388
6389/* usc_enable_async_clock()
6390 *
6391 * Enable the async clock at the specified frequency.
6392 *
6393 * Arguments: info pointer to device instance data
6394 * data_rate data rate of clock in bps
6395 * 0 disables the AUX clock.
6396 * Return Value: None
6397 */
6398static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6399{
6400 if ( data_rate ) {
6401 /*
6402 * Clock mode Control Register (CMCR)
6403 *
6404 * <15..14> 00 counter 1 Disabled
6405 * <13..12> 00 counter 0 Disabled
6406 * <11..10> 11 BRG1 Input is TxC Pin
6407 * <9..8> 11 BRG0 Input is TxC Pin
6408 * <7..6> 01 DPLL Input is BRG1 Output
6409 * <5..3> 100 TxCLK comes from BRG0
6410 * <2..0> 100 RxCLK comes from BRG0
6411 *
6412 * 0000 1111 0110 0100 = 0x0f64
6413 */
6414
6415 usc_OutReg( info, CMCR, 0x0f64 );
6416
6417
6418 /*
6419 * Write 16-bit Time Constant for BRG0
6420 * Time Constant = (ClkSpeed / data_rate) - 1
6421 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6422 */
6423
6424 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6425 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6426 else
6427 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6428
6429
6430 /*
6431 * Hardware Configuration Register (HCR)
6432 * Clear Bit 1, BRG0 mode = Continuous
6433 * Set Bit 0 to enable BRG0.
6434 */
6435
6436 usc_OutReg( info, HCR,
6437 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6438
6439
6440 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6441
6442 usc_OutReg( info, IOCR,
6443 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6444 } else {
6445 /* data rate == 0 so turn off BRG0 */
6446 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6447 }
6448
6449} /* end of usc_enable_async_clock() */
6450
6451/*
6452 * Buffer Structures:
6453 *
6454 * Normal memory access uses virtual addresses that can make discontiguous
6455 * physical memory pages appear to be contiguous in the virtual address
6456 * space (the processors memory mapping handles the conversions).
6457 *
6458 * DMA transfers require physically contiguous memory. This is because
6459 * the DMA system controller and DMA bus masters deal with memory using
6460 * only physical addresses.
6461 *
6462 * This causes a problem under Windows NT when large DMA buffers are
6463 * needed. Fragmentation of the nonpaged pool prevents allocations of
6464 * physically contiguous buffers larger than the PAGE_SIZE.
6465 *
6466 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6467 * allows DMA transfers to physically discontiguous buffers. Information
6468 * about each data transfer buffer is contained in a memory structure
6469 * called a 'buffer entry'. A list of buffer entries is maintained
6470 * to track and control the use of the data transfer buffers.
6471 *
6472 * To support this strategy we will allocate sufficient PAGE_SIZE
6473 * contiguous memory buffers to allow for the total required buffer
6474 * space.
6475 *
6476 * The 16C32 accesses the list of buffer entries using Bus Master
6477 * DMA. Control information is read from the buffer entries by the
6478 * 16C32 to control data transfers. status information is written to
6479 * the buffer entries by the 16C32 to indicate the status of completed
6480 * transfers.
6481 *
6482 * The CPU writes control information to the buffer entries to control
6483 * the 16C32 and reads status information from the buffer entries to
6484 * determine information about received and transmitted frames.
6485 *
6486 * Because the CPU and 16C32 (adapter) both need simultaneous access
6487 * to the buffer entries, the buffer entry memory is allocated with
6488 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6489 * entry list to PAGE_SIZE.
6490 *
6491 * The actual data buffers on the other hand will only be accessed
6492 * by the CPU or the adapter but not by both simultaneously. This allows
6493 * Scatter/Gather packet based DMA procedures for using physically
6494 * discontiguous pages.
6495 */
6496
6497/*
6498 * mgsl_reset_tx_dma_buffers()
6499 *
6500 * Set the count for all transmit buffers to 0 to indicate the
6501 * buffer is available for use and set the current buffer to the
6502 * first buffer. This effectively makes all buffers free and
6503 * discards any data in buffers.
6504 *
6505 * Arguments: info pointer to device instance data
6506 * Return Value: None
6507 */
6508static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6509{
6510 unsigned int i;
6511
6512 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6513 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6514 }
6515
6516 info->current_tx_buffer = 0;
6517 info->start_tx_dma_buffer = 0;
6518 info->tx_dma_buffers_used = 0;
6519
6520 info->get_tx_holding_index = 0;
6521 info->put_tx_holding_index = 0;
6522 info->tx_holding_count = 0;
6523
6524} /* end of mgsl_reset_tx_dma_buffers() */
6525
6526/*
6527 * num_free_tx_dma_buffers()
6528 *
6529 * returns the number of free tx dma buffers available
6530 *
6531 * Arguments: info pointer to device instance data
6532 * Return Value: number of free tx dma buffers
6533 */
6534static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6535{
6536 return info->tx_buffer_count - info->tx_dma_buffers_used;
6537}
6538
6539/*
6540 * mgsl_reset_rx_dma_buffers()
6541 *
6542 * Set the count for all receive buffers to DMABUFFERSIZE
6543 * and set the current buffer to the first buffer. This effectively
6544 * makes all buffers free and discards any data in buffers.
6545 *
6546 * Arguments: info pointer to device instance data
6547 * Return Value: None
6548 */
6549static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6550{
6551 unsigned int i;
6552
6553 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6554 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6555// info->rx_buffer_list[i].count = DMABUFFERSIZE;
6556// info->rx_buffer_list[i].status = 0;
6557 }
6558
6559 info->current_rx_buffer = 0;
6560
6561} /* end of mgsl_reset_rx_dma_buffers() */
6562
6563/*
6564 * mgsl_free_rx_frame_buffers()
6565 *
6566 * Free the receive buffers used by a received SDLC
6567 * frame such that the buffers can be reused.
6568 *
6569 * Arguments:
6570 *
6571 * info pointer to device instance data
6572 * StartIndex index of 1st receive buffer of frame
6573 * EndIndex index of last receive buffer of frame
6574 *
6575 * Return Value: None
6576 */
6577static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6578{
6579 int Done = 0;
6580 DMABUFFERENTRY *pBufEntry;
6581 unsigned int Index;
6582
6583 /* Starting with 1st buffer entry of the frame clear the status */
6584 /* field and set the count field to DMA Buffer Size. */
6585
6586 Index = StartIndex;
6587
6588 while( !Done ) {
6589 pBufEntry = &(info->rx_buffer_list[Index]);
6590
6591 if ( Index == EndIndex ) {
6592 /* This is the last buffer of the frame! */
6593 Done = 1;
6594 }
6595
6596 /* reset current buffer for reuse */
6597// pBufEntry->status = 0;
6598// pBufEntry->count = DMABUFFERSIZE;
6599 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6600
6601 /* advance to next buffer entry in linked list */
6602 Index++;
6603 if ( Index == info->rx_buffer_count )
6604 Index = 0;
6605 }
6606
6607 /* set current buffer to next buffer after last buffer of frame */
6608 info->current_rx_buffer = Index;
6609
6610} /* end of free_rx_frame_buffers() */
6611
6612/* mgsl_get_rx_frame()
6613 *
6614 * This function attempts to return a received SDLC frame from the
6615 * receive DMA buffers. Only frames received without errors are returned.
6616 *
6617 * Arguments: info pointer to device extension
6618 * Return Value: 1 if frame returned, otherwise 0
6619 */
6620static int mgsl_get_rx_frame(struct mgsl_struct *info)
6621{
6622 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6623 unsigned short status;
6624 DMABUFFERENTRY *pBufEntry;
6625 unsigned int framesize = 0;
6626 int ReturnCode = 0;
6627 unsigned long flags;
6628 struct tty_struct *tty = info->tty;
6629 int return_frame = 0;
6630
6631 /*
6632 * current_rx_buffer points to the 1st buffer of the next available
6633 * receive frame. To find the last buffer of the frame look for
6634 * a non-zero status field in the buffer entries. (The status
6635 * field is set by the 16C32 after completing a receive frame.
6636 */
6637
6638 StartIndex = EndIndex = info->current_rx_buffer;
6639
6640 while( !info->rx_buffer_list[EndIndex].status ) {
6641 /*
6642 * If the count field of the buffer entry is non-zero then
6643 * this buffer has not been used. (The 16C32 clears the count
6644 * field when it starts using the buffer.) If an unused buffer
6645 * is encountered then there are no frames available.
6646 */
6647
6648 if ( info->rx_buffer_list[EndIndex].count )
6649 goto Cleanup;
6650
6651 /* advance to next buffer entry in linked list */
6652 EndIndex++;
6653 if ( EndIndex == info->rx_buffer_count )
6654 EndIndex = 0;
6655
6656 /* if entire list searched then no frame available */
6657 if ( EndIndex == StartIndex ) {
6658 /* If this occurs then something bad happened,
6659 * all buffers have been 'used' but none mark
6660 * the end of a frame. Reset buffers and receiver.
6661 */
6662
6663 if ( info->rx_enabled ){
6664 spin_lock_irqsave(&info->irq_spinlock,flags);
6665 usc_start_receiver(info);
6666 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6667 }
6668 goto Cleanup;
6669 }
6670 }
6671
6672
6673 /* check status of receive frame */
6674
6675 status = info->rx_buffer_list[EndIndex].status;
6676
6677 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6678 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6679 if ( status & RXSTATUS_SHORT_FRAME )
6680 info->icount.rxshort++;
6681 else if ( status & RXSTATUS_ABORT )
6682 info->icount.rxabort++;
6683 else if ( status & RXSTATUS_OVERRUN )
6684 info->icount.rxover++;
6685 else {
6686 info->icount.rxcrc++;
6687 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6688 return_frame = 1;
6689 }
6690 framesize = 0;
6691#ifdef CONFIG_HDLC
6692 {
6693 struct net_device_stats *stats = hdlc_stats(info->netdev);
6694 stats->rx_errors++;
6695 stats->rx_frame_errors++;
6696 }
6697#endif
6698 } else
6699 return_frame = 1;
6700
6701 if ( return_frame ) {
6702 /* receive frame has no errors, get frame size.
6703 * The frame size is the starting value of the RCC (which was
6704 * set to 0xffff) minus the ending value of the RCC (decremented
6705 * once for each receive character) minus 2 for the 16-bit CRC.
6706 */
6707
6708 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6709
6710 /* adjust frame size for CRC if any */
6711 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6712 framesize -= 2;
6713 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6714 framesize -= 4;
6715 }
6716
6717 if ( debug_level >= DEBUG_LEVEL_BH )
6718 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6719 __FILE__,__LINE__,info->device_name,status,framesize);
6720
6721 if ( debug_level >= DEBUG_LEVEL_DATA )
6722 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6723 min_t(int, framesize, DMABUFFERSIZE),0);
6724
6725 if (framesize) {
6726 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6727 ((framesize+1) > info->max_frame_size) ) ||
6728 (framesize > info->max_frame_size) )
6729 info->icount.rxlong++;
6730 else {
6731 /* copy dma buffer(s) to contiguous intermediate buffer */
6732 int copy_count = framesize;
6733 int index = StartIndex;
6734 unsigned char *ptmp = info->intermediate_rxbuffer;
6735
6736 if ( !(status & RXSTATUS_CRC_ERROR))
6737 info->icount.rxok++;
6738
6739 while(copy_count) {
6740 int partial_count;
6741 if ( copy_count > DMABUFFERSIZE )
6742 partial_count = DMABUFFERSIZE;
6743 else
6744 partial_count = copy_count;
6745
6746 pBufEntry = &(info->rx_buffer_list[index]);
6747 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6748 ptmp += partial_count;
6749 copy_count -= partial_count;
6750
6751 if ( ++index == info->rx_buffer_count )
6752 index = 0;
6753 }
6754
6755 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6756 ++framesize;
6757 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6758 RX_CRC_ERROR :
6759 RX_OK);
6760
6761 if ( debug_level >= DEBUG_LEVEL_DATA )
6762 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6763 __FILE__,__LINE__,info->device_name,
6764 *ptmp);
6765 }
6766
6767#ifdef CONFIG_HDLC
6768 if (info->netcount)
6769 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6770 else
6771#endif
6772 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6773 }
6774 }
6775 /* Free the buffers used by this frame. */
6776 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6777
6778 ReturnCode = 1;
6779
6780Cleanup:
6781
6782 if ( info->rx_enabled && info->rx_overflow ) {
6783 /* The receiver needs to restarted because of
6784 * a receive overflow (buffer or FIFO). If the
6785 * receive buffers are now empty, then restart receiver.
6786 */
6787
6788 if ( !info->rx_buffer_list[EndIndex].status &&
6789 info->rx_buffer_list[EndIndex].count ) {
6790 spin_lock_irqsave(&info->irq_spinlock,flags);
6791 usc_start_receiver(info);
6792 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6793 }
6794 }
6795
6796 return ReturnCode;
6797
6798} /* end of mgsl_get_rx_frame() */
6799
6800/* mgsl_get_raw_rx_frame()
6801 *
6802 * This function attempts to return a received frame from the
6803 * receive DMA buffers when running in external loop mode. In this mode,
6804 * we will return at most one DMABUFFERSIZE frame to the application.
6805 * The USC receiver is triggering off of DCD going active to start a new
6806 * frame, and DCD going inactive to terminate the frame (similar to
6807 * processing a closing flag character).
6808 *
6809 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6810 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6811 * status field and the RCC field will indicate the length of the
6812 * entire received frame. We take this RCC field and get the modulus
6813 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6814 * last Rx DMA buffer and return that last portion of the frame.
6815 *
6816 * Arguments: info pointer to device extension
6817 * Return Value: 1 if frame returned, otherwise 0
6818 */
6819static int mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6820{
6821 unsigned int CurrentIndex, NextIndex;
6822 unsigned short status;
6823 DMABUFFERENTRY *pBufEntry;
6824 unsigned int framesize = 0;
6825 int ReturnCode = 0;
6826 unsigned long flags;
6827 struct tty_struct *tty = info->tty;
6828
6829 /*
6830 * current_rx_buffer points to the 1st buffer of the next available
6831 * receive frame. The status field is set by the 16C32 after
6832 * completing a receive frame. If the status field of this buffer
6833 * is zero, either the USC is still filling this buffer or this
6834 * is one of a series of buffers making up a received frame.
6835 *
6836 * If the count field of this buffer is zero, the USC is either
6837 * using this buffer or has used this buffer. Look at the count
6838 * field of the next buffer. If that next buffer's count is
6839 * non-zero, the USC is still actively using the current buffer.
6840 * Otherwise, if the next buffer's count field is zero, the
6841 * current buffer is complete and the USC is using the next
6842 * buffer.
6843 */
6844 CurrentIndex = NextIndex = info->current_rx_buffer;
6845 ++NextIndex;
6846 if ( NextIndex == info->rx_buffer_count )
6847 NextIndex = 0;
6848
6849 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6850 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6851 info->rx_buffer_list[NextIndex].count == 0)) {
6852 /*
6853 * Either the status field of this dma buffer is non-zero
6854 * (indicating the last buffer of a receive frame) or the next
6855 * buffer is marked as in use -- implying this buffer is complete
6856 * and an intermediate buffer for this received frame.
6857 */
6858
6859 status = info->rx_buffer_list[CurrentIndex].status;
6860
6861 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6862 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6863 if ( status & RXSTATUS_SHORT_FRAME )
6864 info->icount.rxshort++;
6865 else if ( status & RXSTATUS_ABORT )
6866 info->icount.rxabort++;
6867 else if ( status & RXSTATUS_OVERRUN )
6868 info->icount.rxover++;
6869 else
6870 info->icount.rxcrc++;
6871 framesize = 0;
6872 } else {
6873 /*
6874 * A receive frame is available, get frame size and status.
6875 *
6876 * The frame size is the starting value of the RCC (which was
6877 * set to 0xffff) minus the ending value of the RCC (decremented
6878 * once for each receive character) minus 2 or 4 for the 16-bit
6879 * or 32-bit CRC.
6880 *
6881 * If the status field is zero, this is an intermediate buffer.
6882 * It's size is 4K.
6883 *
6884 * If the DMA Buffer Entry's Status field is non-zero, the
6885 * receive operation completed normally (ie: DCD dropped). The
6886 * RCC field is valid and holds the received frame size.
6887 * It is possible that the RCC field will be zero on a DMA buffer
6888 * entry with a non-zero status. This can occur if the total
6889 * frame size (number of bytes between the time DCD goes active
6890 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6891 * case the 16C32 has underrun on the RCC count and appears to
6892 * stop updating this counter to let us know the actual received
6893 * frame size. If this happens (non-zero status and zero RCC),
6894 * simply return the entire RxDMA Buffer
6895 */
6896 if ( status ) {
6897 /*
6898 * In the event that the final RxDMA Buffer is
6899 * terminated with a non-zero status and the RCC
6900 * field is zero, we interpret this as the RCC
6901 * having underflowed (received frame > 65535 bytes).
6902 *
6903 * Signal the event to the user by passing back
6904 * a status of RxStatus_CrcError returning the full
6905 * buffer and let the app figure out what data is
6906 * actually valid
6907 */
6908 if ( info->rx_buffer_list[CurrentIndex].rcc )
6909 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6910 else
6911 framesize = DMABUFFERSIZE;
6912 }
6913 else
6914 framesize = DMABUFFERSIZE;
6915 }
6916
6917 if ( framesize > DMABUFFERSIZE ) {
6918 /*
6919 * if running in raw sync mode, ISR handler for
6920 * End Of Buffer events terminates all buffers at 4K.
6921 * If this frame size is said to be >4K, get the
6922 * actual number of bytes of the frame in this buffer.
6923 */
6924 framesize = framesize % DMABUFFERSIZE;
6925 }
6926
6927
6928 if ( debug_level >= DEBUG_LEVEL_BH )
6929 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6930 __FILE__,__LINE__,info->device_name,status,framesize);
6931
6932 if ( debug_level >= DEBUG_LEVEL_DATA )
6933 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6934 min_t(int, framesize, DMABUFFERSIZE),0);
6935
6936 if (framesize) {
6937 /* copy dma buffer(s) to contiguous intermediate buffer */
6938 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6939
6940 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6941 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6942 info->icount.rxok++;
6943
6944 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6945 }
6946
6947 /* Free the buffers used by this frame. */
6948 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6949
6950 ReturnCode = 1;
6951 }
6952
6953
6954 if ( info->rx_enabled && info->rx_overflow ) {
6955 /* The receiver needs to restarted because of
6956 * a receive overflow (buffer or FIFO). If the
6957 * receive buffers are now empty, then restart receiver.
6958 */
6959
6960 if ( !info->rx_buffer_list[CurrentIndex].status &&
6961 info->rx_buffer_list[CurrentIndex].count ) {
6962 spin_lock_irqsave(&info->irq_spinlock,flags);
6963 usc_start_receiver(info);
6964 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6965 }
6966 }
6967
6968 return ReturnCode;
6969
6970} /* end of mgsl_get_raw_rx_frame() */
6971
6972/* mgsl_load_tx_dma_buffer()
6973 *
6974 * Load the transmit DMA buffer with the specified data.
6975 *
6976 * Arguments:
6977 *
6978 * info pointer to device extension
6979 * Buffer pointer to buffer containing frame to load
6980 * BufferSize size in bytes of frame in Buffer
6981 *
6982 * Return Value: None
6983 */
6984static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6985 const char *Buffer, unsigned int BufferSize)
6986{
6987 unsigned short Copycount;
6988 unsigned int i = 0;
6989 DMABUFFERENTRY *pBufEntry;
6990
6991 if ( debug_level >= DEBUG_LEVEL_DATA )
6992 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6993
6994 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6995 /* set CMR:13 to start transmit when
6996 * next GoAhead (abort) is received
6997 */
6998 info->cmr_value |= BIT13;
6999 }
7000
7001 /* begin loading the frame in the next available tx dma
7002 * buffer, remember it's starting location for setting
7003 * up tx dma operation
7004 */
7005 i = info->current_tx_buffer;
7006 info->start_tx_dma_buffer = i;
7007
7008 /* Setup the status and RCC (Frame Size) fields of the 1st */
7009 /* buffer entry in the transmit DMA buffer list. */
7010
7011 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
7012 info->tx_buffer_list[i].rcc = BufferSize;
7013 info->tx_buffer_list[i].count = BufferSize;
7014
7015 /* Copy frame data from 1st source buffer to the DMA buffers. */
7016 /* The frame data may span multiple DMA buffers. */
7017
7018 while( BufferSize ){
7019 /* Get a pointer to next DMA buffer entry. */
7020 pBufEntry = &info->tx_buffer_list[i++];
7021
7022 if ( i == info->tx_buffer_count )
7023 i=0;
7024
7025 /* Calculate the number of bytes that can be copied from */
7026 /* the source buffer to this DMA buffer. */
7027 if ( BufferSize > DMABUFFERSIZE )
7028 Copycount = DMABUFFERSIZE;
7029 else
7030 Copycount = BufferSize;
7031
7032 /* Actually copy data from source buffer to DMA buffer. */
7033 /* Also set the data count for this individual DMA buffer. */
7034 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
7035 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
7036 else
7037 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
7038
7039 pBufEntry->count = Copycount;
7040
7041 /* Advance source pointer and reduce remaining data count. */
7042 Buffer += Copycount;
7043 BufferSize -= Copycount;
7044
7045 ++info->tx_dma_buffers_used;
7046 }
7047
7048 /* remember next available tx dma buffer */
7049 info->current_tx_buffer = i;
7050
7051} /* end of mgsl_load_tx_dma_buffer() */
7052
7053/*
7054 * mgsl_register_test()
7055 *
7056 * Performs a register test of the 16C32.
7057 *
7058 * Arguments: info pointer to device instance data
7059 * Return Value: TRUE if test passed, otherwise FALSE
7060 */
7061static BOOLEAN mgsl_register_test( struct mgsl_struct *info )
7062{
7063 static unsigned short BitPatterns[] =
7064 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7065 static unsigned int Patterncount = sizeof(BitPatterns)/sizeof(unsigned short);
7066 unsigned int i;
7067 BOOLEAN rc = TRUE;
7068 unsigned long flags;
7069
7070 spin_lock_irqsave(&info->irq_spinlock,flags);
7071 usc_reset(info);
7072
7073 /* Verify the reset state of some registers. */
7074
7075 if ( (usc_InReg( info, SICR ) != 0) ||
7076 (usc_InReg( info, IVR ) != 0) ||
7077 (usc_InDmaReg( info, DIVR ) != 0) ){
7078 rc = FALSE;
7079 }
7080
7081 if ( rc == TRUE ){
7082 /* Write bit patterns to various registers but do it out of */
7083 /* sync, then read back and verify values. */
7084
7085 for ( i = 0 ; i < Patterncount ; i++ ) {
7086 usc_OutReg( info, TC0R, BitPatterns[i] );
7087 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7088 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7089 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7090 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
7091 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7092
7093 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7094 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7095 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7096 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7097 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7098 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7099 rc = FALSE;
7100 break;
7101 }
7102 }
7103 }
7104
7105 usc_reset(info);
7106 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7107
7108 return rc;
7109
7110} /* end of mgsl_register_test() */
7111
7112/* mgsl_irq_test() Perform interrupt test of the 16C32.
7113 *
7114 * Arguments: info pointer to device instance data
7115 * Return Value: TRUE if test passed, otherwise FALSE
7116 */
7117static BOOLEAN mgsl_irq_test( struct mgsl_struct *info )
7118{
7119 unsigned long EndTime;
7120 unsigned long flags;
7121
7122 spin_lock_irqsave(&info->irq_spinlock,flags);
7123 usc_reset(info);
7124
7125 /*
7126 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7127 * The ISR sets irq_occurred to 1.
7128 */
7129
7130 info->irq_occurred = FALSE;
7131
7132 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7133 /* Enable INTEN (Port 6, Bit12) */
7134 /* This connects the IRQ request signal to the ISA bus */
7135 /* on the ISA adapter. This has no effect for the PCI adapter */
7136 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7137
7138 usc_EnableMasterIrqBit(info);
7139 usc_EnableInterrupts(info, IO_PIN);
7140 usc_ClearIrqPendingBits(info, IO_PIN);
7141
7142 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7143 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7144
7145 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7146
7147 EndTime=100;
7148 while( EndTime-- && !info->irq_occurred ) {
7149 msleep_interruptible(10);
7150 }
7151
7152 spin_lock_irqsave(&info->irq_spinlock,flags);
7153 usc_reset(info);
7154 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7155
7156 if ( !info->irq_occurred )
7157 return FALSE;
7158 else
7159 return TRUE;
7160
7161} /* end of mgsl_irq_test() */
7162
7163/* mgsl_dma_test()
7164 *
7165 * Perform a DMA test of the 16C32. A small frame is
7166 * transmitted via DMA from a transmit buffer to a receive buffer
7167 * using single buffer DMA mode.
7168 *
7169 * Arguments: info pointer to device instance data
7170 * Return Value: TRUE if test passed, otherwise FALSE
7171 */
7172static BOOLEAN mgsl_dma_test( struct mgsl_struct *info )
7173{
7174 unsigned short FifoLevel;
7175 unsigned long phys_addr;
7176 unsigned int FrameSize;
7177 unsigned int i;
7178 char *TmpPtr;
7179 BOOLEAN rc = TRUE;
7180 unsigned short status=0;
7181 unsigned long EndTime;
7182 unsigned long flags;
7183 MGSL_PARAMS tmp_params;
7184
7185 /* save current port options */
7186 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7187 /* load default port options */
7188 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7189
7190#define TESTFRAMESIZE 40
7191
7192 spin_lock_irqsave(&info->irq_spinlock,flags);
7193
7194 /* setup 16C32 for SDLC DMA transfer mode */
7195
7196 usc_reset(info);
7197 usc_set_sdlc_mode(info);
7198 usc_enable_loopback(info,1);
7199
7200 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7201 * field of the buffer entry after fetching buffer address. This
7202 * way we can detect a DMA failure for a DMA read (which should be
7203 * non-destructive to system memory) before we try and write to
7204 * memory (where a failure could corrupt system memory).
7205 */
7206
7207 /* Receive DMA mode Register (RDMR)
7208 *
7209 * <15..14> 11 DMA mode = Linked List Buffer mode
7210 * <13> 1 RSBinA/L = store Rx status Block in List entry
7211 * <12> 0 1 = Clear count of List Entry after fetching
7212 * <11..10> 00 Address mode = Increment
7213 * <9> 1 Terminate Buffer on RxBound
7214 * <8> 0 Bus Width = 16bits
7215 * <7..0> ? status Bits (write as 0s)
7216 *
7217 * 1110 0010 0000 0000 = 0xe200
7218 */
7219
7220 usc_OutDmaReg( info, RDMR, 0xe200 );
7221
7222 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7223
7224
7225 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7226
7227 FrameSize = TESTFRAMESIZE;
7228
7229 /* setup 1st transmit buffer entry: */
7230 /* with frame size and transmit control word */
7231
7232 info->tx_buffer_list[0].count = FrameSize;
7233 info->tx_buffer_list[0].rcc = FrameSize;
7234 info->tx_buffer_list[0].status = 0x4000;
7235
7236 /* build a transmit frame in 1st transmit DMA buffer */
7237
7238 TmpPtr = info->tx_buffer_list[0].virt_addr;
7239 for (i = 0; i < FrameSize; i++ )
7240 *TmpPtr++ = i;
7241
7242 /* setup 1st receive buffer entry: */
7243 /* clear status, set max receive buffer size */
7244
7245 info->rx_buffer_list[0].status = 0;
7246 info->rx_buffer_list[0].count = FrameSize + 4;
7247
7248 /* zero out the 1st receive buffer */
7249
7250 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7251
7252 /* Set count field of next buffer entries to prevent */
7253 /* 16C32 from using buffers after the 1st one. */
7254
7255 info->tx_buffer_list[1].count = 0;
7256 info->rx_buffer_list[1].count = 0;
7257
7258
7259 /***************************/
7260 /* Program 16C32 receiver. */
7261 /***************************/
7262
7263 spin_lock_irqsave(&info->irq_spinlock,flags);
7264
7265 /* setup DMA transfers */
7266 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7267
7268 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7269 phys_addr = info->rx_buffer_list[0].phys_entry;
7270 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7271 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7272
7273 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7274 usc_InDmaReg( info, RDMR );
7275 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7276
7277 /* Enable Receiver (RMR <1..0> = 10) */
7278 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7279
7280 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7281
7282
7283 /*************************************************************/
7284 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7285 /*************************************************************/
7286
7287 /* Wait 100ms for interrupt. */
7288 EndTime = jiffies + msecs_to_jiffies(100);
7289
7290 for(;;) {
7291 if (time_after(jiffies, EndTime)) {
7292 rc = FALSE;
7293 break;
7294 }
7295
7296 spin_lock_irqsave(&info->irq_spinlock,flags);
7297 status = usc_InDmaReg( info, RDMR );
7298 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7299
7300 if ( !(status & BIT4) && (status & BIT5) ) {
7301 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7302 /* BUSY (BIT 5) is active (channel still active). */
7303 /* This means the buffer entry read has completed. */
7304 break;
7305 }
7306 }
7307
7308
7309 /******************************/
7310 /* Program 16C32 transmitter. */
7311 /******************************/
7312
7313 spin_lock_irqsave(&info->irq_spinlock,flags);
7314
7315 /* Program the Transmit Character Length Register (TCLR) */
7316 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7317
7318 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7319 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7320
7321 /* Program the address of the 1st DMA Buffer Entry in linked list */
7322
7323 phys_addr = info->tx_buffer_list[0].phys_entry;
7324 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7325 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7326
7327 /* unlatch Tx status bits, and start transmit channel. */
7328
7329 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7330 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7331
7332 /* wait for DMA controller to fill transmit FIFO */
7333
7334 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7335
7336 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7337
7338
7339 /**********************************/
7340 /* WAIT FOR TRANSMIT FIFO TO FILL */
7341 /**********************************/
7342
7343 /* Wait 100ms */
7344 EndTime = jiffies + msecs_to_jiffies(100);
7345
7346 for(;;) {
7347 if (time_after(jiffies, EndTime)) {
7348 rc = FALSE;
7349 break;
7350 }
7351
7352 spin_lock_irqsave(&info->irq_spinlock,flags);
7353 FifoLevel = usc_InReg(info, TICR) >> 8;
7354 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7355
7356 if ( FifoLevel < 16 )
7357 break;
7358 else
7359 if ( FrameSize < 32 ) {
7360 /* This frame is smaller than the entire transmit FIFO */
7361 /* so wait for the entire frame to be loaded. */
7362 if ( FifoLevel <= (32 - FrameSize) )
7363 break;
7364 }
7365 }
7366
7367
7368 if ( rc == TRUE )
7369 {
7370 /* Enable 16C32 transmitter. */
7371
7372 spin_lock_irqsave(&info->irq_spinlock,flags);
7373
7374 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7375 usc_TCmd( info, TCmd_SendFrame );
7376 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7377
7378 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7379
7380
7381 /******************************/
7382 /* WAIT FOR TRANSMIT COMPLETE */
7383 /******************************/
7384
7385 /* Wait 100ms */
7386 EndTime = jiffies + msecs_to_jiffies(100);
7387
7388 /* While timer not expired wait for transmit complete */
7389
7390 spin_lock_irqsave(&info->irq_spinlock,flags);
7391 status = usc_InReg( info, TCSR );
7392 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7393
7394 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7395 if (time_after(jiffies, EndTime)) {
7396 rc = FALSE;
7397 break;
7398 }
7399
7400 spin_lock_irqsave(&info->irq_spinlock,flags);
7401 status = usc_InReg( info, TCSR );
7402 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7403 }
7404 }
7405
7406
7407 if ( rc == TRUE ){
7408 /* CHECK FOR TRANSMIT ERRORS */
7409 if ( status & (BIT5 + BIT1) )
7410 rc = FALSE;
7411 }
7412
7413 if ( rc == TRUE ) {
7414 /* WAIT FOR RECEIVE COMPLETE */
7415
7416 /* Wait 100ms */
7417 EndTime = jiffies + msecs_to_jiffies(100);
7418
7419 /* Wait for 16C32 to write receive status to buffer entry. */
7420 status=info->rx_buffer_list[0].status;
7421 while ( status == 0 ) {
7422 if (time_after(jiffies, EndTime)) {
7423 rc = FALSE;
7424 break;
7425 }
7426 status=info->rx_buffer_list[0].status;
7427 }
7428 }
7429
7430
7431 if ( rc == TRUE ) {
7432 /* CHECK FOR RECEIVE ERRORS */
7433 status = info->rx_buffer_list[0].status;
7434
7435 if ( status & (BIT8 + BIT3 + BIT1) ) {
7436 /* receive error has occurred */
7437 rc = FALSE;
7438 } else {
7439 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7440 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7441 rc = FALSE;
7442 }
7443 }
7444 }
7445
7446 spin_lock_irqsave(&info->irq_spinlock,flags);
7447 usc_reset( info );
7448 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7449
7450 /* restore current port options */
7451 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7452
7453 return rc;
7454
7455} /* end of mgsl_dma_test() */
7456
7457/* mgsl_adapter_test()
7458 *
7459 * Perform the register, IRQ, and DMA tests for the 16C32.
7460 *
7461 * Arguments: info pointer to device instance data
7462 * Return Value: 0 if success, otherwise -ENODEV
7463 */
7464static int mgsl_adapter_test( struct mgsl_struct *info )
7465{
7466 if ( debug_level >= DEBUG_LEVEL_INFO )
7467 printk( "%s(%d):Testing device %s\n",
7468 __FILE__,__LINE__,info->device_name );
7469
7470 if ( !mgsl_register_test( info ) ) {
7471 info->init_error = DiagStatus_AddressFailure;
7472 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7473 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7474 return -ENODEV;
7475 }
7476
7477 if ( !mgsl_irq_test( info ) ) {
7478 info->init_error = DiagStatus_IrqFailure;
7479 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7480 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7481 return -ENODEV;
7482 }
7483
7484 if ( !mgsl_dma_test( info ) ) {
7485 info->init_error = DiagStatus_DmaFailure;
7486 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7487 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7488 return -ENODEV;
7489 }
7490
7491 if ( debug_level >= DEBUG_LEVEL_INFO )
7492 printk( "%s(%d):device %s passed diagnostics\n",
7493 __FILE__,__LINE__,info->device_name );
7494
7495 return 0;
7496
7497} /* end of mgsl_adapter_test() */
7498
7499/* mgsl_memory_test()
7500 *
7501 * Test the shared memory on a PCI adapter.
7502 *
7503 * Arguments: info pointer to device instance data
7504 * Return Value: TRUE if test passed, otherwise FALSE
7505 */
7506static BOOLEAN mgsl_memory_test( struct mgsl_struct *info )
7507{
7508 static unsigned long BitPatterns[] = { 0x0, 0x55555555, 0xaaaaaaaa,
7509 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7510 unsigned long Patterncount = sizeof(BitPatterns)/sizeof(unsigned long);
7511 unsigned long i;
7512 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7513 unsigned long * TestAddr;
7514
7515 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7516 return TRUE;
7517
7518 TestAddr = (unsigned long *)info->memory_base;
7519
7520 /* Test data lines with test pattern at one location. */
7521
7522 for ( i = 0 ; i < Patterncount ; i++ ) {
7523 *TestAddr = BitPatterns[i];
7524 if ( *TestAddr != BitPatterns[i] )
7525 return FALSE;
7526 }
7527
7528 /* Test address lines with incrementing pattern over */
7529 /* entire address range. */
7530
7531 for ( i = 0 ; i < TestLimit ; i++ ) {
7532 *TestAddr = i * 4;
7533 TestAddr++;
7534 }
7535
7536 TestAddr = (unsigned long *)info->memory_base;
7537
7538 for ( i = 0 ; i < TestLimit ; i++ ) {
7539 if ( *TestAddr != i * 4 )
7540 return FALSE;
7541 TestAddr++;
7542 }
7543
7544 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7545
7546 return TRUE;
7547
7548} /* End Of mgsl_memory_test() */
7549
7550
7551/* mgsl_load_pci_memory()
7552 *
7553 * Load a large block of data into the PCI shared memory.
7554 * Use this instead of memcpy() or memmove() to move data
7555 * into the PCI shared memory.
7556 *
7557 * Notes:
7558 *
7559 * This function prevents the PCI9050 interface chip from hogging
7560 * the adapter local bus, which can starve the 16C32 by preventing
7561 * 16C32 bus master cycles.
7562 *
7563 * The PCI9050 documentation says that the 9050 will always release
7564 * control of the local bus after completing the current read
7565 * or write operation.
7566 *
7567 * It appears that as long as the PCI9050 write FIFO is full, the
7568 * PCI9050 treats all of the writes as a single burst transaction
7569 * and will not release the bus. This causes DMA latency problems
7570 * at high speeds when copying large data blocks to the shared
7571 * memory.
7572 *
7573 * This function in effect, breaks the a large shared memory write
7574 * into multiple transations by interleaving a shared memory read
7575 * which will flush the write FIFO and 'complete' the write
7576 * transation. This allows any pending DMA request to gain control
7577 * of the local bus in a timely fasion.
7578 *
7579 * Arguments:
7580 *
7581 * TargetPtr pointer to target address in PCI shared memory
7582 * SourcePtr pointer to source buffer for data
7583 * count count in bytes of data to copy
7584 *
7585 * Return Value: None
7586 */
7587static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7588 unsigned short count )
7589{
7590 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7591#define PCI_LOAD_INTERVAL 64
7592
7593 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7594 unsigned short Index;
7595 unsigned long Dummy;
7596
7597 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7598 {
7599 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7600 Dummy = *((volatile unsigned long *)TargetPtr);
7601 TargetPtr += PCI_LOAD_INTERVAL;
7602 SourcePtr += PCI_LOAD_INTERVAL;
7603 }
7604
7605 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7606
7607} /* End Of mgsl_load_pci_memory() */
7608
7609static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7610{
7611 int i;
7612 int linecount;
7613 if (xmit)
7614 printk("%s tx data:\n",info->device_name);
7615 else
7616 printk("%s rx data:\n",info->device_name);
7617
7618 while(count) {
7619 if (count > 16)
7620 linecount = 16;
7621 else
7622 linecount = count;
7623
7624 for(i=0;i<linecount;i++)
7625 printk("%02X ",(unsigned char)data[i]);
7626 for(;i<17;i++)
7627 printk(" ");
7628 for(i=0;i<linecount;i++) {
7629 if (data[i]>=040 && data[i]<=0176)
7630 printk("%c",data[i]);
7631 else
7632 printk(".");
7633 }
7634 printk("\n");
7635
7636 data += linecount;
7637 count -= linecount;
7638 }
7639} /* end of mgsl_trace_block() */
7640
7641/* mgsl_tx_timeout()
7642 *
7643 * called when HDLC frame times out
7644 * update stats and do tx completion processing
7645 *
7646 * Arguments: context pointer to device instance data
7647 * Return Value: None
7648 */
7649static void mgsl_tx_timeout(unsigned long context)
7650{
7651 struct mgsl_struct *info = (struct mgsl_struct*)context;
7652 unsigned long flags;
7653
7654 if ( debug_level >= DEBUG_LEVEL_INFO )
7655 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7656 __FILE__,__LINE__,info->device_name);
7657 if(info->tx_active &&
7658 (info->params.mode == MGSL_MODE_HDLC ||
7659 info->params.mode == MGSL_MODE_RAW) ) {
7660 info->icount.txtimeout++;
7661 }
7662 spin_lock_irqsave(&info->irq_spinlock,flags);
7663 info->tx_active = 0;
7664 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7665
7666 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7667 usc_loopmode_cancel_transmit( info );
7668
7669 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7670
7671#ifdef CONFIG_HDLC
7672 if (info->netcount)
7673 hdlcdev_tx_done(info);
7674 else
7675#endif
7676 mgsl_bh_transmit(info);
7677
7678} /* end of mgsl_tx_timeout() */
7679
7680/* signal that there are no more frames to send, so that
7681 * line is 'released' by echoing RxD to TxD when current
7682 * transmission is complete (or immediately if no tx in progress).
7683 */
7684static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7685{
7686 unsigned long flags;
7687
7688 spin_lock_irqsave(&info->irq_spinlock,flags);
7689 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7690 if (info->tx_active)
7691 info->loopmode_send_done_requested = TRUE;
7692 else
7693 usc_loopmode_send_done(info);
7694 }
7695 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7696
7697 return 0;
7698}
7699
7700/* release the line by echoing RxD to TxD
7701 * upon completion of a transmit frame
7702 */
7703static void usc_loopmode_send_done( struct mgsl_struct * info )
7704{
7705 info->loopmode_send_done_requested = FALSE;
7706 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7707 info->cmr_value &= ~BIT13;
7708 usc_OutReg(info, CMR, info->cmr_value);
7709}
7710
7711/* abort a transmit in progress while in HDLC LoopMode
7712 */
7713static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7714{
7715 /* reset tx dma channel and purge TxFifo */
7716 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7717 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7718 usc_loopmode_send_done( info );
7719}
7720
7721/* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7722 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7723 * we must clear CMR:13 to begin repeating TxData to RxData
7724 */
7725static void usc_loopmode_insert_request( struct mgsl_struct * info )
7726{
7727 info->loopmode_insert_requested = TRUE;
7728
7729 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7730 * begin repeating TxData on RxData (complete insertion)
7731 */
7732 usc_OutReg( info, RICR,
7733 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7734
7735 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7736 info->cmr_value |= BIT13;
7737 usc_OutReg(info, CMR, info->cmr_value);
7738}
7739
7740/* return 1 if station is inserted into the loop, otherwise 0
7741 */
7742static int usc_loopmode_active( struct mgsl_struct * info)
7743{
7744 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7745}
7746
7747#ifdef CONFIG_HDLC
7748
7749/**
7750 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7751 * set encoding and frame check sequence (FCS) options
7752 *
7753 * dev pointer to network device structure
7754 * encoding serial encoding setting
7755 * parity FCS setting
7756 *
7757 * returns 0 if success, otherwise error code
7758 */
7759static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7760 unsigned short parity)
7761{
7762 struct mgsl_struct *info = dev_to_port(dev);
7763 unsigned char new_encoding;
7764 unsigned short new_crctype;
7765
7766 /* return error if TTY interface open */
7767 if (info->count)
7768 return -EBUSY;
7769
7770 switch (encoding)
7771 {
7772 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7773 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7774 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7775 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7776 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7777 default: return -EINVAL;
7778 }
7779
7780 switch (parity)
7781 {
7782 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7783 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7784 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7785 default: return -EINVAL;
7786 }
7787
7788 info->params.encoding = new_encoding;
7789 info->params.crc_type = new_crctype;;
7790
7791 /* if network interface up, reprogram hardware */
7792 if (info->netcount)
7793 mgsl_program_hw(info);
7794
7795 return 0;
7796}
7797
7798/**
7799 * called by generic HDLC layer to send frame
7800 *
7801 * skb socket buffer containing HDLC frame
7802 * dev pointer to network device structure
7803 *
7804 * returns 0 if success, otherwise error code
7805 */
7806static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7807{
7808 struct mgsl_struct *info = dev_to_port(dev);
7809 struct net_device_stats *stats = hdlc_stats(dev);
7810 unsigned long flags;
7811
7812 if (debug_level >= DEBUG_LEVEL_INFO)
7813 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7814
7815 /* stop sending until this frame completes */
7816 netif_stop_queue(dev);
7817
7818 /* copy data to device buffers */
7819 info->xmit_cnt = skb->len;
7820 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7821
7822 /* update network statistics */
7823 stats->tx_packets++;
7824 stats->tx_bytes += skb->len;
7825
7826 /* done with socket buffer, so free it */
7827 dev_kfree_skb(skb);
7828
7829 /* save start time for transmit timeout detection */
7830 dev->trans_start = jiffies;
7831
7832 /* start hardware transmitter if necessary */
7833 spin_lock_irqsave(&info->irq_spinlock,flags);
7834 if (!info->tx_active)
7835 usc_start_transmitter(info);
7836 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7837
7838 return 0;
7839}
7840
7841/**
7842 * called by network layer when interface enabled
7843 * claim resources and initialize hardware
7844 *
7845 * dev pointer to network device structure
7846 *
7847 * returns 0 if success, otherwise error code
7848 */
7849static int hdlcdev_open(struct net_device *dev)
7850{
7851 struct mgsl_struct *info = dev_to_port(dev);
7852 int rc;
7853 unsigned long flags;
7854
7855 if (debug_level >= DEBUG_LEVEL_INFO)
7856 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7857
7858 /* generic HDLC layer open processing */
7859 if ((rc = hdlc_open(dev)))
7860 return rc;
7861
7862 /* arbitrate between network and tty opens */
7863 spin_lock_irqsave(&info->netlock, flags);
7864 if (info->count != 0 || info->netcount != 0) {
7865 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7866 spin_unlock_irqrestore(&info->netlock, flags);
7867 return -EBUSY;
7868 }
7869 info->netcount=1;
7870 spin_unlock_irqrestore(&info->netlock, flags);
7871
7872 /* claim resources and init adapter */
7873 if ((rc = startup(info)) != 0) {
7874 spin_lock_irqsave(&info->netlock, flags);
7875 info->netcount=0;
7876 spin_unlock_irqrestore(&info->netlock, flags);
7877 return rc;
7878 }
7879
7880 /* assert DTR and RTS, apply hardware settings */
7881 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7882 mgsl_program_hw(info);
7883
7884 /* enable network layer transmit */
7885 dev->trans_start = jiffies;
7886 netif_start_queue(dev);
7887
7888 /* inform generic HDLC layer of current DCD status */
7889 spin_lock_irqsave(&info->irq_spinlock, flags);
7890 usc_get_serial_signals(info);
7891 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7892 hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
7893
7894 return 0;
7895}
7896
7897/**
7898 * called by network layer when interface is disabled
7899 * shutdown hardware and release resources
7900 *
7901 * dev pointer to network device structure
7902 *
7903 * returns 0 if success, otherwise error code
7904 */
7905static int hdlcdev_close(struct net_device *dev)
7906{
7907 struct mgsl_struct *info = dev_to_port(dev);
7908 unsigned long flags;
7909
7910 if (debug_level >= DEBUG_LEVEL_INFO)
7911 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7912
7913 netif_stop_queue(dev);
7914
7915 /* shutdown adapter and release resources */
7916 shutdown(info);
7917
7918 hdlc_close(dev);
7919
7920 spin_lock_irqsave(&info->netlock, flags);
7921 info->netcount=0;
7922 spin_unlock_irqrestore(&info->netlock, flags);
7923
7924 return 0;
7925}
7926
7927/**
7928 * called by network layer to process IOCTL call to network device
7929 *
7930 * dev pointer to network device structure
7931 * ifr pointer to network interface request structure
7932 * cmd IOCTL command code
7933 *
7934 * returns 0 if success, otherwise error code
7935 */
7936static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7937{
7938 const size_t size = sizeof(sync_serial_settings);
7939 sync_serial_settings new_line;
7940 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7941 struct mgsl_struct *info = dev_to_port(dev);
7942 unsigned int flags;
7943
7944 if (debug_level >= DEBUG_LEVEL_INFO)
7945 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7946
7947 /* return error if TTY interface open */
7948 if (info->count)
7949 return -EBUSY;
7950
7951 if (cmd != SIOCWANDEV)
7952 return hdlc_ioctl(dev, ifr, cmd);
7953
7954 switch(ifr->ifr_settings.type) {
7955 case IF_GET_IFACE: /* return current sync_serial_settings */
7956
7957 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7958 if (ifr->ifr_settings.size < size) {
7959 ifr->ifr_settings.size = size; /* data size wanted */
7960 return -ENOBUFS;
7961 }
7962
7963 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7964 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7965 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7966 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7967
7968 switch (flags){
7969 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7970 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7971 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7972 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7973 default: new_line.clock_type = CLOCK_DEFAULT;
7974 }
7975
7976 new_line.clock_rate = info->params.clock_speed;
7977 new_line.loopback = info->params.loopback ? 1:0;
7978
7979 if (copy_to_user(line, &new_line, size))
7980 return -EFAULT;
7981 return 0;
7982
7983 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7984
7985 if(!capable(CAP_NET_ADMIN))
7986 return -EPERM;
7987 if (copy_from_user(&new_line, line, size))
7988 return -EFAULT;
7989
7990 switch (new_line.clock_type)
7991 {
7992 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7993 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7994 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7995 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7996 case CLOCK_DEFAULT: flags = info->params.flags &
7997 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7998 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7999 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
8000 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
8001 default: return -EINVAL;
8002 }
8003
8004 if (new_line.loopback != 0 && new_line.loopback != 1)
8005 return -EINVAL;
8006
8007 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
8008 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
8009 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
8010 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
8011 info->params.flags |= flags;
8012
8013 info->params.loopback = new_line.loopback;
8014
8015 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
8016 info->params.clock_speed = new_line.clock_rate;
8017 else
8018 info->params.clock_speed = 0;
8019
8020 /* if network interface up, reprogram hardware */
8021 if (info->netcount)
8022 mgsl_program_hw(info);
8023 return 0;
8024
8025 default:
8026 return hdlc_ioctl(dev, ifr, cmd);
8027 }
8028}
8029
8030/**
8031 * called by network layer when transmit timeout is detected
8032 *
8033 * dev pointer to network device structure
8034 */
8035static void hdlcdev_tx_timeout(struct net_device *dev)
8036{
8037 struct mgsl_struct *info = dev_to_port(dev);
8038 struct net_device_stats *stats = hdlc_stats(dev);
8039 unsigned long flags;
8040
8041 if (debug_level >= DEBUG_LEVEL_INFO)
8042 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
8043
8044 stats->tx_errors++;
8045 stats->tx_aborted_errors++;
8046
8047 spin_lock_irqsave(&info->irq_spinlock,flags);
8048 usc_stop_transmitter(info);
8049 spin_unlock_irqrestore(&info->irq_spinlock,flags);
8050
8051 netif_wake_queue(dev);
8052}
8053
8054/**
8055 * called by device driver when transmit completes
8056 * reenable network layer transmit if stopped
8057 *
8058 * info pointer to device instance information
8059 */
8060static void hdlcdev_tx_done(struct mgsl_struct *info)
8061{
8062 if (netif_queue_stopped(info->netdev))
8063 netif_wake_queue(info->netdev);
8064}
8065
8066/**
8067 * called by device driver when frame received
8068 * pass frame to network layer
8069 *
8070 * info pointer to device instance information
8071 * buf pointer to buffer contianing frame data
8072 * size count of data bytes in buf
8073 */
8074static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
8075{
8076 struct sk_buff *skb = dev_alloc_skb(size);
8077 struct net_device *dev = info->netdev;
8078 struct net_device_stats *stats = hdlc_stats(dev);
8079
8080 if (debug_level >= DEBUG_LEVEL_INFO)
8081 printk("hdlcdev_rx(%s)\n",dev->name);
8082
8083 if (skb == NULL) {
8084 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
8085 stats->rx_dropped++;
8086 return;
8087 }
8088
8089 memcpy(skb_put(skb, size),buf,size);
8090
8091 skb->protocol = hdlc_type_trans(skb, info->netdev);
8092
8093 stats->rx_packets++;
8094 stats->rx_bytes += size;
8095
8096 netif_rx(skb);
8097
8098 info->netdev->last_rx = jiffies;
8099}
8100
8101/**
8102 * called by device driver when adding device instance
8103 * do generic HDLC initialization
8104 *
8105 * info pointer to device instance information
8106 *
8107 * returns 0 if success, otherwise error code
8108 */
8109static int hdlcdev_init(struct mgsl_struct *info)
8110{
8111 int rc;
8112 struct net_device *dev;
8113 hdlc_device *hdlc;
8114
8115 /* allocate and initialize network and HDLC layer objects */
8116
8117 if (!(dev = alloc_hdlcdev(info))) {
8118 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8119 return -ENOMEM;
8120 }
8121
8122 /* for network layer reporting purposes only */
8123 dev->base_addr = info->io_base;
8124 dev->irq = info->irq_level;
8125 dev->dma = info->dma_level;
8126
8127 /* network layer callbacks and settings */
8128 dev->do_ioctl = hdlcdev_ioctl;
8129 dev->open = hdlcdev_open;
8130 dev->stop = hdlcdev_close;
8131 dev->tx_timeout = hdlcdev_tx_timeout;
8132 dev->watchdog_timeo = 10*HZ;
8133 dev->tx_queue_len = 50;
8134
8135 /* generic HDLC layer callbacks and settings */
8136 hdlc = dev_to_hdlc(dev);
8137 hdlc->attach = hdlcdev_attach;
8138 hdlc->xmit = hdlcdev_xmit;
8139
8140 /* register objects with HDLC layer */
8141 if ((rc = register_hdlc_device(dev))) {
8142 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8143 free_netdev(dev);
8144 return rc;
8145 }
8146
8147 info->netdev = dev;
8148 return 0;
8149}
8150
8151/**
8152 * called by device driver when removing device instance
8153 * do generic HDLC cleanup
8154 *
8155 * info pointer to device instance information
8156 */
8157static void hdlcdev_exit(struct mgsl_struct *info)
8158{
8159 unregister_hdlc_device(info->netdev);
8160 free_netdev(info->netdev);
8161 info->netdev = NULL;
8162}
8163
8164#endif /* CONFIG_HDLC */
8165
8166
8167static int __devinit synclink_init_one (struct pci_dev *dev,
8168 const struct pci_device_id *ent)
8169{
8170 struct mgsl_struct *info;
8171
8172 if (pci_enable_device(dev)) {
8173 printk("error enabling pci device %p\n", dev);
8174 return -EIO;
8175 }
8176
8177 if (!(info = mgsl_allocate_device())) {
8178 printk("can't allocate device instance data.\n");
8179 return -EIO;
8180 }
8181
8182 /* Copy user configuration info to device instance data */
8183
8184 info->io_base = pci_resource_start(dev, 2);
8185 info->irq_level = dev->irq;
8186 info->phys_memory_base = pci_resource_start(dev, 3);
8187
8188 /* Because veremap only works on page boundaries we must map
8189 * a larger area than is actually implemented for the LCR
8190 * memory range. We map a full page starting at the page boundary.
8191 */
8192 info->phys_lcr_base = pci_resource_start(dev, 0);
8193 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8194 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8195
8196 info->bus_type = MGSL_BUS_TYPE_PCI;
8197 info->io_addr_size = 8;
8198 info->irq_flags = SA_SHIRQ;
8199
8200 if (dev->device == 0x0210) {
8201 /* Version 1 PCI9030 based universal PCI adapter */
8202 info->misc_ctrl_value = 0x007c4080;
8203 info->hw_version = 1;
8204 } else {
8205 /* Version 0 PCI9050 based 5V PCI adapter
8206 * A PCI9050 bug prevents reading LCR registers if
8207 * LCR base address bit 7 is set. Maintain shadow
8208 * value so we can write to LCR misc control reg.
8209 */
8210 info->misc_ctrl_value = 0x087e4546;
8211 info->hw_version = 0;
8212 }
8213
8214 mgsl_add_device(info);
8215
8216 return 0;
8217}
8218
8219static void __devexit synclink_remove_one (struct pci_dev *dev)
8220{
8221}
8222
Linux 6.x block layer and io_uring tree(s)