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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[linux-2.6-block.git] / drivers / char / rocket.c
CommitLineData
1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
1da177e4
LT		 43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
58#define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
59
60/****** Kernel includes ******/
61
1da177e4
LT		 62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
44b7d1b3 75#include <linux/serial.h>
1da177e4
LT		 76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
69f545ea 79#include <linux/mutex.h>
1da177e4
LT		 80#include <linux/ioport.h>
81#include <linux/delay.h>
8cf5a8c5 82#include <linux/completion.h>
1da177e4
LT		 83#include <linux/wait.h>
84#include <linux/pci.h>
44b7d1b3 85#include <linux/uaccess.h>
1da177e4 86#include <asm/atomic.h>
457fb605 87#include <asm/unaligned.h>
1da177e4
LT		 88#include <linux/bitops.h>
89#include <linux/spinlock.h>
1da177e4
LT		 90#include <linux/init.h>
91
92/****** RocketPort includes ******/
93
94#include "rocket_int.h"
95#include "rocket.h"
96
97#define ROCKET_VERSION "2.09"
98#define ROCKET_DATE "12-June-2003"
99
100/****** RocketPort Local Variables ******/
101
40565f19
JS		 102static void rp_do_poll(unsigned long dummy);
103
1da177e4
LT		 104static struct tty_driver *rocket_driver;
105
106static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108};
109
110static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 114static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 115
116static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117static unsigned long board2;
118static unsigned long board3;
119static unsigned long board4;
120static unsigned long controller;
121static int support_low_speed;
122static unsigned long modem1;
123static unsigned long modem2;
124static unsigned long modem3;
125static unsigned long modem4;
126static unsigned long pc104_1[8];
127static unsigned long pc104_2[8];
128static unsigned long pc104_3[8];
129static unsigned long pc104_4[8];
130static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133static unsigned long rcktpt_io_addr[NUM_BOARDS];
134static int rcktpt_type[NUM_BOARDS];
135static int is_PCI[NUM_BOARDS];
136static rocketModel_t rocketModel[NUM_BOARDS];
137static int max_board;
31f35939 138static const struct tty_port_operations rocket_port_ops;
1da177e4
LT		 139
140/*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151};
152
153static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
157 UPCI_AIOP_INTR_BIT_3
158};
159
f15313bf
AB		 160static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
179};
180
181static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
195};
196
197static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
206};
207
208static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
210};
211
212static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
214};
215
216static int sClockPrescale = 0x14;
217
1da177e4
LT		 218/*
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
222 */
223static unsigned char lineNumbers[MAX_RP_PORTS];
224static unsigned long nextLineNumber;
225
226/***** RocketPort Static Prototypes *********/
227static int __init init_ISA(int i);
228static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229static void rp_flush_buffer(struct tty_struct *tty);
230static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233static void rp_start(struct tty_struct *tty);
f15313bf
AB		 234static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
235 int ChanNum);
236static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237static void sFlushRxFIFO(CHANNEL_T * ChP);
238static void sFlushTxFIFO(CHANNEL_T * ChP);
239static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
248 int UPCIRingInd);
249static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252static int sReadAiopID(ByteIO_t io);
253static int sReadAiopNumChan(WordIO_t io);
1da177e4 254
1da177e4
LT		 255MODULE_AUTHOR("Theodore Ts'o");
256MODULE_DESCRIPTION("Comtrol RocketPort driver");
257module_param(board1, ulong, 0);
258MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259module_param(board2, ulong, 0);
260MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261module_param(board3, ulong, 0);
262MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263module_param(board4, ulong, 0);
264MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265module_param(controller, ulong, 0);
266MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267module_param(support_low_speed, bool, 0);
268MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269module_param(modem1, ulong, 0);
270MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271module_param(modem2, ulong, 0);
272MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273module_param(modem3, ulong, 0);
274MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275module_param(modem4, ulong, 0);
276MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277module_param_array(pc104_1, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279module_param_array(pc104_2, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281module_param_array(pc104_3, ulong, NULL, 0);
282MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283module_param_array(pc104_4, ulong, NULL, 0);
284MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
285
d269cdd0 286static int rp_init(void);
1da177e4
LT		 287static void rp_cleanup_module(void);
288
289module_init(rp_init);
290module_exit(rp_cleanup_module);
291
1da177e4 292
1da177e4 293MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 294
295/*************************************************************************/
296/* Module code starts here */
297
298static inline int rocket_paranoia_check(struct r_port *info,
299 const char *routine)
300{
301#ifdef ROCKET_PARANOIA_CHECK
302 if (!info)
303 return 1;
304 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
1da177e4
LT		 307 return 1;
308 }
309#endif
310 return 0;
311}
312
313
314/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
316 * tty layer.
317 */
318static void rp_do_receive(struct r_port *info,
319 struct tty_struct *tty,
320 CHANNEL_t * cp, unsigned int ChanStatus)
321{
322 unsigned int CharNStat;
cc44a817
PF		 323 int ToRecv, wRecv, space;
324 unsigned char *cbuf;
1da177e4
LT		 325
326 ToRecv = sGetRxCnt(cp);
1da177e4 327#ifdef ROCKET_DEBUG_INTR
68562b79 328 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 329#endif
cc44a817
PF		 330 if (ToRecv == 0)
331 return;
33f0f88f 332
1da177e4
LT		 333 /*
334 * if status indicates there are errored characters in the
335 * FIFO, then enter status mode (a word in FIFO holds
336 * character and status).
337 */
338 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
339 if (!(ChanStatus & STATMODE)) {
340#ifdef ROCKET_DEBUG_RECEIVE
68562b79 341 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 342#endif
343 ChanStatus |= STATMODE;
344 sEnRxStatusMode(cp);
345 }
346 }
347
348 /*
349 * if we previously entered status mode, then read down the
350 * FIFO one word at a time, pulling apart the character and
351 * the status. Update error counters depending on status
352 */
353 if (ChanStatus & STATMODE) {
354#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 355 printk(KERN_INFO "Ignore %x, read %x...\n",
356 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 357#endif
358 while (ToRecv) {
cc44a817
PF		 359 char flag;
360
1da177e4
LT		 361 CharNStat = sInW(sGetTxRxDataIO(cp));
362#ifdef ROCKET_DEBUG_RECEIVE
68562b79 363 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 364#endif
365 if (CharNStat & STMBREAKH)
366 CharNStat &= ~(STMFRAMEH | STMPARITYH);
367 if (CharNStat & info->ignore_status_mask) {
368 ToRecv--;
369 continue;
370 }
371 CharNStat &= info->read_status_mask;
372 if (CharNStat & STMBREAKH)
cc44a817 373 flag = TTY_BREAK;
1da177e4 374 else if (CharNStat & STMPARITYH)
cc44a817 375 flag = TTY_PARITY;
1da177e4 376 else if (CharNStat & STMFRAMEH)
cc44a817 377 flag = TTY_FRAME;
1da177e4 378 else if (CharNStat & STMRCVROVRH)
cc44a817 379 flag = TTY_OVERRUN;
1da177e4 380 else
cc44a817
PF		 381 flag = TTY_NORMAL;
382 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
1da177e4
LT		 383 ToRecv--;
384 }
385
386 /*
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
389 */
390 if (sGetRxCnt(cp) == 0) {
391#ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
393#endif
394 sDisRxStatusMode(cp);
395 }
396 } else {
397 /*
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
400 * transfer.
401 */
cc44a817
PF		 402 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
403 if (space < ToRecv) {
404#ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
406#endif
407 if (space <= 0)
408 return;
409 ToRecv = space;
410 }
1da177e4
LT		 411 wRecv = ToRecv >> 1;
412 if (wRecv)
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
414 if (ToRecv & 1)
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 416 }
417 /* Push the data up to the tty layer */
cc44a817 418 tty_flip_buffer_push(tty);
1da177e4
LT		 419}
420
421/*
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
426 */
427static void rp_do_transmit(struct r_port *info)
428{
429 int c;
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
432 unsigned long flags;
433
434#ifdef ROCKET_DEBUG_INTR
68562b79 435 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 436#endif
437 if (!info)
438 return;
47b01b3a
AC		 439 tty = tty_port_tty_get(&info->port);
440
441 if (tty == NULL) {
442 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
1da177e4
LT		 443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
444 return;
445 }
446
447 spin_lock_irqsave(&info->slock, flags);
1da177e4
LT		 448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
449
450 /* Loop sending data to FIFO until done or FIFO full */
451 while (1) {
452 if (tty->stopped || tty->hw_stopped)
453 break;
709107fc
HH		 454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
1da177e4
LT		 456 if (c <= 0 || info->xmit_fifo_room <= 0)
457 break;
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
459 if (c & 1)
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
463 info->xmit_cnt -= c;
464 info->xmit_fifo_room -= c;
465#ifdef ROCKET_DEBUG_INTR
68562b79 466 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 467#endif
468 }
469
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
472
473 if (info->xmit_cnt < WAKEUP_CHARS) {
474 tty_wakeup(tty);
1da177e4
LT		 475#ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
477#endif
478 }
479
480 spin_unlock_irqrestore(&info->slock, flags);
47b01b3a 481 tty_kref_put(tty);
1da177e4
LT		 482
483#ifdef ROCKET_DEBUG_INTR
68562b79 484 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 485 info->xmit_tail, info->xmit_fifo_room);
486#endif
487}
488
489/*
490 * Called when a serial port signals it has read data in it's RX FIFO.
491 * It checks what interrupts are pending and services them, including
492 * receiving serial data.
493 */
494static void rp_handle_port(struct r_port *info)
495{
496 CHANNEL_t *cp;
497 struct tty_struct *tty;
498 unsigned int IntMask, ChanStatus;
499
500 if (!info)
501 return;
502
21bed701 503 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
68562b79
JS		 504 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
505 "info->flags & NOT_INIT\n");
1da177e4
LT		 506 return;
507 }
47b01b3a
AC		 508 tty = tty_port_tty_get(&info->port);
509 if (!tty) {
68562b79 510 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
47b01b3a 511 "tty==NULL\n");
1da177e4
LT		 512 return;
513 }
514 cp = &info->channel;
1da177e4
LT		 515
516 IntMask = sGetChanIntID(cp) & info->intmask;
517#ifdef ROCKET_DEBUG_INTR
68562b79 518 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 519#endif
520 ChanStatus = sGetChanStatus(cp);
521 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
522 rp_do_receive(info, tty, cp, ChanStatus);
523 }
524 if (IntMask & DELTA_CD) { /* CD change */
525#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 526 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 527 (ChanStatus & CD_ACT) ? "on" : "off");
528#endif
529 if (!(ChanStatus & CD_ACT) && info->cd_status) {
530#ifdef ROCKET_DEBUG_HANGUP
531 printk(KERN_INFO "CD drop, calling hangup.\n");
532#endif
533 tty_hangup(tty);
534 }
535 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
e60a1084 536 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 537 }
538#ifdef ROCKET_DEBUG_INTR
539 if (IntMask & DELTA_CTS) { /* CTS change */
540 printk(KERN_INFO "CTS change...\n");
541 }
542 if (IntMask & DELTA_DSR) { /* DSR change */
543 printk(KERN_INFO "DSR change...\n");
544 }
545#endif
47b01b3a 546 tty_kref_put(tty);
1da177e4
LT		 547}
548
549/*
550 * The top level polling routine. Repeats every 1/100 HZ (10ms).
551 */
552static void rp_do_poll(unsigned long dummy)
553{
554 CONTROLLER_t *ctlp;
6c0286b1
JS		 555 int ctrl, aiop, ch, line;
556 unsigned int xmitmask, i;
1da177e4
LT		 557 unsigned int CtlMask;
558 unsigned char AiopMask;
559 Word_t bit;
560
561 /* Walk through all the boards (ctrl's) */
562 for (ctrl = 0; ctrl < max_board; ctrl++) {
563 if (rcktpt_io_addr[ctrl] <= 0)
564 continue;
565
566 /* Get a ptr to the board's control struct */
567 ctlp = sCtlNumToCtlPtr(ctrl);
568
3a4fa0a2 569 /* Get the interrupt status from the board */
1da177e4
LT		 570#ifdef CONFIG_PCI
571 if (ctlp->BusType == isPCI)
572 CtlMask = sPCIGetControllerIntStatus(ctlp);
573 else
574#endif
575 CtlMask = sGetControllerIntStatus(ctlp);
576
577 /* Check if any AIOP read bits are set */
578 for (aiop = 0; CtlMask; aiop++) {
579 bit = ctlp->AiopIntrBits[aiop];
580 if (CtlMask & bit) {
581 CtlMask &= ~bit;
582 AiopMask = sGetAiopIntStatus(ctlp, aiop);
583
584 /* Check if any port read bits are set */
585 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
586 if (AiopMask & 1) {
587
588 /* Get the line number (/dev/ttyRx number). */
589 /* Read the data from the port. */
590 line = GetLineNumber(ctrl, aiop, ch);
591 rp_handle_port(rp_table[line]);
592 }
593 }
594 }
595 }
596
597 xmitmask = xmit_flags[ctrl];
598
599 /*
600 * xmit_flags contains bit-significant flags, indicating there is data
601 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
602 * 1, ... (32 total possible). The variable i has the aiop and ch
603 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
604 */
605 if (xmitmask) {
606 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
607 if (xmitmask & (1 << i)) {
608 aiop = (i & 0x18) >> 3;
609 ch = i & 0x07;
610 line = GetLineNumber(ctrl, aiop, ch);
611 rp_do_transmit(rp_table[line]);
612 }
613 }
614 }
615 }
616
617 /*
618 * Reset the timer so we get called at the next clock tick (10ms).
619 */
620 if (atomic_read(&rp_num_ports_open))
621 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
622}
623
624/*
625 * Initializes the r_port structure for a port, as well as enabling the port on
626 * the board.
627 * Inputs: board, aiop, chan numbers
628 */
629static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
630{
631 unsigned rocketMode;
632 struct r_port *info;
633 int line;
634 CONTROLLER_T *ctlp;
635
636 /* Get the next available line number */
637 line = SetLineNumber(board, aiop, chan);
638
639 ctlp = sCtlNumToCtlPtr(board);
640
641 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 642 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 643 if (!info) {
68562b79
JS		 644 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
645 line);
1da177e4
LT		 646 return;
647 }
1da177e4
LT		 648
649 info->magic = RPORT_MAGIC;
650 info->line = line;
651 info->ctlp = ctlp;
652 info->board = board;
653 info->aiop = aiop;
654 info->chan = chan;
31f35939
AC		 655 tty_port_init(&info->port);
656 info->port.ops = &rocket_port_ops;
8cf5a8c5 657 init_completion(&info->close_wait);
1da177e4
LT		 658 info->flags &= ~ROCKET_MODE_MASK;
659 switch (pc104[board][line]) {
660 case 422:
661 info->flags |= ROCKET_MODE_RS422;
662 break;
663 case 485:
664 info->flags |= ROCKET_MODE_RS485;
665 break;
666 case 232:
667 default:
668 info->flags |= ROCKET_MODE_RS232;
669 break;
670 }
671
672 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
673 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 674 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
675 board, aiop, chan);
1da177e4
LT		 676 kfree(info);
677 return;
678 }
679
680 rocketMode = info->flags & ROCKET_MODE_MASK;
681
682 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
683 sEnRTSToggle(&info->channel);
684 else
685 sDisRTSToggle(&info->channel);
686
687 if (ctlp->boardType == ROCKET_TYPE_PC104) {
688 switch (rocketMode) {
689 case ROCKET_MODE_RS485:
690 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
691 break;
692 case ROCKET_MODE_RS422:
693 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
694 break;
695 case ROCKET_MODE_RS232:
696 default:
697 if (info->flags & ROCKET_RTS_TOGGLE)
698 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
699 else
700 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
701 break;
702 }
703 }
704 spin_lock_init(&info->slock);
69f545ea 705 mutex_init(&info->write_mtx);
1da177e4 706 rp_table[line] = info;
ac6aec2f
JS		 707 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
708 NULL);
1da177e4
LT		 709}
710
711/*
712 * Configures a rocketport port according to its termio settings. Called from
713 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
714 */
47b01b3a 715static void configure_r_port(struct tty_struct *tty, struct r_port *info,
606d099c 716 struct ktermios *old_termios)
1da177e4
LT		 717{
718 unsigned cflag;
719 unsigned long flags;
720 unsigned rocketMode;
721 int bits, baud, divisor;
722 CHANNEL_t *cp;
47b01b3a 723 struct ktermios *t = tty->termios;
1da177e4 724
1da177e4 725 cp = &info->channel;
6df3526b 726 cflag = t->c_cflag;
1da177e4
LT		 727
728 /* Byte size and parity */
729 if ((cflag & CSIZE) == CS8) {
730 sSetData8(cp);
731 bits = 10;
732 } else {
733 sSetData7(cp);
734 bits = 9;
735 }
736 if (cflag & CSTOPB) {
737 sSetStop2(cp);
738 bits++;
739 } else {
740 sSetStop1(cp);
741 }
742
743 if (cflag & PARENB) {
744 sEnParity(cp);
745 bits++;
746 if (cflag & PARODD) {
747 sSetOddParity(cp);
748 } else {
749 sSetEvenParity(cp);
750 }
751 } else {
752 sDisParity(cp);
753 }
754
755 /* baud rate */
47b01b3a 756 baud = tty_get_baud_rate(tty);
1da177e4
LT		 757 if (!baud)
758 baud = 9600;
759 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
760 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 761 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 762 if (!baud)
763 baud = 9600;
764 divisor = (rp_baud_base[info->board] / baud) - 1;
765 }
766 if (divisor >= 8192 || divisor < 0) {
767 baud = 9600;
768 divisor = (rp_baud_base[info->board] / baud) - 1;
769 }
770 info->cps = baud / bits;
771 sSetBaud(cp, divisor);
772
6df3526b 773 /* FIXME: Should really back compute a baud rate from the divisor */
47b01b3a 774 tty_encode_baud_rate(tty, baud, baud);
6df3526b 775
1da177e4
LT		 776 if (cflag & CRTSCTS) {
777 info->intmask |= DELTA_CTS;
778 sEnCTSFlowCtl(cp);
779 } else {
780 info->intmask &= ~DELTA_CTS;
781 sDisCTSFlowCtl(cp);
782 }
783 if (cflag & CLOCAL) {
784 info->intmask &= ~DELTA_CD;
785 } else {
786 spin_lock_irqsave(&info->slock, flags);
787 if (sGetChanStatus(cp) & CD_ACT)
788 info->cd_status = 1;
789 else
790 info->cd_status = 0;
791 info->intmask |= DELTA_CD;
792 spin_unlock_irqrestore(&info->slock, flags);
793 }
794
795 /*
796 * Handle software flow control in the board
797 */
798#ifdef ROCKET_SOFT_FLOW
47b01b3a 799 if (I_IXON(tty)) {
1da177e4 800 sEnTxSoftFlowCtl(cp);
47b01b3a 801 if (I_IXANY(tty)) {
1da177e4
LT		 802 sEnIXANY(cp);
803 } else {
804 sDisIXANY(cp);
805 }
47b01b3a
AC		 806 sSetTxXONChar(cp, START_CHAR(tty));
807 sSetTxXOFFChar(cp, STOP_CHAR(tty));
1da177e4
LT		 808 } else {
809 sDisTxSoftFlowCtl(cp);
810 sDisIXANY(cp);
811 sClrTxXOFF(cp);
812 }
813#endif
814
815 /*
816 * Set up ignore/read mask words
817 */
818 info->read_status_mask = STMRCVROVRH | 0xFF;
47b01b3a 819 if (I_INPCK(tty))
1da177e4 820 info->read_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 821 if (I_BRKINT(tty) || I_PARMRK(tty))
1da177e4
LT		 822 info->read_status_mask |= STMBREAKH;
823
824 /*
825 * Characters to ignore
826 */
827 info->ignore_status_mask = 0;
47b01b3a 828 if (I_IGNPAR(tty))
1da177e4 829 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 830 if (I_IGNBRK(tty)) {
1da177e4
LT		 831 info->ignore_status_mask |= STMBREAKH;
832 /*
833 * If we're ignoring parity and break indicators,
834 * ignore overruns too. (For real raw support).
835 */
47b01b3a 836 if (I_IGNPAR(tty))
1da177e4
LT		 837 info->ignore_status_mask |= STMRCVROVRH;
838 }
839
840 rocketMode = info->flags & ROCKET_MODE_MASK;
841
842 if ((info->flags & ROCKET_RTS_TOGGLE)
843 || (rocketMode == ROCKET_MODE_RS485))
844 sEnRTSToggle(cp);
845 else
846 sDisRTSToggle(cp);
847
848 sSetRTS(&info->channel);
849
850 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
851 switch (rocketMode) {
852 case ROCKET_MODE_RS485:
853 sSetInterfaceMode(cp, InterfaceModeRS485);
854 break;
855 case ROCKET_MODE_RS422:
856 sSetInterfaceMode(cp, InterfaceModeRS422);
857 break;
858 case ROCKET_MODE_RS232:
859 default:
860 if (info->flags & ROCKET_RTS_TOGGLE)
861 sSetInterfaceMode(cp, InterfaceModeRS232T);
862 else
863 sSetInterfaceMode(cp, InterfaceModeRS232);
864 break;
865 }
866 }
867}
868
31f35939
AC		 869static int carrier_raised(struct tty_port *port)
870{
871 struct r_port *info = container_of(port, struct r_port, port);
872 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
873}
874
fcc8ac18 875static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 876{
877 struct r_port *info = container_of(port, struct r_port, port);
fcc8ac18
AC		 878 if (on) {
879 sSetDTR(&info->channel);
880 sSetRTS(&info->channel);
881 } else {
882 sClrDTR(&info->channel);
883 sClrRTS(&info->channel);
884 }
5d951fb4
AC		 885}
886
1da177e4
LT		 887/*
888 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
889 * port's r_port struct. Initializes the port hardware.
890 */
891static int rp_open(struct tty_struct *tty, struct file *filp)
892{
893 struct r_port *info;
fba85e01 894 struct tty_port *port;
1da177e4
LT		 895 int line = 0, retval;
896 CHANNEL_t *cp;
897 unsigned long page;
898
f6de0c98 899 line = tty->index;
fba85e01 900 if (line < 0 || line >= MAX_RP_PORTS || ((info = rp_table[line]) == NULL))
1da177e4 901 return -ENXIO;
fba85e01
AC		 902 port = &info->port;
903
1da177e4
LT		 904 page = __get_free_page(GFP_KERNEL);
905 if (!page)
906 return -ENOMEM;
907
fba85e01 908 if (port->flags & ASYNC_CLOSING) {
8cf5a8c5 909 retval = wait_for_completion_interruptible(&info->close_wait);
1da177e4 910 free_page(page);
8cf5a8c5
JS		 911 if (retval)
912 return retval;
fba85e01 913 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
1da177e4
LT		 914 }
915
916 /*
917 * We must not sleep from here until the port is marked fully in use.
918 */
919 if (info->xmit_buf)
920 free_page(page);
921 else
922 info->xmit_buf = (unsigned char *) page;
923
924 tty->driver_data = info;
fba85e01 925 tty_port_tty_set(port, tty);
1da177e4 926
fba85e01 927 if (port->count++ == 0) {
1da177e4
LT		 928 atomic_inc(&rp_num_ports_open);
929
930#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 931 printk(KERN_INFO "rocket mod++ = %d...\n",
932 atomic_read(&rp_num_ports_open));
1da177e4
LT		 933#endif
934 }
935#ifdef ROCKET_DEBUG_OPEN
e60a1084 936 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1da177e4
LT		 937#endif
938
939 /*
940 * Info->count is now 1; so it's safe to sleep now.
941 */
a391ad0f 942 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
1da177e4
LT		 943 cp = &info->channel;
944 sSetRxTrigger(cp, TRIG_1);
945 if (sGetChanStatus(cp) & CD_ACT)
946 info->cd_status = 1;
947 else
948 info->cd_status = 0;
949 sDisRxStatusMode(cp);
950 sFlushRxFIFO(cp);
951 sFlushTxFIFO(cp);
952
953 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
954 sSetRxTrigger(cp, TRIG_1);
955
956 sGetChanStatus(cp);
957 sDisRxStatusMode(cp);
958 sClrTxXOFF(cp);
959
960 sDisCTSFlowCtl(cp);
961 sDisTxSoftFlowCtl(cp);
962
963 sEnRxFIFO(cp);
964 sEnTransmit(cp);
965
a391ad0f 966 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
1da177e4
LT		 967
968 /*
969 * Set up the tty->alt_speed kludge
970 */
971 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 972 tty->alt_speed = 57600;
1da177e4 973 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 974 tty->alt_speed = 115200;
1da177e4 975 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 976 tty->alt_speed = 230400;
1da177e4 977 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 978 tty->alt_speed = 460800;
1da177e4 979
47b01b3a 980 configure_r_port(tty, info, NULL);
1da177e4
LT		 981 if (tty->termios->c_cflag & CBAUD) {
982 sSetDTR(cp);
983 sSetRTS(cp);
984 }
985 }
986 /* Starts (or resets) the maint polling loop */
987 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
988
fba85e01 989 retval = tty_port_block_til_ready(port, tty, filp);
1da177e4
LT		 990 if (retval) {
991#ifdef ROCKET_DEBUG_OPEN
992 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
993#endif
994 return retval;
995 }
996 return 0;
997}
998
999/*
e60a1084 1000 * Exception handler that closes a serial port. info->port.count is considered critical.
1da177e4
LT		 1001 */
1002static void rp_close(struct tty_struct *tty, struct file *filp)
1003{
c9f19e96 1004 struct r_port *info = tty->driver_data;
c1314a49 1005 struct tty_port *port = &info->port;
1da177e4
LT		 1006 int timeout;
1007 CHANNEL_t *cp;
1008
1009 if (rocket_paranoia_check(info, "rp_close"))
1010 return;
1011
1012#ifdef ROCKET_DEBUG_OPEN
e60a1084 1013 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1da177e4
LT		 1014#endif
1015
fba85e01 1016 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 1017 return;
1da177e4
LT		 1018
1019 cp = &info->channel;
1da177e4
LT		 1020 /*
1021 * Before we drop DTR, make sure the UART transmitter
1022 * has completely drained; this is especially
1023 * important if there is a transmit FIFO!
1024 */
1025 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1026 if (timeout == 0)
1027 timeout = 1;
1028 rp_wait_until_sent(tty, timeout);
1029 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1030
1031 sDisTransmit(cp);
1032 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1033 sDisCTSFlowCtl(cp);
1034 sDisTxSoftFlowCtl(cp);
1035 sClrTxXOFF(cp);
1036 sFlushRxFIFO(cp);
1037 sFlushTxFIFO(cp);
1038 sClrRTS(cp);
1039 if (C_HUPCL(tty))
1040 sClrDTR(cp);
1041
f6de0c98 1042 rp_flush_buffer(tty);
1da177e4
LT		 1043
1044 tty_ldisc_flush(tty);
1045
1046 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1047
fba85e01
AC		 1048 /* We can't yet use tty_port_close_end as the buffer handling in this
1049 driver is a bit different to the usual */
1050
c1314a49
AC		 1051 if (port->blocked_open) {
1052 if (port->close_delay) {
1053 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1da177e4 1054 }
c1314a49 1055 wake_up_interruptible(&port->open_wait);
1da177e4
LT		 1056 } else {
1057 if (info->xmit_buf) {
1058 free_page((unsigned long) info->xmit_buf);
1059 info->xmit_buf = NULL;
1060 }
1061 }
21bed701 1062 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1da177e4 1063 tty->closing = 0;
fba85e01
AC		 1064 tty_port_tty_set(port, NULL);
1065 wake_up_interruptible(&port->close_wait);
8cf5a8c5 1066 complete_all(&info->close_wait);
1da177e4
LT		 1067 atomic_dec(&rp_num_ports_open);
1068
1069#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1070 printk(KERN_INFO "rocket mod-- = %d...\n",
1071 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1072 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1073#endif
1074
1075}
1076
1077static void rp_set_termios(struct tty_struct *tty,
606d099c 1078 struct ktermios *old_termios)
1da177e4 1079{
c9f19e96 1080 struct r_port *info = tty->driver_data;
1da177e4
LT		 1081 CHANNEL_t *cp;
1082 unsigned cflag;
1083
1084 if (rocket_paranoia_check(info, "rp_set_termios"))
1085 return;
1086
1087 cflag = tty->termios->c_cflag;
1088
1da177e4
LT		 1089 /*
1090 * This driver doesn't support CS5 or CS6
1091 */
1092 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1093 tty->termios->c_cflag =
1094 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b
AC		 1095 /* Or CMSPAR */
1096 tty->termios->c_cflag &= ~CMSPAR;
1da177e4 1097
47b01b3a 1098 configure_r_port(tty, info, old_termios);
1da177e4
LT		 1099
1100 cp = &info->channel;
1101
1102 /* Handle transition to B0 status */
1103 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1104 sClrDTR(cp);
1105 sClrRTS(cp);
1106 }
1107
1108 /* Handle transition away from B0 status */
1109 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1110 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1111 sSetRTS(cp);
1112 sSetDTR(cp);
1113 }
1114
1115 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1116 tty->hw_stopped = 0;
1117 rp_start(tty);
1118 }
1119}
1120
9e98966c 1121static int rp_break(struct tty_struct *tty, int break_state)
1da177e4 1122{
c9f19e96 1123 struct r_port *info = tty->driver_data;
1da177e4
LT		 1124 unsigned long flags;
1125
1126 if (rocket_paranoia_check(info, "rp_break"))
9e98966c 1127 return -EINVAL;
1da177e4
LT		 1128
1129 spin_lock_irqsave(&info->slock, flags);
1130 if (break_state == -1)
1131 sSendBreak(&info->channel);
1132 else
1133 sClrBreak(&info->channel);
1134 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 1135 return 0;
1da177e4
LT		 1136}
1137
1138/*
1139 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1140 * the UPCI boards was added, it was decided to make this a function because
1141 * the macro was getting too complicated. All cases except the first one
1142 * (UPCIRingInd) are taken directly from the original macro.
1143 */
1144static int sGetChanRI(CHANNEL_T * ChP)
1145{
1146 CONTROLLER_t *CtlP = ChP->CtlP;
1147 int ChanNum = ChP->ChanNum;
1148 int RingInd = 0;
1149
1150 if (CtlP->UPCIRingInd)
1151 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1152 else if (CtlP->AltChanRingIndicator)
1153 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1154 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1155 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1156
1157 return RingInd;
1158}
1159
1160/********************************************************************************************/
1161/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1162
1163/*
1164 * Returns the state of the serial modem control lines. These next 2 functions
1165 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1166 */
1167static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1168{
c9f19e96 1169 struct r_port *info = tty->driver_data;
1da177e4
LT		 1170 unsigned int control, result, ChanStatus;
1171
1172 ChanStatus = sGetChanStatusLo(&info->channel);
1173 control = info->channel.TxControl[3];
1174 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1175 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1176 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1177 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1178 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1179 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1180
1181 return result;
1182}
1183
1184/*
1185 * Sets the modem control lines
1186 */
1187static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1188 unsigned int set, unsigned int clear)
1189{
c9f19e96 1190 struct r_port *info = tty->driver_data;
1da177e4
LT		 1191
1192 if (set & TIOCM_RTS)
1193 info->channel.TxControl[3] |= SET_RTS;
1194 if (set & TIOCM_DTR)
1195 info->channel.TxControl[3] |= SET_DTR;
1196 if (clear & TIOCM_RTS)
1197 info->channel.TxControl[3] &= ~SET_RTS;
1198 if (clear & TIOCM_DTR)
1199 info->channel.TxControl[3] &= ~SET_DTR;
1200
457fb605 1201 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1202 return 0;
1203}
1204
1205static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1206{
1207 struct rocket_config tmp;
1208
1209 if (!retinfo)
1210 return -EFAULT;
1211 memset(&tmp, 0, sizeof (tmp));
1212 tmp.line = info->line;
1213 tmp.flags = info->flags;
44b7d1b3
AC		 1214 tmp.close_delay = info->port.close_delay;
1215 tmp.closing_wait = info->port.closing_wait;
1da177e4
LT		 1216 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1217
1218 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1219 return -EFAULT;
1220 return 0;
1221}
1222
47b01b3a
AC		 1223static int set_config(struct tty_struct *tty, struct r_port *info,
1224 struct rocket_config __user *new_info)
1da177e4
LT		 1225{
1226 struct rocket_config new_serial;
1227
1228 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1229 return -EFAULT;
1230
1231 if (!capable(CAP_SYS_ADMIN))
1232 {
1233 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1234 return -EPERM;
1235 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
47b01b3a 1236 configure_r_port(tty, info, NULL);
1da177e4
LT		 1237 return 0;
1238 }
1239
1240 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
44b7d1b3
AC		 1241 info->port.close_delay = new_serial.close_delay;
1242 info->port.closing_wait = new_serial.closing_wait;
1da177e4
LT		 1243
1244 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 1245 tty->alt_speed = 57600;
1da177e4 1246 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 1247 tty->alt_speed = 115200;
1da177e4 1248 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 1249 tty->alt_speed = 230400;
1da177e4 1250 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 1251 tty->alt_speed = 460800;
1da177e4 1252
47b01b3a 1253 configure_r_port(tty, info, NULL);
1da177e4
LT		 1254 return 0;
1255}
1256
1257/*
1258 * This function fills in a rocket_ports struct with information
1259 * about what boards/ports are in the system. This info is passed
1260 * to user space. See setrocket.c where the info is used to create
1261 * the /dev/ttyRx ports.
1262 */
1263static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1264{
1265 struct rocket_ports tmp;
1266 int board;
1267
1268 if (!retports)
1269 return -EFAULT;
1270 memset(&tmp, 0, sizeof (tmp));
1271 tmp.tty_major = rocket_driver->major;
1272
1273 for (board = 0; board < 4; board++) {
1274 tmp.rocketModel[board].model = rocketModel[board].model;
1275 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1276 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1277 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1278 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1279 }
1280 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1281 return -EFAULT;
1282 return 0;
1283}
1284
1285static int reset_rm2(struct r_port *info, void __user *arg)
1286{
1287 int reset;
1288
4129a645
AC		 1289 if (!capable(CAP_SYS_ADMIN))
1290 return -EPERM;
1291
1da177e4
LT		 1292 if (copy_from_user(&reset, arg, sizeof (int)))
1293 return -EFAULT;
1294 if (reset)
1295 reset = 1;
1296
1297 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1298 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1299 return -EINVAL;
1300
1301 if (info->ctlp->BusType == isISA)
1302 sModemReset(info->ctlp, info->chan, reset);
1303 else
1304 sPCIModemReset(info->ctlp, info->chan, reset);
1305
1306 return 0;
1307}
1308
1309static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1310{
1311 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1312 return -EFAULT;
1313 return 0;
1314}
1315
1316/* IOCTL call handler into the driver */
1317static int rp_ioctl(struct tty_struct *tty, struct file *file,
1318 unsigned int cmd, unsigned long arg)
1319{
c9f19e96 1320 struct r_port *info = tty->driver_data;
1da177e4 1321 void __user *argp = (void __user *)arg;
bdf183aa 1322 int ret = 0;
1da177e4
LT		 1323
1324 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1325 return -ENXIO;
1326
bdf183aa
AC		 1327 lock_kernel();
1328
1da177e4
LT		 1329 switch (cmd) {
1330 case RCKP_GET_STRUCT:
1331 if (copy_to_user(argp, info, sizeof (struct r_port)))
bdf183aa
AC		 1332 ret = -EFAULT;
1333 break;
1da177e4 1334 case RCKP_GET_CONFIG:
bdf183aa
AC		 1335 ret = get_config(info, argp);
1336 break;
1da177e4 1337 case RCKP_SET_CONFIG:
47b01b3a 1338 ret = set_config(tty, info, argp);
bdf183aa 1339 break;
1da177e4 1340 case RCKP_GET_PORTS:
bdf183aa
AC		 1341 ret = get_ports(info, argp);
1342 break;
1da177e4 1343 case RCKP_RESET_RM2:
bdf183aa
AC		 1344 ret = reset_rm2(info, argp);
1345 break;
1da177e4 1346 case RCKP_GET_VERSION:
bdf183aa
AC		 1347 ret = get_version(info, argp);
1348 break;
1da177e4 1349 default:
bdf183aa 1350 ret = -ENOIOCTLCMD;
1da177e4 1351 }
bdf183aa
AC		 1352 unlock_kernel();
1353 return ret;
1da177e4
LT		 1354}
1355
1356static void rp_send_xchar(struct tty_struct *tty, char ch)
1357{
c9f19e96 1358 struct r_port *info = tty->driver_data;
1da177e4
LT		 1359 CHANNEL_t *cp;
1360
1361 if (rocket_paranoia_check(info, "rp_send_xchar"))
1362 return;
1363
1364 cp = &info->channel;
1365 if (sGetTxCnt(cp))
1366 sWriteTxPrioByte(cp, ch);
1367 else
1368 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1369}
1370
1371static void rp_throttle(struct tty_struct *tty)
1372{
c9f19e96 1373 struct r_port *info = tty->driver_data;
1da177e4
LT		 1374 CHANNEL_t *cp;
1375
1376#ifdef ROCKET_DEBUG_THROTTLE
1377 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1378 tty->ldisc.chars_in_buffer(tty));
1379#endif
1380
1381 if (rocket_paranoia_check(info, "rp_throttle"))
1382 return;
1383
1384 cp = &info->channel;
1385 if (I_IXOFF(tty))
1386 rp_send_xchar(tty, STOP_CHAR(tty));
1387
1388 sClrRTS(&info->channel);
1389}
1390
1391static void rp_unthrottle(struct tty_struct *tty)
1392{
c9f19e96 1393 struct r_port *info = tty->driver_data;
1da177e4
LT		 1394 CHANNEL_t *cp;
1395#ifdef ROCKET_DEBUG_THROTTLE
1396 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1397 tty->ldisc.chars_in_buffer(tty));
1398#endif
1399
1400 if (rocket_paranoia_check(info, "rp_throttle"))
1401 return;
1402
1403 cp = &info->channel;
1404 if (I_IXOFF(tty))
1405 rp_send_xchar(tty, START_CHAR(tty));
1406
1407 sSetRTS(&info->channel);
1408}
1409
1410/*
1411 * ------------------------------------------------------------
1412 * rp_stop() and rp_start()
1413 *
1414 * This routines are called before setting or resetting tty->stopped.
1415 * They enable or disable transmitter interrupts, as necessary.
1416 * ------------------------------------------------------------
1417 */
1418static void rp_stop(struct tty_struct *tty)
1419{
c9f19e96 1420 struct r_port *info = tty->driver_data;
1da177e4
LT		 1421
1422#ifdef ROCKET_DEBUG_FLOW
1423 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1424 info->xmit_cnt, info->xmit_fifo_room);
1425#endif
1426
1427 if (rocket_paranoia_check(info, "rp_stop"))
1428 return;
1429
1430 if (sGetTxCnt(&info->channel))
1431 sDisTransmit(&info->channel);
1432}
1433
1434static void rp_start(struct tty_struct *tty)
1435{
c9f19e96 1436 struct r_port *info = tty->driver_data;
1da177e4
LT		 1437
1438#ifdef ROCKET_DEBUG_FLOW
1439 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1440 info->xmit_cnt, info->xmit_fifo_room);
1441#endif
1442
1443 if (rocket_paranoia_check(info, "rp_stop"))
1444 return;
1445
1446 sEnTransmit(&info->channel);
1447 set_bit((info->aiop * 8) + info->chan,
1448 (void *) &xmit_flags[info->board]);
1449}
1450
1451/*
1452 * rp_wait_until_sent() --- wait until the transmitter is empty
1453 */
1454static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1455{
c9f19e96 1456 struct r_port *info = tty->driver_data;
1da177e4
LT		 1457 CHANNEL_t *cp;
1458 unsigned long orig_jiffies;
1459 int check_time, exit_time;
1460 int txcnt;
1461
1462 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1463 return;
1464
1465 cp = &info->channel;
1466
1467 orig_jiffies = jiffies;
1468#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79 1469 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1da177e4 1470 jiffies);
68562b79 1471 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4 1472#endif
978e595f 1473 lock_kernel();
1da177e4
LT		 1474 while (1) {
1475 txcnt = sGetTxCnt(cp);
1476 if (!txcnt) {
1477 if (sGetChanStatusLo(cp) & TXSHRMT)
1478 break;
1479 check_time = (HZ / info->cps) / 5;
1480 } else {
1481 check_time = HZ * txcnt / info->cps;
1482 }
1483 if (timeout) {
1484 exit_time = orig_jiffies + timeout - jiffies;
1485 if (exit_time <= 0)
1486 break;
1487 if (exit_time < check_time)
1488 check_time = exit_time;
1489 }
1490 if (check_time == 0)
1491 check_time = 1;
1492#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1493 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1494 jiffies, check_time);
1da177e4
LT		 1495#endif
1496 msleep_interruptible(jiffies_to_msecs(check_time));
1497 if (signal_pending(current))
1498 break;
1499 }
cc0a8fbb 1500 __set_current_state(TASK_RUNNING);
978e595f 1501 unlock_kernel();
1da177e4
LT		 1502#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1503 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1504#endif
1505}
1506
1507/*
1508 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1509 */
1510static void rp_hangup(struct tty_struct *tty)
1511{
1512 CHANNEL_t *cp;
c9f19e96 1513 struct r_port *info = tty->driver_data;
1da177e4
LT		 1514
1515 if (rocket_paranoia_check(info, "rp_hangup"))
1516 return;
1517
1518#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1519 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1520#endif
1521 rp_flush_buffer(tty);
21bed701 1522 if (info->port.flags & ASYNC_CLOSING)
1da177e4 1523 return;
e60a1084 1524 if (info->port.count)
1da177e4
LT		 1525 atomic_dec(&rp_num_ports_open);
1526 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1527
fba85e01 1528 tty_port_hangup(&info->port);
1da177e4
LT		 1529
1530 cp = &info->channel;
1531 sDisRxFIFO(cp);
1532 sDisTransmit(cp);
1533 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1534 sDisCTSFlowCtl(cp);
1535 sDisTxSoftFlowCtl(cp);
1536 sClrTxXOFF(cp);
21bed701 1537 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4 1538
e60a1084 1539 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1540}
1541
1542/*
1543 * Exception handler - write char routine. The RocketPort driver uses a
1544 * double-buffering strategy, with the twist that if the in-memory CPU
1545 * buffer is empty, and there's space in the transmit FIFO, the
1546 * writing routines will write directly to transmit FIFO.
1547 * Write buffer and counters protected by spinlocks
1548 */
bbbbb96f 1549static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1550{
c9f19e96 1551 struct r_port *info = tty->driver_data;
1da177e4
LT		 1552 CHANNEL_t *cp;
1553 unsigned long flags;
1554
1555 if (rocket_paranoia_check(info, "rp_put_char"))
bbbbb96f 1556 return 0;
1da177e4 1557
69f545ea
MK		 1558 /*
1559 * Grab the port write mutex, locking out other processes that try to
1560 * write to this port
1561 */
1562 mutex_lock(&info->write_mtx);
1da177e4
LT		 1563
1564#ifdef ROCKET_DEBUG_WRITE
68562b79 1565 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1566#endif
1567
1568 spin_lock_irqsave(&info->slock, flags);
1569 cp = &info->channel;
1570
1571 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1572 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1573
1574 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1575 info->xmit_buf[info->xmit_head++] = ch;
1576 info->xmit_head &= XMIT_BUF_SIZE - 1;
1577 info->xmit_cnt++;
1578 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1579 } else {
1580 sOutB(sGetTxRxDataIO(cp), ch);
1581 info->xmit_fifo_room--;
1582 }
1583 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1584 mutex_unlock(&info->write_mtx);
bbbbb96f 1585 return 1;
1da177e4
LT		 1586}
1587
1588/*
1589 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1590 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1591 * this port at the same time. This other process could be running on the other CPU
1592 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1593 * Spinlocks protect the info xmit members.
1594 */
1595static int rp_write(struct tty_struct *tty,
1596 const unsigned char *buf, int count)
1597{
c9f19e96 1598 struct r_port *info = tty->driver_data;
1da177e4
LT		 1599 CHANNEL_t *cp;
1600 const unsigned char *b;
1601 int c, retval = 0;
1602 unsigned long flags;
1603
1604 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1605 return 0;
1606
1e3e8d91
SS		 1607 if (mutex_lock_interruptible(&info->write_mtx))
1608 return -ERESTARTSYS;
1da177e4
LT		 1609
1610#ifdef ROCKET_DEBUG_WRITE
68562b79 1611 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1612#endif
1613 cp = &info->channel;
1614
1615 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1616 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1617
1618 /*
1619 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1620 * into FIFO. Use the write queue for temp storage.
1621 */
1622 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1623 c = min(count, info->xmit_fifo_room);
1624 b = buf;
1625
1626 /* Push data into FIFO, 2 bytes at a time */
1627 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1628
1629 /* If there is a byte remaining, write it */
1630 if (c & 1)
1631 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1632
1633 retval += c;
1634 buf += c;
1635 count -= c;
1636
1637 spin_lock_irqsave(&info->slock, flags);
1638 info->xmit_fifo_room -= c;
1639 spin_unlock_irqrestore(&info->slock, flags);
1640 }
1641
1642 /* If count is zero, we wrote it all and are done */
1643 if (!count)
1644 goto end;
1645
1646 /* Write remaining data into the port's xmit_buf */
1647 while (1) {
47b01b3a 1648 /* Hung up ? */
a391ad0f 1649 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1da177e4 1650 goto end;
709107fc
HH		 1651 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1652 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1da177e4
LT		 1653 if (c <= 0)
1654 break;
1655
1656 b = buf;
1657 memcpy(info->xmit_buf + info->xmit_head, b, c);
1658
1659 spin_lock_irqsave(&info->slock, flags);
1660 info->xmit_head =
1661 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1662 info->xmit_cnt += c;
1663 spin_unlock_irqrestore(&info->slock, flags);
1664
1665 buf += c;
1666 count -= c;
1667 retval += c;
1668 }
1669
1670 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1671 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1672
1673end:
1674 if (info->xmit_cnt < WAKEUP_CHARS) {
1675 tty_wakeup(tty);
1da177e4
LT		 1676#ifdef ROCKETPORT_HAVE_POLL_WAIT
1677 wake_up_interruptible(&tty->poll_wait);
1678#endif
1679 }
69f545ea 1680 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1681 return retval;
1682}
1683
1684/*
1685 * Return the number of characters that can be sent. We estimate
1686 * only using the in-memory transmit buffer only, and ignore the
1687 * potential space in the transmit FIFO.
1688 */
1689static int rp_write_room(struct tty_struct *tty)
1690{
c9f19e96 1691 struct r_port *info = tty->driver_data;
1da177e4
LT		 1692 int ret;
1693
1694 if (rocket_paranoia_check(info, "rp_write_room"))
1695 return 0;
1696
1697 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1698 if (ret < 0)
1699 ret = 0;
1700#ifdef ROCKET_DEBUG_WRITE
68562b79 1701 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1702#endif
1703 return ret;
1704}
1705
1706/*
1707 * Return the number of characters in the buffer. Again, this only
1708 * counts those characters in the in-memory transmit buffer.
1709 */
1710static int rp_chars_in_buffer(struct tty_struct *tty)
1711{
c9f19e96 1712 struct r_port *info = tty->driver_data;
1da177e4
LT		 1713 CHANNEL_t *cp;
1714
1715 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1716 return 0;
1717
1718 cp = &info->channel;
1719
1720#ifdef ROCKET_DEBUG_WRITE
68562b79 1721 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1722#endif
1723 return info->xmit_cnt;
1724}
1725
1726/*
1727 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1728 * r_port struct for the port. Note that spinlock are used to protect info members,
1729 * do not call this function if the spinlock is already held.
1730 */
1731static void rp_flush_buffer(struct tty_struct *tty)
1732{
c9f19e96 1733 struct r_port *info = tty->driver_data;
1da177e4
LT		 1734 CHANNEL_t *cp;
1735 unsigned long flags;
1736
1737 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1738 return;
1739
1740 spin_lock_irqsave(&info->slock, flags);
1741 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1742 spin_unlock_irqrestore(&info->slock, flags);
1743
1da177e4
LT		 1744#ifdef ROCKETPORT_HAVE_POLL_WAIT
1745 wake_up_interruptible(&tty->poll_wait);
1746#endif
1747 tty_wakeup(tty);
1748
1749 cp = &info->channel;
1750 sFlushTxFIFO(cp);
1751}
1752
1753#ifdef CONFIG_PCI
1754
8d5916d3
JS		 1755static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1756 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1757 { }
1758};
1759MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1760
1da177e4
LT		 1761/*
1762 * Called when a PCI card is found. Retrieves and stores model information,
1763 * init's aiopic and serial port hardware.
1764 * Inputs: i is the board number (0-n)
1765 */
f15313bf 1766static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1767{
1768 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1769 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1770 char *str, *board_type;
1771 CONTROLLER_t *ctlp;
1772
1773 int fast_clock = 0;
1774 int altChanRingIndicator = 0;
1775 int ports_per_aiop = 8;
1da177e4
LT		 1776 WordIO_t ConfigIO = 0;
1777 ByteIO_t UPCIRingInd = 0;
1778
1779 if (!dev || pci_enable_device(dev))
1780 return 0;
1781
1782 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1783
1784 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1785 rocketModel[i].loadrm2 = 0;
1786 rocketModel[i].startingPortNumber = nextLineNumber;
1787
1788 /* Depending on the model, set up some config variables */
1789 switch (dev->device) {
1790 case PCI_DEVICE_ID_RP4QUAD:
1791 str = "Quadcable";
1792 max_num_aiops = 1;
1793 ports_per_aiop = 4;
1794 rocketModel[i].model = MODEL_RP4QUAD;
1795 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1796 rocketModel[i].numPorts = 4;
1797 break;
1798 case PCI_DEVICE_ID_RP8OCTA:
1799 str = "Octacable";
1800 max_num_aiops = 1;
1801 rocketModel[i].model = MODEL_RP8OCTA;
1802 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1803 rocketModel[i].numPorts = 8;
1804 break;
1805 case PCI_DEVICE_ID_URP8OCTA:
1806 str = "Octacable";
1807 max_num_aiops = 1;
1808 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1809 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1810 rocketModel[i].numPorts = 8;
1811 break;
1812 case PCI_DEVICE_ID_RP8INTF:
1813 str = "8";
1814 max_num_aiops = 1;
1815 rocketModel[i].model = MODEL_RP8INTF;
1816 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1817 rocketModel[i].numPorts = 8;
1818 break;
1819 case PCI_DEVICE_ID_URP8INTF:
1820 str = "8";
1821 max_num_aiops = 1;
1822 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1823 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1824 rocketModel[i].numPorts = 8;
1825 break;
1826 case PCI_DEVICE_ID_RP8J:
1827 str = "8J";
1828 max_num_aiops = 1;
1829 rocketModel[i].model = MODEL_RP8J;
1830 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1831 rocketModel[i].numPorts = 8;
1832 break;
1833 case PCI_DEVICE_ID_RP4J:
1834 str = "4J";
1835 max_num_aiops = 1;
1836 ports_per_aiop = 4;
1837 rocketModel[i].model = MODEL_RP4J;
1838 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1839 rocketModel[i].numPorts = 4;
1840 break;
1841 case PCI_DEVICE_ID_RP8SNI:
1842 str = "8 (DB78 Custom)";
1843 max_num_aiops = 1;
1844 rocketModel[i].model = MODEL_RP8SNI;
1845 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1846 rocketModel[i].numPorts = 8;
1847 break;
1848 case PCI_DEVICE_ID_RP16SNI:
1849 str = "16 (DB78 Custom)";
1850 max_num_aiops = 2;
1851 rocketModel[i].model = MODEL_RP16SNI;
1852 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1853 rocketModel[i].numPorts = 16;
1854 break;
1855 case PCI_DEVICE_ID_RP16INTF:
1856 str = "16";
1857 max_num_aiops = 2;
1858 rocketModel[i].model = MODEL_RP16INTF;
1859 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1860 rocketModel[i].numPorts = 16;
1861 break;
1862 case PCI_DEVICE_ID_URP16INTF:
1863 str = "16";
1864 max_num_aiops = 2;
1865 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1866 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1867 rocketModel[i].numPorts = 16;
1868 break;
1869 case PCI_DEVICE_ID_CRP16INTF:
1870 str = "16";
1871 max_num_aiops = 2;
1872 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1873 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1874 rocketModel[i].numPorts = 16;
1875 break;
1876 case PCI_DEVICE_ID_RP32INTF:
1877 str = "32";
1878 max_num_aiops = 4;
1879 rocketModel[i].model = MODEL_RP32INTF;
1880 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1881 rocketModel[i].numPorts = 32;
1882 break;
1883 case PCI_DEVICE_ID_URP32INTF:
1884 str = "32";
1885 max_num_aiops = 4;
1886 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1887 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1888 rocketModel[i].numPorts = 32;
1889 break;
1890 case PCI_DEVICE_ID_RPP4:
1891 str = "Plus Quadcable";
1892 max_num_aiops = 1;
1893 ports_per_aiop = 4;
1894 altChanRingIndicator++;
1895 fast_clock++;
1896 rocketModel[i].model = MODEL_RPP4;
1897 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1898 rocketModel[i].numPorts = 4;
1899 break;
1900 case PCI_DEVICE_ID_RPP8:
1901 str = "Plus Octacable";
1902 max_num_aiops = 2;
1903 ports_per_aiop = 4;
1904 altChanRingIndicator++;
1905 fast_clock++;
1906 rocketModel[i].model = MODEL_RPP8;
1907 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1908 rocketModel[i].numPorts = 8;
1909 break;
1910 case PCI_DEVICE_ID_RP2_232:
1911 str = "Plus 2 (RS-232)";
1912 max_num_aiops = 1;
1913 ports_per_aiop = 2;
1914 altChanRingIndicator++;
1915 fast_clock++;
1916 rocketModel[i].model = MODEL_RP2_232;
1917 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1918 rocketModel[i].numPorts = 2;
1919 break;
1920 case PCI_DEVICE_ID_RP2_422:
1921 str = "Plus 2 (RS-422)";
1922 max_num_aiops = 1;
1923 ports_per_aiop = 2;
1924 altChanRingIndicator++;
1925 fast_clock++;
1926 rocketModel[i].model = MODEL_RP2_422;
1927 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1928 rocketModel[i].numPorts = 2;
1929 break;
1930 case PCI_DEVICE_ID_RP6M:
1931
1932 max_num_aiops = 1;
1933 ports_per_aiop = 6;
1934 str = "6-port";
1935
57fedc7a
JS		 1936 /* If revision is 1, the rocketmodem flash must be loaded.
1937 * If it is 2 it is a "socketed" version. */
1938 if (dev->revision == 1) {
1da177e4
LT		 1939 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1940 rocketModel[i].loadrm2 = 1;
1941 } else {
1942 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1943 }
1944
1945 rocketModel[i].model = MODEL_RP6M;
1946 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1947 rocketModel[i].numPorts = 6;
1948 break;
1949 case PCI_DEVICE_ID_RP4M:
1950 max_num_aiops = 1;
1951 ports_per_aiop = 4;
1952 str = "4-port";
57fedc7a 1953 if (dev->revision == 1) {
1da177e4
LT		 1954 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1955 rocketModel[i].loadrm2 = 1;
1956 } else {
1957 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1958 }
1959
1960 rocketModel[i].model = MODEL_RP4M;
1961 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1962 rocketModel[i].numPorts = 4;
1963 break;
1964 default:
1965 str = "(unknown/unsupported)";
1966 max_num_aiops = 0;
1967 break;
1968 }
1969
1970 /*
1971 * Check for UPCI boards.
1972 */
1973
1974 switch (dev->device) {
1975 case PCI_DEVICE_ID_URP32INTF:
1976 case PCI_DEVICE_ID_URP8INTF:
1977 case PCI_DEVICE_ID_URP16INTF:
1978 case PCI_DEVICE_ID_CRP16INTF:
1979 case PCI_DEVICE_ID_URP8OCTA:
1980 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1981 ConfigIO = pci_resource_start(dev, 1);
1982 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1983 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1984
1985 /*
1986 * Check for octa or quad cable.
1987 */
1988 if (!
1989 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
1990 PCI_GPIO_CTRL_8PORT)) {
1991 str = "Quadcable";
1992 ports_per_aiop = 4;
1993 rocketModel[i].numPorts = 4;
1994 }
1995 }
1996 break;
1997 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1998 str = "8 ports";
1999 max_num_aiops = 1;
2000 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2001 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2002 rocketModel[i].numPorts = 8;
2003 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2004 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2005 ConfigIO = pci_resource_start(dev, 1);
2006 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2007 break;
2008 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2009 str = "4 ports";
2010 max_num_aiops = 1;
2011 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2012 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2013 rocketModel[i].numPorts = 4;
2014 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2015 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2016 ConfigIO = pci_resource_start(dev, 1);
2017 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2018 break;
2019 default:
2020 break;
2021 }
2022
2023 switch (rcktpt_type[i]) {
2024 case ROCKET_TYPE_MODEM:
2025 board_type = "RocketModem";
2026 break;
2027 case ROCKET_TYPE_MODEMII:
2028 board_type = "RocketModem II";
2029 break;
2030 case ROCKET_TYPE_MODEMIII:
2031 board_type = "RocketModem III";
2032 break;
2033 default:
2034 board_type = "RocketPort";
2035 break;
2036 }
2037
2038 if (fast_clock) {
2039 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2040 rp_baud_base[i] = 921600;
2041 } else {
2042 /*
2043 * If support_low_speed is set, use the slow clock
2044 * prescale, which supports 50 bps
2045 */
2046 if (support_low_speed) {
2047 /* mod 9 (divide by 10) prescale */
2048 sClockPrescale = 0x19;
2049 rp_baud_base[i] = 230400;
2050 } else {
2051 /* mod 4 (devide by 5) prescale */
2052 sClockPrescale = 0x14;
2053 rp_baud_base[i] = 460800;
2054 }
2055 }
2056
2057 for (aiop = 0; aiop < max_num_aiops; aiop++)
2058 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2059 ctlp = sCtlNumToCtlPtr(i);
2060 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2061 for (aiop = 0; aiop < max_num_aiops; aiop++)
2062 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2063
68562b79
JS		 2064 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2065 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2066 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2067 rocketModel[i].startingPortNumber,
2068 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2069
2070 if (num_aiops <= 0) {
2071 rcktpt_io_addr[i] = 0;
2072 return (0);
2073 }
2074 is_PCI[i] = 1;
2075
2076 /* Reset the AIOPIC, init the serial ports */
2077 for (aiop = 0; aiop < num_aiops; aiop++) {
2078 sResetAiopByNum(ctlp, aiop);
2079 num_chan = ports_per_aiop;
2080 for (chan = 0; chan < num_chan; chan++)
2081 init_r_port(i, aiop, chan, dev);
2082 }
2083
2084 /* Rocket modems must be reset */
2085 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2086 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2087 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2088 num_chan = ports_per_aiop;
2089 for (chan = 0; chan < num_chan; chan++)
2090 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2091 msleep(500);
1da177e4
LT		 2092 for (chan = 0; chan < num_chan; chan++)
2093 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2094 msleep(500);
1da177e4
LT		 2095 rmSpeakerReset(ctlp, rocketModel[i].model);
2096 }
2097 return (1);
2098}
2099
2100/*
2101 * Probes for PCI cards, inits them if found
2102 * Input: board_found = number of ISA boards already found, or the
2103 * starting board number
2104 * Returns: Number of PCI boards found
2105 */
2106static int __init init_PCI(int boards_found)
2107{
2108 struct pci_dev *dev = NULL;
2109 int count = 0;
2110
2111 /* Work through the PCI device list, pulling out ours */
606d099c 2112 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2113 if (register_PCI(count + boards_found, dev))
2114 count++;
2115 }
2116 return (count);
2117}
2118
2119#endif /* CONFIG_PCI */
2120
2121/*
2122 * Probes for ISA cards
2123 * Input: i = the board number to look for
2124 * Returns: 1 if board found, 0 else
2125 */
2126static int __init init_ISA(int i)
2127{
2128 int num_aiops, num_chan = 0, total_num_chan = 0;
2129 int aiop, chan;
2130 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2131 CONTROLLER_t *ctlp;
2132 char *type_string;
2133
2134 /* If io_addr is zero, no board configured */
2135 if (rcktpt_io_addr[i] == 0)
2136 return (0);
2137
2138 /* Reserve the IO region */
2139 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2140 printk(KERN_ERR "Unable to reserve IO region for configured "
2141 "ISA RocketPort at address 0x%lx, board not "
2142 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2143 rcktpt_io_addr[i] = 0;
2144 return (0);
2145 }
2146
2147 ctlp = sCtlNumToCtlPtr(i);
2148
2149 ctlp->boardType = rcktpt_type[i];
2150
2151 switch (rcktpt_type[i]) {
2152 case ROCKET_TYPE_PC104:
2153 type_string = "(PC104)";
2154 break;
2155 case ROCKET_TYPE_MODEM:
2156 type_string = "(RocketModem)";
2157 break;
2158 case ROCKET_TYPE_MODEMII:
2159 type_string = "(RocketModem II)";
2160 break;
2161 default:
2162 type_string = "";
2163 break;
2164 }
2165
2166 /*
2167 * If support_low_speed is set, use the slow clock prescale,
2168 * which supports 50 bps
2169 */
2170 if (support_low_speed) {
2171 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2172 rp_baud_base[i] = 230400;
2173 } else {
2174 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2175 rp_baud_base[i] = 460800;
2176 }
2177
2178 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2179 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2180
2181 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2182
2183 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2184 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2185 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2186 }
2187
2188 /* If something went wrong initing the AIOP's release the ISA IO memory */
2189 if (num_aiops <= 0) {
2190 release_region(rcktpt_io_addr[i], 64);
2191 rcktpt_io_addr[i] = 0;
2192 return (0);
2193 }
2194
2195 rocketModel[i].startingPortNumber = nextLineNumber;
2196
2197 for (aiop = 0; aiop < num_aiops; aiop++) {
2198 sResetAiopByNum(ctlp, aiop);
2199 sEnAiop(ctlp, aiop);
2200 num_chan = sGetAiopNumChan(ctlp, aiop);
2201 total_num_chan += num_chan;
2202 for (chan = 0; chan < num_chan; chan++)
2203 init_r_port(i, aiop, chan, NULL);
2204 }
2205 is_PCI[i] = 0;
2206 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2207 num_chan = sGetAiopNumChan(ctlp, 0);
2208 total_num_chan = num_chan;
2209 for (chan = 0; chan < num_chan; chan++)
2210 sModemReset(ctlp, chan, 1);
48a67f5d 2211 msleep(500);
1da177e4
LT		 2212 for (chan = 0; chan < num_chan; chan++)
2213 sModemReset(ctlp, chan, 0);
48a67f5d 2214 msleep(500);
1da177e4
LT		 2215 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2216 } else {
2217 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2218 }
2219 rocketModel[i].numPorts = total_num_chan;
2220 rocketModel[i].model = MODEL_ISA;
2221
2222 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2223 i, rcktpt_io_addr[i], num_aiops, type_string);
2224
2225 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2226 rocketModel[i].modelString,
2227 rocketModel[i].startingPortNumber,
2228 rocketModel[i].startingPortNumber +
2229 rocketModel[i].numPorts - 1);
2230
2231 return (1);
2232}
2233
b68e31d0 2234static const struct tty_operations rocket_ops = {
1da177e4
LT		 2235 .open = rp_open,
2236 .close = rp_close,
2237 .write = rp_write,
2238 .put_char = rp_put_char,
2239 .write_room = rp_write_room,
2240 .chars_in_buffer = rp_chars_in_buffer,
2241 .flush_buffer = rp_flush_buffer,
2242 .ioctl = rp_ioctl,
2243 .throttle = rp_throttle,
2244 .unthrottle = rp_unthrottle,
2245 .set_termios = rp_set_termios,
2246 .stop = rp_stop,
2247 .start = rp_start,
2248 .hangup = rp_hangup,
2249 .break_ctl = rp_break,
2250 .send_xchar = rp_send_xchar,
2251 .wait_until_sent = rp_wait_until_sent,
2252 .tiocmget = rp_tiocmget,
2253 .tiocmset = rp_tiocmset,
2254};
2255
31f35939
AC		 2256static const struct tty_port_operations rocket_port_ops = {
2257 .carrier_raised = carrier_raised,
fcc8ac18 2258 .dtr_rts = dtr_rts,
31f35939
AC		 2259};
2260
1da177e4
LT		 2261/*
2262 * The module "startup" routine; it's run when the module is loaded.
2263 */
d269cdd0 2264static int __init rp_init(void)
1da177e4 2265{
4384a3fa 2266 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2267
2268 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2269 ROCKET_VERSION, ROCKET_DATE);
2270
2271 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2272 if (!rocket_driver)
4384a3fa 2273 goto err;
1da177e4 2274
1da177e4
LT		 2275 /*
2276 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2277 * zero, use the default controller IO address of board1 + 0x40.
2278 */
2279 if (board1) {
2280 if (controller == 0)
2281 controller = board1 + 0x40;
2282 } else {
2283 controller = 0; /* Used as a flag, meaning no ISA boards */
2284 }
2285
2286 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2287 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2288 printk(KERN_ERR "Unable to reserve IO region for first "
2289 "configured ISA RocketPort controller 0x%lx. "
2290 "Driver exiting\n", controller);
2291 ret = -EBUSY;
2292 goto err_tty;
1da177e4
LT		 2293 }
2294
2295 /* Store ISA variable retrieved from command line or .conf file. */
2296 rcktpt_io_addr[0] = board1;
2297 rcktpt_io_addr[1] = board2;
2298 rcktpt_io_addr[2] = board3;
2299 rcktpt_io_addr[3] = board4;
2300
2301 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2302 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2303 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2304 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2305 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2306 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2307 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2308 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2309
2310 /*
2311 * Set up the tty driver structure and then register this
2312 * driver with the tty layer.
2313 */
2314
2315 rocket_driver->owner = THIS_MODULE;
331b8319 2316 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2317 rocket_driver->name = "ttyR";
2318 rocket_driver->driver_name = "Comtrol RocketPort";
2319 rocket_driver->major = TTY_ROCKET_MAJOR;
2320 rocket_driver->minor_start = 0;
2321 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2322 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2323 rocket_driver->init_termios = tty_std_termios;
2324 rocket_driver->init_termios.c_cflag =
2325 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2326 rocket_driver->init_termios.c_ispeed = 9600;
2327 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2328#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2329 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2330#endif
2331 tty_set_operations(rocket_driver, &rocket_ops);
2332
4384a3fa
JS		 2333 ret = tty_register_driver(rocket_driver);
2334 if (ret < 0) {
2335 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2336 goto err_tty;
1da177e4
LT		 2337 }
2338
2339#ifdef ROCKET_DEBUG_OPEN
2340 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2341#endif
2342
2343 /*
2344 * OK, let's probe each of the controllers looking for boards. Any boards found
2345 * will be initialized here.
2346 */
2347 isa_boards_found = 0;
2348 pci_boards_found = 0;
2349
2350 for (i = 0; i < NUM_BOARDS; i++) {
2351 if (init_ISA(i))
2352 isa_boards_found++;
2353 }
2354
2355#ifdef CONFIG_PCI
2356 if (isa_boards_found < NUM_BOARDS)
2357 pci_boards_found = init_PCI(isa_boards_found);
2358#endif
2359
2360 max_board = pci_boards_found + isa_boards_found;
2361
2362 if (max_board == 0) {
4384a3fa
JS		 2363 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2364 ret = -ENXIO;
2365 goto err_ttyu;
1da177e4
LT		 2366 }
2367
2368 return 0;
4384a3fa
JS		 2369err_ttyu:
2370 tty_unregister_driver(rocket_driver);
2371err_tty:
2372 put_tty_driver(rocket_driver);
2373err:
2374 return ret;
1da177e4
LT		 2375}
2376
1da177e4
LT		 2377
2378static void rp_cleanup_module(void)
2379{
2380 int retval;
2381 int i;
2382
2383 del_timer_sync(&rocket_timer);
2384
2385 retval = tty_unregister_driver(rocket_driver);
2386 if (retval)
68562b79 2387 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2388 "rocketport driver\n", -retval);
1da177e4 2389
735d5661 2390 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2391 if (rp_table[i]) {
2392 tty_unregister_device(rocket_driver, i);
2393 kfree(rp_table[i]);
2394 }
2395
2396 put_tty_driver(rocket_driver);
1da177e4
LT		 2397
2398 for (i = 0; i < NUM_BOARDS; i++) {
2399 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2400 continue;
2401 release_region(rcktpt_io_addr[i], 64);
2402 }
2403 if (controller)
2404 release_region(controller, 4);
2405}
1da177e4 2406
1da177e4
LT		 2407/***************************************************************************
2408Function: sInitController
2409Purpose: Initialization of controller global registers and controller
2410 structure.
2411Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2412 IRQNum,Frequency,PeriodicOnly)
2413 CONTROLLER_T *CtlP; Ptr to controller structure
2414 int CtlNum; Controller number
2415 ByteIO_t MudbacIO; Mudbac base I/O address.
2416 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2417 This list must be in the order the AIOPs will be found on the
2418 controller. Once an AIOP in the list is not found, it is
2419 assumed that there are no more AIOPs on the controller.
2420 int AiopIOListSize; Number of addresses in AiopIOList
2421 int IRQNum; Interrupt Request number. Can be any of the following:
2422 0: Disable global interrupts
2423 3: IRQ 3
2424 4: IRQ 4
2425 5: IRQ 5
2426 9: IRQ 9
2427 10: IRQ 10
2428 11: IRQ 11
2429 12: IRQ 12
2430 15: IRQ 15
2431 Byte_t Frequency: A flag identifying the frequency
2432 of the periodic interrupt, can be any one of the following:
2433 FREQ_DIS - periodic interrupt disabled
2434 FREQ_137HZ - 137 Hertz
2435 FREQ_69HZ - 69 Hertz
2436 FREQ_34HZ - 34 Hertz
2437 FREQ_17HZ - 17 Hertz
2438 FREQ_9HZ - 9 Hertz
2439 FREQ_4HZ - 4 Hertz
2440 If IRQNum is set to 0 the Frequency parameter is
2441 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2442 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2443 interrupt are to be blocked.
f15313bf 2444 0 is both the periodic interrupt and
1da177e4
LT		 2445 other channel interrupts are allowed.
2446 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2447 overidden, it is forced to a value of 0.
1da177e4
LT		 2448Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2449 initialization failed.
2450
2451Comments:
2452 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2453 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2454
2455 If interrupts are to be completely disabled set IRQNum to 0.
2456
f15313bf 2457 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2458 invalid combination.
2459
2460 This function performs initialization of global interrupt modes,
2461 but it does not actually enable global interrupts. To enable
2462 and disable global interrupts use functions sEnGlobalInt() and
2463 sDisGlobalInt(). Enabling of global interrupts is normally not
2464 done until all other initializations are complete.
2465
2466 Even if interrupts are globally enabled, they must also be
2467 individually enabled for each channel that is to generate
2468 interrupts.
2469
2470Warnings: No range checking on any of the parameters is done.
2471
2472 No context switches are allowed while executing this function.
2473
2474 After this function all AIOPs on the controller are disabled,
2475 they can be enabled with sEnAiop().
2476*/
f15313bf
AB		 2477static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2478 ByteIO_t * AiopIOList, int AiopIOListSize,
2479 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2480{
2481 int i;
2482 ByteIO_t io;
2483 int done;
2484
2485 CtlP->AiopIntrBits = aiop_intr_bits;
2486 CtlP->AltChanRingIndicator = 0;
2487 CtlP->CtlNum = CtlNum;
2488 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2489 CtlP->BusType = isISA;
2490 CtlP->MBaseIO = MudbacIO;
2491 CtlP->MReg1IO = MudbacIO + 1;
2492 CtlP->MReg2IO = MudbacIO + 2;
2493 CtlP->MReg3IO = MudbacIO + 3;
2494#if 1
2495 CtlP->MReg2 = 0; /* interrupt disable */
2496 CtlP->MReg3 = 0; /* no periodic interrupts */
2497#else
2498 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2499 CtlP->MReg2 = 0; /* interrupt disable */
2500 CtlP->MReg3 = 0; /* no periodic interrupts */
2501 } else {
2502 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2503 CtlP->MReg3 = Frequency; /* set frequency */
2504 if (PeriodicOnly) { /* periodic interrupt only */
2505 CtlP->MReg3 |= PERIODIC_ONLY;
2506 }
2507 }
2508#endif
2509 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2510 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2511 sControllerEOI(CtlP); /* clear EOI if warm init */
2512 /* Init AIOPs */
2513 CtlP->NumAiop = 0;
2514 for (i = done = 0; i < AiopIOListSize; i++) {
2515 io = AiopIOList[i];
2516 CtlP->AiopIO[i] = (WordIO_t) io;
2517 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2518 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2519 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2520 if (done)
2521 continue;
2522 sEnAiop(CtlP, i); /* enable the AIOP */
2523 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2524 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2525 done = 1; /* done looking for AIOPs */
2526 else {
2527 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2528 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2529 sOutB(io + _INDX_DATA, sClockPrescale);
2530 CtlP->NumAiop++; /* bump count of AIOPs */
2531 }
2532 sDisAiop(CtlP, i); /* disable AIOP */
2533 }
2534
2535 if (CtlP->NumAiop == 0)
2536 return (-1);
2537 else
2538 return (CtlP->NumAiop);
2539}
2540
2541/***************************************************************************
2542Function: sPCIInitController
2543Purpose: Initialization of controller global registers and controller
2544 structure.
2545Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2546 IRQNum,Frequency,PeriodicOnly)
2547 CONTROLLER_T *CtlP; Ptr to controller structure
2548 int CtlNum; Controller number
2549 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2550 This list must be in the order the AIOPs will be found on the
2551 controller. Once an AIOP in the list is not found, it is
2552 assumed that there are no more AIOPs on the controller.
2553 int AiopIOListSize; Number of addresses in AiopIOList
2554 int IRQNum; Interrupt Request number. Can be any of the following:
2555 0: Disable global interrupts
2556 3: IRQ 3
2557 4: IRQ 4
2558 5: IRQ 5
2559 9: IRQ 9
2560 10: IRQ 10
2561 11: IRQ 11
2562 12: IRQ 12
2563 15: IRQ 15
2564 Byte_t Frequency: A flag identifying the frequency
2565 of the periodic interrupt, can be any one of the following:
2566 FREQ_DIS - periodic interrupt disabled
2567 FREQ_137HZ - 137 Hertz
2568 FREQ_69HZ - 69 Hertz
2569 FREQ_34HZ - 34 Hertz
2570 FREQ_17HZ - 17 Hertz
2571 FREQ_9HZ - 9 Hertz
2572 FREQ_4HZ - 4 Hertz
2573 If IRQNum is set to 0 the Frequency parameter is
2574 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2575 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2576 interrupt are to be blocked.
f15313bf 2577 0 is both the periodic interrupt and
1da177e4
LT		 2578 other channel interrupts are allowed.
2579 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2580 overidden, it is forced to a value of 0.
1da177e4
LT		 2581Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2582 initialization failed.
2583
2584Comments:
2585 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2586 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2587
2588 If interrupts are to be completely disabled set IRQNum to 0.
2589
f15313bf 2590 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2591 invalid combination.
2592
2593 This function performs initialization of global interrupt modes,
2594 but it does not actually enable global interrupts. To enable
2595 and disable global interrupts use functions sEnGlobalInt() and
2596 sDisGlobalInt(). Enabling of global interrupts is normally not
2597 done until all other initializations are complete.
2598
2599 Even if interrupts are globally enabled, they must also be
2600 individually enabled for each channel that is to generate
2601 interrupts.
2602
2603Warnings: No range checking on any of the parameters is done.
2604
2605 No context switches are allowed while executing this function.
2606
2607 After this function all AIOPs on the controller are disabled,
2608 they can be enabled with sEnAiop().
2609*/
f15313bf
AB		 2610static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2611 ByteIO_t * AiopIOList, int AiopIOListSize,
2612 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2613 int PeriodicOnly, int altChanRingIndicator,
2614 int UPCIRingInd)
1da177e4
LT		 2615{
2616 int i;
2617 ByteIO_t io;
2618
2619 CtlP->AltChanRingIndicator = altChanRingIndicator;
2620 CtlP->UPCIRingInd = UPCIRingInd;
2621 CtlP->CtlNum = CtlNum;
2622 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2623 CtlP->BusType = isPCI; /* controller release 1 */
2624
2625 if (ConfigIO) {
2626 CtlP->isUPCI = 1;
2627 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2628 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2629 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2630 } else {
2631 CtlP->isUPCI = 0;
2632 CtlP->PCIIO =
2633 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2634 CtlP->AiopIntrBits = aiop_intr_bits;
2635 }
2636
2637 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2638 /* Init AIOPs */
2639 CtlP->NumAiop = 0;
2640 for (i = 0; i < AiopIOListSize; i++) {
2641 io = AiopIOList[i];
2642 CtlP->AiopIO[i] = (WordIO_t) io;
2643 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2644
2645 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2646 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2647 break; /* done looking for AIOPs */
2648
2649 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2650 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2651 sOutB(io + _INDX_DATA, sClockPrescale);
2652 CtlP->NumAiop++; /* bump count of AIOPs */
2653 }
2654
2655 if (CtlP->NumAiop == 0)
2656 return (-1);
2657 else
2658 return (CtlP->NumAiop);
2659}
2660
2661/***************************************************************************
2662Function: sReadAiopID
2663Purpose: Read the AIOP idenfication number directly from an AIOP.
2664Call: sReadAiopID(io)
2665 ByteIO_t io: AIOP base I/O address
2666Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2667 is replace by an identifying number.
2668 Flag AIOPID_NULL if no valid AIOP is found
2669Warnings: No context switches are allowed while executing this function.
2670
2671*/
f15313bf 2672static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2673{
2674 Byte_t AiopID; /* ID byte from AIOP */
2675
2676 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2677 sOutB(io + _CMD_REG, 0x0);
2678 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2679 if (AiopID == 0x06)
2680 return (1);
2681 else /* AIOP does not exist */
2682 return (-1);
2683}
2684
2685/***************************************************************************
2686Function: sReadAiopNumChan
2687Purpose: Read the number of channels available in an AIOP directly from
2688 an AIOP.
2689Call: sReadAiopNumChan(io)
2690 WordIO_t io: AIOP base I/O address
2691Return: int: The number of channels available
2692Comments: The number of channels is determined by write/reads from identical
2693 offsets within the SRAM address spaces for channels 0 and 4.
2694 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2695 AIOP, otherwise it is an 8 channel.
2696Warnings: No context switches are allowed while executing this function.
2697*/
f15313bf 2698static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2699{
2700 Word_t x;
2701 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2702
2703 /* write to chan 0 SRAM */
457fb605 2704 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2705 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2706 x = sInW(io + _INDX_DATA);
2707 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2708 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2709 return (8);
2710 else
2711 return (4);
2712}
2713
2714/***************************************************************************
2715Function: sInitChan
2716Purpose: Initialization of a channel and channel structure
2717Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2718 CONTROLLER_T *CtlP; Ptr to controller structure
2719 CHANNEL_T *ChP; Ptr to channel structure
2720 int AiopNum; AIOP number within controller
2721 int ChanNum; Channel number within AIOP
f15313bf 2722Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2723 number exceeds number of channels available in AIOP.
2724Comments: This function must be called before a channel can be used.
2725Warnings: No range checking on any of the parameters is done.
2726
2727 No context switches are allowed while executing this function.
2728*/
f15313bf
AB		 2729static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2730 int ChanNum)
1da177e4
LT		 2731{
2732 int i;
2733 WordIO_t AiopIO;
2734 WordIO_t ChIOOff;
2735 Byte_t *ChR;
2736 Word_t ChOff;
2737 static Byte_t R[4];
2738 int brd9600;
2739
2740 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2741 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2742
2743 /* Channel, AIOP, and controller identifiers */
2744 ChP->CtlP = CtlP;
2745 ChP->ChanID = CtlP->AiopID[AiopNum];
2746 ChP->AiopNum = AiopNum;
2747 ChP->ChanNum = ChanNum;
2748
2749 /* Global direct addresses */
2750 AiopIO = CtlP->AiopIO[AiopNum];
2751 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2752 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2753 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2754 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2755 ChP->IndexData = AiopIO + _INDX_DATA;
2756
2757 /* Channel direct addresses */
2758 ChIOOff = AiopIO + ChP->ChanNum * 2;
2759 ChP->TxRxData = ChIOOff + _TD0;
2760 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2761 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2762 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2763
2764 /* Initialize the channel from the RData array */
2765 for (i = 0; i < RDATASIZE; i += 4) {
2766 R[0] = RData[i];
2767 R[1] = RData[i + 1] + 0x10 * ChanNum;
2768 R[2] = RData[i + 2];
2769 R[3] = RData[i + 3];
457fb605 2770 out32(ChP->IndexAddr, R);
1da177e4
LT		 2771 }
2772
2773 ChR = ChP->R;
2774 for (i = 0; i < RREGDATASIZE; i += 4) {
2775 ChR[i] = RRegData[i];
2776 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2777 ChR[i + 2] = RRegData[i + 2];
2778 ChR[i + 3] = RRegData[i + 3];
2779 }
2780
2781 /* Indexed registers */
2782 ChOff = (Word_t) ChanNum *0x1000;
2783
2784 if (sClockPrescale == 0x14)
2785 brd9600 = 47;
2786 else
2787 brd9600 = 23;
2788
2789 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2790 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2791 ChP->BaudDiv[2] = (Byte_t) brd9600;
2792 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2793 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2794
2795 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2796 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2797 ChP->TxControl[2] = 0;
2798 ChP->TxControl[3] = 0;
457fb605 2799 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2800
2801 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2802 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2803 ChP->RxControl[2] = 0;
2804 ChP->RxControl[3] = 0;
457fb605 2805 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2806
2807 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2808 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2809 ChP->TxEnables[2] = 0;
2810 ChP->TxEnables[3] = 0;
457fb605 2811 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2812
2813 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2814 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2815 ChP->TxCompare[2] = 0;
2816 ChP->TxCompare[3] = 0;
457fb605 2817 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2818
2819 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2820 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2821 ChP->TxReplace1[2] = 0;
2822 ChP->TxReplace1[3] = 0;
457fb605 2823 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2824
2825 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2826 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2827 ChP->TxReplace2[2] = 0;
2828 ChP->TxReplace2[3] = 0;
457fb605 2829 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2830
2831 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2832 ChP->TxFIFO = ChOff + _TX_FIFO;
2833
2834 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2835 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2836 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2837 sOutW(ChP->IndexData, 0);
2838 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2839 ChP->RxFIFO = ChOff + _RX_FIFO;
2840
2841 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2842 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2843 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2844 sOutW(ChP->IndexData, 0);
2845 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2846 sOutW(ChP->IndexData, 0);
2847 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2848 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2849 sOutB(ChP->IndexData, 0);
2850 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2851 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2852 sOutB(ChP->IndexData, 0);
2853 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2854 sEnRxProcessor(ChP); /* start the Rx processor */
2855
f15313bf 2856 return 1;
1da177e4
LT		 2857}
2858
2859/***************************************************************************
2860Function: sStopRxProcessor
2861Purpose: Stop the receive processor from processing a channel.
2862Call: sStopRxProcessor(ChP)
2863 CHANNEL_T *ChP; Ptr to channel structure
2864
2865Comments: The receive processor can be started again with sStartRxProcessor().
2866 This function causes the receive processor to skip over the
2867 stopped channel. It does not stop it from processing other channels.
2868
2869Warnings: No context switches are allowed while executing this function.
2870
2871 Do not leave the receive processor stopped for more than one
2872 character time.
2873
2874 After calling this function a delay of 4 uS is required to ensure
2875 that the receive processor is no longer processing this channel.
2876*/
f15313bf 2877static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2878{
2879 Byte_t R[4];
2880
2881 R[0] = ChP->R[0];
2882 R[1] = ChP->R[1];
2883 R[2] = 0x0a;
2884 R[3] = ChP->R[3];
457fb605 2885 out32(ChP->IndexAddr, R);
1da177e4
LT		 2886}
2887
2888/***************************************************************************
2889Function: sFlushRxFIFO
2890Purpose: Flush the Rx FIFO
2891Call: sFlushRxFIFO(ChP)
2892 CHANNEL_T *ChP; Ptr to channel structure
2893Return: void
2894Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2895 while it is being flushed the receive processor is stopped
2896 and the transmitter is disabled. After these operations a
2897 4 uS delay is done before clearing the pointers to allow
2898 the receive processor to stop. These items are handled inside
2899 this function.
2900Warnings: No context switches are allowed while executing this function.
2901*/
f15313bf 2902static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2903{
2904 int i;
2905 Byte_t Ch; /* channel number within AIOP */
f15313bf 2906 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 2907
2908 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2909 return; /* don't need to flush */
2910
f15313bf 2911 RxFIFOEnabled = 0;
1da177e4 2912 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 2913 RxFIFOEnabled = 1;
1da177e4
LT		 2914 sDisRxFIFO(ChP); /* disable it */
2915 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2916 sInB(ChP->IntChan); /* depends on bus i/o timing */
2917 }
2918 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2919 Ch = (Byte_t) sGetChanNum(ChP);
2920 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2921 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2922 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2923 sOutW(ChP->IndexData, 0);
2924 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2925 sOutW(ChP->IndexData, 0);
2926 if (RxFIFOEnabled)
2927 sEnRxFIFO(ChP); /* enable Rx FIFO */
2928}
2929
2930/***************************************************************************
2931Function: sFlushTxFIFO
2932Purpose: Flush the Tx FIFO
2933Call: sFlushTxFIFO(ChP)
2934 CHANNEL_T *ChP; Ptr to channel structure
2935Return: void
2936Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2937 while it is being flushed the receive processor is stopped
2938 and the transmitter is disabled. After these operations a
2939 4 uS delay is done before clearing the pointers to allow
2940 the receive processor to stop. These items are handled inside
2941 this function.
2942Warnings: No context switches are allowed while executing this function.
2943*/
f15313bf 2944static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2945{
2946 int i;
2947 Byte_t Ch; /* channel number within AIOP */
f15313bf 2948 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 2949
2950 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2951 return; /* don't need to flush */
2952
f15313bf 2953 TxEnabled = 0;
1da177e4 2954 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 2955 TxEnabled = 1;
1da177e4
LT		 2956 sDisTransmit(ChP); /* disable transmitter */
2957 }
2958 sStopRxProcessor(ChP); /* stop Rx processor */
2959 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2960 sInB(ChP->IntChan); /* depends on bus i/o timing */
2961 Ch = (Byte_t) sGetChanNum(ChP);
2962 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2963 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2964 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2965 sOutW(ChP->IndexData, 0);
2966 if (TxEnabled)
2967 sEnTransmit(ChP); /* enable transmitter */
2968 sStartRxProcessor(ChP); /* restart Rx processor */
2969}
2970
2971/***************************************************************************
2972Function: sWriteTxPrioByte
2973Purpose: Write a byte of priority transmit data to a channel
2974Call: sWriteTxPrioByte(ChP,Data)
2975 CHANNEL_T *ChP; Ptr to channel structure
2976 Byte_t Data; The transmit data byte
2977
2978Return: int: 1 if the bytes is successfully written, otherwise 0.
2979
2980Comments: The priority byte is transmitted before any data in the Tx FIFO.
2981
2982Warnings: No context switches are allowed while executing this function.
2983*/
f15313bf 2984static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 2985{
2986 Byte_t DWBuf[4]; /* buffer for double word writes */
2987 Word_t *WordPtr; /* must be far because Win SS != DS */
2988 register DWordIO_t IndexAddr;
2989
2990 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2991 IndexAddr = ChP->IndexAddr;
2992 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2993 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2994 return (0); /* nothing sent */
2995
2996 WordPtr = (Word_t *) (&DWBuf[0]);
2997 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2998
2999 DWBuf[2] = Data; /* data byte value */
457fb605 3000 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3001
3002 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3003
3004 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3005 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 3006 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3007 } else { /* write it to Tx FIFO */
3008
3009 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3010 }
3011 return (1); /* 1 byte sent */
3012}
3013
3014/***************************************************************************
3015Function: sEnInterrupts
3016Purpose: Enable one or more interrupts for a channel
3017Call: sEnInterrupts(ChP,Flags)
3018 CHANNEL_T *ChP; Ptr to channel structure
3019 Word_t Flags: Interrupt enable flags, can be any combination
3020 of the following flags:
3021 TXINT_EN: Interrupt on Tx FIFO empty
3022 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3023 sSetRxTrigger())
3024 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3025 MCINT_EN: Interrupt on modem input change
3026 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3027 Interrupt Channel Register.
3028Return: void
3029Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3030 enabled. If an interrupt enable flag is not set in Flags, that
3031 interrupt will not be changed. Interrupts can be disabled with
3032 function sDisInterrupts().
3033
3034 This function sets the appropriate bit for the channel in the AIOP's
3035 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3036 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3037
3038 Interrupts must also be globally enabled before channel interrupts
3039 will be passed on to the host. This is done with function
3040 sEnGlobalInt().
3041
3042 In some cases it may be desirable to disable interrupts globally but
3043 enable channel interrupts. This would allow the global interrupt
3044 status register to be used to determine which AIOPs need service.
3045*/
f15313bf 3046static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3047{
3048 Byte_t Mask; /* Interrupt Mask Register */
3049
3050 ChP->RxControl[2] |=
3051 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3052
457fb605 3053 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3054
3055 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3056
457fb605 3057 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3058
3059 if (Flags & CHANINT_EN) {
3060 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3061 sOutB(ChP->IntMask, Mask);
3062 }
3063}
3064
3065/***************************************************************************
3066Function: sDisInterrupts
3067Purpose: Disable one or more interrupts for a channel
3068Call: sDisInterrupts(ChP,Flags)
3069 CHANNEL_T *ChP; Ptr to channel structure
3070 Word_t Flags: Interrupt flags, can be any combination
3071 of the following flags:
3072 TXINT_EN: Interrupt on Tx FIFO empty
3073 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3074 sSetRxTrigger())
3075 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3076 MCINT_EN: Interrupt on modem input change
3077 CHANINT_EN: Disable channel interrupt signal to the
3078 AIOP's Interrupt Channel Register.
3079Return: void
3080Comments: If an interrupt flag is set in Flags, that interrupt will be
3081 disabled. If an interrupt flag is not set in Flags, that
3082 interrupt will not be changed. Interrupts can be enabled with
3083 function sEnInterrupts().
3084
3085 This function clears the appropriate bit for the channel in the AIOP's
3086 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3087 this channel's bit from being set in the AIOP's Interrupt Channel
3088 Register.
3089*/
f15313bf 3090static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3091{
3092 Byte_t Mask; /* Interrupt Mask Register */
3093
3094 ChP->RxControl[2] &=
3095 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3096 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3097 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3098 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3099
3100 if (Flags & CHANINT_EN) {
3101 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3102 sOutB(ChP->IntMask, Mask);
3103 }
3104}
3105
f15313bf 3106static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3107{
3108 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3109}
3110
3111/*
3112 * Not an official SSCI function, but how to reset RocketModems.
3113 * ISA bus version
3114 */
f15313bf 3115static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3116{
3117 ByteIO_t addr;
3118 Byte_t val;
3119
3120 addr = CtlP->AiopIO[0] + 0x400;
3121 val = sInB(CtlP->MReg3IO);
3122 /* if AIOP[1] is not enabled, enable it */
3123 if ((val & 2) == 0) {
3124 val = sInB(CtlP->MReg2IO);
3125 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3126 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3127 }
3128
3129 sEnAiop(CtlP, 1);
3130 if (!on)
3131 addr += 8;
3132 sOutB(addr + chan, 0); /* apply or remove reset */
3133 sDisAiop(CtlP, 1);
3134}
3135
3136/*
3137 * Not an official SSCI function, but how to reset RocketModems.
3138 * PCI bus version
3139 */
f15313bf 3140static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3141{
3142 ByteIO_t addr;
3143
3144 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3145 if (!on)
3146 addr += 8;
3147 sOutB(addr + chan, 0); /* apply or remove reset */
3148}
3149
3150/* Resets the speaker controller on RocketModem II and III devices */
3151static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3152{
3153 ByteIO_t addr;
3154
3155 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3156 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3157 addr = CtlP->AiopIO[0] + 0x4F;
3158 sOutB(addr, 0);
3159 }
3160
3161 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3162 if ((model == MODEL_UPCI_RM3_8PORT)
3163 || (model == MODEL_UPCI_RM3_4PORT)) {
3164 addr = CtlP->AiopIO[0] + 0x88;
3165 sOutB(addr, 0);
3166 }
3167}
3168
3169/* Returns the line number given the controller (board), aiop and channel number */
3170static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3171{
3172 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3173}
3174
3175/*
3176 * Stores the line number associated with a given controller (board), aiop
3177 * and channel number.
3178 * Returns: The line number assigned
3179 */
3180static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3181{
3182 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3183 return (nextLineNumber - 1);
3184}
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