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Replace <asm/uaccess.h> with <linux/uaccess.h> globally
[linux-block.git] / drivers / char / pcmcia / synclink_cs.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/pcmcia/synclink_cs.c
3 *
a7482a2e 4 * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
1da177e4
LT		 5 *
6 * Device driver for Microgate SyncLink PC Card
7 * multiprotocol serial adapter.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * This code is released under the GNU General Public License (GPL)
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
26 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30#if defined(__i386__)
31# define BREAKPOINT() asm(" int $3");
32#else
33# define BREAKPOINT() { }
34#endif
35
36#define MAX_DEVICE_COUNT 4
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/errno.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/timer.h>
43#include <linux/time.h>
44#include <linux/interrupt.h>
1da177e4
LT		 45#include <linux/tty.h>
46#include <linux/tty_flip.h>
47#include <linux/serial.h>
48#include <linux/major.h>
49#include <linux/string.h>
50#include <linux/fcntl.h>
51#include <linux/ptrace.h>
52#include <linux/ioport.h>
53#include <linux/mm.h>
87687144 54#include <linux/seq_file.h>
1da177e4
LT		 55#include <linux/slab.h>
56#include <linux/netdevice.h>
57#include <linux/vmalloc.h>
58#include <linux/init.h>
1da177e4
LT		 59#include <linux/delay.h>
60#include <linux/ioctl.h>
3dd1247f 61#include <linux/synclink.h>
1da177e4 62
1da177e4
LT		 63#include <asm/io.h>
64#include <asm/irq.h>
65#include <asm/dma.h>
66#include <linux/bitops.h>
67#include <asm/types.h>
68#include <linux/termios.h>
69#include <linux/workqueue.h>
70#include <linux/hdlc.h>
71
1da177e4
LT		 72#include <pcmcia/cistpl.h>
73#include <pcmcia/cisreg.h>
74#include <pcmcia/ds.h>
75
af69c7f9
PF		 76#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
77#define SYNCLINK_GENERIC_HDLC 1
78#else
79#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 80#endif
81
82#define GET_USER(error,value,addr) error = get_user(value,addr)
83#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
84#define PUT_USER(error,value,addr) error = put_user(value,addr)
85#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
86
7c0f6ba6 87#include <linux/uaccess.h>
1da177e4 88
1da177e4
LT		 89static MGSL_PARAMS default_params = {
90 MGSL_MODE_HDLC, /* unsigned long mode */
91 0, /* unsigned char loopback; */
92 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
93 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
94 0, /* unsigned long clock_speed; */
95 0xff, /* unsigned char addr_filter; */
96 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
97 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
98 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
99 9600, /* unsigned long data_rate; */
100 8, /* unsigned char data_bits; */
101 1, /* unsigned char stop_bits; */
102 ASYNC_PARITY_NONE /* unsigned char parity; */
103};
104
3d553993 105typedef struct {
1da177e4
LT		 106 int count;
107 unsigned char status;
108 char data[1];
109} RXBUF;
110
111/* The queue of BH actions to be performed */
112
113#define BH_RECEIVE 1
114#define BH_TRANSMIT 2
115#define BH_STATUS 4
116
117#define IO_PIN_SHUTDOWN_LIMIT 100
118
119#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
120
121struct _input_signal_events {
d12341f9 122 int ri_up;
1da177e4
LT		 123 int ri_down;
124 int dsr_up;
125 int dsr_down;
126 int dcd_up;
127 int dcd_down;
128 int cts_up;
129 int cts_down;
130};
131
132
133/*
134 * Device instance data structure
135 */
d12341f9 136
1da177e4 137typedef struct _mgslpc_info {
eeb46134 138 struct tty_port port;
1da177e4
LT		 139 void *if_ptr; /* General purpose pointer (used by SPPP) */
140 int magic;
1da177e4 141 int line;
d12341f9 142
1da177e4 143 struct mgsl_icount icount;
d12341f9 144
1da177e4
LT		 145 int timeout;
146 int x_char; /* xon/xoff character */
1da177e4 147 unsigned char read_status_mask;
d12341f9 148 unsigned char ignore_status_mask;
1da177e4
LT		 149
150 unsigned char *tx_buf;
151 int tx_put;
152 int tx_get;
153 int tx_count;
154
155 /* circular list of fixed length rx buffers */
156
157 unsigned char *rx_buf; /* memory allocated for all rx buffers */
158 int rx_buf_total_size; /* size of memory allocated for rx buffers */
159 int rx_put; /* index of next empty rx buffer */
160 int rx_get; /* index of next full rx buffer */
161 int rx_buf_size; /* size in bytes of single rx buffer */
162 int rx_buf_count; /* total number of rx buffers */
163 int rx_frame_count; /* number of full rx buffers */
d12341f9 164
1da177e4
LT		 165 wait_queue_head_t status_event_wait_q;
166 wait_queue_head_t event_wait_q;
167 struct timer_list tx_timer; /* HDLC transmit timeout timer */
168 struct _mgslpc_info *next_device; /* device list link */
169
170 unsigned short imra_value;
171 unsigned short imrb_value;
172 unsigned char pim_value;
173
174 spinlock_t lock;
175 struct work_struct task; /* task structure for scheduling bh */
176
177 u32 max_frame_size;
178
179 u32 pending_bh;
180
0fab6de0
JP		 181 bool bh_running;
182 bool bh_requested;
d12341f9 183
1da177e4
LT		 184 int dcd_chkcount; /* check counts to prevent */
185 int cts_chkcount; /* too many IRQs if a signal */
186 int dsr_chkcount; /* is floating */
187 int ri_chkcount;
188
0fab6de0
JP		 189 bool rx_enabled;
190 bool rx_overflow;
1da177e4 191
0fab6de0
JP		 192 bool tx_enabled;
193 bool tx_active;
194 bool tx_aborting;
1da177e4
LT		 195 u32 idle_mode;
196
197 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
198
199 char device_name[25]; /* device instance name */
200
201 unsigned int io_base; /* base I/O address of adapter */
202 unsigned int irq_level;
d12341f9 203
1da177e4
LT		 204 MGSL_PARAMS params; /* communications parameters */
205
206 unsigned char serial_signals; /* current serial signal states */
207
0fab6de0 208 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 209 char testing_irq;
210 unsigned int init_error; /* startup error (DIAGS) */
211
a6b68a69 212 char *flag_buf;
0fab6de0 213 bool drop_rts_on_tx_done;
1da177e4
LT		 214
215 struct _input_signal_events input_signal_events;
216
217 /* PCMCIA support */
fd238232 218 struct pcmcia_device *p_dev;
1da177e4
LT		 219 int stop;
220
221 /* SPPP/Cisco HDLC device parts */
222 int netcount;
1da177e4
LT		 223 spinlock_t netlock;
224
af69c7f9 225#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 226 struct net_device *netdev;
227#endif
228
229} MGSLPC_INFO;
230
231#define MGSLPC_MAGIC 0x5402
232
233/*
234 * The size of the serial xmit buffer is 1 page, or 4096 bytes
235 */
236#define TXBUFSIZE 4096
237
d12341f9 238
1da177e4
LT		 239#define CHA 0x00 /* channel A offset */
240#define CHB 0x40 /* channel B offset */
241
242/*
243 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
244 */
245#undef PVR
246
247#define RXFIFO 0
248#define TXFIFO 0
249#define STAR 0x20
250#define CMDR 0x20
251#define RSTA 0x21
252#define PRE 0x21
253#define MODE 0x22
254#define TIMR 0x23
255#define XAD1 0x24
256#define XAD2 0x25
257#define RAH1 0x26
258#define RAH2 0x27
259#define DAFO 0x27
260#define RAL1 0x28
261#define RFC 0x28
262#define RHCR 0x29
263#define RAL2 0x29
264#define RBCL 0x2a
265#define XBCL 0x2a
266#define RBCH 0x2b
267#define XBCH 0x2b
268#define CCR0 0x2c
269#define CCR1 0x2d
270#define CCR2 0x2e
271#define CCR3 0x2f
272#define VSTR 0x34
273#define BGR 0x34
274#define RLCR 0x35
275#define AML 0x36
276#define AMH 0x37
277#define GIS 0x38
278#define IVA 0x38
279#define IPC 0x39
280#define ISR 0x3a
281#define IMR 0x3a
282#define PVR 0x3c
283#define PIS 0x3d
284#define PIM 0x3d
285#define PCR 0x3e
286#define CCR4 0x3f
d12341f9 287
1da177e4 288// IMR/ISR
d12341f9 289
1da177e4
LT		 290#define IRQ_BREAK_ON BIT15 // rx break detected
291#define IRQ_DATAOVERRUN BIT14 // receive data overflow
292#define IRQ_ALLSENT BIT13 // all sent
293#define IRQ_UNDERRUN BIT12 // transmit data underrun
294#define IRQ_TIMER BIT11 // timer interrupt
295#define IRQ_CTS BIT10 // CTS status change
296#define IRQ_TXREPEAT BIT9 // tx message repeat
297#define IRQ_TXFIFO BIT8 // transmit pool ready
298#define IRQ_RXEOM BIT7 // receive message end
299#define IRQ_EXITHUNT BIT6 // receive frame start
300#define IRQ_RXTIME BIT6 // rx char timeout
301#define IRQ_DCD BIT2 // carrier detect status change
302#define IRQ_OVERRUN BIT1 // receive frame overflow
303#define IRQ_RXFIFO BIT0 // receive pool full
d12341f9 304
1da177e4 305// STAR
d12341f9 306
1da177e4
LT		 307#define XFW BIT6 // transmit FIFO write enable
308#define CEC BIT2 // command executing
309#define CTS BIT1 // CTS state
d12341f9 310
1da177e4
LT		 311#define PVR_DTR BIT0
312#define PVR_DSR BIT1
313#define PVR_RI BIT2
314#define PVR_AUTOCTS BIT3
315#define PVR_RS232 0x20 /* 0010b */
316#define PVR_V35 0xe0 /* 1110b */
317#define PVR_RS422 0x40 /* 0100b */
d12341f9
JG		 318
319/* Register access functions */
320
1da177e4
LT		 321#define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
322#define read_reg(info, reg) inb((info)->io_base + (reg))
323
d12341f9 324#define read_reg16(info, reg) inw((info)->io_base + (reg))
1da177e4 325#define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
d12341f9 326
1da177e4 327#define set_reg_bits(info, reg, mask) \
3d553993 328 write_reg(info, (reg), \
d12341f9 329 (unsigned char) (read_reg(info, (reg)) | (mask)))
1da177e4 330#define clear_reg_bits(info, reg, mask) \
3d553993 331 write_reg(info, (reg), \
d12341f9 332 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
1da177e4
LT		 333/*
334 * interrupt enable/disable routines
d12341f9
JG		 335 */
336static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 337{
338 if (channel == CHA) {
339 info->imra_value |= mask;
340 write_reg16(info, CHA + IMR, info->imra_value);
341 } else {
342 info->imrb_value |= mask;
343 write_reg16(info, CHB + IMR, info->imrb_value);
344 }
345}
d12341f9 346static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 347{
348 if (channel == CHA) {
349 info->imra_value &= ~mask;
350 write_reg16(info, CHA + IMR, info->imra_value);
351 } else {
352 info->imrb_value &= ~mask;
353 write_reg16(info, CHB + IMR, info->imrb_value);
354 }
355}
356
357#define port_irq_disable(info, mask) \
3d553993 358 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
1da177e4
LT		 359
360#define port_irq_enable(info, mask) \
3d553993 361 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
1da177e4
LT		 362
363static void rx_start(MGSLPC_INFO *info);
364static void rx_stop(MGSLPC_INFO *info);
365
eeb46134 366static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 367static void tx_stop(MGSLPC_INFO *info);
368static void tx_set_idle(MGSLPC_INFO *info);
369
370static void get_signals(MGSLPC_INFO *info);
371static void set_signals(MGSLPC_INFO *info);
372
373static void reset_device(MGSLPC_INFO *info);
374
375static void hdlc_mode(MGSLPC_INFO *info);
376static void async_mode(MGSLPC_INFO *info);
377
378static void tx_timeout(unsigned long context);
379
eeb46134 380static int carrier_raised(struct tty_port *port);
fcc8ac18 381static void dtr_rts(struct tty_port *port, int onoff);
1da177e4 382
af69c7f9 383#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 384#define dev_to_port(D) (dev_to_hdlc(D)->priv)
385static void hdlcdev_tx_done(MGSLPC_INFO *info);
386static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
387static int hdlcdev_init(MGSLPC_INFO *info);
388static void hdlcdev_exit(MGSLPC_INFO *info);
389#endif
390
391static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
392
0fab6de0
JP		 393static bool register_test(MGSLPC_INFO *info);
394static bool irq_test(MGSLPC_INFO *info);
1da177e4
LT		 395static int adapter_test(MGSLPC_INFO *info);
396
397static int claim_resources(MGSLPC_INFO *info);
398static void release_resources(MGSLPC_INFO *info);
d34138d0 399static int mgslpc_add_device(MGSLPC_INFO *info);
1da177e4
LT		 400static void mgslpc_remove_device(MGSLPC_INFO *info);
401
eeb46134 402static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 403static void rx_reset_buffers(MGSLPC_INFO *info);
404static int rx_alloc_buffers(MGSLPC_INFO *info);
405static void rx_free_buffers(MGSLPC_INFO *info);
406
7d12e780 407static irqreturn_t mgslpc_isr(int irq, void *dev_id);
1da177e4
LT		 408
409/*
410 * Bottom half interrupt handlers
411 */
c4028958 412static void bh_handler(struct work_struct *work);
eeb46134 413static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 414static void bh_status(MGSLPC_INFO *info);
415
416/*
417 * ioctl handlers
418 */
60b33c13 419static int tiocmget(struct tty_struct *tty);
20b9d177
AC		 420static int tiocmset(struct tty_struct *tty,
421 unsigned int set, unsigned int clear);
1da177e4
LT		 422static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
423static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
eeb46134 424static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
1da177e4
LT		 425static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
426static int set_txidle(MGSLPC_INFO *info, int idle_mode);
eeb46134 427static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
1da177e4
LT		 428static int tx_abort(MGSLPC_INFO *info);
429static int set_rxenable(MGSLPC_INFO *info, int enable);
430static int wait_events(MGSLPC_INFO *info, int __user *mask);
431
432static MGSLPC_INFO *mgslpc_device_list = NULL;
433static int mgslpc_device_count = 0;
434
435/*
436 * Set this param to non-zero to load eax with the
437 * .text section address and breakpoint on module load.
438 * This is useful for use with gdb and add-symbol-file command.
439 */
208250dd 440static bool break_on_load;
1da177e4
LT		 441
442/*
443 * Driver major number, defaults to zero to get auto
444 * assigned major number. May be forced as module parameter.
445 */
446static int ttymajor=0;
447
448static int debug_level = 0;
449static int maxframe[MAX_DEVICE_COUNT] = {0,};
1da177e4
LT		 450
451module_param(break_on_load, bool, 0);
452module_param(ttymajor, int, 0);
453module_param(debug_level, int, 0);
454module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 455
456MODULE_LICENSE("GPL");
457
458static char *driver_name = "SyncLink PC Card driver";
a7482a2e 459static char *driver_version = "$Revision: 4.34 $";
1da177e4
LT		 460
461static struct tty_driver *serial_driver;
462
463/* number of characters left in xmit buffer before we ask for more */
464#define WAKEUP_CHARS 256
465
eeb46134 466static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 467static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
468
469/* PCMCIA prototypes */
470
15b99ac1 471static int mgslpc_config(struct pcmcia_device *link);
1da177e4 472static void mgslpc_release(u_long arg);
cc3b4866 473static void mgslpc_detach(struct pcmcia_device *p_dev);
1da177e4 474
1da177e4
LT		 475/*
476 * 1st function defined in .text section. Calling this function in
477 * init_module() followed by a breakpoint allows a remote debugger
478 * (gdb) to get the .text address for the add-symbol-file command.
479 * This allows remote debugging of dynamically loadable modules.
480 */
481static void* mgslpc_get_text_ptr(void)
482{
483 return mgslpc_get_text_ptr;
484}
485
486/**
487 * line discipline callback wrappers
488 *
489 * The wrappers maintain line discipline references
490 * while calling into the line discipline.
491 *
1da177e4
LT		 492 * ldisc_receive_buf - pass receive data to line discipline
493 */
494
1da177e4
LT		 495static void ldisc_receive_buf(struct tty_struct *tty,
496 const __u8 *data, char *flags, int count)
497{
498 struct tty_ldisc *ld;
499 if (!tty)
500 return;
501 ld = tty_ldisc_ref(tty);
502 if (ld) {
a352def2
AC		 503 if (ld->ops->receive_buf)
504 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 505 tty_ldisc_deref(ld);
506 }
507}
508
eeb46134
AC		 509static const struct tty_port_operations mgslpc_port_ops = {
510 .carrier_raised = carrier_raised,
fcc8ac18 511 .dtr_rts = dtr_rts
eeb46134
AC		 512};
513
15b99ac1 514static int mgslpc_probe(struct pcmcia_device *link)
1da177e4 515{
3d553993
AK		 516 MGSLPC_INFO *info;
517 int ret;
518
519 if (debug_level >= DEBUG_LEVEL_INFO)
520 printk("mgslpc_attach\n");
521
522 info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
523 if (!info) {
524 printk("Error can't allocate device instance data\n");
525 return -ENOMEM;
526 }
527
528 info->magic = MGSLPC_MAGIC;
529 tty_port_init(&info->port);
530 info->port.ops = &mgslpc_port_ops;
531 INIT_WORK(&info->task, bh_handler);
532 info->max_frame_size = 4096;
533 info->port.close_delay = 5*HZ/10;
534 info->port.closing_wait = 30*HZ;
535 init_waitqueue_head(&info->status_event_wait_q);
536 init_waitqueue_head(&info->event_wait_q);
537 spin_lock_init(&info->lock);
538 spin_lock_init(&info->netlock);
539 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
540 info->idle_mode = HDLC_TXIDLE_FLAGS;
541 info->imra_value = 0xffff;
542 info->imrb_value = 0xffff;
543 info->pim_value = 0xff;
544
545 info->p_dev = link;
546 link->priv = info;
547
548 /* Initialize the struct pcmcia_device structure */
549
550 ret = mgslpc_config(link);
551 if (ret != 0)
552 goto failed;
553
554 ret = mgslpc_add_device(info);
555 if (ret != 0)
556 goto failed_release;
557
558 return 0;
d34138d0
AK		 559
560failed_release:
3d553993 561 mgslpc_release((u_long)link);
d34138d0 562failed:
3d553993
AK		 563 tty_port_destroy(&info->port);
564 kfree(info);
565 return ret;
1da177e4
LT		 566}
567
568/* Card has been inserted.
569 */
570
00990e7c 571static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
aaa8cfda 572{
90abdc3b 573 return pcmcia_request_io(p_dev);
aaa8cfda
DB		 574}
575
15b99ac1 576static int mgslpc_config(struct pcmcia_device *link)
1da177e4 577{
3d553993
AK		 578 MGSLPC_INFO *info = link->priv;
579 int ret;
d12341f9 580
3d553993
AK		 581 if (debug_level >= DEBUG_LEVEL_INFO)
582 printk("mgslpc_config(0x%p)\n", link);
1da177e4 583
3d553993 584 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
00990e7c 585
3d553993
AK		 586 ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
587 if (ret != 0)
588 goto failed;
1da177e4 589
3d553993
AK		 590 link->config_index = 8;
591 link->config_regs = PRESENT_OPTION;
d12341f9 592
3d553993
AK		 593 ret = pcmcia_request_irq(link, mgslpc_isr);
594 if (ret)
595 goto failed;
596 ret = pcmcia_enable_device(link);
597 if (ret)
598 goto failed;
1da177e4 599
3d553993
AK		 600 info->io_base = link->resource[0]->start;
601 info->irq_level = link->irq;
602 return 0;
1da177e4 603
cbf624f0 604failed:
3d553993
AK		 605 mgslpc_release((u_long)link);
606 return -ENODEV;
1da177e4
LT		 607}
608
609/* Card has been removed.
610 * Unregister device and release PCMCIA configuration.
611 * If device is open, postpone until it is closed.
612 */
613static void mgslpc_release(u_long arg)
614{
e2d40963 615 struct pcmcia_device *link = (struct pcmcia_device *)arg;
1da177e4 616
e2d40963
DB		 617 if (debug_level >= DEBUG_LEVEL_INFO)
618 printk("mgslpc_release(0x%p)\n", link);
1da177e4 619
e2d40963 620 pcmcia_disable_device(link);
1da177e4
LT		 621}
622
fba395ee 623static void mgslpc_detach(struct pcmcia_device *link)
1da177e4 624{
e2d40963
DB		 625 if (debug_level >= DEBUG_LEVEL_INFO)
626 printk("mgslpc_detach(0x%p)\n", link);
cc3b4866 627
e2d40963
DB		 628 ((MGSLPC_INFO *)link->priv)->stop = 1;
629 mgslpc_release((u_long)link);
1da177e4 630
e2d40963 631 mgslpc_remove_device((MGSLPC_INFO *)link->priv);
1da177e4
LT		 632}
633
fba395ee 634static int mgslpc_suspend(struct pcmcia_device *link)
98e4c28b 635{
98e4c28b
DB		 636 MGSLPC_INFO *info = link->priv;
637
98e4c28b 638 info->stop = 1;
98e4c28b
DB		 639
640 return 0;
641}
642
fba395ee 643static int mgslpc_resume(struct pcmcia_device *link)
98e4c28b 644{
98e4c28b
DB		 645 MGSLPC_INFO *info = link->priv;
646
98e4c28b
DB		 647 info->stop = 0;
648
649 return 0;
650}
651
652
0fab6de0 653static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
1da177e4
LT		 654 char *name, const char *routine)
655{
656#ifdef MGSLPC_PARANOIA_CHECK
657 static const char *badmagic =
658 "Warning: bad magic number for mgsl struct (%s) in %s\n";
659 static const char *badinfo =
660 "Warning: null mgslpc_info for (%s) in %s\n";
661
662 if (!info) {
663 printk(badinfo, name, routine);
0fab6de0 664 return true;
1da177e4
LT		 665 }
666 if (info->magic != MGSLPC_MAGIC) {
667 printk(badmagic, name, routine);
0fab6de0 668 return true;
1da177e4
LT		 669 }
670#else
671 if (!info)
0fab6de0 672 return true;
1da177e4 673#endif
0fab6de0 674 return false;
1da177e4
LT		 675}
676
677
678#define CMD_RXFIFO BIT7 // release current rx FIFO
679#define CMD_RXRESET BIT6 // receiver reset
680#define CMD_RXFIFO_READ BIT5
681#define CMD_START_TIMER BIT4
682#define CMD_TXFIFO BIT3 // release current tx FIFO
683#define CMD_TXEOM BIT1 // transmit end message
684#define CMD_TXRESET BIT0 // transmit reset
685
0fab6de0 686static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
1da177e4
LT		 687{
688 int i = 0;
d12341f9 689 /* wait for command completion */
1da177e4
LT		 690 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
691 udelay(1);
692 if (i++ == 1000)
0fab6de0 693 return false;
1da177e4 694 }
0fab6de0 695 return true;
1da177e4
LT		 696}
697
d12341f9 698static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
1da177e4
LT		 699{
700 wait_command_complete(info, channel);
701 write_reg(info, (unsigned char) (channel + CMDR), cmd);
702}
703
704static void tx_pause(struct tty_struct *tty)
705{
706 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
707 unsigned long flags;
d12341f9 708
1da177e4
LT		 709 if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
710 return;
711 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 712 printk("tx_pause(%s)\n", info->device_name);
d12341f9 713
3d553993 714 spin_lock_irqsave(&info->lock, flags);
1da177e4 715 if (info->tx_enabled)
3d553993
AK		 716 tx_stop(info);
717 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 718}
719
720static void tx_release(struct tty_struct *tty)
721{
722 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
723 unsigned long flags;
d12341f9 724
1da177e4
LT		 725 if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
726 return;
727 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 728 printk("tx_release(%s)\n", info->device_name);
d12341f9 729
3d553993 730 spin_lock_irqsave(&info->lock, flags);
1da177e4 731 if (!info->tx_enabled)
3d553993
AK		 732 tx_start(info, tty);
733 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 734}
735
736/* Return next bottom half action to perform.
737 * or 0 if nothing to do.
738 */
739static int bh_action(MGSLPC_INFO *info)
740{
741 unsigned long flags;
742 int rc = 0;
d12341f9 743
3d553993 744 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 745
746 if (info->pending_bh & BH_RECEIVE) {
747 info->pending_bh &= ~BH_RECEIVE;
748 rc = BH_RECEIVE;
749 } else if (info->pending_bh & BH_TRANSMIT) {
750 info->pending_bh &= ~BH_TRANSMIT;
751 rc = BH_TRANSMIT;
752 } else if (info->pending_bh & BH_STATUS) {
753 info->pending_bh &= ~BH_STATUS;
754 rc = BH_STATUS;
755 }
756
757 if (!rc) {
758 /* Mark BH routine as complete */
0fab6de0
JP		 759 info->bh_running = false;
760 info->bh_requested = false;
1da177e4 761 }
d12341f9 762
3d553993 763 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 764
1da177e4
LT		 765 return rc;
766}
767
c4028958 768static void bh_handler(struct work_struct *work)
1da177e4 769{
c4028958 770 MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
eeb46134 771 struct tty_struct *tty;
1da177e4
LT		 772 int action;
773
1da177e4 774 if (debug_level >= DEBUG_LEVEL_BH)
3d553993 775 printk("%s(%d):bh_handler(%s) entry\n",
1da177e4 776 __FILE__,__LINE__,info->device_name);
d12341f9 777
0fab6de0 778 info->bh_running = true;
eeb46134 779 tty = tty_port_tty_get(&info->port);
1da177e4
LT		 780
781 while((action = bh_action(info)) != 0) {
d12341f9 782
1da177e4 783 /* Process work item */
3d553993
AK		 784 if (debug_level >= DEBUG_LEVEL_BH)
785 printk("%s(%d):bh_handler() work item action=%d\n",
1da177e4
LT		 786 __FILE__,__LINE__,action);
787
788 switch (action) {
d12341f9 789
1da177e4 790 case BH_RECEIVE:
eeb46134 791 while(rx_get_frame(info, tty));
1da177e4
LT		 792 break;
793 case BH_TRANSMIT:
eeb46134 794 bh_transmit(info, tty);
1da177e4
LT		 795 break;
796 case BH_STATUS:
797 bh_status(info);
798 break;
799 default:
800 /* unknown work item ID */
801 printk("Unknown work item ID=%08X!\n", action);
802 break;
803 }
804 }
805
eeb46134 806 tty_kref_put(tty);
1da177e4 807 if (debug_level >= DEBUG_LEVEL_BH)
3d553993 808 printk("%s(%d):bh_handler(%s) exit\n",
1da177e4
LT		 809 __FILE__,__LINE__,info->device_name);
810}
811
eeb46134 812static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4 813{
1da177e4
LT		 814 if (debug_level >= DEBUG_LEVEL_BH)
815 printk("bh_transmit() entry on %s\n", info->device_name);
816
b963a844 817 if (tty)
1da177e4 818 tty_wakeup(tty);
1da177e4
LT		 819}
820
cdaad343 821static void bh_status(MGSLPC_INFO *info)
1da177e4
LT		 822{
823 info->ri_chkcount = 0;
824 info->dsr_chkcount = 0;
825 info->dcd_chkcount = 0;
826 info->cts_chkcount = 0;
827}
828
d12341f9 829/* eom: non-zero = end of frame */
1da177e4
LT		 830static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
831{
832 unsigned char data[2];
833 unsigned char fifo_count, read_count, i;
834 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
835
836 if (debug_level >= DEBUG_LEVEL_ISR)
3d553993 837 printk("%s(%d):rx_ready_hdlc(eom=%d)\n", __FILE__, __LINE__, eom);
d12341f9 838
1da177e4
LT		 839 if (!info->rx_enabled)
840 return;
841
842 if (info->rx_frame_count >= info->rx_buf_count) {
843 /* no more free buffers */
844 issue_command(info, CHA, CMD_RXRESET);
845 info->pending_bh |= BH_RECEIVE;
0fab6de0 846 info->rx_overflow = true;
1da177e4
LT		 847 info->icount.buf_overrun++;
848 return;
849 }
850
851 if (eom) {
d12341f9 852 /* end of frame, get FIFO count from RBCL register */
3d553993
AK		 853 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
854 if (fifo_count == 0)
1da177e4
LT		 855 fifo_count = 32;
856 } else
857 fifo_count = 32;
d12341f9 858
1da177e4
LT		 859 do {
860 if (fifo_count == 1) {
861 read_count = 1;
862 data[0] = read_reg(info, CHA + RXFIFO);
863 } else {
864 read_count = 2;
865 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
866 }
867 fifo_count -= read_count;
868 if (!fifo_count && eom)
869 buf->status = data[--read_count];
870
871 for (i = 0; i < read_count; i++) {
872 if (buf->count >= info->max_frame_size) {
873 /* frame too large, reset receiver and reset current buffer */
874 issue_command(info, CHA, CMD_RXRESET);
875 buf->count = 0;
876 return;
877 }
878 *(buf->data + buf->count) = data[i];
879 buf->count++;
880 }
881 } while (fifo_count);
882
883 if (eom) {
884 info->pending_bh |= BH_RECEIVE;
885 info->rx_frame_count++;
886 info->rx_put++;
887 if (info->rx_put >= info->rx_buf_count)
888 info->rx_put = 0;
889 }
890 issue_command(info, CHA, CMD_RXFIFO);
891}
892
2e124b4a 893static void rx_ready_async(MGSLPC_INFO *info, int tcd)
1da177e4 894{
227434f8 895 struct tty_port *port = &info->port;
33f0f88f 896 unsigned char data, status, flag;
1da177e4 897 int fifo_count;
33f0f88f 898 int work = 0;
3d553993 899 struct mgsl_icount *icount = &info->icount;
1da177e4
LT		 900
901 if (tcd) {
d12341f9 902 /* early termination, get FIFO count from RBCL register */
1da177e4
LT		 903 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
904
905 /* Zero fifo count could mean 0 or 32 bytes available.
906 * If BIT5 of STAR is set then at least 1 byte is available.
907 */
908 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
909 fifo_count = 32;
910 } else
911 fifo_count = 32;
33f0f88f 912
227434f8 913 tty_buffer_request_room(port, fifo_count);
d12341f9 914 /* Flush received async data to receive data buffer. */
1da177e4
LT		 915 while (fifo_count) {
916 data = read_reg(info, CHA + RXFIFO);
917 status = read_reg(info, CHA + RXFIFO);
918 fifo_count -= 2;
919
1da177e4 920 icount->rx++;
33f0f88f 921 flag = TTY_NORMAL;
1da177e4
LT		 922
923 // if no frameing/crc error then save data
924 // BIT7:parity error
925 // BIT6:framing error
926
927 if (status & (BIT7 + BIT6)) {
d12341f9 928 if (status & BIT7)
1da177e4
LT		 929 icount->parity++;
930 else
931 icount->frame++;
932
933 /* discard char if tty control flags say so */
934 if (status & info->ignore_status_mask)
935 continue;
d12341f9 936
1da177e4
LT		 937 status &= info->read_status_mask;
938
939 if (status & BIT7)
33f0f88f 940 flag = TTY_PARITY;
1da177e4 941 else if (status & BIT6)
33f0f88f 942 flag = TTY_FRAME;
1da177e4 943 }
92a19f9c 944 work += tty_insert_flip_char(port, data, flag);
1da177e4
LT		 945 }
946 issue_command(info, CHA, CMD_RXFIFO);
947
948 if (debug_level >= DEBUG_LEVEL_ISR) {
33f0f88f
AC		 949 printk("%s(%d):rx_ready_async",
950 __FILE__,__LINE__);
1da177e4
LT		 951 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
952 __FILE__,__LINE__,icount->rx,icount->brk,
953 icount->parity,icount->frame,icount->overrun);
954 }
d12341f9 955
33f0f88f 956 if (work)
2e124b4a 957 tty_flip_buffer_push(port);
1da177e4
LT		 958}
959
960
eeb46134 961static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 962{
963 if (!info->tx_active)
964 return;
d12341f9 965
0fab6de0
JP		 966 info->tx_active = false;
967 info->tx_aborting = false;
1da177e4
LT		 968
969 if (info->params.mode == MGSL_MODE_ASYNC)
970 return;
971
972 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9
JG		 973 del_timer(&info->tx_timer);
974
1da177e4
LT		 975 if (info->drop_rts_on_tx_done) {
976 get_signals(info);
977 if (info->serial_signals & SerialSignal_RTS) {
978 info->serial_signals &= ~SerialSignal_RTS;
979 set_signals(info);
980 }
0fab6de0 981 info->drop_rts_on_tx_done = false;
1da177e4
LT		 982 }
983
af69c7f9 984#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 985 if (info->netcount)
986 hdlcdev_tx_done(info);
d12341f9 987 else
1da177e4
LT		 988#endif
989 {
221b7b57 990 if (tty && (tty->stopped || tty->hw_stopped)) {
1da177e4
LT		 991 tx_stop(info);
992 return;
993 }
994 info->pending_bh |= BH_TRANSMIT;
995 }
996}
997
eeb46134 998static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 999{
1000 unsigned char fifo_count = 32;
1001 int c;
1002
1003 if (debug_level >= DEBUG_LEVEL_ISR)
3d553993 1004 printk("%s(%d):tx_ready(%s)\n", __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1005
1006 if (info->params.mode == MGSL_MODE_HDLC) {
1007 if (!info->tx_active)
1008 return;
1009 } else {
221b7b57 1010 if (tty && (tty->stopped || tty->hw_stopped)) {
1da177e4
LT		 1011 tx_stop(info);
1012 return;
1013 }
1014 if (!info->tx_count)
0fab6de0 1015 info->tx_active = false;
1da177e4
LT		 1016 }
1017
1018 if (!info->tx_count)
1019 return;
1020
1021 while (info->tx_count && fifo_count) {
1022 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
d12341f9 1023
1da177e4
LT		 1024 if (c == 1) {
1025 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
1026 } else {
1027 write_reg16(info, CHA + TXFIFO,
1028 *((unsigned short*)(info->tx_buf + info->tx_get)));
1029 }
1030 info->tx_count -= c;
1031 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
1032 fifo_count -= c;
1033 }
1034
1035 if (info->params.mode == MGSL_MODE_ASYNC) {
1036 if (info->tx_count < WAKEUP_CHARS)
1037 info->pending_bh |= BH_TRANSMIT;
1038 issue_command(info, CHA, CMD_TXFIFO);
1039 } else {
1040 if (info->tx_count)
1041 issue_command(info, CHA, CMD_TXFIFO);
1042 else
1043 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
1044 }
1045}
1046
eeb46134 1047static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1048{
1049 get_signals(info);
1050 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1051 irq_disable(info, CHB, IRQ_CTS);
1052 info->icount.cts++;
1053 if (info->serial_signals & SerialSignal_CTS)
1054 info->input_signal_events.cts_up++;
1055 else
1056 info->input_signal_events.cts_down++;
1057 wake_up_interruptible(&info->status_event_wait_q);
1058 wake_up_interruptible(&info->event_wait_q);
1059
3498d13b 1060 if (tty && tty_port_cts_enabled(&info->port)) {
eeb46134 1061 if (tty->hw_stopped) {
1da177e4
LT		 1062 if (info->serial_signals & SerialSignal_CTS) {
1063 if (debug_level >= DEBUG_LEVEL_ISR)
1064 printk("CTS tx start...");
221b7b57 1065 tty->hw_stopped = 0;
eeb46134 1066 tx_start(info, tty);
1da177e4
LT		 1067 info->pending_bh |= BH_TRANSMIT;
1068 return;
1069 }
1070 } else {
1071 if (!(info->serial_signals & SerialSignal_CTS)) {
1072 if (debug_level >= DEBUG_LEVEL_ISR)
1073 printk("CTS tx stop...");
221b7b57 1074 tty->hw_stopped = 1;
1da177e4
LT		 1075 tx_stop(info);
1076 }
1077 }
1078 }
1079 info->pending_bh |= BH_STATUS;
1080}
1081
eeb46134 1082static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1083{
1084 get_signals(info);
1085 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1086 irq_disable(info, CHB, IRQ_DCD);
1087 info->icount.dcd++;
1088 if (info->serial_signals & SerialSignal_DCD) {
1089 info->input_signal_events.dcd_up++;
1090 }
1091 else
1092 info->input_signal_events.dcd_down++;
af69c7f9 1093#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1094 if (info->netcount) {
1095 if (info->serial_signals & SerialSignal_DCD)
1096 netif_carrier_on(info->netdev);
1097 else
1098 netif_carrier_off(info->netdev);
1099 }
1da177e4
LT		 1100#endif
1101 wake_up_interruptible(&info->status_event_wait_q);
1102 wake_up_interruptible(&info->event_wait_q);
1103
2d68655d 1104 if (tty_port_check_carrier(&info->port)) {
1da177e4
LT		 1105 if (debug_level >= DEBUG_LEVEL_ISR)
1106 printk("%s CD now %s...", info->device_name,
1107 (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
1108 if (info->serial_signals & SerialSignal_DCD)
eeb46134 1109 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1110 else {
1111 if (debug_level >= DEBUG_LEVEL_ISR)
1112 printk("doing serial hangup...");
eeb46134
AC		 1113 if (tty)
1114 tty_hangup(tty);
1da177e4
LT		 1115 }
1116 }
1117 info->pending_bh |= BH_STATUS;
1118}
1119
1120static void dsr_change(MGSLPC_INFO *info)
1121{
1122 get_signals(info);
1123 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1124 port_irq_disable(info, PVR_DSR);
1125 info->icount.dsr++;
1126 if (info->serial_signals & SerialSignal_DSR)
1127 info->input_signal_events.dsr_up++;
1128 else
1129 info->input_signal_events.dsr_down++;
1130 wake_up_interruptible(&info->status_event_wait_q);
1131 wake_up_interruptible(&info->event_wait_q);
1132 info->pending_bh |= BH_STATUS;
1133}
1134
1135static void ri_change(MGSLPC_INFO *info)
1136{
1137 get_signals(info);
1138 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1139 port_irq_disable(info, PVR_RI);
1140 info->icount.rng++;
1141 if (info->serial_signals & SerialSignal_RI)
1142 info->input_signal_events.ri_up++;
1143 else
1144 info->input_signal_events.ri_down++;
1145 wake_up_interruptible(&info->status_event_wait_q);
1146 wake_up_interruptible(&info->event_wait_q);
1147 info->pending_bh |= BH_STATUS;
1148}
1149
1150/* Interrupt service routine entry point.
d12341f9 1151 *
1da177e4 1152 * Arguments:
d12341f9 1153 *
1da177e4
LT		 1154 * irq interrupt number that caused interrupt
1155 * dev_id device ID supplied during interrupt registration
1da177e4 1156 */
a6f97b29 1157static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
1da177e4 1158{
a6f97b29 1159 MGSLPC_INFO *info = dev_id;
eeb46134 1160 struct tty_struct *tty;
1da177e4
LT		 1161 unsigned short isr;
1162 unsigned char gis, pis;
1163 int count=0;
1164
d12341f9 1165 if (debug_level >= DEBUG_LEVEL_ISR)
a6f97b29 1166 printk("mgslpc_isr(%d) entry.\n", info->irq_level);
d12341f9 1167
e2d40963 1168 if (!(info->p_dev->_locked))
1da177e4
LT		 1169 return IRQ_HANDLED;
1170
eeb46134
AC		 1171 tty = tty_port_tty_get(&info->port);
1172
1da177e4
LT		 1173 spin_lock(&info->lock);
1174
1175 while ((gis = read_reg(info, CHA + GIS))) {
d12341f9 1176 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4
LT		 1177 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
1178
1179 if ((gis & 0x70) || count > 1000) {
1180 printk("synclink_cs:hardware failed or ejected\n");
1181 break;
1182 }
1183 count++;
1184
ecda040f 1185 if (gis & (BIT1 | BIT0)) {
1da177e4
LT		 1186 isr = read_reg16(info, CHB + ISR);
1187 if (isr & IRQ_DCD)
eeb46134 1188 dcd_change(info, tty);
1da177e4 1189 if (isr & IRQ_CTS)
eeb46134 1190 cts_change(info, tty);
1da177e4 1191 }
ecda040f 1192 if (gis & (BIT3 | BIT2))
1da177e4
LT		 1193 {
1194 isr = read_reg16(info, CHA + ISR);
1195 if (isr & IRQ_TIMER) {
0fab6de0 1196 info->irq_occurred = true;
1da177e4
LT		 1197 irq_disable(info, CHA, IRQ_TIMER);
1198 }
1199
d12341f9 1200 /* receive IRQs */
1da177e4
LT		 1201 if (isr & IRQ_EXITHUNT) {
1202 info->icount.exithunt++;
1203 wake_up_interruptible(&info->event_wait_q);
1204 }
1205 if (isr & IRQ_BREAK_ON) {
1206 info->icount.brk++;
eeb46134
AC		 1207 if (info->port.flags & ASYNC_SAK)
1208 do_SAK(tty);
1da177e4
LT		 1209 }
1210 if (isr & IRQ_RXTIME) {
1211 issue_command(info, CHA, CMD_RXFIFO_READ);
1212 }
ecda040f 1213 if (isr & (IRQ_RXEOM | IRQ_RXFIFO)) {
1da177e4 1214 if (info->params.mode == MGSL_MODE_HDLC)
d12341f9 1215 rx_ready_hdlc(info, isr & IRQ_RXEOM);
1da177e4 1216 else
2e124b4a 1217 rx_ready_async(info, isr & IRQ_RXEOM);
1da177e4
LT		 1218 }
1219
d12341f9 1220 /* transmit IRQs */
1da177e4
LT		 1221 if (isr & IRQ_UNDERRUN) {
1222 if (info->tx_aborting)
1223 info->icount.txabort++;
1224 else
1225 info->icount.txunder++;
eeb46134 1226 tx_done(info, tty);
1da177e4
LT		 1227 }
1228 else if (isr & IRQ_ALLSENT) {
1229 info->icount.txok++;
eeb46134 1230 tx_done(info, tty);
1da177e4
LT		 1231 }
1232 else if (isr & IRQ_TXFIFO)
eeb46134 1233 tx_ready(info, tty);
1da177e4
LT		 1234 }
1235 if (gis & BIT7) {
1236 pis = read_reg(info, CHA + PIS);
1237 if (pis & BIT1)
1238 dsr_change(info);
1239 if (pis & BIT2)
1240 ri_change(info);
1241 }
1242 }
d12341f9
JG		 1243
1244 /* Request bottom half processing if there's something
1da177e4
LT		 1245 * for it to do and the bh is not already running
1246 */
1247
1248 if (info->pending_bh && !info->bh_running && !info->bh_requested) {
3d553993 1249 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4
LT		 1250 printk("%s(%d):%s queueing bh task.\n",
1251 __FILE__,__LINE__,info->device_name);
1252 schedule_work(&info->task);
0fab6de0 1253 info->bh_requested = true;
1da177e4
LT		 1254 }
1255
1256 spin_unlock(&info->lock);
eeb46134 1257 tty_kref_put(tty);
d12341f9
JG		 1258
1259 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4 1260 printk("%s(%d):mgslpc_isr(%d)exit.\n",
a6f97b29 1261 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 1262
1263 return IRQ_HANDLED;
1264}
1265
1266/* Initialize and start device.
1267 */
eeb46134 1268static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1269{
1270 int retval = 0;
d12341f9 1271
1da177e4 1272 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 1273 printk("%s(%d):startup(%s)\n", __FILE__, __LINE__, info->device_name);
d12341f9 1274
d41861ca 1275 if (tty_port_initialized(&info->port))
1da177e4 1276 return 0;
d12341f9 1277
1da177e4
LT		 1278 if (!info->tx_buf) {
1279 /* allocate a page of memory for a transmit buffer */
1280 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1281 if (!info->tx_buf) {
1282 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
3d553993 1283 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1284 return -ENOMEM;
1285 }
1286 }
1287
1288 info->pending_bh = 0;
d12341f9 1289
a7482a2e
PF		 1290 memset(&info->icount, 0, sizeof(info->icount));
1291
40565f19 1292 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
1da177e4
LT		 1293
1294 /* Allocate and claim adapter resources */
1295 retval = claim_resources(info);
d12341f9 1296
25985edc 1297 /* perform existence check and diagnostics */
3d553993 1298 if (!retval)
1da177e4 1299 retval = adapter_test(info);
d12341f9 1300
3d553993
AK		 1301 if (retval) {
1302 if (capable(CAP_SYS_ADMIN) && tty)
eeb46134 1303 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1304 release_resources(info);
3d553993
AK		 1305 return retval;
1306 }
1da177e4
LT		 1307
1308 /* program hardware for current parameters */
eeb46134 1309 mgslpc_change_params(info, tty);
d12341f9 1310
eeb46134
AC		 1311 if (tty)
1312 clear_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1313
d41861ca 1314 tty_port_set_initialized(&info->port, 1);
d12341f9 1315
1da177e4
LT		 1316 return 0;
1317}
1318
1319/* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
1320 */
eeb46134 1321static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1322{
1323 unsigned long flags;
d12341f9 1324
d41861ca 1325 if (!tty_port_initialized(&info->port))
1da177e4
LT		 1326 return;
1327
1328 if (debug_level >= DEBUG_LEVEL_INFO)
1329 printk("%s(%d):mgslpc_shutdown(%s)\n",
3d553993 1330 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1331
1332 /* clear status wait queue because status changes */
1333 /* can't happen after shutting down the hardware */
1334 wake_up_interruptible(&info->status_event_wait_q);
1335 wake_up_interruptible(&info->event_wait_q);
1336
40565f19 1337 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1338
1339 if (info->tx_buf) {
1340 free_page((unsigned long) info->tx_buf);
1341 info->tx_buf = NULL;
1342 }
1343
3d553993 1344 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1345
1346 rx_stop(info);
1347 tx_stop(info);
1348
1349 /* TODO:disable interrupts instead of reset to preserve signal states */
1350 reset_device(info);
d12341f9 1351
9db276f8 1352 if (!tty || C_HUPCL(tty)) {
9fe8074b 1353 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 1354 set_signals(info);
1355 }
d12341f9 1356
3d553993 1357 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 1358
d12341f9
JG		 1359 release_resources(info);
1360
eeb46134
AC		 1361 if (tty)
1362 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1363
d41861ca 1364 tty_port_set_initialized(&info->port, 0);
1da177e4
LT		 1365}
1366
eeb46134 1367static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1368{
1369 unsigned long flags;
1370
3d553993 1371 spin_lock_irqsave(&info->lock, flags);
d12341f9 1372
1da177e4
LT		 1373 rx_stop(info);
1374 tx_stop(info);
1375 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1376
1da177e4
LT		 1377 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1378 hdlc_mode(info);
1379 else
1380 async_mode(info);
d12341f9 1381
1da177e4 1382 set_signals(info);
d12341f9 1383
1da177e4
LT		 1384 info->dcd_chkcount = 0;
1385 info->cts_chkcount = 0;
1386 info->ri_chkcount = 0;
1387 info->dsr_chkcount = 0;
1388
1389 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
1390 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
1391 get_signals(info);
d12341f9 1392
9db276f8 1393 if (info->netcount || (tty && C_CREAD(tty)))
1da177e4 1394 rx_start(info);
d12341f9 1395
3d553993 1396 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1397}
1398
1399/* Reconfigure adapter based on new parameters
1400 */
eeb46134 1401static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1402{
1403 unsigned cflag;
1404 int bits_per_char;
1405
373f5aed 1406 if (!tty)
1da177e4 1407 return;
d12341f9 1408
1da177e4
LT		 1409 if (debug_level >= DEBUG_LEVEL_INFO)
1410 printk("%s(%d):mgslpc_change_params(%s)\n",
3d553993 1411 __FILE__, __LINE__, info->device_name);
d12341f9 1412
373f5aed 1413 cflag = tty->termios.c_cflag;
1da177e4 1414
9fe8074b
JP		 1415 /* if B0 rate (hangup) specified then negate RTS and DTR */
1416 /* otherwise assert RTS and DTR */
3d553993 1417 if (cflag & CBAUD)
9fe8074b 1418 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1da177e4 1419 else
9fe8074b 1420 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
d12341f9 1421
1da177e4 1422 /* byte size and parity */
d12341f9 1423
1da177e4
LT		 1424 switch (cflag & CSIZE) {
1425 case CS5: info->params.data_bits = 5; break;
1426 case CS6: info->params.data_bits = 6; break;
1427 case CS7: info->params.data_bits = 7; break;
1428 case CS8: info->params.data_bits = 8; break;
1429 default: info->params.data_bits = 7; break;
1430 }
d12341f9 1431
1da177e4
LT		 1432 if (cflag & CSTOPB)
1433 info->params.stop_bits = 2;
1434 else
1435 info->params.stop_bits = 1;
1436
1437 info->params.parity = ASYNC_PARITY_NONE;
1438 if (cflag & PARENB) {
1439 if (cflag & PARODD)
1440 info->params.parity = ASYNC_PARITY_ODD;
1441 else
1442 info->params.parity = ASYNC_PARITY_EVEN;
1443#ifdef CMSPAR
1444 if (cflag & CMSPAR)
1445 info->params.parity = ASYNC_PARITY_SPACE;
1446#endif
1447 }
1448
1449 /* calculate number of jiffies to transmit a full
1450 * FIFO (32 bytes) at specified data rate
1451 */
d12341f9 1452 bits_per_char = info->params.data_bits +
1da177e4
LT		 1453 info->params.stop_bits + 1;
1454
1455 /* if port data rate is set to 460800 or less then
1456 * allow tty settings to override, otherwise keep the
1457 * current data rate.
1458 */
1459 if (info->params.data_rate <= 460800) {
eeb46134 1460 info->params.data_rate = tty_get_baud_rate(tty);
1da177e4 1461 }
d12341f9 1462
3d553993 1463 if (info->params.data_rate) {
d12341f9 1464 info->timeout = (32*HZ*bits_per_char) /
1da177e4
LT		 1465 info->params.data_rate;
1466 }
1467 info->timeout += HZ/50; /* Add .02 seconds of slop */
1468
5604a98e 1469 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2d68655d 1470 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
1da177e4
LT		 1471
1472 /* process tty input control flags */
d12341f9 1473
1da177e4 1474 info->read_status_mask = 0;
eeb46134 1475 if (I_INPCK(tty))
1da177e4 1476 info->read_status_mask |= BIT7 | BIT6;
eeb46134 1477 if (I_IGNPAR(tty))
1da177e4
LT		 1478 info->ignore_status_mask |= BIT7 | BIT6;
1479
eeb46134 1480 mgslpc_program_hw(info, tty);
1da177e4
LT		 1481}
1482
1483/* Add a character to the transmit buffer
1484 */
d7e752e2 1485static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4
LT		 1486{
1487 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1488 unsigned long flags;
1489
1490 if (debug_level >= DEBUG_LEVEL_INFO) {
3d553993
AK		 1491 printk("%s(%d):mgslpc_put_char(%d) on %s\n",
1492 __FILE__, __LINE__, ch, info->device_name);
1da177e4
LT		 1493 }
1494
1495 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
d7e752e2 1496 return 0;
1da177e4 1497
326f28e9 1498 if (!info->tx_buf)
d7e752e2 1499 return 0;
1da177e4 1500
3d553993 1501 spin_lock_irqsave(&info->lock, flags);
d12341f9 1502
1da177e4
LT		 1503 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
1504 if (info->tx_count < TXBUFSIZE - 1) {
1505 info->tx_buf[info->tx_put++] = ch;
1506 info->tx_put &= TXBUFSIZE-1;
1507 info->tx_count++;
1508 }
1509 }
d12341f9 1510
3d553993 1511 spin_unlock_irqrestore(&info->lock, flags);
d7e752e2 1512 return 1;
1da177e4
LT		 1513}
1514
1515/* Enable transmitter so remaining characters in the
1516 * transmit buffer are sent.
1517 */
1518static void mgslpc_flush_chars(struct tty_struct *tty)
1519{
1520 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1521 unsigned long flags;
d12341f9 1522
1da177e4 1523 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 1524 printk("%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
1525 __FILE__, __LINE__, info->device_name, info->tx_count);
d12341f9 1526
1da177e4
LT		 1527 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
1528 return;
1529
1530 if (info->tx_count <= 0 || tty->stopped ||
1531 tty->hw_stopped || !info->tx_buf)
1532 return;
1533
1534 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 1535 printk("%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
1536 __FILE__, __LINE__, info->device_name);
1da177e4 1537
3d553993 1538 spin_lock_irqsave(&info->lock, flags);
1da177e4 1539 if (!info->tx_active)
3d553993
AK		 1540 tx_start(info, tty);
1541 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1542}
1543
1544/* Send a block of data
d12341f9 1545 *
1da177e4 1546 * Arguments:
d12341f9 1547 *
1da177e4
LT		 1548 * tty pointer to tty information structure
1549 * buf pointer to buffer containing send data
1550 * count size of send data in bytes
d12341f9 1551 *
1da177e4
LT		 1552 * Returns: number of characters written
1553 */
1554static int mgslpc_write(struct tty_struct * tty,
1555 const unsigned char *buf, int count)
1556{
1557 int c, ret = 0;
1558 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1559 unsigned long flags;
d12341f9 1560
1da177e4 1561 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 1562 printk("%s(%d):mgslpc_write(%s) count=%d\n",
1563 __FILE__, __LINE__, info->device_name, count);
d12341f9 1564
1da177e4 1565 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
326f28e9 1566 !info->tx_buf)
1da177e4
LT		 1567 goto cleanup;
1568
1569 if (info->params.mode == MGSL_MODE_HDLC) {
1570 if (count > TXBUFSIZE) {
1571 ret = -EIO;
1572 goto cleanup;
1573 }
1574 if (info->tx_active)
1575 goto cleanup;
1576 else if (info->tx_count)
1577 goto start;
1578 }
1579
1580 for (;;) {
1581 c = min(count,
1582 min(TXBUFSIZE - info->tx_count - 1,
1583 TXBUFSIZE - info->tx_put));
1584 if (c <= 0)
1585 break;
d12341f9 1586
1da177e4
LT		 1587 memcpy(info->tx_buf + info->tx_put, buf, c);
1588
3d553993 1589 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1590 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
1591 info->tx_count += c;
3d553993 1592 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1593
1594 buf += c;
1595 count -= c;
1596 ret += c;
1597 }
1598start:
3d553993
AK		 1599 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1600 spin_lock_irqsave(&info->lock, flags);
1da177e4 1601 if (!info->tx_active)
3d553993
AK		 1602 tx_start(info, tty);
1603 spin_unlock_irqrestore(&info->lock, flags);
1604 }
d12341f9 1605cleanup:
1da177e4 1606 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 1607 printk("%s(%d):mgslpc_write(%s) returning=%d\n",
1608 __FILE__, __LINE__, info->device_name, ret);
1da177e4
LT		 1609 return ret;
1610}
1611
1612/* Return the count of free bytes in transmit buffer
1613 */
1614static int mgslpc_write_room(struct tty_struct *tty)
1615{
1616 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1617 int ret;
d12341f9 1618
1da177e4
LT		 1619 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
1620 return 0;
1621
1622 if (info->params.mode == MGSL_MODE_HDLC) {
1623 /* HDLC (frame oriented) mode */
1624 if (info->tx_active)
1625 return 0;
1626 else
1627 return HDLC_MAX_FRAME_SIZE;
1628 } else {
1629 ret = TXBUFSIZE - info->tx_count - 1;
1630 if (ret < 0)
1631 ret = 0;
1632 }
d12341f9 1633
1da177e4
LT		 1634 if (debug_level >= DEBUG_LEVEL_INFO)
1635 printk("%s(%d):mgslpc_write_room(%s)=%d\n",
3d553993 1636 __FILE__, __LINE__, info->device_name, ret);
1da177e4
LT		 1637 return ret;
1638}
1639
1640/* Return the count of bytes in transmit buffer
1641 */
1642static int mgslpc_chars_in_buffer(struct tty_struct *tty)
1643{
1644 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1645 int rc;
d12341f9 1646
1da177e4
LT		 1647 if (debug_level >= DEBUG_LEVEL_INFO)
1648 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
3d553993 1649 __FILE__, __LINE__, info->device_name);
d12341f9 1650
1da177e4
LT		 1651 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
1652 return 0;
d12341f9 1653
1da177e4
LT		 1654 if (info->params.mode == MGSL_MODE_HDLC)
1655 rc = info->tx_active ? info->max_frame_size : 0;
1656 else
1657 rc = info->tx_count;
1658
1659 if (debug_level >= DEBUG_LEVEL_INFO)
1660 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
3d553993 1661 __FILE__, __LINE__, info->device_name, rc);
d12341f9 1662
1da177e4
LT		 1663 return rc;
1664}
1665
1666/* Discard all data in the send buffer
1667 */
1668static void mgslpc_flush_buffer(struct tty_struct *tty)
1669{
1670 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1671 unsigned long flags;
d12341f9 1672
1da177e4
LT		 1673 if (debug_level >= DEBUG_LEVEL_INFO)
1674 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
3d553993 1675 __FILE__, __LINE__, info->device_name);
d12341f9 1676
1da177e4
LT		 1677 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
1678 return;
d12341f9 1679
3d553993 1680 spin_lock_irqsave(&info->lock, flags);
1da177e4 1681 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1682 del_timer(&info->tx_timer);
3d553993 1683 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1684
1685 wake_up_interruptible(&tty->write_wait);
1686 tty_wakeup(tty);
1687}
1688
1689/* Send a high-priority XON/XOFF character
1690 */
1691static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
1692{
1693 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1694 unsigned long flags;
1695
1696 if (debug_level >= DEBUG_LEVEL_INFO)
1697 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
3d553993 1698 __FILE__, __LINE__, info->device_name, ch);
d12341f9 1699
1da177e4
LT		 1700 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
1701 return;
1702
1703 info->x_char = ch;
1704 if (ch) {
3d553993 1705 spin_lock_irqsave(&info->lock, flags);
1da177e4 1706 if (!info->tx_enabled)
3d553993
AK		 1707 tx_start(info, tty);
1708 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1709 }
1710}
1711
1712/* Signal remote device to throttle send data (our receive data)
1713 */
1714static void mgslpc_throttle(struct tty_struct * tty)
1715{
1716 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1717 unsigned long flags;
d12341f9 1718
1da177e4
LT		 1719 if (debug_level >= DEBUG_LEVEL_INFO)
1720 printk("%s(%d):mgslpc_throttle(%s) entry\n",
3d553993 1721 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1722
1723 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
1724 return;
d12341f9 1725
1da177e4
LT		 1726 if (I_IXOFF(tty))
1727 mgslpc_send_xchar(tty, STOP_CHAR(tty));
d12341f9 1728
9db276f8 1729 if (C_CRTSCTS(tty)) {
3d553993 1730 spin_lock_irqsave(&info->lock, flags);
1da177e4 1731 info->serial_signals &= ~SerialSignal_RTS;
3d553993
AK		 1732 set_signals(info);
1733 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1734 }
1735}
1736
1737/* Signal remote device to stop throttling send data (our receive data)
1738 */
1739static void mgslpc_unthrottle(struct tty_struct * tty)
1740{
1741 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1742 unsigned long flags;
d12341f9 1743
1da177e4
LT		 1744 if (debug_level >= DEBUG_LEVEL_INFO)
1745 printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
3d553993 1746 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1747
1748 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
1749 return;
d12341f9 1750
1da177e4
LT		 1751 if (I_IXOFF(tty)) {
1752 if (info->x_char)
1753 info->x_char = 0;
1754 else
1755 mgslpc_send_xchar(tty, START_CHAR(tty));
1756 }
d12341f9 1757
9db276f8 1758 if (C_CRTSCTS(tty)) {
3d553993 1759 spin_lock_irqsave(&info->lock, flags);
1da177e4 1760 info->serial_signals |= SerialSignal_RTS;
3d553993
AK		 1761 set_signals(info);
1762 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1763 }
1764}
1765
1766/* get the current serial statistics
1767 */
1768static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
1769{
1770 int err;
1771 if (debug_level >= DEBUG_LEVEL_INFO)
1772 printk("get_params(%s)\n", info->device_name);
a7482a2e
PF		 1773 if (!user_icount) {
1774 memset(&info->icount, 0, sizeof(info->icount));
1775 } else {
1776 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
1777 if (err)
1778 return -EFAULT;
1779 }
1da177e4
LT		 1780 return 0;
1781}
1782
1783/* get the current serial parameters
1784 */
1785static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
1786{
1787 int err;
1788 if (debug_level >= DEBUG_LEVEL_INFO)
1789 printk("get_params(%s)\n", info->device_name);
1790 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
1791 if (err)
1792 return -EFAULT;
1793 return 0;
1794}
1795
1796/* set the serial parameters
d12341f9 1797 *
1da177e4 1798 * Arguments:
d12341f9 1799 *
3d553993
AK		 1800 * info pointer to device instance data
1801 * new_params user buffer containing new serial params
1da177e4
LT		 1802 *
1803 * Returns: 0 if success, otherwise error code
1804 */
eeb46134 1805static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
1da177e4 1806{
3d553993 1807 unsigned long flags;
1da177e4
LT		 1808 MGSL_PARAMS tmp_params;
1809 int err;
d12341f9 1810
1da177e4
LT		 1811 if (debug_level >= DEBUG_LEVEL_INFO)
1812 printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
3d553993 1813 info->device_name);
1da177e4
LT		 1814 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
1815 if (err) {
3d553993
AK		 1816 if (debug_level >= DEBUG_LEVEL_INFO)
1817 printk("%s(%d):set_params(%s) user buffer copy failed\n",
1818 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1819 return -EFAULT;
1820 }
d12341f9 1821
3d553993 1822 spin_lock_irqsave(&info->lock, flags);
1da177e4 1823 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3d553993 1824 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 1825
3d553993 1826 mgslpc_change_params(info, tty);
d12341f9 1827
1da177e4
LT		 1828 return 0;
1829}
1830
1831static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
1832{
1833 int err;
1834 if (debug_level >= DEBUG_LEVEL_INFO)
1835 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
1836 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
1837 if (err)
1838 return -EFAULT;
1839 return 0;
1840}
1841
1842static int set_txidle(MGSLPC_INFO * info, int idle_mode)
1843{
3d553993 1844 unsigned long flags;
1da177e4
LT		 1845 if (debug_level >= DEBUG_LEVEL_INFO)
1846 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
3d553993 1847 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1848 info->idle_mode = idle_mode;
1849 tx_set_idle(info);
3d553993 1850 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1851 return 0;
1852}
1853
1854static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
1855{
1856 int err;
1857 if (debug_level >= DEBUG_LEVEL_INFO)
1858 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
1859 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
1860 if (err)
1861 return -EFAULT;
1862 return 0;
1863}
1864
1865static int set_interface(MGSLPC_INFO * info, int if_mode)
1866{
3d553993 1867 unsigned long flags;
1da177e4
LT		 1868 unsigned char val;
1869 if (debug_level >= DEBUG_LEVEL_INFO)
1870 printk("set_interface(%s,%d)\n", info->device_name, if_mode);
3d553993 1871 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1872 info->if_mode = if_mode;
1873
1874 val = read_reg(info, PVR) & 0x0f;
1875 switch (info->if_mode)
1876 {
1877 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
1878 case MGSL_INTERFACE_V35: val |= PVR_V35; break;
1879 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
1880 }
1881 write_reg(info, PVR, val);
1882
3d553993 1883 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1884 return 0;
1885}
1886
eeb46134 1887static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
1da177e4 1888{
3d553993 1889 unsigned long flags;
d12341f9 1890
1da177e4
LT		 1891 if (debug_level >= DEBUG_LEVEL_INFO)
1892 printk("set_txenable(%s,%d)\n", info->device_name, enable);
d12341f9 1893
3d553993 1894 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1895 if (enable) {
1896 if (!info->tx_enabled)
eeb46134 1897 tx_start(info, tty);
1da177e4
LT		 1898 } else {
1899 if (info->tx_enabled)
1900 tx_stop(info);
1901 }
3d553993 1902 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1903 return 0;
1904}
1905
1906static int tx_abort(MGSLPC_INFO * info)
1907{
3d553993 1908 unsigned long flags;
d12341f9 1909
1da177e4
LT		 1910 if (debug_level >= DEBUG_LEVEL_INFO)
1911 printk("tx_abort(%s)\n", info->device_name);
d12341f9 1912
3d553993 1913 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1914 if (info->tx_active && info->tx_count &&
1915 info->params.mode == MGSL_MODE_HDLC) {
1916 /* clear data count so FIFO is not filled on next IRQ.
1917 * This results in underrun and abort transmission.
1918 */
1919 info->tx_count = info->tx_put = info->tx_get = 0;
0fab6de0 1920 info->tx_aborting = true;
1da177e4 1921 }
3d553993 1922 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1923 return 0;
1924}
1925
1926static int set_rxenable(MGSLPC_INFO * info, int enable)
1927{
3d553993 1928 unsigned long flags;
d12341f9 1929
1da177e4
LT		 1930 if (debug_level >= DEBUG_LEVEL_INFO)
1931 printk("set_rxenable(%s,%d)\n", info->device_name, enable);
d12341f9 1932
3d553993 1933 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1934 if (enable) {
1935 if (!info->rx_enabled)
1936 rx_start(info);
1937 } else {
1938 if (info->rx_enabled)
1939 rx_stop(info);
1940 }
3d553993 1941 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1942 return 0;
1943}
1944
1945/* wait for specified event to occur
d12341f9 1946 *
3d553993
AK		 1947 * Arguments: info pointer to device instance data
1948 * mask pointer to bitmask of events to wait for
1949 * Return Value: 0 if successful and bit mask updated with
1da177e4 1950 * of events triggerred,
3d553993 1951 * otherwise error code
1da177e4
LT		 1952 */
1953static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
1954{
3d553993 1955 unsigned long flags;
1da177e4
LT		 1956 int s;
1957 int rc=0;
1958 struct mgsl_icount cprev, cnow;
1959 int events;
1960 int mask;
1961 struct _input_signal_events oldsigs, newsigs;
1962 DECLARE_WAITQUEUE(wait, current);
1963
1964 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
1965 if (rc)
1966 return -EFAULT;
d12341f9 1967
1da177e4
LT		 1968 if (debug_level >= DEBUG_LEVEL_INFO)
1969 printk("wait_events(%s,%d)\n", info->device_name, mask);
1970
3d553993 1971 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1972
1973 /* return immediately if state matches requested events */
1974 get_signals(info);
1975 s = info->serial_signals;
1976 events = mask &
1977 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3d553993 1978 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
1da177e4
LT		 1979 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
1980 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
1981 if (events) {
3d553993 1982 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1983 goto exit;
1984 }
1985
1986 /* save current irq counts */
1987 cprev = info->icount;
1988 oldsigs = info->input_signal_events;
d12341f9 1989
1da177e4
LT		 1990 if ((info->params.mode == MGSL_MODE_HDLC) &&
1991 (mask & MgslEvent_ExitHuntMode))
1992 irq_enable(info, CHA, IRQ_EXITHUNT);
d12341f9 1993
1da177e4
LT		 1994 set_current_state(TASK_INTERRUPTIBLE);
1995 add_wait_queue(&info->event_wait_q, &wait);
d12341f9 1996
3d553993 1997 spin_unlock_irqrestore(&info->lock, flags);
d12341f9
JG		 1998
1999
1da177e4
LT		 2000 for(;;) {
2001 schedule();
2002 if (signal_pending(current)) {
2003 rc = -ERESTARTSYS;
2004 break;
2005 }
d12341f9 2006
1da177e4 2007 /* get current irq counts */
3d553993 2008 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 2009 cnow = info->icount;
2010 newsigs = info->input_signal_events;
2011 set_current_state(TASK_INTERRUPTIBLE);
3d553993 2012 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2013
2014 /* if no change, wait aborted for some reason */
2015 if (newsigs.dsr_up == oldsigs.dsr_up &&
2016 newsigs.dsr_down == oldsigs.dsr_down &&
2017 newsigs.dcd_up == oldsigs.dcd_up &&
2018 newsigs.dcd_down == oldsigs.dcd_down &&
2019 newsigs.cts_up == oldsigs.cts_up &&
2020 newsigs.cts_down == oldsigs.cts_down &&
2021 newsigs.ri_up == oldsigs.ri_up &&
2022 newsigs.ri_down == oldsigs.ri_down &&
2023 cnow.exithunt == cprev.exithunt &&
2024 cnow.rxidle == cprev.rxidle) {
2025 rc = -EIO;
2026 break;
2027 }
2028
2029 events = mask &
2030 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2031 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2032 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2033 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2034 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2035 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2036 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2037 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2038 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2039 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2040 if (events)
2041 break;
d12341f9 2042
1da177e4
LT		 2043 cprev = cnow;
2044 oldsigs = newsigs;
2045 }
d12341f9 2046
1da177e4
LT		 2047 remove_wait_queue(&info->event_wait_q, &wait);
2048 set_current_state(TASK_RUNNING);
2049
2050 if (mask & MgslEvent_ExitHuntMode) {
3d553993 2051 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 2052 if (!waitqueue_active(&info->event_wait_q))
2053 irq_disable(info, CHA, IRQ_EXITHUNT);
3d553993 2054 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2055 }
2056exit:
2057 if (rc == 0)
2058 PUT_USER(rc, events, mask_ptr);
2059 return rc;
2060}
2061
2062static int modem_input_wait(MGSLPC_INFO *info,int arg)
2063{
3d553993 2064 unsigned long flags;
1da177e4
LT		 2065 int rc;
2066 struct mgsl_icount cprev, cnow;
2067 DECLARE_WAITQUEUE(wait, current);
2068
2069 /* save current irq counts */
3d553993 2070 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 2071 cprev = info->icount;
2072 add_wait_queue(&info->status_event_wait_q, &wait);
2073 set_current_state(TASK_INTERRUPTIBLE);
3d553993 2074 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2075
2076 for(;;) {
2077 schedule();
2078 if (signal_pending(current)) {
2079 rc = -ERESTARTSYS;
2080 break;
2081 }
2082
2083 /* get new irq counts */
3d553993 2084 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 2085 cnow = info->icount;
2086 set_current_state(TASK_INTERRUPTIBLE);
3d553993 2087 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2088
2089 /* if no change, wait aborted for some reason */
2090 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2091 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2092 rc = -EIO;
2093 break;
2094 }
2095
2096 /* check for change in caller specified modem input */
2097 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2098 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2099 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2100 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2101 rc = 0;
2102 break;
2103 }
2104
2105 cprev = cnow;
2106 }
2107 remove_wait_queue(&info->status_event_wait_q, &wait);
2108 set_current_state(TASK_RUNNING);
2109 return rc;
2110}
2111
2112/* return the state of the serial control and status signals
2113 */
60b33c13 2114static int tiocmget(struct tty_struct *tty)
1da177e4
LT		 2115{
2116 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2117 unsigned int result;
3d553993 2118 unsigned long flags;
1da177e4 2119
3d553993
AK		 2120 spin_lock_irqsave(&info->lock, flags);
2121 get_signals(info);
2122 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2123
2124 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2125 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2126 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2127 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2128 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2129 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2130
2131 if (debug_level >= DEBUG_LEVEL_INFO)
2132 printk("%s(%d):%s tiocmget() value=%08X\n",
3d553993 2133 __FILE__, __LINE__, info->device_name, result);
1da177e4
LT		 2134 return result;
2135}
2136
2137/* set modem control signals (DTR/RTS)
2138 */
20b9d177 2139static int tiocmset(struct tty_struct *tty,
1da177e4
LT		 2140 unsigned int set, unsigned int clear)
2141{
2142 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
3d553993 2143 unsigned long flags;
1da177e4
LT		 2144
2145 if (debug_level >= DEBUG_LEVEL_INFO)
2146 printk("%s(%d):%s tiocmset(%x,%x)\n",
3d553993 2147 __FILE__, __LINE__, info->device_name, set, clear);
1da177e4
LT		 2148
2149 if (set & TIOCM_RTS)
2150 info->serial_signals |= SerialSignal_RTS;
2151 if (set & TIOCM_DTR)
2152 info->serial_signals |= SerialSignal_DTR;
2153 if (clear & TIOCM_RTS)
2154 info->serial_signals &= ~SerialSignal_RTS;
2155 if (clear & TIOCM_DTR)
2156 info->serial_signals &= ~SerialSignal_DTR;
2157
3d553993
AK		 2158 spin_lock_irqsave(&info->lock, flags);
2159 set_signals(info);
2160 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2161
2162 return 0;
2163}
2164
2165/* Set or clear transmit break condition
2166 *
2167 * Arguments: tty pointer to tty instance data
2168 * break_state -1=set break condition, 0=clear
2169 */
9e98966c 2170static int mgslpc_break(struct tty_struct *tty, int break_state)
1da177e4
LT		 2171{
2172 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2173 unsigned long flags;
d12341f9 2174
1da177e4
LT		 2175 if (debug_level >= DEBUG_LEVEL_INFO)
2176 printk("%s(%d):mgslpc_break(%s,%d)\n",
3d553993 2177 __FILE__, __LINE__, info->device_name, break_state);
d12341f9 2178
1da177e4 2179 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
9e98966c 2180 return -EINVAL;
1da177e4 2181
3d553993
AK		 2182 spin_lock_irqsave(&info->lock, flags);
2183 if (break_state == -1)
1da177e4 2184 set_reg_bits(info, CHA+DAFO, BIT6);
d12341f9 2185 else
1da177e4 2186 clear_reg_bits(info, CHA+DAFO, BIT6);
3d553993 2187 spin_unlock_irqrestore(&info->lock, flags);
9e98966c 2188 return 0;
1da177e4
LT		 2189}
2190
0587102c
AC		 2191static int mgslpc_get_icount(struct tty_struct *tty,
2192 struct serial_icounter_struct *icount)
2193{
2194 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2195 struct mgsl_icount cnow; /* kernel counter temps */
2196 unsigned long flags;
2197
3d553993 2198 spin_lock_irqsave(&info->lock, flags);
0587102c 2199 cnow = info->icount;
3d553993 2200 spin_unlock_irqrestore(&info->lock, flags);
0587102c
AC		 2201
2202 icount->cts = cnow.cts;
2203 icount->dsr = cnow.dsr;
2204 icount->rng = cnow.rng;
2205 icount->dcd = cnow.dcd;
2206 icount->rx = cnow.rx;
2207 icount->tx = cnow.tx;
2208 icount->frame = cnow.frame;
2209 icount->overrun = cnow.overrun;
2210 icount->parity = cnow.parity;
2211 icount->brk = cnow.brk;
2212 icount->buf_overrun = cnow.buf_overrun;
2213
2214 return 0;
2215}
2216
1da177e4 2217/* Service an IOCTL request
d12341f9 2218 *
1da177e4 2219 * Arguments:
d12341f9 2220 *
3d553993
AK		 2221 * tty pointer to tty instance data
2222 * cmd IOCTL command code
2223 * arg command argument/context
d12341f9 2224 *
1da177e4
LT		 2225 * Return Value: 0 if success, otherwise error code
2226 */
751b3840 2227static int mgslpc_ioctl(struct tty_struct *tty,
1da177e4
LT		 2228 unsigned int cmd, unsigned long arg)
2229{
2230 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2231 void __user *argp = (void __user *)arg;
d12341f9 2232
1da177e4 2233 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 2234 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__, __LINE__,
2235 info->device_name, cmd);
d12341f9 2236
1da177e4
LT		 2237 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
2238 return -ENODEV;
2239
2240 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 2241 (cmd != TIOCMIWAIT)) {
18900ca6 2242 if (tty_io_error(tty))
1da177e4
LT		 2243 return -EIO;
2244 }
2245
1da177e4
LT		 2246 switch (cmd) {
2247 case MGSL_IOCGPARAMS:
2248 return get_params(info, argp);
2249 case MGSL_IOCSPARAMS:
eeb46134 2250 return set_params(info, argp, tty);
1da177e4
LT		 2251 case MGSL_IOCGTXIDLE:
2252 return get_txidle(info, argp);
2253 case MGSL_IOCSTXIDLE:
2254 return set_txidle(info, (int)arg);
2255 case MGSL_IOCGIF:
2256 return get_interface(info, argp);
2257 case MGSL_IOCSIF:
2258 return set_interface(info,(int)arg);
2259 case MGSL_IOCTXENABLE:
eeb46134 2260 return set_txenable(info,(int)arg, tty);
1da177e4
LT		 2261 case MGSL_IOCRXENABLE:
2262 return set_rxenable(info,(int)arg);
2263 case MGSL_IOCTXABORT:
2264 return tx_abort(info);
2265 case MGSL_IOCGSTATS:
2266 return get_stats(info, argp);
2267 case MGSL_IOCWAITEVENT:
2268 return wait_events(info, argp);
2269 case TIOCMIWAIT:
2270 return modem_input_wait(info,(int)arg);
1da177e4
LT		 2271 default:
2272 return -ENOIOCTLCMD;
2273 }
2274 return 0;
2275}
2276
2277/* Set new termios settings
d12341f9 2278 *
1da177e4 2279 * Arguments:
d12341f9 2280 *
3d553993
AK		 2281 * tty pointer to tty structure
2282 * termios pointer to buffer to hold returned old termios
1da177e4 2283 */
606d099c 2284static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 2285{
2286 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2287 unsigned long flags;
d12341f9 2288
1da177e4 2289 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 2290 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__, __LINE__,
2291 tty->driver->name);
d12341f9 2292
1da177e4 2293 /* just return if nothing has changed */
373f5aed
AC		 2294 if ((tty->termios.c_cflag == old_termios->c_cflag)
2295 && (RELEVANT_IFLAG(tty->termios.c_iflag)
1da177e4
LT		 2296 == RELEVANT_IFLAG(old_termios->c_iflag)))
2297 return;
2298
eeb46134 2299 mgslpc_change_params(info, tty);
1da177e4
LT		 2300
2301 /* Handle transition to B0 status */
9db276f8 2302 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
9fe8074b 2303 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3d553993
AK		 2304 spin_lock_irqsave(&info->lock, flags);
2305 set_signals(info);
2306 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 2307 }
d12341f9 2308
1da177e4 2309 /* Handle transition away from B0 status */
9db276f8 2310 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1da177e4 2311 info->serial_signals |= SerialSignal_DTR;
97ef38b8 2312 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
1da177e4 2313 info->serial_signals |= SerialSignal_RTS;
3d553993
AK		 2314 spin_lock_irqsave(&info->lock, flags);
2315 set_signals(info);
2316 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 2317 }
d12341f9 2318
1da177e4 2319 /* Handle turning off CRTSCTS */
9db276f8 2320 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
1da177e4
LT		 2321 tty->hw_stopped = 0;
2322 tx_release(tty);
2323 }
2324}
2325
2326static void mgslpc_close(struct tty_struct *tty, struct file * filp)
2327{
2328 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2329 struct tty_port *port = &info->port;
1da177e4
LT		 2330
2331 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
2332 return;
d12341f9 2333
1da177e4
LT		 2334 if (debug_level >= DEBUG_LEVEL_INFO)
2335 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
3d553993 2336 __FILE__, __LINE__, info->device_name, port->count);
1da177e4 2337
eeb46134 2338 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 2339 goto cleanup;
d12341f9 2340
d41861ca 2341 if (tty_port_initialized(port))
3d553993 2342 mgslpc_wait_until_sent(tty, info->timeout);
1da177e4 2343
978e595f 2344 mgslpc_flush_buffer(tty);
1da177e4 2345
978e595f 2346 tty_ldisc_flush(tty);
eeb46134
AC		 2347 shutdown(info, tty);
2348
2349 tty_port_close_end(port, tty);
2350 tty_port_tty_set(port, NULL);
d12341f9 2351cleanup:
1da177e4 2352 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 2353 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__, __LINE__,
eeb46134 2354 tty->driver->name, port->count);
1da177e4
LT		 2355}
2356
2357/* Wait until the transmitter is empty.
2358 */
2359static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
2360{
2361 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2362 unsigned long orig_jiffies, char_time;
2363
3d553993 2364 if (!info)
1da177e4
LT		 2365 return;
2366
2367 if (debug_level >= DEBUG_LEVEL_INFO)
2368 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
3d553993 2369 __FILE__, __LINE__, info->device_name);
d12341f9 2370
1da177e4
LT		 2371 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
2372 return;
2373
d41861ca 2374 if (!tty_port_initialized(&info->port))
1da177e4 2375 goto exit;
d12341f9 2376
1da177e4 2377 orig_jiffies = jiffies;
d12341f9 2378
1da177e4
LT		 2379 /* Set check interval to 1/5 of estimated time to
2380 * send a character, and make it at least 1. The check
2381 * interval should also be less than the timeout.
2382 * Note: use tight timings here to satisfy the NIST-PCTS.
d12341f9
JG		 2383 */
2384
3d553993
AK		 2385 if (info->params.data_rate) {
2386 char_time = info->timeout/(32 * 5);
1da177e4
LT		 2387 if (!char_time)
2388 char_time++;
2389 } else
2390 char_time = 1;
d12341f9 2391
1da177e4
LT		 2392 if (timeout)
2393 char_time = min_t(unsigned long, char_time, timeout);
d12341f9 2394
1da177e4
LT		 2395 if (info->params.mode == MGSL_MODE_HDLC) {
2396 while (info->tx_active) {
2397 msleep_interruptible(jiffies_to_msecs(char_time));
2398 if (signal_pending(current))
2399 break;
2400 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2401 break;
2402 }
2403 } else {
2404 while ((info->tx_count || info->tx_active) &&
2405 info->tx_enabled) {
2406 msleep_interruptible(jiffies_to_msecs(char_time));
2407 if (signal_pending(current))
2408 break;
2409 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2410 break;
2411 }
2412 }
d12341f9 2413
1da177e4
LT		 2414exit:
2415 if (debug_level >= DEBUG_LEVEL_INFO)
2416 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
3d553993 2417 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 2418}
2419
2420/* Called by tty_hangup() when a hangup is signaled.
2421 * This is the same as closing all open files for the port.
2422 */
2423static void mgslpc_hangup(struct tty_struct *tty)
2424{
2425 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
d12341f9 2426
1da177e4
LT		 2427 if (debug_level >= DEBUG_LEVEL_INFO)
2428 printk("%s(%d):mgslpc_hangup(%s)\n",
3d553993 2429 __FILE__, __LINE__, info->device_name);
d12341f9 2430
1da177e4
LT		 2431 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
2432 return;
2433
2434 mgslpc_flush_buffer(tty);
eeb46134
AC		 2435 shutdown(info, tty);
2436 tty_port_hangup(&info->port);
1da177e4
LT		 2437}
2438
eeb46134 2439static int carrier_raised(struct tty_port *port)
1da177e4 2440{
eeb46134
AC		 2441 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2442 unsigned long flags;
d12341f9 2443
3d553993
AK		 2444 spin_lock_irqsave(&info->lock, flags);
2445 get_signals(info);
2446 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 2447
eeb46134
AC		 2448 if (info->serial_signals & SerialSignal_DCD)
2449 return 1;
2450 return 0;
2451}
d12341f9 2452
fcc8ac18 2453static void dtr_rts(struct tty_port *port, int onoff)
eeb46134
AC		 2454{
2455 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2456 unsigned long flags;
d12341f9 2457
3d553993 2458 spin_lock_irqsave(&info->lock, flags);
fcc8ac18 2459 if (onoff)
9fe8074b 2460 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
fcc8ac18 2461 else
9fe8074b 2462 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
eeb46134 2463 set_signals(info);
3d553993 2464 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2465}
2466
eeb46134 2467
1da177e4
LT		 2468static int mgslpc_open(struct tty_struct *tty, struct file * filp)
2469{
2470 MGSLPC_INFO *info;
eeb46134 2471 struct tty_port *port;
3d553993
AK		 2472 int retval, line;
2473 unsigned long flags;
1da177e4 2474
d12341f9 2475 /* verify range of specified line number */
1da177e4 2476 line = tty->index;
410235fd 2477 if (line >= mgslpc_device_count) {
1da177e4 2478 printk("%s(%d):mgslpc_open with invalid line #%d.\n",
3d553993 2479 __FILE__, __LINE__, line);
1da177e4
LT		 2480 return -ENODEV;
2481 }
2482
2483 /* find the info structure for the specified line */
2484 info = mgslpc_device_list;
2485 while(info && info->line != line)
2486 info = info->next_device;
2487 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
2488 return -ENODEV;
d12341f9 2489
eeb46134 2490 port = &info->port;
1da177e4 2491 tty->driver_data = info;
eeb46134 2492 tty_port_tty_set(port, tty);
d12341f9 2493
1da177e4
LT		 2494 if (debug_level >= DEBUG_LEVEL_INFO)
2495 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
3d553993 2496 __FILE__, __LINE__, tty->driver->name, port->count);
1da177e4 2497
d6c53c0e 2498 port->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 2499
2500 spin_lock_irqsave(&info->netlock, flags);
2501 if (info->netcount) {
2502 retval = -EBUSY;
2503 spin_unlock_irqrestore(&info->netlock, flags);
2504 goto cleanup;
2505 }
eeb46134
AC		 2506 spin_lock(&port->lock);
2507 port->count++;
2508 spin_unlock(&port->lock);
1da177e4
LT		 2509 spin_unlock_irqrestore(&info->netlock, flags);
2510
eeb46134 2511 if (port->count == 1) {
1da177e4 2512 /* 1st open on this device, init hardware */
eeb46134 2513 retval = startup(info, tty);
1da177e4
LT		 2514 if (retval < 0)
2515 goto cleanup;
2516 }
2517
eeb46134 2518 retval = tty_port_block_til_ready(&info->port, tty, filp);
1da177e4
LT		 2519 if (retval) {
2520 if (debug_level >= DEBUG_LEVEL_INFO)
2521 printk("%s(%d):block_til_ready(%s) returned %d\n",
3d553993 2522 __FILE__, __LINE__, info->device_name, retval);
1da177e4
LT		 2523 goto cleanup;
2524 }
2525
2526 if (debug_level >= DEBUG_LEVEL_INFO)
2527 printk("%s(%d):mgslpc_open(%s) success\n",
3d553993 2528 __FILE__, __LINE__, info->device_name);
1da177e4 2529 retval = 0;
d12341f9
JG		 2530
2531cleanup:
1da177e4
LT		 2532 return retval;
2533}
2534
2535/*
2536 * /proc fs routines....
2537 */
2538
87687144 2539static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
1da177e4
LT		 2540{
2541 char stat_buf[30];
1da177e4
LT		 2542 unsigned long flags;
2543
87687144 2544 seq_printf(m, "%s:io:%04X irq:%d",
1da177e4
LT		 2545 info->device_name, info->io_base, info->irq_level);
2546
2547 /* output current serial signal states */
3d553993
AK		 2548 spin_lock_irqsave(&info->lock, flags);
2549 get_signals(info);
2550 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 2551
1da177e4
LT		 2552 stat_buf[0] = 0;
2553 stat_buf[1] = 0;
2554 if (info->serial_signals & SerialSignal_RTS)
2555 strcat(stat_buf, "|RTS");
2556 if (info->serial_signals & SerialSignal_CTS)
2557 strcat(stat_buf, "|CTS");
2558 if (info->serial_signals & SerialSignal_DTR)
2559 strcat(stat_buf, "|DTR");
2560 if (info->serial_signals & SerialSignal_DSR)
2561 strcat(stat_buf, "|DSR");
2562 if (info->serial_signals & SerialSignal_DCD)
2563 strcat(stat_buf, "|CD");
2564 if (info->serial_signals & SerialSignal_RI)
2565 strcat(stat_buf, "|RI");
2566
2567 if (info->params.mode == MGSL_MODE_HDLC) {
87687144 2568 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 2569 info->icount.txok, info->icount.rxok);
2570 if (info->icount.txunder)
87687144 2571 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 2572 if (info->icount.txabort)
87687144 2573 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 2574 if (info->icount.rxshort)
87687144 2575 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 2576 if (info->icount.rxlong)
87687144 2577 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 2578 if (info->icount.rxover)
87687144 2579 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 2580 if (info->icount.rxcrc)
87687144 2581 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 2582 } else {
87687144 2583 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 2584 info->icount.tx, info->icount.rx);
2585 if (info->icount.frame)
87687144 2586 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 2587 if (info->icount.parity)
87687144 2588 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 2589 if (info->icount.brk)
87687144 2590 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 2591 if (info->icount.overrun)
87687144 2592 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4 2593 }
d12341f9 2594
1da177e4 2595 /* Append serial signal status to end */
87687144 2596 seq_printf(m, " %s\n", stat_buf+1);
d12341f9 2597
87687144 2598 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 2599 info->tx_active,info->bh_requested,info->bh_running,
2600 info->pending_bh);
1da177e4
LT		 2601}
2602
2603/* Called to print information about devices
2604 */
87687144 2605static int mgslpc_proc_show(struct seq_file *m, void *v)
1da177e4 2606{
1da177e4 2607 MGSLPC_INFO *info;
d12341f9 2608
87687144 2609 seq_printf(m, "synclink driver:%s\n", driver_version);
d12341f9 2610
1da177e4 2611 info = mgslpc_device_list;
3d553993 2612 while (info) {
87687144 2613 line_info(m, info);
1da177e4
LT		 2614 info = info->next_device;
2615 }
87687144
AD		 2616 return 0;
2617}
1da177e4 2618
87687144
AD		 2619static int mgslpc_proc_open(struct inode *inode, struct file *file)
2620{
2621 return single_open(file, mgslpc_proc_show, NULL);
1da177e4
LT		 2622}
2623
87687144
AD		 2624static const struct file_operations mgslpc_proc_fops = {
2625 .owner = THIS_MODULE,
2626 .open = mgslpc_proc_open,
2627 .read = seq_read,
2628 .llseek = seq_lseek,
2629 .release = single_release,
2630};
2631
cdaad343 2632static int rx_alloc_buffers(MGSLPC_INFO *info)
1da177e4
LT		 2633{
2634 /* each buffer has header and data */
2635 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
2636
2637 /* calculate total allocation size for 8 buffers */
2638 info->rx_buf_total_size = info->rx_buf_size * 8;
2639
2640 /* limit total allocated memory */
2641 if (info->rx_buf_total_size > 0x10000)
2642 info->rx_buf_total_size = 0x10000;
2643
2644 /* calculate number of buffers */
2645 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
2646
2647 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
2648 if (info->rx_buf == NULL)
2649 return -ENOMEM;
2650
a6b68a69
PF		 2651 /* unused flag buffer to satisfy receive_buf calling interface */
2652 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
2653 if (!info->flag_buf) {
2654 kfree(info->rx_buf);
2655 info->rx_buf = NULL;
2656 return -ENOMEM;
2657 }
2658
1da177e4
LT		 2659 rx_reset_buffers(info);
2660 return 0;
2661}
2662
cdaad343 2663static void rx_free_buffers(MGSLPC_INFO *info)
1da177e4 2664{
735d5661 2665 kfree(info->rx_buf);
1da177e4 2666 info->rx_buf = NULL;
a6b68a69
PF		 2667 kfree(info->flag_buf);
2668 info->flag_buf = NULL;
1da177e4
LT		 2669}
2670
cdaad343 2671static int claim_resources(MGSLPC_INFO *info)
1da177e4 2672{
3d553993
AK		 2673 if (rx_alloc_buffers(info) < 0) {
2674 printk("Can't allocate rx buffer %s\n", info->device_name);
1da177e4
LT		 2675 release_resources(info);
2676 return -ENODEV;
d12341f9 2677 }
1da177e4
LT		 2678 return 0;
2679}
2680
cdaad343 2681static void release_resources(MGSLPC_INFO *info)
1da177e4
LT		 2682{
2683 if (debug_level >= DEBUG_LEVEL_INFO)
2684 printk("release_resources(%s)\n", info->device_name);
2685 rx_free_buffers(info);
2686}
2687
2688/* Add the specified device instance data structure to the
2689 * global linked list of devices and increment the device count.
d12341f9 2690 *
1da177e4
LT		 2691 * Arguments: info pointer to device instance data
2692 */
d34138d0 2693static int mgslpc_add_device(MGSLPC_INFO *info)
1da177e4 2694{
d34138d0
AK		 2695 MGSLPC_INFO *current_dev = NULL;
2696 struct device *tty_dev;
2697 int ret;
2698
1da177e4
LT		 2699 info->next_device = NULL;
2700 info->line = mgslpc_device_count;
2701 sprintf(info->device_name,"ttySLP%d",info->line);
d12341f9 2702
1da177e4
LT		 2703 if (info->line < MAX_DEVICE_COUNT) {
2704 if (maxframe[info->line])
2705 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 2706 }
2707
2708 mgslpc_device_count++;
d12341f9 2709
1da177e4
LT		 2710 if (!mgslpc_device_list)
2711 mgslpc_device_list = info;
d12341f9 2712 else {
d34138d0 2713 current_dev = mgslpc_device_list;
3d553993 2714 while (current_dev->next_device)
1da177e4
LT		 2715 current_dev = current_dev->next_device;
2716 current_dev->next_device = info;
2717 }
d12341f9 2718
1da177e4
LT		 2719 if (info->max_frame_size < 4096)
2720 info->max_frame_size = 4096;
2721 else if (info->max_frame_size > 65535)
2722 info->max_frame_size = 65535;
d12341f9 2723
3d553993 2724 printk("SyncLink PC Card %s:IO=%04X IRQ=%d\n",
1da177e4
LT		 2725 info->device_name, info->io_base, info->irq_level);
2726
af69c7f9 2727#if SYNCLINK_GENERIC_HDLC
d34138d0
AK		 2728 ret = hdlcdev_init(info);
2729 if (ret != 0)
2730 goto failed;
1da177e4 2731#endif
d34138d0
AK		 2732
2733 tty_dev = tty_port_register_device(&info->port, serial_driver, info->line,
a33ba827 2734 &info->p_dev->dev);
d34138d0
AK		 2735 if (IS_ERR(tty_dev)) {
2736 ret = PTR_ERR(tty_dev);
2737#if SYNCLINK_GENERIC_HDLC
2738 hdlcdev_exit(info);
2739#endif
2740 goto failed;
2741 }
2742
2743 return 0;
2744
2745failed:
2746 if (current_dev)
2747 current_dev->next_device = NULL;
2748 else
2749 mgslpc_device_list = NULL;
2750 mgslpc_device_count--;
2751 return ret;
1da177e4
LT		 2752}
2753
cdaad343 2754static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
1da177e4
LT		 2755{
2756 MGSLPC_INFO *info = mgslpc_device_list;
2757 MGSLPC_INFO *last = NULL;
2758
2759 while(info) {
2760 if (info == remove_info) {
2761 if (last)
2762 last->next_device = info->next_device;
2763 else
2764 mgslpc_device_list = info->next_device;
16a1065f 2765 tty_unregister_device(serial_driver, info->line);
af69c7f9 2766#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2767 hdlcdev_exit(info);
2768#endif
2769 release_resources(info);
191c5f10 2770 tty_port_destroy(&info->port);
1da177e4
LT		 2771 kfree(info);
2772 mgslpc_device_count--;
2773 return;
2774 }
2775 last = info;
2776 info = info->next_device;
2777 }
2778}
2779
25f8f54f 2780static const struct pcmcia_device_id mgslpc_ids[] = {
4af48c8c
DB		 2781 PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
2782 PCMCIA_DEVICE_NULL
2783};
2784MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
2785
1da177e4
LT		 2786static struct pcmcia_driver mgslpc_driver = {
2787 .owner = THIS_MODULE,
2e9b981a 2788 .name = "synclink_cs",
15b99ac1 2789 .probe = mgslpc_probe,
cc3b4866 2790 .remove = mgslpc_detach,
4af48c8c 2791 .id_table = mgslpc_ids,
98e4c28b
DB		 2792 .suspend = mgslpc_suspend,
2793 .resume = mgslpc_resume,
1da177e4
LT		 2794};
2795
b68e31d0 2796static const struct tty_operations mgslpc_ops = {
1da177e4
LT		 2797 .open = mgslpc_open,
2798 .close = mgslpc_close,
2799 .write = mgslpc_write,
2800 .put_char = mgslpc_put_char,
2801 .flush_chars = mgslpc_flush_chars,
2802 .write_room = mgslpc_write_room,
2803 .chars_in_buffer = mgslpc_chars_in_buffer,
2804 .flush_buffer = mgslpc_flush_buffer,
2805 .ioctl = mgslpc_ioctl,
2806 .throttle = mgslpc_throttle,
2807 .unthrottle = mgslpc_unthrottle,
2808 .send_xchar = mgslpc_send_xchar,
2809 .break_ctl = mgslpc_break,
2810 .wait_until_sent = mgslpc_wait_until_sent,
1da177e4
LT		 2811 .set_termios = mgslpc_set_termios,
2812 .stop = tx_pause,
2813 .start = tx_release,
2814 .hangup = mgslpc_hangup,
2815 .tiocmget = tiocmget,
2816 .tiocmset = tiocmset,
dc98d965 2817 .get_icount = mgslpc_get_icount,
87687144 2818 .proc_fops = &mgslpc_proc_fops,
1da177e4
LT		 2819};
2820
1da177e4 2821static int __init synclink_cs_init(void)
1da177e4
LT		 2822{
2823 int rc;
2824
cc93441e
JS		 2825 if (break_on_load) {
2826 mgslpc_get_text_ptr();
2827 BREAKPOINT();
1da177e4
LT		 2828 }
2829
cc93441e
JS		 2830 serial_driver = tty_alloc_driver(MAX_DEVICE_COUNT,
2831 TTY_DRIVER_REAL_RAW |
2832 TTY_DRIVER_DYNAMIC_DEV);
c3a6344a
DC		 2833 if (IS_ERR(serial_driver)) {
2834 rc = PTR_ERR(serial_driver);
cc93441e
JS		 2835 goto err;
2836 }
1da177e4 2837
cc93441e
JS		 2838 /* Initialize the tty_driver structure */
2839 serial_driver->driver_name = "synclink_cs";
2840 serial_driver->name = "ttySLP";
2841 serial_driver->major = ttymajor;
2842 serial_driver->minor_start = 64;
2843 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2844 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2845 serial_driver->init_termios = tty_std_termios;
2846 serial_driver->init_termios.c_cflag =
2847 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2848 tty_set_operations(serial_driver, &mgslpc_ops);
1da177e4 2849
cc93441e
JS		 2850 rc = tty_register_driver(serial_driver);
2851 if (rc < 0) {
2852 printk(KERN_ERR "%s(%d):Couldn't register serial driver\n",
2853 __FILE__, __LINE__);
2854 goto err_put_tty;
2855 }
1da177e4 2856
16a1065f
JS		 2857 rc = pcmcia_register_driver(&mgslpc_driver);
2858 if (rc < 0)
2859 goto err_unreg_tty;
d12341f9 2860
cc93441e
JS		 2861 printk(KERN_INFO "%s %s, tty major#%d\n", driver_name, driver_version,
2862 serial_driver->major);
d12341f9 2863
737586fe 2864 return 0;
16a1065f
JS		 2865err_unreg_tty:
2866 tty_unregister_driver(serial_driver);
737586fe
JS		 2867err_put_tty:
2868 put_tty_driver(serial_driver);
16a1065f 2869err:
737586fe 2870 return rc;
1da177e4
LT		 2871}
2872
d12341f9 2873static void __exit synclink_cs_exit(void)
1da177e4 2874{
16a1065f 2875 pcmcia_unregister_driver(&mgslpc_driver);
737586fe
JS		 2876 tty_unregister_driver(serial_driver);
2877 put_tty_driver(serial_driver);
1da177e4
LT		 2878}
2879
2880module_init(synclink_cs_init);
2881module_exit(synclink_cs_exit);
2882
2883static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
2884{
2885 unsigned int M, N;
2886 unsigned char val;
2887
d12341f9
JG		 2888 /* note:standard BRG mode is broken in V3.2 chip
2889 * so enhanced mode is always used
1da177e4
LT		 2890 */
2891
2892 if (rate) {
2893 N = 3686400 / rate;
2894 if (!N)
2895 N = 1;
2896 N >>= 1;
2897 for (M = 1; N > 64 && M < 16; M++)
2898 N >>= 1;
2899 N--;
2900
2901 /* BGR[5..0] = N
2902 * BGR[9..6] = M
2903 * BGR[7..0] contained in BGR register
2904 * BGR[9..8] contained in CCR2[7..6]
2905 * divisor = (N+1)*2^M
2906 *
2907 * Note: M *must* not be zero (causes asymetric duty cycle)
d12341f9 2908 */
1da177e4
LT		 2909 write_reg(info, (unsigned char) (channel + BGR),
2910 (unsigned char) ((M << 6) + N));
2911 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
2912 val |= ((M << 4) & 0xc0);
2913 write_reg(info, (unsigned char) (channel + CCR2), val);
2914 }
2915}
2916
2917/* Enabled the AUX clock output at the specified frequency.
2918 */
2919static void enable_auxclk(MGSLPC_INFO *info)
2920{
2921 unsigned char val;
d12341f9 2922
1da177e4
LT		 2923 /* MODE
2924 *
2925 * 07..06 MDS[1..0] 10 = transparent HDLC mode
2926 * 05 ADM Address Mode, 0 = no addr recognition
2927 * 04 TMD Timer Mode, 0 = external
2928 * 03 RAC Receiver Active, 0 = inactive
2929 * 02 RTS 0=RTS active during xmit, 1=RTS always active
2930 * 01 TRS Timer Resolution, 1=512
2931 * 00 TLP Test Loop, 0 = no loop
2932 *
2933 * 1000 0010
d12341f9 2934 */
1da177e4 2935 val = 0x82;
d12341f9
JG		 2936
2937 /* channel B RTS is used to enable AUXCLK driver on SP505 */
1da177e4
LT		 2938 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2939 val |= BIT2;
2940 write_reg(info, CHB + MODE, val);
d12341f9 2941
1da177e4
LT		 2942 /* CCR0
2943 *
2944 * 07 PU Power Up, 1=active, 0=power down
2945 * 06 MCE Master Clock Enable, 1=enabled
2946 * 05 Reserved, 0
2947 * 04..02 SC[2..0] Encoding
2948 * 01..00 SM[1..0] Serial Mode, 00=HDLC
2949 *
2950 * 11000000
d12341f9 2951 */
1da177e4 2952 write_reg(info, CHB + CCR0, 0xc0);
d12341f9 2953
1da177e4
LT		 2954 /* CCR1
2955 *
2956 * 07 SFLG Shared Flag, 0 = disable shared flags
2957 * 06 GALP Go Active On Loop, 0 = not used
2958 * 05 GLP Go On Loop, 0 = not used
2959 * 04 ODS Output Driver Select, 1=TxD is push-pull output
2960 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
2961 * 02..00 CM[2..0] Clock Mode
2962 *
2963 * 0001 0111
d12341f9 2964 */
1da177e4 2965 write_reg(info, CHB + CCR1, 0x17);
d12341f9 2966
1da177e4
LT		 2967 /* CCR2 (Channel B)
2968 *
2969 * 07..06 BGR[9..8] Baud rate bits 9..8
2970 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
2971 * 04 SSEL Clock source select, 1=submode b
2972 * 03 TOE 0=TxCLK is input, 1=TxCLK is output
2973 * 02 RWX Read/Write Exchange 0=disabled
2974 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
2975 * 00 DIV, data inversion 0=disabled, 1=enabled
2976 *
2977 * 0011 1000
d12341f9 2978 */
1da177e4
LT		 2979 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2980 write_reg(info, CHB + CCR2, 0x38);
2981 else
2982 write_reg(info, CHB + CCR2, 0x30);
d12341f9 2983
1da177e4
LT		 2984 /* CCR4
2985 *
2986 * 07 MCK4 Master Clock Divide by 4, 1=enabled
2987 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
2988 * 05 TST1 Test Pin, 0=normal operation
2989 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
2990 * 03..02 Reserved, must be 0
2991 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
2992 *
2993 * 0101 0000
d12341f9 2994 */
1da177e4 2995 write_reg(info, CHB + CCR4, 0x50);
d12341f9 2996
1da177e4
LT		 2997 /* if auxclk not enabled, set internal BRG so
2998 * CTS transitions can be detected (requires TxC)
d12341f9 2999 */
1da177e4
LT		 3000 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
3001 mgslpc_set_rate(info, CHB, info->params.clock_speed);
3002 else
3003 mgslpc_set_rate(info, CHB, 921600);
3004}
3005
d12341f9 3006static void loopback_enable(MGSLPC_INFO *info)
1da177e4
LT		 3007{
3008 unsigned char val;
d12341f9
JG		 3009
3010 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
ecda040f 3011 val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0);
1da177e4 3012 write_reg(info, CHA + CCR1, val);
d12341f9
JG		 3013
3014 /* CCR2:04 SSEL Clock source select, 1=submode b */
ecda040f 3015 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5);
1da177e4 3016 write_reg(info, CHA + CCR2, val);
d12341f9
JG		 3017
3018 /* set LinkSpeed if available, otherwise default to 2Mbps */
1da177e4
LT		 3019 if (info->params.clock_speed)
3020 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3021 else
3022 mgslpc_set_rate(info, CHA, 1843200);
d12341f9
JG		 3023
3024 /* MODE:00 TLP Test Loop, 1=loopback enabled */
1da177e4
LT		 3025 val = read_reg(info, CHA + MODE) | BIT0;
3026 write_reg(info, CHA + MODE, val);
3027}
3028
cdaad343 3029static void hdlc_mode(MGSLPC_INFO *info)
1da177e4
LT		 3030{
3031 unsigned char val;
3032 unsigned char clkmode, clksubmode;
3033
d12341f9 3034 /* disable all interrupts */
1da177e4
LT		 3035 irq_disable(info, CHA, 0xffff);
3036 irq_disable(info, CHB, 0xffff);
3037 port_irq_disable(info, 0xff);
d12341f9
JG		 3038
3039 /* assume clock mode 0a, rcv=RxC xmt=TxC */
1da177e4
LT		 3040 clkmode = clksubmode = 0;
3041 if (info->params.flags & HDLC_FLAG_RXC_DPLL
3042 && info->params.flags & HDLC_FLAG_TXC_DPLL) {
d12341f9 3043 /* clock mode 7a, rcv = DPLL, xmt = DPLL */
1da177e4
LT		 3044 clkmode = 7;
3045 } else if (info->params.flags & HDLC_FLAG_RXC_BRG
3046 && info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3047 /* clock mode 7b, rcv = BRG, xmt = BRG */
1da177e4
LT		 3048 clkmode = 7;
3049 clksubmode = 1;
3050 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
3051 if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3052 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
1da177e4
LT		 3053 clkmode = 6;
3054 clksubmode = 1;
3055 } else {
d12341f9 3056 /* clock mode 6a, rcv = DPLL, xmt = TxC */
1da177e4
LT		 3057 clkmode = 6;
3058 }
3059 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3060 /* clock mode 0b, rcv = RxC, xmt = BRG */
1da177e4
LT		 3061 clksubmode = 1;
3062 }
d12341f9 3063
1da177e4
LT		 3064 /* MODE
3065 *
3066 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3067 * 05 ADM Address Mode, 0 = no addr recognition
3068 * 04 TMD Timer Mode, 0 = external
3069 * 03 RAC Receiver Active, 0 = inactive
3070 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3071 * 01 TRS Timer Resolution, 1=512
3072 * 00 TLP Test Loop, 0 = no loop
3073 *
3074 * 1000 0010
d12341f9 3075 */
1da177e4
LT		 3076 val = 0x82;
3077 if (info->params.loopback)
3078 val |= BIT0;
d12341f9
JG		 3079
3080 /* preserve RTS state */
1da177e4
LT		 3081 if (info->serial_signals & SerialSignal_RTS)
3082 val |= BIT2;
3083 write_reg(info, CHA + MODE, val);
d12341f9 3084
1da177e4
LT		 3085 /* CCR0
3086 *
3087 * 07 PU Power Up, 1=active, 0=power down
3088 * 06 MCE Master Clock Enable, 1=enabled
3089 * 05 Reserved, 0
3090 * 04..02 SC[2..0] Encoding
3091 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3092 *
3093 * 11000000
d12341f9 3094 */
1da177e4
LT		 3095 val = 0xc0;
3096 switch (info->params.encoding)
3097 {
3098 case HDLC_ENCODING_NRZI:
3099 val |= BIT3;
3100 break;
3101 case HDLC_ENCODING_BIPHASE_SPACE:
3102 val |= BIT4;
3103 break; // FM0
3104 case HDLC_ENCODING_BIPHASE_MARK:
ecda040f 3105 val |= BIT4 | BIT2;
1da177e4
LT		 3106 break; // FM1
3107 case HDLC_ENCODING_BIPHASE_LEVEL:
ecda040f 3108 val |= BIT4 | BIT3;
1da177e4
LT		 3109 break; // Manchester
3110 }
3111 write_reg(info, CHA + CCR0, val);
d12341f9 3112
1da177e4
LT		 3113 /* CCR1
3114 *
3115 * 07 SFLG Shared Flag, 0 = disable shared flags
3116 * 06 GALP Go Active On Loop, 0 = not used
3117 * 05 GLP Go On Loop, 0 = not used
3118 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3119 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3120 * 02..00 CM[2..0] Clock Mode
3121 *
3122 * 0001 0000
d12341f9 3123 */
1da177e4
LT		 3124 val = 0x10 + clkmode;
3125 write_reg(info, CHA + CCR1, val);
d12341f9 3126
1da177e4
LT		 3127 /* CCR2
3128 *
3129 * 07..06 BGR[9..8] Baud rate bits 9..8
3130 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3131 * 04 SSEL Clock source select, 1=submode b
3132 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3133 * 02 RWX Read/Write Exchange 0=disabled
3134 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3135 * 00 DIV, data inversion 0=disabled, 1=enabled
3136 *
3137 * 0000 0000
d12341f9 3138 */
1da177e4
LT		 3139 val = 0x00;
3140 if (clkmode == 2 || clkmode == 3 || clkmode == 6
3141 || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
3142 val |= BIT5;
3143 if (clksubmode)
3144 val |= BIT4;
3145 if (info->params.crc_type == HDLC_CRC_32_CCITT)
3146 val |= BIT1;
3147 if (info->params.encoding == HDLC_ENCODING_NRZB)
3148 val |= BIT0;
3149 write_reg(info, CHA + CCR2, val);
d12341f9 3150
1da177e4
LT		 3151 /* CCR3
3152 *
3153 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
3154 * 05 EPT Enable preamble transmission, 1=enabled
3155 * 04 RADD Receive address pushed to FIFO, 0=disabled
3156 * 03 CRL CRC Reset Level, 0=FFFF
3157 * 02 RCRC Rx CRC 0=On 1=Off
3158 * 01 TCRC Tx CRC 0=On 1=Off
3159 * 00 PSD DPLL Phase Shift Disable
3160 *
3161 * 0000 0000
d12341f9 3162 */
1da177e4
LT		 3163 val = 0x00;
3164 if (info->params.crc_type == HDLC_CRC_NONE)
ecda040f 3165 val |= BIT2 | BIT1;
1da177e4
LT		 3166 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3167 val |= BIT5;
3168 switch (info->params.preamble_length)
3169 {
3170 case HDLC_PREAMBLE_LENGTH_16BITS:
3171 val |= BIT6;
3172 break;
3173 case HDLC_PREAMBLE_LENGTH_32BITS:
3174 val |= BIT6;
3175 break;
3176 case HDLC_PREAMBLE_LENGTH_64BITS:
ecda040f 3177 val |= BIT7 | BIT6;
1da177e4
LT		 3178 break;
3179 }
3180 write_reg(info, CHA + CCR3, val);
d12341f9
JG		 3181
3182 /* PRE - Preamble pattern */
1da177e4
LT		 3183 val = 0;
3184 switch (info->params.preamble)
3185 {
3186 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3187 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
3188 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
3189 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3190 }
3191 write_reg(info, CHA + PRE, val);
d12341f9 3192
1da177e4
LT		 3193 /* CCR4
3194 *
3195 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3196 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3197 * 05 TST1 Test Pin, 0=normal operation
3198 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3199 * 03..02 Reserved, must be 0
3200 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3201 *
3202 * 0101 0000
d12341f9 3203 */
1da177e4
LT		 3204 val = 0x50;
3205 write_reg(info, CHA + CCR4, val);
3206 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3207 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
3208 else
3209 mgslpc_set_rate(info, CHA, info->params.clock_speed);
d12341f9 3210
1da177e4
LT		 3211 /* RLCR Receive length check register
3212 *
3213 * 7 1=enable receive length check
3214 * 6..0 Max frame length = (RL + 1) * 32
d12341f9 3215 */
1da177e4 3216 write_reg(info, CHA + RLCR, 0);
d12341f9 3217
1da177e4
LT		 3218 /* XBCH Transmit Byte Count High
3219 *
3220 * 07 DMA mode, 0 = interrupt driven
3221 * 06 NRM, 0=ABM (ignored)
3222 * 05 CAS Carrier Auto Start
3223 * 04 XC Transmit Continuously (ignored)
3224 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3225 *
3226 * 0000 0000
d12341f9 3227 */
1da177e4
LT		 3228 val = 0x00;
3229 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3230 val |= BIT5;
3231 write_reg(info, CHA + XBCH, val);
3232 enable_auxclk(info);
3233 if (info->params.loopback || info->testing_irq)
3234 loopback_enable(info);
3235 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3236 {
3237 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3238 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3239 set_reg_bits(info, CHA + PVR, BIT3);
3240 } else
3241 clear_reg_bits(info, CHA + PVR, BIT3);
3242
3243 irq_enable(info, CHA,
ecda040f
AJ		 3244 IRQ_RXEOM | IRQ_RXFIFO | IRQ_ALLSENT |
3245 IRQ_UNDERRUN | IRQ_TXFIFO);
1da177e4
LT		 3246 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3247 wait_command_complete(info, CHA);
3248 read_reg16(info, CHA + ISR); /* clear pending IRQs */
d12341f9 3249
1da177e4
LT		 3250 /* Master clock mode enabled above to allow reset commands
3251 * to complete even if no data clocks are present.
3252 *
3253 * Disable master clock mode for normal communications because
3254 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
3255 * IRQ when in master clock mode.
3256 *
3257 * Leave master clock mode enabled for IRQ test because the
3258 * timer IRQ used by the test can only happen in master clock mode.
d12341f9 3259 */
1da177e4
LT		 3260 if (!info->testing_irq)
3261 clear_reg_bits(info, CHA + CCR0, BIT6);
3262
3263 tx_set_idle(info);
3264
3265 tx_stop(info);
3266 rx_stop(info);
3267}
3268
cdaad343 3269static void rx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3270{
3271 if (debug_level >= DEBUG_LEVEL_ISR)
3272 printk("%s(%d):rx_stop(%s)\n",
3d553993 3273 __FILE__, __LINE__, info->device_name);
d12341f9
JG		 3274
3275 /* MODE:03 RAC Receiver Active, 0=inactive */
1da177e4
LT		 3276 clear_reg_bits(info, CHA + MODE, BIT3);
3277
0fab6de0
JP		 3278 info->rx_enabled = false;
3279 info->rx_overflow = false;
1da177e4
LT		 3280}
3281
cdaad343 3282static void rx_start(MGSLPC_INFO *info)
1da177e4
LT		 3283{
3284 if (debug_level >= DEBUG_LEVEL_ISR)
3285 printk("%s(%d):rx_start(%s)\n",
3d553993 3286 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 3287
3288 rx_reset_buffers(info);
0fab6de0
JP		 3289 info->rx_enabled = false;
3290 info->rx_overflow = false;
1da177e4 3291
d12341f9 3292 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3293 set_reg_bits(info, CHA + MODE, BIT3);
3294
0fab6de0 3295 info->rx_enabled = true;
1da177e4
LT		 3296}
3297
eeb46134 3298static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3299{
3300 if (debug_level >= DEBUG_LEVEL_ISR)
3301 printk("%s(%d):tx_start(%s)\n",
3d553993 3302 __FILE__, __LINE__, info->device_name);
d12341f9 3303
1da177e4
LT		 3304 if (info->tx_count) {
3305 /* If auto RTS enabled and RTS is inactive, then assert */
3306 /* RTS and set a flag indicating that the driver should */
3307 /* negate RTS when the transmission completes. */
0fab6de0 3308 info->drop_rts_on_tx_done = false;
1da177e4
LT		 3309
3310 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3311 get_signals(info);
3312 if (!(info->serial_signals & SerialSignal_RTS)) {
3313 info->serial_signals |= SerialSignal_RTS;
3314 set_signals(info);
0fab6de0 3315 info->drop_rts_on_tx_done = true;
1da177e4
LT		 3316 }
3317 }
3318
3319 if (info->params.mode == MGSL_MODE_ASYNC) {
3320 if (!info->tx_active) {
0fab6de0 3321 info->tx_active = true;
eeb46134 3322 tx_ready(info, tty);
1da177e4
LT		 3323 }
3324 } else {
0fab6de0 3325 info->tx_active = true;
eeb46134 3326 tx_ready(info, tty);
40565f19
JS		 3327 mod_timer(&info->tx_timer, jiffies +
3328 msecs_to_jiffies(5000));
1da177e4
LT		 3329 }
3330 }
3331
3332 if (!info->tx_enabled)
0fab6de0 3333 info->tx_enabled = true;
1da177e4
LT		 3334}
3335
cdaad343 3336static void tx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3337{
3338 if (debug_level >= DEBUG_LEVEL_ISR)
3339 printk("%s(%d):tx_stop(%s)\n",
3d553993 3340 __FILE__, __LINE__, info->device_name);
d12341f9
JG		 3341
3342 del_timer(&info->tx_timer);
1da177e4 3343
0fab6de0
JP		 3344 info->tx_enabled = false;
3345 info->tx_active = false;
1da177e4
LT		 3346}
3347
3348/* Reset the adapter to a known state and prepare it for further use.
3349 */
cdaad343 3350static void reset_device(MGSLPC_INFO *info)
1da177e4 3351{
d12341f9 3352 /* power up both channels (set BIT7) */
1da177e4
LT		 3353 write_reg(info, CHA + CCR0, 0x80);
3354 write_reg(info, CHB + CCR0, 0x80);
3355 write_reg(info, CHA + MODE, 0);
3356 write_reg(info, CHB + MODE, 0);
d12341f9
JG		 3357
3358 /* disable all interrupts */
1da177e4
LT		 3359 irq_disable(info, CHA, 0xffff);
3360 irq_disable(info, CHB, 0xffff);
3361 port_irq_disable(info, 0xff);
d12341f9 3362
1da177e4
LT		 3363 /* PCR Port Configuration Register
3364 *
3365 * 07..04 DEC[3..0] Serial I/F select outputs
3366 * 03 output, 1=AUTO CTS control enabled
3367 * 02 RI Ring Indicator input 0=active
3368 * 01 DSR input 0=active
3369 * 00 DTR output 0=active
3370 *
3371 * 0000 0110
d12341f9 3372 */
1da177e4 3373 write_reg(info, PCR, 0x06);
d12341f9 3374
1da177e4
LT		 3375 /* PVR Port Value Register
3376 *
3377 * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
3378 * 03 AUTO CTS output 1=enabled
3379 * 02 RI Ring Indicator input
3380 * 01 DSR input
3381 * 00 DTR output (1=inactive)
3382 *
3383 * 0000 0001
3384 */
3385// write_reg(info, PVR, PVR_DTR);
d12341f9 3386
1da177e4
LT		 3387 /* IPC Interrupt Port Configuration
3388 *
3389 * 07 VIS 1=Masked interrupts visible
3390 * 06..05 Reserved, 0
3391 * 04..03 SLA Slave address, 00 ignored
3392 * 02 CASM Cascading Mode, 1=daisy chain
3393 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
3394 *
3395 * 0000 0101
d12341f9 3396 */
1da177e4
LT		 3397 write_reg(info, IPC, 0x05);
3398}
3399
cdaad343 3400static void async_mode(MGSLPC_INFO *info)
1da177e4
LT		 3401{
3402 unsigned char val;
3403
d12341f9 3404 /* disable all interrupts */
1da177e4
LT		 3405 irq_disable(info, CHA, 0xffff);
3406 irq_disable(info, CHB, 0xffff);
3407 port_irq_disable(info, 0xff);
d12341f9 3408
1da177e4
LT		 3409 /* MODE
3410 *
3411 * 07 Reserved, 0
3412 * 06 FRTS RTS State, 0=active
3413 * 05 FCTS Flow Control on CTS
3414 * 04 FLON Flow Control Enable
3415 * 03 RAC Receiver Active, 0 = inactive
3416 * 02 RTS 0=Auto RTS, 1=manual RTS
3417 * 01 TRS Timer Resolution, 1=512
3418 * 00 TLP Test Loop, 0 = no loop
3419 *
3420 * 0000 0110
d12341f9 3421 */
1da177e4
LT		 3422 val = 0x06;
3423 if (info->params.loopback)
3424 val |= BIT0;
d12341f9
JG		 3425
3426 /* preserve RTS state */
1da177e4
LT		 3427 if (!(info->serial_signals & SerialSignal_RTS))
3428 val |= BIT6;
3429 write_reg(info, CHA + MODE, val);
d12341f9 3430
1da177e4
LT		 3431 /* CCR0
3432 *
3433 * 07 PU Power Up, 1=active, 0=power down
3434 * 06 MCE Master Clock Enable, 1=enabled
3435 * 05 Reserved, 0
3436 * 04..02 SC[2..0] Encoding, 000=NRZ
3437 * 01..00 SM[1..0] Serial Mode, 11=Async
3438 *
3439 * 1000 0011
d12341f9 3440 */
1da177e4 3441 write_reg(info, CHA + CCR0, 0x83);
d12341f9 3442
1da177e4
LT		 3443 /* CCR1
3444 *
3445 * 07..05 Reserved, 0
3446 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3447 * 03 BCR Bit Clock Rate, 1=16x
3448 * 02..00 CM[2..0] Clock Mode, 111=BRG
3449 *
3450 * 0001 1111
d12341f9 3451 */
1da177e4 3452 write_reg(info, CHA + CCR1, 0x1f);
d12341f9 3453
1da177e4
LT		 3454 /* CCR2 (channel A)
3455 *
3456 * 07..06 BGR[9..8] Baud rate bits 9..8
3457 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3458 * 04 SSEL Clock source select, 1=submode b
3459 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3460 * 02 RWX Read/Write Exchange 0=disabled
3461 * 01 Reserved, 0
3462 * 00 DIV, data inversion 0=disabled, 1=enabled
3463 *
3464 * 0001 0000
d12341f9 3465 */
1da177e4 3466 write_reg(info, CHA + CCR2, 0x10);
d12341f9 3467
1da177e4
LT		 3468 /* CCR3
3469 *
3470 * 07..01 Reserved, 0
3471 * 00 PSD DPLL Phase Shift Disable
3472 *
3473 * 0000 0000
d12341f9 3474 */
1da177e4 3475 write_reg(info, CHA + CCR3, 0);
d12341f9 3476
1da177e4
LT		 3477 /* CCR4
3478 *
3479 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3480 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3481 * 05 TST1 Test Pin, 0=normal operation
3482 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3483 * 03..00 Reserved, must be 0
3484 *
3485 * 0101 0000
d12341f9 3486 */
1da177e4
LT		 3487 write_reg(info, CHA + CCR4, 0x50);
3488 mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
d12341f9 3489
1da177e4
LT		 3490 /* DAFO Data Format
3491 *
3492 * 07 Reserved, 0
3493 * 06 XBRK transmit break, 0=normal operation
3494 * 05 Stop bits (0=1, 1=2)
3495 * 04..03 PAR[1..0] Parity (01=odd, 10=even)
3496 * 02 PAREN Parity Enable
3497 * 01..00 CHL[1..0] Character Length (00=8, 01=7)
3498 *
d12341f9 3499 */
1da177e4
LT		 3500 val = 0x00;
3501 if (info->params.data_bits != 8)
3502 val |= BIT0; /* 7 bits */
3503 if (info->params.stop_bits != 1)
3504 val |= BIT5;
3505 if (info->params.parity != ASYNC_PARITY_NONE)
3506 {
3507 val |= BIT2; /* Parity enable */
3508 if (info->params.parity == ASYNC_PARITY_ODD)
3509 val |= BIT3;
3510 else
3511 val |= BIT4;
3512 }
3513 write_reg(info, CHA + DAFO, val);
d12341f9 3514
1da177e4
LT		 3515 /* RFC Rx FIFO Control
3516 *
3517 * 07 Reserved, 0
3518 * 06 DPS, 1=parity bit not stored in data byte
3519 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
3520 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
3521 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
3522 * 01 Reserved, 0
3523 * 00 TCDE Terminate Char Detect Enable, 0=disabled
3524 *
3525 * 0101 1100
d12341f9 3526 */
1da177e4 3527 write_reg(info, CHA + RFC, 0x5c);
d12341f9 3528
1da177e4
LT		 3529 /* RLCR Receive length check register
3530 *
3531 * Max frame length = (RL + 1) * 32
d12341f9 3532 */
1da177e4 3533 write_reg(info, CHA + RLCR, 0);
d12341f9 3534
1da177e4
LT		 3535 /* XBCH Transmit Byte Count High
3536 *
3537 * 07 DMA mode, 0 = interrupt driven
3538 * 06 NRM, 0=ABM (ignored)
3539 * 05 CAS Carrier Auto Start
3540 * 04 XC Transmit Continuously (ignored)
3541 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3542 *
3543 * 0000 0000
d12341f9 3544 */
1da177e4
LT		 3545 val = 0x00;
3546 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3547 val |= BIT5;
3548 write_reg(info, CHA + XBCH, val);
3549 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3550 irq_enable(info, CHA, IRQ_CTS);
d12341f9
JG		 3551
3552 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3553 set_reg_bits(info, CHA + MODE, BIT3);
3554 enable_auxclk(info);
3555 if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
3556 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3557 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3558 set_reg_bits(info, CHA + PVR, BIT3);
3559 } else
3560 clear_reg_bits(info, CHA + PVR, BIT3);
3561 irq_enable(info, CHA,
ecda040f
AJ		 3562 IRQ_RXEOM | IRQ_RXFIFO | IRQ_BREAK_ON | IRQ_RXTIME |
3563 IRQ_ALLSENT | IRQ_TXFIFO);
1da177e4
LT		 3564 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3565 wait_command_complete(info, CHA);
3566 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3567}
3568
3569/* Set the HDLC idle mode for the transmitter.
3570 */
cdaad343 3571static void tx_set_idle(MGSLPC_INFO *info)
1da177e4 3572{
d12341f9 3573 /* Note: ESCC2 only supports flags and one idle modes */
1da177e4
LT		 3574 if (info->idle_mode == HDLC_TXIDLE_FLAGS)
3575 set_reg_bits(info, CHA + CCR1, BIT3);
3576 else
3577 clear_reg_bits(info, CHA + CCR1, BIT3);
3578}
3579
3580/* get state of the V24 status (input) signals.
3581 */
cdaad343 3582static void get_signals(MGSLPC_INFO *info)
1da177e4
LT		 3583{
3584 unsigned char status = 0;
d12341f9 3585
9fe8074b
JP		 3586 /* preserve RTS and DTR */
3587 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
1da177e4
LT		 3588
3589 if (read_reg(info, CHB + VSTR) & BIT7)
3590 info->serial_signals |= SerialSignal_DCD;
3591 if (read_reg(info, CHB + STAR) & BIT1)
3592 info->serial_signals |= SerialSignal_CTS;
3593
3594 status = read_reg(info, CHA + PVR);
3595 if (!(status & PVR_RI))
3596 info->serial_signals |= SerialSignal_RI;
3597 if (!(status & PVR_DSR))
3598 info->serial_signals |= SerialSignal_DSR;
3599}
3600
9fe8074b 3601/* Set the state of RTS and DTR based on contents of
1da177e4
LT		 3602 * serial_signals member of device extension.
3603 */
cdaad343 3604static void set_signals(MGSLPC_INFO *info)
1da177e4
LT		 3605{
3606 unsigned char val;
3607
3608 val = read_reg(info, CHA + MODE);
3609 if (info->params.mode == MGSL_MODE_ASYNC) {
3610 if (info->serial_signals & SerialSignal_RTS)
3611 val &= ~BIT6;
3612 else
3613 val |= BIT6;
3614 } else {
3615 if (info->serial_signals & SerialSignal_RTS)
3616 val |= BIT2;
3617 else
3618 val &= ~BIT2;
3619 }
3620 write_reg(info, CHA + MODE, val);
3621
3622 if (info->serial_signals & SerialSignal_DTR)
3623 clear_reg_bits(info, CHA + PVR, PVR_DTR);
3624 else
3625 set_reg_bits(info, CHA + PVR, PVR_DTR);
3626}
3627
cdaad343 3628static void rx_reset_buffers(MGSLPC_INFO *info)
1da177e4
LT		 3629{
3630 RXBUF *buf;
3631 int i;
3632
3633 info->rx_put = 0;
3634 info->rx_get = 0;
3635 info->rx_frame_count = 0;
3636 for (i=0 ; i < info->rx_buf_count ; i++) {
3637 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
3638 buf->status = buf->count = 0;
3639 }
3640}
3641
3642/* Attempt to return a received HDLC frame
3643 * Only frames received without errors are returned.
3644 *
0fab6de0 3645 * Returns true if frame returned, otherwise false
1da177e4 3646 */
eeb46134 3647static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3648{
3649 unsigned short status;
3650 RXBUF *buf;
3651 unsigned int framesize = 0;
3652 unsigned long flags;
0fab6de0 3653 bool return_frame = false;
d12341f9 3654
1da177e4 3655 if (info->rx_frame_count == 0)
0fab6de0 3656 return false;
1da177e4
LT		 3657
3658 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
3659
3660 status = buf->status;
3661
3662 /* 07 VFR 1=valid frame
3663 * 06 RDO 1=data overrun
3664 * 05 CRC 1=OK, 0=error
3665 * 04 RAB 1=frame aborted
3666 */
3667 if ((status & 0xf0) != 0xA0) {
3668 if (!(status & BIT7) || (status & BIT4))
3669 info->icount.rxabort++;
3670 else if (status & BIT6)
3671 info->icount.rxover++;
3672 else if (!(status & BIT5)) {
3673 info->icount.rxcrc++;
3674 if (info->params.crc_type & HDLC_CRC_RETURN_EX)
0fab6de0 3675 return_frame = true;
1da177e4
LT		 3676 }
3677 framesize = 0;
af69c7f9 3678#if SYNCLINK_GENERIC_HDLC
1da177e4 3679 {
198191c4
KH		 3680 info->netdev->stats.rx_errors++;
3681 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 3682 }
3683#endif
3684 } else
0fab6de0 3685 return_frame = true;
1da177e4
LT		 3686
3687 if (return_frame)
3688 framesize = buf->count;
3689
3690 if (debug_level >= DEBUG_LEVEL_BH)
3691 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
3d553993 3692 __FILE__, __LINE__, info->device_name, status, framesize);
d12341f9 3693
1da177e4 3694 if (debug_level >= DEBUG_LEVEL_DATA)
d12341f9
JG		 3695 trace_block(info, buf->data, framesize, 0);
3696
1da177e4
LT		 3697 if (framesize) {
3698 if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
3699 framesize+1 > info->max_frame_size) ||
3700 framesize > info->max_frame_size)
3701 info->icount.rxlong++;
3702 else {
3703 if (status & BIT5)
3704 info->icount.rxok++;
3705
3706 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
3707 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
3708 ++framesize;
3709 }
3710
af69c7f9 3711#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3712 if (info->netcount)
3713 hdlcdev_rx(info, buf->data, framesize);
3714 else
3715#endif
3716 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
3717 }
3718 }
3719
3d553993 3720 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 3721 buf->status = buf->count = 0;
3722 info->rx_frame_count--;
3723 info->rx_get++;
3724 if (info->rx_get >= info->rx_buf_count)
3725 info->rx_get = 0;
3d553993 3726 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 3727
0fab6de0 3728 return true;
1da177e4
LT		 3729}
3730
0fab6de0 3731static bool register_test(MGSLPC_INFO *info)
1da177e4 3732{
d12341f9 3733 static unsigned char patterns[] =
1da177e4 3734 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
fe971071 3735 static unsigned int count = ARRAY_SIZE(patterns);
1da177e4 3736 unsigned int i;
0fab6de0 3737 bool rc = true;
1da177e4
LT		 3738 unsigned long flags;
3739
3d553993 3740 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 3741 reset_device(info);
3742
3743 for (i = 0; i < count; i++) {
3744 write_reg(info, XAD1, patterns[i]);
3745 write_reg(info, XAD2, patterns[(i + 1) % count]);
fe971071 3746 if ((read_reg(info, XAD1) != patterns[i]) ||
1da177e4 3747 (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
0fab6de0 3748 rc = false;
1da177e4
LT		 3749 break;
3750 }
3751 }
3752
3d553993 3753 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 3754 return rc;
3755}
3756
0fab6de0 3757static bool irq_test(MGSLPC_INFO *info)
1da177e4
LT		 3758{
3759 unsigned long end_time;
3760 unsigned long flags;
3761
3d553993 3762 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 3763 reset_device(info);
3764
0fab6de0 3765 info->testing_irq = true;
1da177e4
LT		 3766 hdlc_mode(info);
3767
0fab6de0 3768 info->irq_occurred = false;
1da177e4
LT		 3769
3770 /* init hdlc mode */
3771
3772 irq_enable(info, CHA, IRQ_TIMER);
3773 write_reg(info, CHA + TIMR, 0); /* 512 cycles */
3774 issue_command(info, CHA, CMD_START_TIMER);
3775
3d553993 3776 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 3777
3778 end_time=100;
3779 while(end_time-- && !info->irq_occurred) {
3780 msleep_interruptible(10);
3781 }
d12341f9 3782
0fab6de0 3783 info->testing_irq = false;
1da177e4 3784
3d553993 3785 spin_lock_irqsave(&info->lock, flags);
1da177e4 3786 reset_device(info);
3d553993 3787 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 3788
0fab6de0 3789 return info->irq_occurred;
1da177e4
LT		 3790}
3791
cdaad343 3792static int adapter_test(MGSLPC_INFO *info)
1da177e4
LT		 3793{
3794 if (!register_test(info)) {
3795 info->init_error = DiagStatus_AddressFailure;
3d553993
AK		 3796 printk("%s(%d):Register test failure for device %s Addr=%04X\n",
3797 __FILE__, __LINE__, info->device_name, (unsigned short)(info->io_base));
1da177e4
LT		 3798 return -ENODEV;
3799 }
3800
3801 if (!irq_test(info)) {
3802 info->init_error = DiagStatus_IrqFailure;
3d553993
AK		 3803 printk("%s(%d):Interrupt test failure for device %s IRQ=%d\n",
3804 __FILE__, __LINE__, info->device_name, (unsigned short)(info->irq_level));
1da177e4
LT		 3805 return -ENODEV;
3806 }
3807
3808 if (debug_level >= DEBUG_LEVEL_INFO)
3809 printk("%s(%d):device %s passed diagnostics\n",
3d553993 3810 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 3811 return 0;
3812}
3813
cdaad343 3814static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
1da177e4
LT		 3815{
3816 int i;
3817 int linecount;
3818 if (xmit)
3d553993 3819 printk("%s tx data:\n", info->device_name);
1da177e4 3820 else
3d553993 3821 printk("%s rx data:\n", info->device_name);
d12341f9 3822
1da177e4
LT		 3823 while(count) {
3824 if (count > 16)
3825 linecount = 16;
3826 else
3827 linecount = count;
d12341f9 3828
1da177e4 3829 for(i=0;i<linecount;i++)
3d553993 3830 printk("%02X ", (unsigned char)data[i]);
1da177e4
LT		 3831 for(;i<17;i++)
3832 printk(" ");
3833 for(i=0;i<linecount;i++) {
3834 if (data[i]>=040 && data[i]<=0176)
3d553993 3835 printk("%c", data[i]);
1da177e4
LT		 3836 else
3837 printk(".");
3838 }
3839 printk("\n");
d12341f9 3840
1da177e4
LT		 3841 data += linecount;
3842 count -= linecount;
3843 }
3844}
3845
3846/* HDLC frame time out
3847 * update stats and do tx completion processing
3848 */
cdaad343 3849static void tx_timeout(unsigned long context)
1da177e4
LT		 3850{
3851 MGSLPC_INFO *info = (MGSLPC_INFO*)context;
3852 unsigned long flags;
d12341f9 3853
3d553993
AK		 3854 if (debug_level >= DEBUG_LEVEL_INFO)
3855 printk("%s(%d):tx_timeout(%s)\n",
3856 __FILE__, __LINE__, info->device_name);
3857 if (info->tx_active &&
3858 info->params.mode == MGSL_MODE_HDLC) {
1da177e4
LT		 3859 info->icount.txtimeout++;
3860 }
3d553993 3861 spin_lock_irqsave(&info->lock, flags);
0fab6de0 3862 info->tx_active = false;
1da177e4
LT		 3863 info->tx_count = info->tx_put = info->tx_get = 0;
3864
3d553993 3865 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 3866
af69c7f9 3867#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3868 if (info->netcount)
3869 hdlcdev_tx_done(info);
3870 else
3871#endif
eeb46134
AC		 3872 {
3873 struct tty_struct *tty = tty_port_tty_get(&info->port);
3874 bh_transmit(info, tty);
3875 tty_kref_put(tty);
3876 }
1da177e4
LT		 3877}
3878
af69c7f9 3879#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3880
3881/**
3882 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
3883 * set encoding and frame check sequence (FCS) options
3884 *
3885 * dev pointer to network device structure
3886 * encoding serial encoding setting
3887 * parity FCS setting
3888 *
3889 * returns 0 if success, otherwise error code
3890 */
3891static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
3892 unsigned short parity)
3893{
3894 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3895 struct tty_struct *tty;
1da177e4
LT		 3896 unsigned char new_encoding;
3897 unsigned short new_crctype;
3898
3899 /* return error if TTY interface open */
eeb46134 3900 if (info->port.count)
1da177e4
LT		 3901 return -EBUSY;
3902
3903 switch (encoding)
3904 {
3905 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
3906 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
3907 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
3908 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
3909 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
3910 default: return -EINVAL;
3911 }
3912
3913 switch (parity)
3914 {
3915 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
3916 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
3917 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
3918 default: return -EINVAL;
3919 }
3920
3921 info->params.encoding = new_encoding;
53b3531b 3922 info->params.crc_type = new_crctype;
1da177e4
LT		 3923
3924 /* if network interface up, reprogram hardware */
eeb46134
AC		 3925 if (info->netcount) {
3926 tty = tty_port_tty_get(&info->port);
3927 mgslpc_program_hw(info, tty);
3928 tty_kref_put(tty);
3929 }
1da177e4
LT		 3930
3931 return 0;
3932}
3933
3934/**
3935 * called by generic HDLC layer to send frame
3936 *
3937 * skb socket buffer containing HDLC frame
3938 * dev pointer to network device structure
1da177e4 3939 */
4c5d502d
SH		 3940static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
3941 struct net_device *dev)
1da177e4
LT		 3942{
3943 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 3944 unsigned long flags;
3945
3946 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 3947 printk(KERN_INFO "%s:hdlc_xmit(%s)\n", __FILE__, dev->name);
1da177e4
LT		 3948
3949 /* stop sending until this frame completes */
3950 netif_stop_queue(dev);
3951
3952 /* copy data to device buffers */
d626f62b 3953 skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
1da177e4
LT		 3954 info->tx_get = 0;
3955 info->tx_put = info->tx_count = skb->len;
3956
3957 /* update network statistics */
198191c4
KH		 3958 dev->stats.tx_packets++;
3959 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 3960
3961 /* done with socket buffer, so free it */
3962 dev_kfree_skb(skb);
3963
3964 /* save start time for transmit timeout detection */
860e9538 3965 netif_trans_update(dev);
1da177e4
LT		 3966
3967 /* start hardware transmitter if necessary */
3d553993 3968 spin_lock_irqsave(&info->lock, flags);
eeb46134
AC		 3969 if (!info->tx_active) {
3970 struct tty_struct *tty = tty_port_tty_get(&info->port);
3d553993
AK		 3971 tx_start(info, tty);
3972 tty_kref_put(tty);
eeb46134 3973 }
3d553993 3974 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 3975
4c5d502d 3976 return NETDEV_TX_OK;
1da177e4
LT		 3977}
3978
3979/**
3980 * called by network layer when interface enabled
3981 * claim resources and initialize hardware
3982 *
3983 * dev pointer to network device structure
3984 *
3985 * returns 0 if success, otherwise error code
3986 */
3987static int hdlcdev_open(struct net_device *dev)
3988{
3989 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3990 struct tty_struct *tty;
1da177e4
LT		 3991 int rc;
3992 unsigned long flags;
3993
3994 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 3995 printk("%s:hdlcdev_open(%s)\n", __FILE__, dev->name);
1da177e4
LT		 3996
3997 /* generic HDLC layer open processing */
3d553993
AK		 3998 rc = hdlc_open(dev);
3999 if (rc != 0)
1da177e4
LT		 4000 return rc;
4001
4002 /* arbitrate between network and tty opens */
4003 spin_lock_irqsave(&info->netlock, flags);
eeb46134 4004 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 4005 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
4006 spin_unlock_irqrestore(&info->netlock, flags);
4007 return -EBUSY;
4008 }
4009 info->netcount=1;
4010 spin_unlock_irqrestore(&info->netlock, flags);
4011
eeb46134 4012 tty = tty_port_tty_get(&info->port);
1da177e4 4013 /* claim resources and init adapter */
3d553993
AK		 4014 rc = startup(info, tty);
4015 if (rc != 0) {
eeb46134 4016 tty_kref_put(tty);
1da177e4
LT		 4017 spin_lock_irqsave(&info->netlock, flags);
4018 info->netcount=0;
4019 spin_unlock_irqrestore(&info->netlock, flags);
4020 return rc;
4021 }
9fe8074b
JP		 4022 /* assert RTS and DTR, apply hardware settings */
4023 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
eeb46134
AC		 4024 mgslpc_program_hw(info, tty);
4025 tty_kref_put(tty);
1da177e4
LT		 4026
4027 /* enable network layer transmit */
860e9538 4028 netif_trans_update(dev);
1da177e4
LT		 4029 netif_start_queue(dev);
4030
4031 /* inform generic HDLC layer of current DCD status */
4032 spin_lock_irqsave(&info->lock, flags);
4033 get_signals(info);
4034 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 4035 if (info->serial_signals & SerialSignal_DCD)
4036 netif_carrier_on(dev);
4037 else
4038 netif_carrier_off(dev);
1da177e4
LT		 4039 return 0;
4040}
4041
4042/**
4043 * called by network layer when interface is disabled
4044 * shutdown hardware and release resources
4045 *
4046 * dev pointer to network device structure
4047 *
4048 * returns 0 if success, otherwise error code
4049 */
4050static int hdlcdev_close(struct net_device *dev)
4051{
4052 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 4053 struct tty_struct *tty = tty_port_tty_get(&info->port);
1da177e4
LT		 4054 unsigned long flags;
4055
4056 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4057 printk("%s:hdlcdev_close(%s)\n", __FILE__, dev->name);
1da177e4
LT		 4058
4059 netif_stop_queue(dev);
4060
4061 /* shutdown adapter and release resources */
eeb46134
AC		 4062 shutdown(info, tty);
4063 tty_kref_put(tty);
1da177e4
LT		 4064 hdlc_close(dev);
4065
4066 spin_lock_irqsave(&info->netlock, flags);
4067 info->netcount=0;
4068 spin_unlock_irqrestore(&info->netlock, flags);
4069
4070 return 0;
4071}
4072
4073/**
4074 * called by network layer to process IOCTL call to network device
4075 *
4076 * dev pointer to network device structure
4077 * ifr pointer to network interface request structure
4078 * cmd IOCTL command code
4079 *
4080 * returns 0 if success, otherwise error code
4081 */
4082static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4083{
4084 const size_t size = sizeof(sync_serial_settings);
4085 sync_serial_settings new_line;
4086 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
4087 MGSLPC_INFO *info = dev_to_port(dev);
4088 unsigned int flags;
4089
4090 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4091 printk("%s:hdlcdev_ioctl(%s)\n", __FILE__, dev->name);
1da177e4
LT		 4092
4093 /* return error if TTY interface open */
eeb46134 4094 if (info->port.count)
1da177e4
LT		 4095 return -EBUSY;
4096
4097 if (cmd != SIOCWANDEV)
4098 return hdlc_ioctl(dev, ifr, cmd);
4099
5b917a14
VK		 4100 memset(&new_line, 0, size);
4101
1da177e4
LT		 4102 switch(ifr->ifr_settings.type) {
4103 case IF_GET_IFACE: /* return current sync_serial_settings */
4104
4105 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
4106 if (ifr->ifr_settings.size < size) {
4107 ifr->ifr_settings.size = size; /* data size wanted */
4108 return -ENOBUFS;
4109 }
4110
4111 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4112 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4113 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4114 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4115
4116 switch (flags){
4117 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4118 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4119 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4120 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4121 default: new_line.clock_type = CLOCK_DEFAULT;
4122 }
4123
4124 new_line.clock_rate = info->params.clock_speed;
4125 new_line.loopback = info->params.loopback ? 1:0;
4126
4127 if (copy_to_user(line, &new_line, size))
4128 return -EFAULT;
4129 return 0;
4130
4131 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
4132
4133 if(!capable(CAP_NET_ADMIN))
4134 return -EPERM;
4135 if (copy_from_user(&new_line, line, size))
4136 return -EFAULT;
4137
4138 switch (new_line.clock_type)
4139 {
4140 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
4141 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
4142 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
4143 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
4144 case CLOCK_DEFAULT: flags = info->params.flags &
4145 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4146 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4147 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4148 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
4149 default: return -EINVAL;
4150 }
4151
4152 if (new_line.loopback != 0 && new_line.loopback != 1)
4153 return -EINVAL;
4154
4155 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4156 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4157 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4158 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4159 info->params.flags |= flags;
4160
4161 info->params.loopback = new_line.loopback;
4162
4163 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
4164 info->params.clock_speed = new_line.clock_rate;
4165 else
4166 info->params.clock_speed = 0;
4167
4168 /* if network interface up, reprogram hardware */
eeb46134
AC		 4169 if (info->netcount) {
4170 struct tty_struct *tty = tty_port_tty_get(&info->port);
4171 mgslpc_program_hw(info, tty);
4172 tty_kref_put(tty);
4173 }
1da177e4
LT		 4174 return 0;
4175
4176 default:
4177 return hdlc_ioctl(dev, ifr, cmd);
4178 }
4179}
4180
4181/**
4182 * called by network layer when transmit timeout is detected
4183 *
4184 * dev pointer to network device structure
4185 */
4186static void hdlcdev_tx_timeout(struct net_device *dev)
4187{
4188 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 4189 unsigned long flags;
4190
4191 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4192 printk("hdlcdev_tx_timeout(%s)\n", dev->name);
1da177e4 4193
198191c4
KH		 4194 dev->stats.tx_errors++;
4195 dev->stats.tx_aborted_errors++;
1da177e4 4196
3d553993 4197 spin_lock_irqsave(&info->lock, flags);
1da177e4 4198 tx_stop(info);
3d553993 4199 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 4200
4201 netif_wake_queue(dev);
4202}
4203
4204/**
4205 * called by device driver when transmit completes
4206 * reenable network layer transmit if stopped
4207 *
4208 * info pointer to device instance information
4209 */
4210static void hdlcdev_tx_done(MGSLPC_INFO *info)
4211{
4212 if (netif_queue_stopped(info->netdev))
4213 netif_wake_queue(info->netdev);
4214}
4215
4216/**
4217 * called by device driver when frame received
4218 * pass frame to network layer
4219 *
4220 * info pointer to device instance information
4221 * buf pointer to buffer contianing frame data
4222 * size count of data bytes in buf
4223 */
4224static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
4225{
4226 struct sk_buff *skb = dev_alloc_skb(size);
4227 struct net_device *dev = info->netdev;
1da177e4
LT		 4228
4229 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4230 printk("hdlcdev_rx(%s)\n", dev->name);
1da177e4
LT		 4231
4232 if (skb == NULL) {
4233 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
198191c4 4234 dev->stats.rx_dropped++;
1da177e4
LT		 4235 return;
4236 }
4237
198191c4 4238 memcpy(skb_put(skb, size), buf, size);
1da177e4 4239
198191c4 4240 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 4241
198191c4
KH		 4242 dev->stats.rx_packets++;
4243 dev->stats.rx_bytes += size;
1da177e4
LT		 4244
4245 netif_rx(skb);
1da177e4
LT		 4246}
4247
991990a1
KH		 4248static const struct net_device_ops hdlcdev_ops = {
4249 .ndo_open = hdlcdev_open,
4250 .ndo_stop = hdlcdev_close,
991990a1
KH		 4251 .ndo_start_xmit = hdlc_start_xmit,
4252 .ndo_do_ioctl = hdlcdev_ioctl,
4253 .ndo_tx_timeout = hdlcdev_tx_timeout,
4254};
4255
1da177e4
LT		 4256/**
4257 * called by device driver when adding device instance
4258 * do generic HDLC initialization
4259 *
4260 * info pointer to device instance information
4261 *
4262 * returns 0 if success, otherwise error code
4263 */
4264static int hdlcdev_init(MGSLPC_INFO *info)
4265{
4266 int rc;
4267 struct net_device *dev;
4268 hdlc_device *hdlc;
4269
4270 /* allocate and initialize network and HDLC layer objects */
4271
3d553993
AK		 4272 dev = alloc_hdlcdev(info);
4273 if (dev == NULL) {
4274 printk(KERN_ERR "%s:hdlc device allocation failure\n", __FILE__);
1da177e4
LT		 4275 return -ENOMEM;
4276 }
4277
4278 /* for network layer reporting purposes only */
4279 dev->base_addr = info->io_base;
4280 dev->irq = info->irq_level;
4281
4282 /* network layer callbacks and settings */
991990a1
KH		 4283 dev->netdev_ops = &hdlcdev_ops;
4284 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 4285 dev->tx_queue_len = 50;
4286
4287 /* generic HDLC layer callbacks and settings */
4288 hdlc = dev_to_hdlc(dev);
4289 hdlc->attach = hdlcdev_attach;
4290 hdlc->xmit = hdlcdev_xmit;
4291
4292 /* register objects with HDLC layer */
3d553993
AK		 4293 rc = register_hdlc_device(dev);
4294 if (rc) {
4295 printk(KERN_WARNING "%s:unable to register hdlc device\n", __FILE__);
1da177e4
LT		 4296 free_netdev(dev);
4297 return rc;
4298 }
4299
4300 info->netdev = dev;
4301 return 0;
4302}
4303
4304/**
4305 * called by device driver when removing device instance
4306 * do generic HDLC cleanup
4307 *
4308 * info pointer to device instance information
4309 */
4310static void hdlcdev_exit(MGSLPC_INFO *info)
4311{
4312 unregister_hdlc_device(info->netdev);
4313 free_netdev(info->netdev);
4314 info->netdev = NULL;
4315}
4316
4317#endif /* CONFIG_HDLC */
4318
Linux 6.x block layer and io_uring tree(s)