Commit | Line | Data |
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037ad48b JS |
1 | /* |
2 | * mxser.c -- MOXA Smartio/Industio family multiport serial driver. | |
3 | * | |
3306ce3d | 4 | * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com.tw). |
c88cb8f9 | 5 | * Copyright (C) 2006 Jiri Slaby <jirislaby@gmail.com> |
037ad48b | 6 | * |
c88cb8f9 JS |
7 | * This code is loosely based on the 1.8 moxa driver which is based on |
8 | * Linux serial driver, written by Linus Torvalds, Theodore T'so and | |
9 | * others. | |
037ad48b JS |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
037ad48b JS |
16 | * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox |
17 | * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com. | |
18 | * - Fixed x86_64 cleanness | |
19 | * - Fixed sleep with spinlock held in mxser_send_break | |
20 | */ | |
21 | ||
037ad48b JS |
22 | #include <linux/module.h> |
23 | #include <linux/autoconf.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/signal.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/timer.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/tty.h> | |
30 | #include <linux/tty_flip.h> | |
31 | #include <linux/serial.h> | |
32 | #include <linux/serial_reg.h> | |
33 | #include <linux/major.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/fcntl.h> | |
36 | #include <linux/ptrace.h> | |
37 | #include <linux/gfp.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/mm.h> | |
40 | #include <linux/smp_lock.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/pci.h> | |
43 | ||
44 | #include <asm/system.h> | |
45 | #include <asm/io.h> | |
46 | #include <asm/irq.h> | |
47 | #include <asm/bitops.h> | |
48 | #include <asm/uaccess.h> | |
49 | ||
771f2d1a | 50 | #include "mxser_new.h" |
037ad48b | 51 | |
55b307da | 52 | #define MXSER_VERSION "2.0" |
037ad48b JS |
53 | #define MXSERMAJOR 174 |
54 | #define MXSERCUMAJOR 175 | |
55 | ||
56 | #define MXSER_EVENT_TXLOW 1 | |
037ad48b JS |
57 | |
58 | #define MXSER_BOARDS 4 /* Max. boards */ | |
037ad48b | 59 | #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ |
a8b74de9 | 60 | #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) |
3306ce3d | 61 | #define MXSER_ISR_PASS_LIMIT 99999L |
037ad48b JS |
62 | |
63 | #define MXSER_ERR_IOADDR -1 | |
64 | #define MXSER_ERR_IRQ -2 | |
65 | #define MXSER_ERR_IRQ_CONFLIT -3 | |
66 | #define MXSER_ERR_VECTOR -4 | |
67 | ||
037ad48b JS |
68 | #define WAKEUP_CHARS 256 |
69 | ||
70 | #define UART_MCR_AFE 0x20 | |
71 | #define UART_LSR_SPECIAL 0x1E | |
72 | ||
73 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK|\ | |
74 | IXON|IXOFF)) | |
75 | ||
037ad48b JS |
76 | #define C168_ASIC_ID 1 |
77 | #define C104_ASIC_ID 2 | |
78 | #define C102_ASIC_ID 0xB | |
79 | #define CI132_ASIC_ID 4 | |
80 | #define CI134_ASIC_ID 3 | |
81 | #define CI104J_ASIC_ID 5 | |
82 | ||
cd7ed64e JS |
83 | #define MXSER_HIGHBAUD 1 |
84 | #define MXSER_HAS2 2 | |
037ad48b JS |
85 | |
86 | /* This is only for PCI */ | |
cd7ed64e | 87 | static const struct { |
037ad48b JS |
88 | int type; |
89 | int tx_fifo; | |
90 | int rx_fifo; | |
91 | int xmit_fifo_size; | |
92 | int rx_high_water; | |
93 | int rx_trigger; | |
94 | int rx_low_water; | |
95 | long max_baud; | |
cd7ed64e | 96 | } Gpci_uart_info[] = { |
037ad48b JS |
97 | {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L}, |
98 | {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L}, | |
99 | {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L} | |
100 | }; | |
cd7ed64e JS |
101 | #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) |
102 | ||
103 | struct mxser_cardinfo { | |
104 | unsigned int nports; | |
105 | char *name; | |
106 | unsigned int flags; | |
107 | }; | |
108 | ||
109 | static const struct mxser_cardinfo mxser_cards[] = { | |
110 | { 8, "C168 series", }, /* C168-ISA */ | |
111 | { 4, "C104 series", }, /* C104-ISA */ | |
112 | { 4, "CI-104J series", }, /* CI104J */ | |
113 | { 8, "C168H/PCI series", }, /* C168-PCI */ | |
114 | { 4, "C104H/PCI series", }, /* C104-PCI */ | |
115 | { 4, "C102 series", MXSER_HAS2 }, /* C102-ISA */ | |
116 | { 4, "CI-132 series", MXSER_HAS2 }, /* CI132 */ | |
117 | { 4, "CI-134 series", }, /* CI134 */ | |
118 | { 2, "CP-132 series", }, /* CP132 */ | |
119 | { 4, "CP-114 series", }, /* CP114 */ | |
120 | { 4, "CT-114 series", }, /* CT114 */ | |
121 | { 2, "CP-102 series", MXSER_HIGHBAUD }, /* CP102 */ | |
122 | { 4, "CP-104U series", }, /* CP104U */ | |
123 | { 8, "CP-168U series", }, /* CP168U */ | |
124 | { 2, "CP-132U series", }, /* CP132U */ | |
125 | { 4, "CP-134U series", }, /* CP134U */ | |
126 | { 4, "CP-104JU series", }, /* CP104JU */ | |
127 | { 8, "Moxa UC7000 Serial", }, /* RC7000 */ | |
128 | { 8, "CP-118U series", }, /* CP118U */ | |
129 | { 2, "CP-102UL series", }, /* CP102UL */ | |
130 | { 2, "CP-102U series", }, /* CP102U */ | |
131 | { 8, "CP-118EL series", }, /* CP118EL */ | |
132 | { 8, "CP-168EL series", }, /* CP168EL */ | |
133 | { 4, "CP-104EL series", } /* CP104EL */ | |
134 | }; | |
037ad48b | 135 | |
cd7ed64e JS |
136 | /* driver_data correspond to the lines in the structure above |
137 | see also ISA probe function before you change something */ | |
037ad48b | 138 | static struct pci_device_id mxser_pcibrds[] = { |
3306ce3d | 139 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C168), |
cd7ed64e | 140 | .driver_data = 3 }, |
3306ce3d | 141 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C104), |
cd7ed64e | 142 | .driver_data = 4 }, |
3306ce3d | 143 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132), |
cd7ed64e | 144 | .driver_data = 8 }, |
3306ce3d | 145 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114), |
cd7ed64e | 146 | .driver_data = 9 }, |
3306ce3d | 147 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CT114), |
cd7ed64e | 148 | .driver_data = 10 }, |
3306ce3d | 149 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102), |
cd7ed64e | 150 | .driver_data = 11 }, |
3306ce3d | 151 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104U), |
cd7ed64e | 152 | .driver_data = 12 }, |
3306ce3d | 153 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168U), |
cd7ed64e | 154 | .driver_data = 13 }, |
3306ce3d | 155 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132U), |
cd7ed64e | 156 | .driver_data = 14 }, |
3306ce3d | 157 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134U), |
cd7ed64e | 158 | .driver_data = 15 }, |
3306ce3d | 159 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104JU), |
cd7ed64e | 160 | .driver_data = 16 }, |
3306ce3d | 161 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_RC7000), |
cd7ed64e | 162 | .driver_data = 17 }, |
3306ce3d | 163 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118U), |
cd7ed64e | 164 | .driver_data = 18 }, |
3306ce3d | 165 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102UL), |
cd7ed64e | 166 | .driver_data = 19 }, |
3306ce3d | 167 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102U), |
cd7ed64e | 168 | .driver_data = 20 }, |
3306ce3d | 169 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL), |
cd7ed64e | 170 | .driver_data = 21 }, |
3306ce3d | 171 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL), |
cd7ed64e | 172 | .driver_data = 22 }, |
3306ce3d | 173 | { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL), |
cd7ed64e | 174 | .driver_data = 23 }, |
3306ce3d | 175 | { } |
037ad48b | 176 | }; |
037ad48b JS |
177 | MODULE_DEVICE_TABLE(pci, mxser_pcibrds); |
178 | ||
037ad48b JS |
179 | static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 }; |
180 | static int ttymajor = MXSERMAJOR; | |
181 | static int calloutmajor = MXSERCUMAJOR; | |
037ad48b JS |
182 | |
183 | /* Variables for insmod */ | |
184 | ||
185 | MODULE_AUTHOR("Casper Yang"); | |
186 | MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); | |
187 | module_param_array(ioaddr, int, NULL, 0); | |
188 | module_param(ttymajor, int, 0); | |
037ad48b JS |
189 | MODULE_LICENSE("GPL"); |
190 | ||
191 | struct mxser_log { | |
192 | int tick; | |
193 | unsigned long rxcnt[MXSER_PORTS]; | |
194 | unsigned long txcnt[MXSER_PORTS]; | |
195 | }; | |
196 | ||
197 | ||
198 | struct mxser_mon { | |
199 | unsigned long rxcnt; | |
200 | unsigned long txcnt; | |
201 | unsigned long up_rxcnt; | |
202 | unsigned long up_txcnt; | |
203 | int modem_status; | |
204 | unsigned char hold_reason; | |
205 | }; | |
206 | ||
207 | struct mxser_mon_ext { | |
208 | unsigned long rx_cnt[32]; | |
209 | unsigned long tx_cnt[32]; | |
210 | unsigned long up_rxcnt[32]; | |
211 | unsigned long up_txcnt[32]; | |
212 | int modem_status[32]; | |
213 | ||
214 | long baudrate[32]; | |
215 | int databits[32]; | |
216 | int stopbits[32]; | |
217 | int parity[32]; | |
218 | int flowctrl[32]; | |
219 | int fifo[32]; | |
220 | int iftype[32]; | |
221 | }; | |
222 | ||
55b307da JS |
223 | struct mxser_board; |
224 | ||
225 | struct mxser_port { | |
226 | struct mxser_board *board; | |
227 | struct tty_struct *tty; | |
228 | ||
229 | unsigned long ioaddr; | |
230 | unsigned long opmode_ioaddr; | |
231 | int max_baud; | |
037ad48b | 232 | |
037ad48b JS |
233 | int rx_high_water; |
234 | int rx_trigger; /* Rx fifo trigger level */ | |
235 | int rx_low_water; | |
236 | int baud_base; /* max. speed */ | |
55b307da | 237 | long realbaud; |
037ad48b | 238 | int type; /* UART type */ |
55b307da JS |
239 | int flags; /* defined in tty.h */ |
240 | long session; /* Session of opening process */ | |
241 | long pgrp; /* pgrp of opening process */ | |
242 | ||
037ad48b | 243 | int x_char; /* xon/xoff character */ |
037ad48b JS |
244 | int IER; /* Interrupt Enable Register */ |
245 | int MCR; /* Modem control register */ | |
55b307da JS |
246 | |
247 | unsigned char stop_rx; | |
248 | unsigned char ldisc_stop_rx; | |
249 | ||
250 | int custom_divisor; | |
251 | int close_delay; | |
252 | unsigned short closing_wait; | |
253 | unsigned char err_shadow; | |
037ad48b | 254 | unsigned long event; |
55b307da | 255 | |
037ad48b JS |
256 | int count; /* # of fd on device */ |
257 | int blocked_open; /* # of blocked opens */ | |
55b307da JS |
258 | struct async_icount icount; /* kernel counters for 4 input interrupts */ |
259 | int timeout; | |
260 | ||
261 | int read_status_mask; | |
262 | int ignore_status_mask; | |
263 | int xmit_fifo_size; | |
037ad48b JS |
264 | unsigned char *xmit_buf; |
265 | int xmit_head; | |
266 | int xmit_tail; | |
267 | int xmit_cnt; | |
55b307da | 268 | |
606d099c AC |
269 | struct ktermios normal_termios; |
270 | struct ktermios callout_termios; | |
55b307da JS |
271 | |
272 | struct mxser_mon mon_data; | |
273 | ||
274 | spinlock_t slock; | |
275 | struct work_struct tqueue; | |
037ad48b JS |
276 | wait_queue_head_t open_wait; |
277 | wait_queue_head_t close_wait; | |
278 | wait_queue_head_t delta_msr_wait; | |
55b307da JS |
279 | }; |
280 | ||
281 | struct mxser_board { | |
2094e757 | 282 | unsigned int idx; |
55b307da | 283 | int irq; |
cd7ed64e | 284 | const struct mxser_cardinfo *info; |
55b307da JS |
285 | unsigned long vector; |
286 | unsigned long vector_mask; | |
287 | ||
288 | int chip_flag; | |
289 | int uart_type; | |
290 | ||
291 | struct mxser_port ports[MXSER_PORTS_PER_BOARD]; | |
037ad48b JS |
292 | }; |
293 | ||
294 | struct mxser_mstatus { | |
295 | tcflag_t cflag; | |
296 | int cts; | |
297 | int dsr; | |
298 | int ri; | |
299 | int dcd; | |
300 | }; | |
301 | ||
302 | static struct mxser_mstatus GMStatus[MXSER_PORTS]; | |
303 | ||
304 | static int mxserBoardCAP[MXSER_BOARDS] = { | |
305 | 0, 0, 0, 0 | |
306 | /* 0x180, 0x280, 0x200, 0x320 */ | |
307 | }; | |
308 | ||
55b307da | 309 | static struct mxser_board mxser_boards[MXSER_BOARDS]; |
037ad48b | 310 | static struct tty_driver *mxvar_sdriver; |
037ad48b JS |
311 | static struct mxser_log mxvar_log; |
312 | static int mxvar_diagflag; | |
313 | static unsigned char mxser_msr[MXSER_PORTS + 1]; | |
314 | static struct mxser_mon_ext mon_data_ext; | |
315 | static int mxser_set_baud_method[MXSER_PORTS + 1]; | |
316 | static spinlock_t gm_lock; | |
317 | ||
fb0c9295 | 318 | #ifdef CONFIG_PCI |
037ad48b JS |
319 | static int CheckIsMoxaMust(int io) |
320 | { | |
321 | u8 oldmcr, hwid; | |
322 | int i; | |
323 | ||
324 | outb(0, io + UART_LCR); | |
325 | DISABLE_MOXA_MUST_ENCHANCE_MODE(io); | |
326 | oldmcr = inb(io + UART_MCR); | |
327 | outb(0, io + UART_MCR); | |
328 | SET_MOXA_MUST_XON1_VALUE(io, 0x11); | |
329 | if ((hwid = inb(io + UART_MCR)) != 0) { | |
330 | outb(oldmcr, io + UART_MCR); | |
331 | return MOXA_OTHER_UART; | |
332 | } | |
333 | ||
334 | GET_MOXA_MUST_HARDWARE_ID(io, &hwid); | |
cd7ed64e JS |
335 | for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */ |
336 | if (hwid == Gpci_uart_info[i].type) | |
037ad48b JS |
337 | return (int)hwid; |
338 | } | |
339 | return MOXA_OTHER_UART; | |
340 | } | |
fb0c9295 | 341 | #endif |
037ad48b | 342 | |
55b307da | 343 | static void process_txrx_fifo(struct mxser_port *info) |
037ad48b JS |
344 | { |
345 | int i; | |
346 | ||
347 | if ((info->type == PORT_16450) || (info->type == PORT_8250)) { | |
348 | info->rx_trigger = 1; | |
349 | info->rx_high_water = 1; | |
350 | info->rx_low_water = 1; | |
351 | info->xmit_fifo_size = 1; | |
55b307da JS |
352 | } else |
353 | for (i = 0; i < UART_INFO_NUM; i++) | |
354 | if (info->board->chip_flag == Gpci_uart_info[i].type) { | |
037ad48b JS |
355 | info->rx_trigger = Gpci_uart_info[i].rx_trigger; |
356 | info->rx_low_water = Gpci_uart_info[i].rx_low_water; | |
357 | info->rx_high_water = Gpci_uart_info[i].rx_high_water; | |
358 | info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size; | |
359 | break; | |
360 | } | |
037ad48b JS |
361 | } |
362 | ||
95a7b8b9 | 363 | static void mxser_do_softint(struct work_struct *work) |
037ad48b | 364 | { |
95a7b8b9 | 365 | struct mxser_port *info = container_of(work, struct mxser_port, tqueue); |
a8b74de9 | 366 | struct tty_struct *tty = info->tty; |
037ad48b | 367 | |
a8dea4ec JS |
368 | if (test_and_clear_bit(MXSER_EVENT_TXLOW, &info->event)) |
369 | tty_wakeup(tty); | |
a8dea4ec | 370 | } |
037ad48b | 371 | |
a8dea4ec JS |
372 | static unsigned char mxser_get_msr(int baseaddr, int mode, int port) |
373 | { | |
374 | unsigned char status = 0; | |
037ad48b | 375 | |
a8dea4ec | 376 | status = inb(baseaddr + UART_MSR); |
037ad48b | 377 | |
a8dea4ec JS |
378 | mxser_msr[port] &= 0x0F; |
379 | mxser_msr[port] |= status; | |
380 | status = mxser_msr[port]; | |
381 | if (mode) | |
382 | mxser_msr[port] = 0; | |
037ad48b | 383 | |
a8dea4ec JS |
384 | return status; |
385 | } | |
55b307da | 386 | |
a8dea4ec JS |
387 | static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp, |
388 | struct mxser_port *port) | |
389 | { | |
390 | DECLARE_WAITQUEUE(wait, current); | |
391 | int retval; | |
392 | int do_clocal = 0; | |
393 | unsigned long flags; | |
394 | ||
395 | /* | |
396 | * If non-blocking mode is set, or the port is not enabled, | |
397 | * then make the check up front and then exit. | |
398 | */ | |
214efebb JS |
399 | if ((filp->f_flags & O_NONBLOCK) || |
400 | test_bit(TTY_IO_ERROR, &tty->flags)) { | |
a8dea4ec JS |
401 | port->flags |= ASYNC_NORMAL_ACTIVE; |
402 | return 0; | |
037ad48b | 403 | } |
a8dea4ec JS |
404 | |
405 | if (tty->termios->c_cflag & CLOCAL) | |
406 | do_clocal = 1; | |
407 | ||
037ad48b | 408 | /* |
a8dea4ec JS |
409 | * Block waiting for the carrier detect and the line to become |
410 | * free (i.e., not in use by the callout). While we are in | |
411 | * this loop, port->count is dropped by one, so that | |
412 | * mxser_close() knows when to free things. We restore it upon | |
413 | * exit, either normal or abnormal. | |
037ad48b | 414 | */ |
a8dea4ec JS |
415 | retval = 0; |
416 | add_wait_queue(&port->open_wait, &wait); | |
037ad48b | 417 | |
a8dea4ec JS |
418 | spin_lock_irqsave(&port->slock, flags); |
419 | if (!tty_hung_up_p(filp)) | |
420 | port->count--; | |
421 | spin_unlock_irqrestore(&port->slock, flags); | |
422 | port->blocked_open++; | |
423 | while (1) { | |
424 | spin_lock_irqsave(&port->slock, flags); | |
425 | outb(inb(port->ioaddr + UART_MCR) | | |
426 | UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR); | |
427 | spin_unlock_irqrestore(&port->slock, flags); | |
428 | set_current_state(TASK_INTERRUPTIBLE); | |
429 | if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)) { | |
430 | if (port->flags & ASYNC_HUP_NOTIFY) | |
431 | retval = -EAGAIN; | |
432 | else | |
433 | retval = -ERESTARTSYS; | |
434 | break; | |
435 | } | |
436 | if (!(port->flags & ASYNC_CLOSING) && | |
437 | (do_clocal || | |
438 | (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD))) | |
439 | break; | |
440 | if (signal_pending(current)) { | |
441 | retval = -ERESTARTSYS; | |
442 | break; | |
443 | } | |
444 | schedule(); | |
037ad48b | 445 | } |
a8dea4ec JS |
446 | set_current_state(TASK_RUNNING); |
447 | remove_wait_queue(&port->open_wait, &wait); | |
448 | if (!tty_hung_up_p(filp)) | |
449 | port->count++; | |
450 | port->blocked_open--; | |
451 | if (retval) | |
452 | return retval; | |
453 | port->flags |= ASYNC_NORMAL_ACTIVE; | |
037ad48b JS |
454 | return 0; |
455 | } | |
456 | ||
a8dea4ec | 457 | static int mxser_set_baud(struct mxser_port *info, long newspd) |
037ad48b | 458 | { |
a8dea4ec JS |
459 | int quot = 0; |
460 | unsigned char cval; | |
461 | int ret = 0; | |
462 | unsigned long flags; | |
037ad48b | 463 | |
a8dea4ec JS |
464 | if (!info->tty || !info->tty->termios) |
465 | return ret; | |
037ad48b | 466 | |
a8dea4ec JS |
467 | if (!(info->ioaddr)) |
468 | return ret; | |
037ad48b | 469 | |
a8dea4ec JS |
470 | if (newspd > info->max_baud) |
471 | return 0; | |
037ad48b | 472 | |
a8dea4ec JS |
473 | info->realbaud = newspd; |
474 | if (newspd == 134) { | |
475 | quot = (2 * info->baud_base / 269); | |
476 | } else if (newspd) { | |
477 | quot = info->baud_base / newspd; | |
478 | if (quot == 0) | |
479 | quot = 1; | |
480 | } else { | |
481 | quot = 0; | |
037ad48b JS |
482 | } |
483 | ||
a8dea4ec JS |
484 | info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base); |
485 | info->timeout += HZ / 50; /* Add .02 seconds of slop */ | |
037ad48b | 486 | |
a8dea4ec JS |
487 | if (quot) { |
488 | spin_lock_irqsave(&info->slock, flags); | |
489 | info->MCR |= UART_MCR_DTR; | |
490 | outb(info->MCR, info->ioaddr + UART_MCR); | |
491 | spin_unlock_irqrestore(&info->slock, flags); | |
492 | } else { | |
493 | spin_lock_irqsave(&info->slock, flags); | |
494 | info->MCR &= ~UART_MCR_DTR; | |
495 | outb(info->MCR, info->ioaddr + UART_MCR); | |
496 | spin_unlock_irqrestore(&info->slock, flags); | |
497 | return ret; | |
037ad48b | 498 | } |
037ad48b | 499 | |
a8dea4ec | 500 | cval = inb(info->ioaddr + UART_LCR); |
037ad48b | 501 | |
a8dea4ec | 502 | outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ |
037ad48b | 503 | |
a8dea4ec JS |
504 | outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ |
505 | outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ | |
506 | outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ | |
037ad48b | 507 | |
037ad48b | 508 | |
a8dea4ec JS |
509 | return ret; |
510 | } | |
037ad48b | 511 | |
a8dea4ec JS |
512 | /* |
513 | * This routine is called to set the UART divisor registers to match | |
514 | * the specified baud rate for a serial port. | |
515 | */ | |
516 | static int mxser_change_speed(struct mxser_port *info, | |
606d099c | 517 | struct ktermios *old_termios) |
a8dea4ec JS |
518 | { |
519 | unsigned cflag, cval, fcr; | |
520 | int ret = 0; | |
521 | unsigned char status; | |
522 | long baud; | |
523 | unsigned long flags; | |
037ad48b | 524 | |
a8dea4ec JS |
525 | if (!info->tty || !info->tty->termios) |
526 | return ret; | |
527 | cflag = info->tty->termios->c_cflag; | |
528 | if (!(info->ioaddr)) | |
529 | return ret; | |
037ad48b | 530 | |
a8dea4ec JS |
531 | if (mxser_set_baud_method[info->tty->index] == 0) { |
532 | baud = tty_get_baud_rate(info->tty); | |
533 | mxser_set_baud(info, baud); | |
534 | } | |
037ad48b | 535 | |
a8dea4ec JS |
536 | /* byte size and parity */ |
537 | switch (cflag & CSIZE) { | |
538 | case CS5: | |
539 | cval = 0x00; | |
540 | break; | |
541 | case CS6: | |
542 | cval = 0x01; | |
543 | break; | |
544 | case CS7: | |
545 | cval = 0x02; | |
546 | break; | |
547 | case CS8: | |
548 | cval = 0x03; | |
549 | break; | |
550 | default: | |
551 | cval = 0x00; | |
552 | break; /* too keep GCC shut... */ | |
553 | } | |
554 | if (cflag & CSTOPB) | |
555 | cval |= 0x04; | |
556 | if (cflag & PARENB) | |
557 | cval |= UART_LCR_PARITY; | |
558 | if (!(cflag & PARODD)) | |
559 | cval |= UART_LCR_EPAR; | |
560 | if (cflag & CMSPAR) | |
561 | cval |= UART_LCR_SPAR; | |
037ad48b | 562 | |
a8dea4ec JS |
563 | if ((info->type == PORT_8250) || (info->type == PORT_16450)) { |
564 | if (info->board->chip_flag) { | |
565 | fcr = UART_FCR_ENABLE_FIFO; | |
566 | fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; | |
567 | SET_MOXA_MUST_FIFO_VALUE(info); | |
568 | } else | |
569 | fcr = 0; | |
570 | } else { | |
571 | fcr = UART_FCR_ENABLE_FIFO; | |
a8dea4ec JS |
572 | if (info->board->chip_flag) { |
573 | fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; | |
574 | SET_MOXA_MUST_FIFO_VALUE(info); | |
575 | } else { | |
a8dea4ec JS |
576 | switch (info->rx_trigger) { |
577 | case 1: | |
578 | fcr |= UART_FCR_TRIGGER_1; | |
579 | break; | |
580 | case 4: | |
581 | fcr |= UART_FCR_TRIGGER_4; | |
582 | break; | |
583 | case 8: | |
584 | fcr |= UART_FCR_TRIGGER_8; | |
585 | break; | |
586 | default: | |
587 | fcr |= UART_FCR_TRIGGER_14; | |
588 | break; | |
589 | } | |
037ad48b | 590 | } |
037ad48b JS |
591 | } |
592 | ||
a8dea4ec JS |
593 | /* CTS flow control flag and modem status interrupts */ |
594 | info->IER &= ~UART_IER_MSI; | |
595 | info->MCR &= ~UART_MCR_AFE; | |
596 | if (cflag & CRTSCTS) { | |
597 | info->flags |= ASYNC_CTS_FLOW; | |
598 | info->IER |= UART_IER_MSI; | |
599 | if ((info->type == PORT_16550A) || (info->board->chip_flag)) { | |
600 | info->MCR |= UART_MCR_AFE; | |
a8dea4ec | 601 | } else { |
a8dea4ec | 602 | status = inb(info->ioaddr + UART_MSR); |
a8dea4ec JS |
603 | if (info->tty->hw_stopped) { |
604 | if (status & UART_MSR_CTS) { | |
605 | info->tty->hw_stopped = 0; | |
606 | if (info->type != PORT_16550A && | |
607 | !info->board->chip_flag) { | |
608 | outb(info->IER & ~UART_IER_THRI, | |
609 | info->ioaddr + | |
610 | UART_IER); | |
611 | info->IER |= UART_IER_THRI; | |
612 | outb(info->IER, info->ioaddr + | |
613 | UART_IER); | |
614 | } | |
615 | set_bit(MXSER_EVENT_TXLOW, &info->event); | |
616 | schedule_work(&info->tqueue); } | |
617 | } else { | |
618 | if (!(status & UART_MSR_CTS)) { | |
619 | info->tty->hw_stopped = 1; | |
620 | if ((info->type != PORT_16550A) && | |
621 | (!info->board->chip_flag)) { | |
622 | info->IER &= ~UART_IER_THRI; | |
623 | outb(info->IER, info->ioaddr + | |
624 | UART_IER); | |
625 | } | |
626 | } | |
627 | } | |
628 | } | |
629 | } else { | |
630 | info->flags &= ~ASYNC_CTS_FLOW; | |
631 | } | |
632 | outb(info->MCR, info->ioaddr + UART_MCR); | |
633 | if (cflag & CLOCAL) { | |
634 | info->flags &= ~ASYNC_CHECK_CD; | |
635 | } else { | |
636 | info->flags |= ASYNC_CHECK_CD; | |
637 | info->IER |= UART_IER_MSI; | |
638 | } | |
639 | outb(info->IER, info->ioaddr + UART_IER); | |
037ad48b | 640 | |
a8dea4ec JS |
641 | /* |
642 | * Set up parity check flag | |
643 | */ | |
644 | info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
645 | if (I_INPCK(info->tty)) | |
646 | info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
647 | if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) | |
648 | info->read_status_mask |= UART_LSR_BI; | |
037ad48b | 649 | |
a8dea4ec | 650 | info->ignore_status_mask = 0; |
037ad48b | 651 | |
a8dea4ec JS |
652 | if (I_IGNBRK(info->tty)) { |
653 | info->ignore_status_mask |= UART_LSR_BI; | |
654 | info->read_status_mask |= UART_LSR_BI; | |
655 | /* | |
656 | * If we're ignore parity and break indicators, ignore | |
657 | * overruns too. (For real raw support). | |
658 | */ | |
659 | if (I_IGNPAR(info->tty)) { | |
660 | info->ignore_status_mask |= | |
661 | UART_LSR_OE | | |
662 | UART_LSR_PE | | |
663 | UART_LSR_FE; | |
664 | info->read_status_mask |= | |
665 | UART_LSR_OE | | |
666 | UART_LSR_PE | | |
667 | UART_LSR_FE; | |
037ad48b | 668 | } |
037ad48b | 669 | } |
a8dea4ec JS |
670 | if (info->board->chip_flag) { |
671 | spin_lock_irqsave(&info->slock, flags); | |
672 | SET_MOXA_MUST_XON1_VALUE(info->ioaddr, START_CHAR(info->tty)); | |
673 | SET_MOXA_MUST_XOFF1_VALUE(info->ioaddr, STOP_CHAR(info->tty)); | |
674 | if (I_IXON(info->tty)) { | |
675 | ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); | |
676 | } else { | |
677 | DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); | |
037ad48b | 678 | } |
a8dea4ec JS |
679 | if (I_IXOFF(info->tty)) { |
680 | ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr); | |
681 | } else { | |
682 | DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr); | |
037ad48b | 683 | } |
a8dea4ec | 684 | spin_unlock_irqrestore(&info->slock, flags); |
037ad48b | 685 | } |
037ad48b | 686 | |
037ad48b | 687 | |
a8dea4ec JS |
688 | outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ |
689 | outb(cval, info->ioaddr + UART_LCR); | |
037ad48b | 690 | |
a8dea4ec | 691 | return ret; |
037ad48b JS |
692 | } |
693 | ||
a8dea4ec | 694 | static void mxser_check_modem_status(struct mxser_port *port, int status) |
037ad48b | 695 | { |
a8dea4ec JS |
696 | /* update input line counters */ |
697 | if (status & UART_MSR_TERI) | |
698 | port->icount.rng++; | |
699 | if (status & UART_MSR_DDSR) | |
700 | port->icount.dsr++; | |
701 | if (status & UART_MSR_DDCD) | |
702 | port->icount.dcd++; | |
703 | if (status & UART_MSR_DCTS) | |
704 | port->icount.cts++; | |
705 | port->mon_data.modem_status = status; | |
706 | wake_up_interruptible(&port->delta_msr_wait); | |
037ad48b | 707 | |
a8dea4ec JS |
708 | if ((port->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) { |
709 | if (status & UART_MSR_DCD) | |
710 | wake_up_interruptible(&port->open_wait); | |
711 | schedule_work(&port->tqueue); | |
712 | } | |
037ad48b | 713 | |
a8dea4ec JS |
714 | if (port->flags & ASYNC_CTS_FLOW) { |
715 | if (port->tty->hw_stopped) { | |
716 | if (status & UART_MSR_CTS) { | |
717 | port->tty->hw_stopped = 0; | |
718 | ||
719 | if ((port->type != PORT_16550A) && | |
720 | (!port->board->chip_flag)) { | |
721 | outb(port->IER & ~UART_IER_THRI, | |
722 | port->ioaddr + UART_IER); | |
723 | port->IER |= UART_IER_THRI; | |
724 | outb(port->IER, port->ioaddr + | |
725 | UART_IER); | |
726 | } | |
727 | set_bit(MXSER_EVENT_TXLOW, &port->event); | |
728 | schedule_work(&port->tqueue); | |
729 | } | |
730 | } else { | |
731 | if (!(status & UART_MSR_CTS)) { | |
732 | port->tty->hw_stopped = 1; | |
733 | if (port->type != PORT_16550A && | |
734 | !port->board->chip_flag) { | |
735 | port->IER &= ~UART_IER_THRI; | |
736 | outb(port->IER, port->ioaddr + | |
737 | UART_IER); | |
738 | } | |
739 | } | |
740 | } | |
741 | } | |
037ad48b JS |
742 | } |
743 | ||
a8dea4ec | 744 | static int mxser_startup(struct mxser_port *info) |
037ad48b | 745 | { |
a8dea4ec JS |
746 | unsigned long page; |
747 | unsigned long flags; | |
037ad48b | 748 | |
a8dea4ec JS |
749 | page = __get_free_page(GFP_KERNEL); |
750 | if (!page) | |
751 | return -ENOMEM; | |
037ad48b | 752 | |
a8dea4ec | 753 | spin_lock_irqsave(&info->slock, flags); |
037ad48b | 754 | |
a8dea4ec JS |
755 | if (info->flags & ASYNC_INITIALIZED) { |
756 | free_page(page); | |
757 | spin_unlock_irqrestore(&info->slock, flags); | |
758 | return 0; | |
759 | } | |
037ad48b | 760 | |
a8dea4ec JS |
761 | if (!info->ioaddr || !info->type) { |
762 | if (info->tty) | |
763 | set_bit(TTY_IO_ERROR, &info->tty->flags); | |
764 | free_page(page); | |
765 | spin_unlock_irqrestore(&info->slock, flags); | |
037ad48b | 766 | return 0; |
a8dea4ec JS |
767 | } |
768 | if (info->xmit_buf) | |
769 | free_page(page); | |
770 | else | |
771 | info->xmit_buf = (unsigned char *) page; | |
037ad48b | 772 | |
037ad48b | 773 | /* |
a8dea4ec JS |
774 | * Clear the FIFO buffers and disable them |
775 | * (they will be reenabled in mxser_change_speed()) | |
037ad48b | 776 | */ |
a8dea4ec JS |
777 | if (info->board->chip_flag) |
778 | outb((UART_FCR_CLEAR_RCVR | | |
779 | UART_FCR_CLEAR_XMIT | | |
780 | MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR); | |
781 | else | |
782 | outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), | |
783 | info->ioaddr + UART_FCR); | |
784 | ||
785 | /* | |
786 | * At this point there's no way the LSR could still be 0xFF; | |
787 | * if it is, then bail out, because there's likely no UART | |
788 | * here. | |
789 | */ | |
790 | if (inb(info->ioaddr + UART_LSR) == 0xff) { | |
791 | spin_unlock_irqrestore(&info->slock, flags); | |
792 | if (capable(CAP_SYS_ADMIN)) { | |
793 | if (info->tty) | |
794 | set_bit(TTY_IO_ERROR, &info->tty->flags); | |
795 | return 0; | |
796 | } else | |
797 | return -ENODEV; | |
798 | } | |
799 | ||
800 | /* | |
801 | * Clear the interrupt registers. | |
802 | */ | |
803 | (void) inb(info->ioaddr + UART_LSR); | |
804 | (void) inb(info->ioaddr + UART_RX); | |
805 | (void) inb(info->ioaddr + UART_IIR); | |
806 | (void) inb(info->ioaddr + UART_MSR); | |
807 | ||
808 | /* | |
809 | * Now, initialize the UART | |
810 | */ | |
811 | outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ | |
812 | info->MCR = UART_MCR_DTR | UART_MCR_RTS; | |
813 | outb(info->MCR, info->ioaddr + UART_MCR); | |
814 | ||
815 | /* | |
816 | * Finally, enable interrupts | |
817 | */ | |
818 | info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; | |
a8dea4ec | 819 | |
a8dea4ec JS |
820 | if (info->board->chip_flag) |
821 | info->IER |= MOXA_MUST_IER_EGDAI; | |
a8dea4ec JS |
822 | outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ |
823 | ||
824 | /* | |
825 | * And clear the interrupt registers again for luck. | |
826 | */ | |
827 | (void) inb(info->ioaddr + UART_LSR); | |
828 | (void) inb(info->ioaddr + UART_RX); | |
829 | (void) inb(info->ioaddr + UART_IIR); | |
830 | (void) inb(info->ioaddr + UART_MSR); | |
831 | ||
832 | if (info->tty) | |
833 | clear_bit(TTY_IO_ERROR, &info->tty->flags); | |
834 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | |
835 | ||
836 | /* | |
837 | * and set the speed of the serial port | |
838 | */ | |
839 | spin_unlock_irqrestore(&info->slock, flags); | |
840 | mxser_change_speed(info, NULL); | |
841 | ||
842 | info->flags |= ASYNC_INITIALIZED; | |
843 | return 0; | |
844 | } | |
845 | ||
846 | /* | |
847 | * This routine will shutdown a serial port; interrupts maybe disabled, and | |
848 | * DTR is dropped if the hangup on close termio flag is on. | |
849 | */ | |
850 | static void mxser_shutdown(struct mxser_port *info) | |
851 | { | |
852 | unsigned long flags; | |
853 | ||
854 | if (!(info->flags & ASYNC_INITIALIZED)) | |
855 | return; | |
856 | ||
857 | spin_lock_irqsave(&info->slock, flags); | |
858 | ||
859 | /* | |
860 | * clear delta_msr_wait queue to avoid mem leaks: we may free the irq | |
861 | * here so the queue might never be waken up | |
862 | */ | |
863 | wake_up_interruptible(&info->delta_msr_wait); | |
864 | ||
865 | /* | |
866 | * Free the IRQ, if necessary | |
867 | */ | |
868 | if (info->xmit_buf) { | |
869 | free_page((unsigned long) info->xmit_buf); | |
870 | info->xmit_buf = NULL; | |
871 | } | |
872 | ||
873 | info->IER = 0; | |
874 | outb(0x00, info->ioaddr + UART_IER); | |
875 | ||
876 | if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) | |
877 | info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS); | |
878 | outb(info->MCR, info->ioaddr + UART_MCR); | |
879 | ||
880 | /* clear Rx/Tx FIFO's */ | |
a8dea4ec JS |
881 | if (info->board->chip_flag) |
882 | outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | | |
883 | MOXA_MUST_FCR_GDA_MODE_ENABLE, | |
884 | info->ioaddr + UART_FCR); | |
885 | else | |
a8dea4ec JS |
886 | outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, |
887 | info->ioaddr + UART_FCR); | |
888 | ||
889 | /* read data port to reset things */ | |
890 | (void) inb(info->ioaddr + UART_RX); | |
891 | ||
892 | if (info->tty) | |
893 | set_bit(TTY_IO_ERROR, &info->tty->flags); | |
894 | ||
895 | info->flags &= ~ASYNC_INITIALIZED; | |
896 | ||
a8dea4ec JS |
897 | if (info->board->chip_flag) |
898 | SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr); | |
a8dea4ec JS |
899 | |
900 | spin_unlock_irqrestore(&info->slock, flags); | |
901 | } | |
902 | ||
903 | /* | |
904 | * This routine is called whenever a serial port is opened. It | |
905 | * enables interrupts for a serial port, linking in its async structure into | |
906 | * the IRQ chain. It also performs the serial-specific | |
907 | * initialization for the tty structure. | |
908 | */ | |
909 | static int mxser_open(struct tty_struct *tty, struct file *filp) | |
910 | { | |
911 | struct mxser_port *info; | |
912 | int retval, line; | |
913 | ||
914 | /* initialize driver_data in case something fails */ | |
915 | tty->driver_data = NULL; | |
916 | ||
917 | line = tty->index; | |
918 | if (line == MXSER_PORTS) | |
919 | return 0; | |
920 | if (line < 0 || line > MXSER_PORTS) | |
921 | return -ENODEV; | |
922 | info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD]; | |
923 | if (!info->ioaddr) | |
924 | return -ENODEV; | |
925 | ||
926 | tty->driver_data = info; | |
927 | info->tty = tty; | |
928 | /* | |
929 | * Start up serial port | |
930 | */ | |
931 | info->count++; | |
932 | retval = mxser_startup(info); | |
933 | if (retval) | |
934 | return retval; | |
935 | ||
936 | retval = mxser_block_til_ready(tty, filp, info); | |
937 | if (retval) | |
938 | return retval; | |
939 | ||
940 | if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) { | |
037ad48b JS |
941 | if (tty->driver->subtype == SERIAL_TYPE_NORMAL) |
942 | *tty->termios = info->normal_termios; | |
943 | else | |
944 | *tty->termios = info->callout_termios; | |
945 | mxser_change_speed(info, NULL); | |
946 | } | |
947 | ||
08a4ae44 | 948 | info->session = process_session(current); |
037ad48b JS |
949 | info->pgrp = process_group(current); |
950 | ||
e079f495 | 951 | /* unmark here for very high baud rate (ex. 921600 bps) used */ |
037ad48b JS |
952 | tty->low_latency = 1; |
953 | return 0; | |
954 | } | |
955 | ||
956 | /* | |
957 | * This routine is called when the serial port gets closed. First, we | |
958 | * wait for the last remaining data to be sent. Then, we unlink its | |
959 | * async structure from the interrupt chain if necessary, and we free | |
960 | * that IRQ if nothing is left in the chain. | |
961 | */ | |
962 | static void mxser_close(struct tty_struct *tty, struct file *filp) | |
963 | { | |
55b307da | 964 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
965 | |
966 | unsigned long timeout; | |
967 | unsigned long flags; | |
037ad48b JS |
968 | |
969 | if (tty->index == MXSER_PORTS) | |
970 | return; | |
971 | if (!info) | |
972 | return; | |
973 | ||
974 | spin_lock_irqsave(&info->slock, flags); | |
975 | ||
976 | if (tty_hung_up_p(filp)) { | |
977 | spin_unlock_irqrestore(&info->slock, flags); | |
978 | return; | |
979 | } | |
980 | if ((tty->count == 1) && (info->count != 1)) { | |
981 | /* | |
982 | * Uh, oh. tty->count is 1, which means that the tty | |
983 | * structure will be freed. Info->count should always | |
984 | * be one in these conditions. If it's greater than | |
985 | * one, we've got real problems, since it means the | |
986 | * serial port won't be shutdown. | |
987 | */ | |
988 | printk(KERN_ERR "mxser_close: bad serial port count; " | |
989 | "tty->count is 1, info->count is %d\n", info->count); | |
990 | info->count = 1; | |
991 | } | |
992 | if (--info->count < 0) { | |
993 | printk(KERN_ERR "mxser_close: bad serial port count for " | |
55b307da | 994 | "ttys%d: %d\n", tty->index, info->count); |
037ad48b JS |
995 | info->count = 0; |
996 | } | |
997 | if (info->count) { | |
998 | spin_unlock_irqrestore(&info->slock, flags); | |
999 | return; | |
1000 | } | |
1001 | info->flags |= ASYNC_CLOSING; | |
1002 | spin_unlock_irqrestore(&info->slock, flags); | |
1003 | /* | |
1004 | * Save the termios structure, since this port may have | |
1005 | * separate termios for callout and dialin. | |
1006 | */ | |
1007 | if (info->flags & ASYNC_NORMAL_ACTIVE) | |
1008 | info->normal_termios = *tty->termios; | |
1009 | /* | |
1010 | * Now we wait for the transmit buffer to clear; and we notify | |
1011 | * the line discipline to only process XON/XOFF characters. | |
1012 | */ | |
1013 | tty->closing = 1; | |
1014 | if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) | |
1015 | tty_wait_until_sent(tty, info->closing_wait); | |
1016 | /* | |
1017 | * At this point we stop accepting input. To do this, we | |
1018 | * disable the receive line status interrupts, and tell the | |
1019 | * interrupt driver to stop checking the data ready bit in the | |
1020 | * line status register. | |
1021 | */ | |
1022 | info->IER &= ~UART_IER_RLSI; | |
55b307da | 1023 | if (info->board->chip_flag) |
037ad48b | 1024 | info->IER &= ~MOXA_MUST_RECV_ISR; |
e079f495 | 1025 | |
037ad48b | 1026 | if (info->flags & ASYNC_INITIALIZED) { |
55b307da | 1027 | outb(info->IER, info->ioaddr + UART_IER); |
037ad48b JS |
1028 | /* |
1029 | * Before we drop DTR, make sure the UART transmitter | |
1030 | * has completely drained; this is especially | |
1031 | * important if there is a transmit FIFO! | |
1032 | */ | |
1033 | timeout = jiffies + HZ; | |
55b307da | 1034 | while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) { |
037ad48b JS |
1035 | schedule_timeout_interruptible(5); |
1036 | if (time_after(jiffies, timeout)) | |
1037 | break; | |
1038 | } | |
1039 | } | |
1040 | mxser_shutdown(info); | |
1041 | ||
1042 | if (tty->driver->flush_buffer) | |
1043 | tty->driver->flush_buffer(tty); | |
1044 | ||
7e8bcf9a | 1045 | tty_ldisc_flush(tty); |
037ad48b JS |
1046 | |
1047 | tty->closing = 0; | |
1048 | info->event = 0; | |
1049 | info->tty = NULL; | |
1050 | if (info->blocked_open) { | |
1051 | if (info->close_delay) | |
1052 | schedule_timeout_interruptible(info->close_delay); | |
1053 | wake_up_interruptible(&info->open_wait); | |
1054 | } | |
1055 | ||
1056 | info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING); | |
1057 | wake_up_interruptible(&info->close_wait); | |
1058 | ||
1059 | } | |
1060 | ||
1061 | static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) | |
1062 | { | |
1063 | int c, total = 0; | |
55b307da | 1064 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
1065 | unsigned long flags; |
1066 | ||
1067 | if (!info->xmit_buf) | |
1068 | return 0; | |
1069 | ||
1070 | while (1) { | |
1071 | c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, | |
1072 | SERIAL_XMIT_SIZE - info->xmit_head)); | |
1073 | if (c <= 0) | |
1074 | break; | |
1075 | ||
1076 | memcpy(info->xmit_buf + info->xmit_head, buf, c); | |
1077 | spin_lock_irqsave(&info->slock, flags); | |
1078 | info->xmit_head = (info->xmit_head + c) & | |
1079 | (SERIAL_XMIT_SIZE - 1); | |
1080 | info->xmit_cnt += c; | |
1081 | spin_unlock_irqrestore(&info->slock, flags); | |
1082 | ||
1083 | buf += c; | |
1084 | count -= c; | |
1085 | total += c; | |
1086 | } | |
1087 | ||
e079f495 | 1088 | if (info->xmit_cnt && !tty->stopped) { |
037ad48b JS |
1089 | if (!tty->hw_stopped || |
1090 | (info->type == PORT_16550A) || | |
55b307da | 1091 | (info->board->chip_flag)) { |
037ad48b | 1092 | spin_lock_irqsave(&info->slock, flags); |
55b307da JS |
1093 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + |
1094 | UART_IER); | |
037ad48b | 1095 | info->IER |= UART_IER_THRI; |
55b307da | 1096 | outb(info->IER, info->ioaddr + UART_IER); |
037ad48b JS |
1097 | spin_unlock_irqrestore(&info->slock, flags); |
1098 | } | |
1099 | } | |
1100 | return total; | |
1101 | } | |
1102 | ||
1103 | static void mxser_put_char(struct tty_struct *tty, unsigned char ch) | |
1104 | { | |
55b307da | 1105 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
1106 | unsigned long flags; |
1107 | ||
1108 | if (!info->xmit_buf) | |
1109 | return; | |
1110 | ||
1111 | if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) | |
1112 | return; | |
1113 | ||
1114 | spin_lock_irqsave(&info->slock, flags); | |
1115 | info->xmit_buf[info->xmit_head++] = ch; | |
1116 | info->xmit_head &= SERIAL_XMIT_SIZE - 1; | |
1117 | info->xmit_cnt++; | |
1118 | spin_unlock_irqrestore(&info->slock, flags); | |
e079f495 | 1119 | if (!tty->stopped) { |
037ad48b JS |
1120 | if (!tty->hw_stopped || |
1121 | (info->type == PORT_16550A) || | |
55b307da | 1122 | info->board->chip_flag) { |
037ad48b | 1123 | spin_lock_irqsave(&info->slock, flags); |
55b307da | 1124 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); |
037ad48b | 1125 | info->IER |= UART_IER_THRI; |
55b307da | 1126 | outb(info->IER, info->ioaddr + UART_IER); |
037ad48b JS |
1127 | spin_unlock_irqrestore(&info->slock, flags); |
1128 | } | |
1129 | } | |
1130 | } | |
1131 | ||
1132 | ||
1133 | static void mxser_flush_chars(struct tty_struct *tty) | |
1134 | { | |
55b307da | 1135 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
1136 | unsigned long flags; |
1137 | ||
1138 | if (info->xmit_cnt <= 0 || | |
1139 | tty->stopped || | |
1140 | !info->xmit_buf || | |
1141 | (tty->hw_stopped && | |
1142 | (info->type != PORT_16550A) && | |
55b307da | 1143 | (!info->board->chip_flag) |
037ad48b JS |
1144 | )) |
1145 | return; | |
1146 | ||
1147 | spin_lock_irqsave(&info->slock, flags); | |
1148 | ||
55b307da | 1149 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); |
037ad48b | 1150 | info->IER |= UART_IER_THRI; |
55b307da | 1151 | outb(info->IER, info->ioaddr + UART_IER); |
037ad48b JS |
1152 | |
1153 | spin_unlock_irqrestore(&info->slock, flags); | |
1154 | } | |
1155 | ||
1156 | static int mxser_write_room(struct tty_struct *tty) | |
1157 | { | |
55b307da | 1158 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
1159 | int ret; |
1160 | ||
1161 | ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; | |
1162 | if (ret < 0) | |
1163 | ret = 0; | |
1164 | return ret; | |
1165 | } | |
1166 | ||
1167 | static int mxser_chars_in_buffer(struct tty_struct *tty) | |
1168 | { | |
55b307da | 1169 | struct mxser_port *info = tty->driver_data; |
925e9c1c | 1170 | return info->xmit_cnt; |
037ad48b JS |
1171 | } |
1172 | ||
1173 | static void mxser_flush_buffer(struct tty_struct *tty) | |
1174 | { | |
55b307da | 1175 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
1176 | char fcr; |
1177 | unsigned long flags; | |
1178 | ||
1179 | ||
1180 | spin_lock_irqsave(&info->slock, flags); | |
1181 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | |
1182 | ||
55b307da | 1183 | fcr = inb(info->ioaddr + UART_FCR); |
037ad48b | 1184 | outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), |
55b307da JS |
1185 | info->ioaddr + UART_FCR); |
1186 | outb(fcr, info->ioaddr + UART_FCR); | |
037ad48b JS |
1187 | |
1188 | spin_unlock_irqrestore(&info->slock, flags); | |
037ad48b | 1189 | |
7e8bcf9a | 1190 | tty_wakeup(tty); |
037ad48b JS |
1191 | } |
1192 | ||
a8dea4ec JS |
1193 | /* |
1194 | * ------------------------------------------------------------ | |
1195 | * friends of mxser_ioctl() | |
1196 | * ------------------------------------------------------------ | |
1197 | */ | |
1198 | static int mxser_get_serial_info(struct mxser_port *info, | |
1199 | struct serial_struct __user *retinfo) | |
037ad48b | 1200 | { |
a8dea4ec | 1201 | struct serial_struct tmp; |
037ad48b | 1202 | |
a8dea4ec JS |
1203 | if (!retinfo) |
1204 | return -EFAULT; | |
1205 | memset(&tmp, 0, sizeof(tmp)); | |
1206 | tmp.type = info->type; | |
1207 | tmp.line = info->tty->index; | |
1208 | tmp.port = info->ioaddr; | |
1209 | tmp.irq = info->board->irq; | |
1210 | tmp.flags = info->flags; | |
1211 | tmp.baud_base = info->baud_base; | |
1212 | tmp.close_delay = info->close_delay; | |
1213 | tmp.closing_wait = info->closing_wait; | |
1214 | tmp.custom_divisor = info->custom_divisor; | |
1215 | tmp.hub6 = 0; | |
1216 | if (copy_to_user(retinfo, &tmp, sizeof(*retinfo))) | |
1217 | return -EFAULT; | |
1218 | return 0; | |
1219 | } | |
037ad48b | 1220 | |
a8dea4ec JS |
1221 | static int mxser_set_serial_info(struct mxser_port *info, |
1222 | struct serial_struct __user *new_info) | |
1223 | { | |
1224 | struct serial_struct new_serial; | |
1225 | unsigned int flags; | |
1226 | int retval = 0; | |
037ad48b | 1227 | |
a8dea4ec JS |
1228 | if (!new_info || !info->ioaddr) |
1229 | return -EFAULT; | |
1230 | if (copy_from_user(&new_serial, new_info, sizeof(new_serial))) | |
1231 | return -EFAULT; | |
037ad48b | 1232 | |
a8dea4ec JS |
1233 | if ((new_serial.irq != info->board->irq) || |
1234 | (new_serial.port != info->ioaddr) || | |
1235 | (new_serial.custom_divisor != info->custom_divisor) || | |
1236 | (new_serial.baud_base != info->baud_base)) | |
1237 | return -EPERM; | |
037ad48b | 1238 | |
a8dea4ec JS |
1239 | flags = info->flags & ASYNC_SPD_MASK; |
1240 | ||
1241 | if (!capable(CAP_SYS_ADMIN)) { | |
1242 | if ((new_serial.baud_base != info->baud_base) || | |
1243 | (new_serial.close_delay != info->close_delay) || | |
1244 | ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK))) | |
1245 | return -EPERM; | |
1246 | info->flags = ((info->flags & ~ASYNC_USR_MASK) | | |
1247 | (new_serial.flags & ASYNC_USR_MASK)); | |
1248 | } else { | |
037ad48b | 1249 | /* |
a8dea4ec JS |
1250 | * OK, past this point, all the error checking has been done. |
1251 | * At this point, we start making changes..... | |
037ad48b | 1252 | */ |
a8dea4ec JS |
1253 | info->flags = ((info->flags & ~ASYNC_FLAGS) | |
1254 | (new_serial.flags & ASYNC_FLAGS)); | |
1255 | info->close_delay = new_serial.close_delay * HZ / 100; | |
1256 | info->closing_wait = new_serial.closing_wait * HZ / 100; | |
1257 | info->tty->low_latency = | |
1258 | (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; | |
e079f495 | 1259 | info->tty->low_latency = 0; |
a8dea4ec | 1260 | } |
037ad48b | 1261 | |
a8dea4ec | 1262 | info->type = new_serial.type; |
037ad48b | 1263 | |
a8dea4ec JS |
1264 | process_txrx_fifo(info); |
1265 | ||
1266 | if (info->flags & ASYNC_INITIALIZED) { | |
1267 | if (flags != (info->flags & ASYNC_SPD_MASK)) | |
1268 | mxser_change_speed(info, NULL); | |
1269 | } else | |
1270 | retval = mxser_startup(info); | |
1271 | ||
1272 | return retval; | |
1273 | } | |
037ad48b | 1274 | |
a8dea4ec JS |
1275 | /* |
1276 | * mxser_get_lsr_info - get line status register info | |
1277 | * | |
1278 | * Purpose: Let user call ioctl() to get info when the UART physically | |
1279 | * is emptied. On bus types like RS485, the transmitter must | |
1280 | * release the bus after transmitting. This must be done when | |
1281 | * the transmit shift register is empty, not be done when the | |
1282 | * transmit holding register is empty. This functionality | |
1283 | * allows an RS485 driver to be written in user space. | |
1284 | */ | |
1285 | static int mxser_get_lsr_info(struct mxser_port *info, | |
1286 | unsigned int __user *value) | |
1287 | { | |
1288 | unsigned char status; | |
1289 | unsigned int result; | |
1290 | unsigned long flags; | |
037ad48b | 1291 | |
a8dea4ec JS |
1292 | spin_lock_irqsave(&info->slock, flags); |
1293 | status = inb(info->ioaddr + UART_LSR); | |
1294 | spin_unlock_irqrestore(&info->slock, flags); | |
1295 | result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); | |
1296 | return put_user(result, value); | |
1297 | } | |
037ad48b | 1298 | |
a8dea4ec JS |
1299 | /* |
1300 | * This routine sends a break character out the serial port. | |
1301 | */ | |
1302 | static void mxser_send_break(struct mxser_port *info, int duration) | |
1303 | { | |
1304 | unsigned long flags; | |
037ad48b | 1305 | |
a8dea4ec JS |
1306 | if (!info->ioaddr) |
1307 | return; | |
1308 | set_current_state(TASK_INTERRUPTIBLE); | |
1309 | spin_lock_irqsave(&info->slock, flags); | |
1310 | outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, | |
1311 | info->ioaddr + UART_LCR); | |
1312 | spin_unlock_irqrestore(&info->slock, flags); | |
1313 | schedule_timeout(duration); | |
1314 | spin_lock_irqsave(&info->slock, flags); | |
1315 | outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, | |
1316 | info->ioaddr + UART_LCR); | |
1317 | spin_unlock_irqrestore(&info->slock, flags); | |
1318 | } | |
037ad48b | 1319 | |
a8dea4ec JS |
1320 | static int mxser_tiocmget(struct tty_struct *tty, struct file *file) |
1321 | { | |
1322 | struct mxser_port *info = tty->driver_data; | |
1323 | unsigned char control, status; | |
1324 | unsigned long flags; | |
037ad48b | 1325 | |
037ad48b | 1326 | |
a8dea4ec JS |
1327 | if (tty->index == MXSER_PORTS) |
1328 | return -ENOIOCTLCMD; | |
214efebb | 1329 | if (test_bit(TTY_IO_ERROR, &tty->flags)) |
a8dea4ec | 1330 | return -EIO; |
037ad48b | 1331 | |
a8dea4ec | 1332 | control = info->MCR; |
037ad48b | 1333 | |
a8dea4ec JS |
1334 | spin_lock_irqsave(&info->slock, flags); |
1335 | status = inb(info->ioaddr + UART_MSR); | |
1336 | if (status & UART_MSR_ANY_DELTA) | |
1337 | mxser_check_modem_status(info, status); | |
1338 | spin_unlock_irqrestore(&info->slock, flags); | |
1339 | return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | | |
1340 | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | | |
1341 | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) | | |
1342 | ((status & UART_MSR_RI) ? TIOCM_RNG : 0) | | |
1343 | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) | | |
1344 | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); | |
1345 | } | |
037ad48b | 1346 | |
a8dea4ec JS |
1347 | static int mxser_tiocmset(struct tty_struct *tty, struct file *file, |
1348 | unsigned int set, unsigned int clear) | |
1349 | { | |
1350 | struct mxser_port *info = tty->driver_data; | |
1351 | unsigned long flags; | |
037ad48b | 1352 | |
037ad48b | 1353 | |
a8dea4ec JS |
1354 | if (tty->index == MXSER_PORTS) |
1355 | return -ENOIOCTLCMD; | |
214efebb | 1356 | if (test_bit(TTY_IO_ERROR, &tty->flags)) |
a8dea4ec | 1357 | return -EIO; |
037ad48b | 1358 | |
a8dea4ec | 1359 | spin_lock_irqsave(&info->slock, flags); |
037ad48b | 1360 | |
a8dea4ec JS |
1361 | if (set & TIOCM_RTS) |
1362 | info->MCR |= UART_MCR_RTS; | |
1363 | if (set & TIOCM_DTR) | |
1364 | info->MCR |= UART_MCR_DTR; | |
037ad48b | 1365 | |
a8dea4ec JS |
1366 | if (clear & TIOCM_RTS) |
1367 | info->MCR &= ~UART_MCR_RTS; | |
1368 | if (clear & TIOCM_DTR) | |
1369 | info->MCR &= ~UART_MCR_DTR; | |
037ad48b | 1370 | |
a8dea4ec JS |
1371 | outb(info->MCR, info->ioaddr + UART_MCR); |
1372 | spin_unlock_irqrestore(&info->slock, flags); | |
037ad48b JS |
1373 | return 0; |
1374 | } | |
1375 | ||
a8dea4ec | 1376 | static int mxser_program_mode(int port) |
037ad48b | 1377 | { |
a8dea4ec | 1378 | int id, i, j, n; |
037ad48b | 1379 | |
a8dea4ec JS |
1380 | spin_lock(&gm_lock); |
1381 | outb(0, port); | |
1382 | outb(0, port); | |
1383 | outb(0, port); | |
1384 | (void)inb(port); | |
1385 | (void)inb(port); | |
1386 | outb(0, port); | |
1387 | (void)inb(port); | |
a8dea4ec | 1388 | spin_unlock(&gm_lock); |
037ad48b | 1389 | |
a8dea4ec JS |
1390 | id = inb(port + 1) & 0x1F; |
1391 | if ((id != C168_ASIC_ID) && | |
1392 | (id != C104_ASIC_ID) && | |
1393 | (id != C102_ASIC_ID) && | |
1394 | (id != CI132_ASIC_ID) && | |
1395 | (id != CI134_ASIC_ID) && | |
1396 | (id != CI104J_ASIC_ID)) | |
1397 | return -1; | |
1398 | for (i = 0, j = 0; i < 4; i++) { | |
1399 | n = inb(port + 2); | |
1400 | if (n == 'M') { | |
1401 | j = 1; | |
1402 | } else if ((j == 1) && (n == 1)) { | |
1403 | j = 2; | |
1404 | break; | |
1405 | } else | |
1406 | j = 0; | |
1407 | } | |
1408 | if (j != 2) | |
1409 | id = -2; | |
1410 | return id; | |
1411 | } | |
1412 | ||
1413 | static void mxser_normal_mode(int port) | |
1414 | { | |
1415 | int i, n; | |
1416 | ||
1417 | outb(0xA5, port + 1); | |
1418 | outb(0x80, port + 3); | |
1419 | outb(12, port + 0); /* 9600 bps */ | |
1420 | outb(0, port + 1); | |
1421 | outb(0x03, port + 3); /* 8 data bits */ | |
1422 | outb(0x13, port + 4); /* loop back mode */ | |
1423 | for (i = 0; i < 16; i++) { | |
1424 | n = inb(port + 5); | |
1425 | if ((n & 0x61) == 0x60) | |
1426 | break; | |
1427 | if ((n & 1) == 1) | |
1428 | (void)inb(port); | |
1429 | } | |
1430 | outb(0x00, port + 4); | |
1431 | } | |
1432 | ||
1433 | #define CHIP_SK 0x01 /* Serial Data Clock in Eprom */ | |
1434 | #define CHIP_DO 0x02 /* Serial Data Output in Eprom */ | |
1435 | #define CHIP_CS 0x04 /* Serial Chip Select in Eprom */ | |
1436 | #define CHIP_DI 0x08 /* Serial Data Input in Eprom */ | |
1437 | #define EN_CCMD 0x000 /* Chip's command register */ | |
1438 | #define EN0_RSARLO 0x008 /* Remote start address reg 0 */ | |
1439 | #define EN0_RSARHI 0x009 /* Remote start address reg 1 */ | |
1440 | #define EN0_RCNTLO 0x00A /* Remote byte count reg WR */ | |
1441 | #define EN0_RCNTHI 0x00B /* Remote byte count reg WR */ | |
1442 | #define EN0_DCFG 0x00E /* Data configuration reg WR */ | |
1443 | #define EN0_PORT 0x010 /* Rcv missed frame error counter RD */ | |
1444 | #define ENC_PAGE0 0x000 /* Select page 0 of chip registers */ | |
1445 | #define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */ | |
1446 | static int mxser_read_register(int port, unsigned short *regs) | |
1447 | { | |
1448 | int i, k, value, id; | |
1449 | unsigned int j; | |
1450 | ||
1451 | id = mxser_program_mode(port); | |
1452 | if (id < 0) | |
1453 | return id; | |
1454 | for (i = 0; i < 14; i++) { | |
1455 | k = (i & 0x3F) | 0x180; | |
1456 | for (j = 0x100; j > 0; j >>= 1) { | |
1457 | outb(CHIP_CS, port); | |
1458 | if (k & j) { | |
1459 | outb(CHIP_CS | CHIP_DO, port); | |
1460 | outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */ | |
1461 | } else { | |
1462 | outb(CHIP_CS, port); | |
1463 | outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */ | |
1464 | } | |
1465 | } | |
1466 | (void)inb(port); | |
1467 | value = 0; | |
1468 | for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) { | |
1469 | outb(CHIP_CS, port); | |
1470 | outb(CHIP_CS | CHIP_SK, port); | |
1471 | if (inb(port) & CHIP_DI) | |
1472 | value |= j; | |
1473 | } | |
1474 | regs[i] = value; | |
1475 | outb(0, port); | |
1476 | } | |
1477 | mxser_normal_mode(port); | |
1478 | return id; | |
1479 | } | |
1480 | ||
a8dea4ec JS |
1481 | static int mxser_ioctl_special(unsigned int cmd, void __user *argp) |
1482 | { | |
1483 | struct mxser_port *port; | |
1484 | int result, status; | |
1485 | unsigned int i, j; | |
1486 | ||
1487 | switch (cmd) { | |
1488 | case MOXA_GET_CONF: | |
1489 | /* if (copy_to_user(argp, mxsercfg, | |
1490 | sizeof(struct mxser_hwconf) * 4)) | |
1491 | return -EFAULT; | |
1492 | return 0;*/ | |
1493 | return -ENXIO; | |
1494 | case MOXA_GET_MAJOR: | |
1495 | if (copy_to_user(argp, &ttymajor, sizeof(int))) | |
1496 | return -EFAULT; | |
1497 | return 0; | |
1498 | ||
1499 | case MOXA_GET_CUMAJOR: | |
1500 | if (copy_to_user(argp, &calloutmajor, sizeof(int))) | |
037ad48b JS |
1501 | return -EFAULT; |
1502 | return 0; | |
1503 | ||
1504 | case MOXA_CHKPORTENABLE: | |
1505 | result = 0; | |
55b307da JS |
1506 | |
1507 | for (i = 0; i < MXSER_BOARDS; i++) | |
1508 | for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) | |
1509 | if (mxser_boards[i].ports[j].ioaddr) | |
1510 | result |= (1 << i); | |
1511 | ||
037ad48b JS |
1512 | return put_user(result, (unsigned long __user *)argp); |
1513 | case MOXA_GETDATACOUNT: | |
1514 | if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log))) | |
1515 | return -EFAULT; | |
1516 | return 0; | |
1517 | case MOXA_GETMSTATUS: | |
55b307da JS |
1518 | for (i = 0; i < MXSER_BOARDS; i++) |
1519 | for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) { | |
1520 | port = &mxser_boards[i].ports[j]; | |
1521 | ||
1522 | GMStatus[i].ri = 0; | |
1523 | if (!port->ioaddr) { | |
1524 | GMStatus[i].dcd = 0; | |
1525 | GMStatus[i].dsr = 0; | |
1526 | GMStatus[i].cts = 0; | |
1527 | continue; | |
1528 | } | |
037ad48b | 1529 | |
55b307da JS |
1530 | if (!port->tty || !port->tty->termios) |
1531 | GMStatus[i].cflag = | |
1532 | port->normal_termios.c_cflag; | |
1533 | else | |
1534 | GMStatus[i].cflag = | |
1535 | port->tty->termios->c_cflag; | |
037ad48b | 1536 | |
55b307da JS |
1537 | status = inb(port->ioaddr + UART_MSR); |
1538 | if (status & 0x80 /*UART_MSR_DCD */ ) | |
1539 | GMStatus[i].dcd = 1; | |
1540 | else | |
1541 | GMStatus[i].dcd = 0; | |
037ad48b | 1542 | |
55b307da JS |
1543 | if (status & 0x20 /*UART_MSR_DSR */ ) |
1544 | GMStatus[i].dsr = 1; | |
1545 | else | |
1546 | GMStatus[i].dsr = 0; | |
037ad48b JS |
1547 | |
1548 | ||
55b307da JS |
1549 | if (status & 0x10 /*UART_MSR_CTS */ ) |
1550 | GMStatus[i].cts = 1; | |
1551 | else | |
1552 | GMStatus[i].cts = 0; | |
1553 | } | |
037ad48b JS |
1554 | if (copy_to_user(argp, GMStatus, |
1555 | sizeof(struct mxser_mstatus) * MXSER_PORTS)) | |
1556 | return -EFAULT; | |
1557 | return 0; | |
1558 | case MOXA_ASPP_MON_EXT: { | |
55b307da JS |
1559 | int status, p, shiftbit; |
1560 | unsigned long opmode; | |
1561 | unsigned cflag, iflag; | |
037ad48b | 1562 | |
55b307da JS |
1563 | for (i = 0; i < MXSER_BOARDS; i++) |
1564 | for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) { | |
1565 | port = &mxser_boards[i].ports[j]; | |
1566 | if (!port->ioaddr) | |
037ad48b JS |
1567 | continue; |
1568 | ||
55b307da | 1569 | status = mxser_get_msr(port->ioaddr, 0, i); |
55b307da | 1570 | |
037ad48b | 1571 | if (status & UART_MSR_TERI) |
55b307da | 1572 | port->icount.rng++; |
037ad48b | 1573 | if (status & UART_MSR_DDSR) |
55b307da | 1574 | port->icount.dsr++; |
037ad48b | 1575 | if (status & UART_MSR_DDCD) |
55b307da | 1576 | port->icount.dcd++; |
037ad48b | 1577 | if (status & UART_MSR_DCTS) |
55b307da JS |
1578 | port->icount.cts++; |
1579 | ||
1580 | port->mon_data.modem_status = status; | |
1581 | mon_data_ext.rx_cnt[i] = port->mon_data.rxcnt; | |
1582 | mon_data_ext.tx_cnt[i] = port->mon_data.txcnt; | |
1583 | mon_data_ext.up_rxcnt[i] = | |
1584 | port->mon_data.up_rxcnt; | |
1585 | mon_data_ext.up_txcnt[i] = | |
1586 | port->mon_data.up_txcnt; | |
1587 | mon_data_ext.modem_status[i] = | |
1588 | port->mon_data.modem_status; | |
1589 | mon_data_ext.baudrate[i] = port->realbaud; | |
1590 | ||
1591 | if (!port->tty || !port->tty->termios) { | |
1592 | cflag = port->normal_termios.c_cflag; | |
1593 | iflag = port->normal_termios.c_iflag; | |
037ad48b | 1594 | } else { |
55b307da JS |
1595 | cflag = port->tty->termios->c_cflag; |
1596 | iflag = port->tty->termios->c_iflag; | |
037ad48b JS |
1597 | } |
1598 | ||
1599 | mon_data_ext.databits[i] = cflag & CSIZE; | |
1600 | ||
1601 | mon_data_ext.stopbits[i] = cflag & CSTOPB; | |
1602 | ||
55b307da JS |
1603 | mon_data_ext.parity[i] = |
1604 | cflag & (PARENB | PARODD | CMSPAR); | |
037ad48b JS |
1605 | |
1606 | mon_data_ext.flowctrl[i] = 0x00; | |
1607 | ||
1608 | if (cflag & CRTSCTS) | |
1609 | mon_data_ext.flowctrl[i] |= 0x03; | |
1610 | ||
1611 | if (iflag & (IXON | IXOFF)) | |
1612 | mon_data_ext.flowctrl[i] |= 0x0C; | |
1613 | ||
55b307da | 1614 | if (port->type == PORT_16550A) |
037ad48b JS |
1615 | mon_data_ext.fifo[i] = 1; |
1616 | else | |
1617 | mon_data_ext.fifo[i] = 0; | |
1618 | ||
1619 | p = i % 4; | |
1620 | shiftbit = p * 2; | |
55b307da | 1621 | opmode = inb(port->opmode_ioaddr) >> shiftbit; |
037ad48b JS |
1622 | opmode &= OP_MODE_MASK; |
1623 | ||
1624 | mon_data_ext.iftype[i] = opmode; | |
1625 | ||
1626 | } | |
55b307da JS |
1627 | if (copy_to_user(argp, &mon_data_ext, |
1628 | sizeof(mon_data_ext))) | |
037ad48b JS |
1629 | return -EFAULT; |
1630 | ||
1631 | return 0; | |
1632 | ||
55b307da | 1633 | } default: |
037ad48b JS |
1634 | return -ENOIOCTLCMD; |
1635 | } | |
1636 | return 0; | |
1637 | } | |
1638 | ||
a8dea4ec JS |
1639 | static int mxser_ioctl(struct tty_struct *tty, struct file *file, |
1640 | unsigned int cmd, unsigned long arg) | |
037ad48b | 1641 | { |
55b307da | 1642 | struct mxser_port *info = tty->driver_data; |
a8dea4ec JS |
1643 | struct async_icount cprev, cnow; /* kernel counter temps */ |
1644 | struct serial_icounter_struct __user *p_cuser; | |
1645 | unsigned long templ; | |
1646 | unsigned long flags; | |
1647 | void __user *argp = (void __user *)arg; | |
1648 | int retval; | |
037ad48b | 1649 | |
a8dea4ec JS |
1650 | if (tty->index == MXSER_PORTS) |
1651 | return mxser_ioctl_special(cmd, argp); | |
1652 | ||
a8dea4ec JS |
1653 | if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) { |
1654 | int p; | |
1655 | unsigned long opmode; | |
1656 | static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f }; | |
1657 | int shiftbit; | |
1658 | unsigned char val, mask; | |
1659 | ||
1660 | p = tty->index % 4; | |
1661 | if (cmd == MOXA_SET_OP_MODE) { | |
1662 | if (get_user(opmode, (int __user *) argp)) | |
1663 | return -EFAULT; | |
1664 | if (opmode != RS232_MODE && | |
1665 | opmode != RS485_2WIRE_MODE && | |
1666 | opmode != RS422_MODE && | |
1667 | opmode != RS485_4WIRE_MODE) | |
1668 | return -EFAULT; | |
1669 | mask = ModeMask[p]; | |
1670 | shiftbit = p * 2; | |
1671 | val = inb(info->opmode_ioaddr); | |
1672 | val &= mask; | |
1673 | val |= (opmode << shiftbit); | |
1674 | outb(val, info->opmode_ioaddr); | |
1675 | } else { | |
1676 | shiftbit = p * 2; | |
1677 | opmode = inb(info->opmode_ioaddr) >> shiftbit; | |
1678 | opmode &= OP_MODE_MASK; | |
1679 | if (copy_to_user(argp, &opmode, sizeof(int))) | |
1680 | return -EFAULT; | |
3306ce3d | 1681 | } |
a8dea4ec | 1682 | return 0; |
037ad48b JS |
1683 | } |
1684 | ||
214efebb JS |
1685 | if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT && |
1686 | test_bit(TTY_IO_ERROR, &tty->flags)) | |
1687 | return -EIO; | |
1688 | ||
a8dea4ec JS |
1689 | switch (cmd) { |
1690 | case TCSBRK: /* SVID version: non-zero arg --> no break */ | |
1691 | retval = tty_check_change(tty); | |
1692 | if (retval) | |
1693 | return retval; | |
1694 | tty_wait_until_sent(tty, 0); | |
1695 | if (!arg) | |
1696 | mxser_send_break(info, HZ / 4); /* 1/4 second */ | |
1697 | return 0; | |
1698 | case TCSBRKP: /* support for POSIX tcsendbreak() */ | |
1699 | retval = tty_check_change(tty); | |
1700 | if (retval) | |
1701 | return retval; | |
1702 | tty_wait_until_sent(tty, 0); | |
1703 | mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4); | |
1704 | return 0; | |
1705 | case TIOCGSOFTCAR: | |
1706 | return put_user(C_CLOCAL(tty) ? 1 : 0, (unsigned long __user *)argp); | |
1707 | case TIOCSSOFTCAR: | |
1708 | if (get_user(templ, (unsigned long __user *) argp)) | |
1709 | return -EFAULT; | |
1710 | arg = templ; | |
1711 | tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0)); | |
1712 | return 0; | |
1713 | case TIOCGSERIAL: | |
1714 | return mxser_get_serial_info(info, argp); | |
1715 | case TIOCSSERIAL: | |
1716 | return mxser_set_serial_info(info, argp); | |
1717 | case TIOCSERGETLSR: /* Get line status register */ | |
1718 | return mxser_get_lsr_info(info, argp); | |
1719 | /* | |
1720 | * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change | |
1721 | * - mask passed in arg for lines of interest | |
1722 | * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) | |
1723 | * Caller should use TIOCGICOUNT to see which one it was | |
1724 | */ | |
1725 | case TIOCMIWAIT: { | |
1726 | DECLARE_WAITQUEUE(wait, current); | |
1727 | int ret; | |
1728 | spin_lock_irqsave(&info->slock, flags); | |
1729 | cprev = info->icount; /* note the counters on entry */ | |
1730 | spin_unlock_irqrestore(&info->slock, flags); | |
037ad48b | 1731 | |
a8dea4ec JS |
1732 | add_wait_queue(&info->delta_msr_wait, &wait); |
1733 | while (1) { | |
1734 | spin_lock_irqsave(&info->slock, flags); | |
1735 | cnow = info->icount; /* atomic copy */ | |
1736 | spin_unlock_irqrestore(&info->slock, flags); | |
037ad48b | 1737 | |
a8dea4ec JS |
1738 | set_current_state(TASK_INTERRUPTIBLE); |
1739 | if (((arg & TIOCM_RNG) && | |
1740 | (cnow.rng != cprev.rng)) || | |
1741 | ((arg & TIOCM_DSR) && | |
1742 | (cnow.dsr != cprev.dsr)) || | |
1743 | ((arg & TIOCM_CD) && | |
1744 | (cnow.dcd != cprev.dcd)) || | |
1745 | ((arg & TIOCM_CTS) && | |
1746 | (cnow.cts != cprev.cts))) { | |
1747 | ret = 0; | |
1748 | break; | |
3306ce3d | 1749 | } |
a8dea4ec JS |
1750 | /* see if a signal did it */ |
1751 | if (signal_pending(current)) { | |
1752 | ret = -ERESTARTSYS; | |
1753 | break; | |
1754 | } | |
1755 | cprev = cnow; | |
037ad48b | 1756 | } |
a8dea4ec JS |
1757 | current->state = TASK_RUNNING; |
1758 | remove_wait_queue(&info->delta_msr_wait, &wait); | |
1759 | break; | |
037ad48b | 1760 | } |
a8dea4ec JS |
1761 | /* NOTREACHED */ |
1762 | /* | |
1763 | * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) | |
1764 | * Return: write counters to the user passed counter struct | |
1765 | * NB: both 1->0 and 0->1 transitions are counted except for | |
1766 | * RI where only 0->1 is counted. | |
1767 | */ | |
1768 | case TIOCGICOUNT: | |
1769 | spin_lock_irqsave(&info->slock, flags); | |
1770 | cnow = info->icount; | |
1771 | spin_unlock_irqrestore(&info->slock, flags); | |
1772 | p_cuser = argp; | |
a8dea4ec JS |
1773 | if (put_user(cnow.frame, &p_cuser->frame)) |
1774 | return -EFAULT; | |
1775 | if (put_user(cnow.brk, &p_cuser->brk)) | |
1776 | return -EFAULT; | |
1777 | if (put_user(cnow.overrun, &p_cuser->overrun)) | |
1778 | return -EFAULT; | |
1779 | if (put_user(cnow.buf_overrun, &p_cuser->buf_overrun)) | |
1780 | return -EFAULT; | |
1781 | if (put_user(cnow.parity, &p_cuser->parity)) | |
1782 | return -EFAULT; | |
1783 | if (put_user(cnow.rx, &p_cuser->rx)) | |
1784 | return -EFAULT; | |
1785 | if (put_user(cnow.tx, &p_cuser->tx)) | |
1786 | return -EFAULT; | |
1787 | put_user(cnow.cts, &p_cuser->cts); | |
1788 | put_user(cnow.dsr, &p_cuser->dsr); | |
1789 | put_user(cnow.rng, &p_cuser->rng); | |
1790 | put_user(cnow.dcd, &p_cuser->dcd); | |
1791 | return 0; | |
1792 | case MOXA_HighSpeedOn: | |
1793 | return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp); | |
1794 | case MOXA_SDS_RSTICOUNTER: | |
1795 | info->mon_data.rxcnt = 0; | |
1796 | info->mon_data.txcnt = 0; | |
1797 | return 0; | |
a8dea4ec JS |
1798 | case MOXA_ASPP_SETBAUD:{ |
1799 | long baud; | |
1800 | if (get_user(baud, (long __user *)argp)) | |
1801 | return -EFAULT; | |
1802 | mxser_set_baud(info, baud); | |
1803 | return 0; | |
1804 | } | |
1805 | case MOXA_ASPP_GETBAUD: | |
1806 | if (copy_to_user(argp, &info->realbaud, sizeof(long))) | |
1807 | return -EFAULT; | |
037ad48b | 1808 | |
a8dea4ec | 1809 | return 0; |
037ad48b | 1810 | |
a8dea4ec JS |
1811 | case MOXA_ASPP_OQUEUE:{ |
1812 | int len, lsr; | |
037ad48b | 1813 | |
a8dea4ec JS |
1814 | len = mxser_chars_in_buffer(tty); |
1815 | ||
1816 | lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT; | |
1817 | ||
1818 | len += (lsr ? 0 : 1); | |
1819 | ||
1820 | if (copy_to_user(argp, &len, sizeof(int))) | |
1821 | return -EFAULT; | |
1822 | ||
1823 | return 0; | |
037ad48b | 1824 | } |
a8dea4ec JS |
1825 | case MOXA_ASPP_MON: { |
1826 | int mcr, status; | |
037ad48b | 1827 | |
a8dea4ec JS |
1828 | status = mxser_get_msr(info->ioaddr, 1, tty->index); |
1829 | mxser_check_modem_status(info, status); | |
1830 | ||
1831 | mcr = inb(info->ioaddr + UART_MCR); | |
1832 | if (mcr & MOXA_MUST_MCR_XON_FLAG) | |
1833 | info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD; | |
1834 | else | |
1835 | info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD; | |
1836 | ||
1837 | if (mcr & MOXA_MUST_MCR_TX_XON) | |
1838 | info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT; | |
1839 | else | |
1840 | info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT; | |
1841 | ||
1842 | if (info->tty->hw_stopped) | |
1843 | info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD; | |
1844 | else | |
1845 | info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD; | |
1846 | ||
1847 | if (copy_to_user(argp, &info->mon_data, | |
1848 | sizeof(struct mxser_mon))) | |
1849 | return -EFAULT; | |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | case MOXA_ASPP_LSTATUS: { | |
1854 | if (copy_to_user(argp, &info->err_shadow, | |
1855 | sizeof(unsigned char))) | |
1856 | return -EFAULT; | |
1857 | ||
1858 | info->err_shadow = 0; | |
1859 | return 0; | |
1860 | } | |
1861 | case MOXA_SET_BAUD_METHOD: { | |
1862 | int method; | |
1863 | ||
1864 | if (get_user(method, (int __user *)argp)) | |
1865 | return -EFAULT; | |
1866 | mxser_set_baud_method[tty->index] = method; | |
1867 | if (copy_to_user(argp, &method, sizeof(int))) | |
1868 | return -EFAULT; | |
1869 | ||
1870 | return 0; | |
1871 | } | |
1872 | default: | |
1873 | return -ENOIOCTLCMD; | |
1874 | } | |
1875 | return 0; | |
1876 | } | |
1877 | ||
1878 | static void mxser_stoprx(struct tty_struct *tty) | |
1879 | { | |
1880 | struct mxser_port *info = tty->driver_data; | |
037ad48b | 1881 | |
a8dea4ec JS |
1882 | info->ldisc_stop_rx = 1; |
1883 | if (I_IXOFF(tty)) { | |
55b307da | 1884 | if (info->board->chip_flag) { |
a8dea4ec JS |
1885 | info->IER &= ~MOXA_MUST_RECV_ISR; |
1886 | outb(info->IER, info->ioaddr + UART_IER); | |
925e9c1c | 1887 | } else { |
a8dea4ec JS |
1888 | info->x_char = STOP_CHAR(tty); |
1889 | outb(0, info->ioaddr + UART_IER); | |
1890 | info->IER |= UART_IER_THRI; | |
1891 | outb(info->IER, info->ioaddr + UART_IER); | |
037ad48b | 1892 | } |
a8dea4ec | 1893 | } |
037ad48b | 1894 | |
a8dea4ec JS |
1895 | if (info->tty->termios->c_cflag & CRTSCTS) { |
1896 | info->MCR &= ~UART_MCR_RTS; | |
1897 | outb(info->MCR, info->ioaddr + UART_MCR); | |
1898 | } | |
1899 | } | |
1900 | ||
1901 | /* | |
1902 | * This routine is called by the upper-layer tty layer to signal that | |
1903 | * incoming characters should be throttled. | |
1904 | */ | |
1905 | static void mxser_throttle(struct tty_struct *tty) | |
1906 | { | |
1907 | mxser_stoprx(tty); | |
1908 | } | |
1909 | ||
1910 | static void mxser_unthrottle(struct tty_struct *tty) | |
1911 | { | |
1912 | struct mxser_port *info = tty->driver_data; | |
1913 | ||
1914 | /* startrx */ | |
1915 | info->ldisc_stop_rx = 0; | |
1916 | if (I_IXOFF(tty)) { | |
1917 | if (info->x_char) | |
1918 | info->x_char = 0; | |
1919 | else { | |
a8dea4ec JS |
1920 | if (info->board->chip_flag) { |
1921 | info->IER |= MOXA_MUST_RECV_ISR; | |
1922 | outb(info->IER, info->ioaddr + UART_IER); | |
925e9c1c | 1923 | } else { |
a8dea4ec JS |
1924 | info->x_char = START_CHAR(tty); |
1925 | outb(0, info->ioaddr + UART_IER); | |
1926 | info->IER |= UART_IER_THRI; | |
1927 | outb(info->IER, info->ioaddr + UART_IER); | |
1928 | } | |
1929 | } | |
1930 | } | |
1931 | ||
1932 | if (info->tty->termios->c_cflag & CRTSCTS) { | |
1933 | info->MCR |= UART_MCR_RTS; | |
1934 | outb(info->MCR, info->ioaddr + UART_MCR); | |
037ad48b JS |
1935 | } |
1936 | } | |
1937 | ||
1938 | /* | |
1939 | * mxser_stop() and mxser_start() | |
1940 | * | |
1941 | * This routines are called before setting or resetting tty->stopped. | |
1942 | * They enable or disable transmitter interrupts, as necessary. | |
1943 | */ | |
1944 | static void mxser_stop(struct tty_struct *tty) | |
1945 | { | |
55b307da | 1946 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
1947 | unsigned long flags; |
1948 | ||
1949 | spin_lock_irqsave(&info->slock, flags); | |
1950 | if (info->IER & UART_IER_THRI) { | |
1951 | info->IER &= ~UART_IER_THRI; | |
55b307da | 1952 | outb(info->IER, info->ioaddr + UART_IER); |
037ad48b JS |
1953 | } |
1954 | spin_unlock_irqrestore(&info->slock, flags); | |
1955 | } | |
1956 | ||
1957 | static void mxser_start(struct tty_struct *tty) | |
1958 | { | |
55b307da | 1959 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
1960 | unsigned long flags; |
1961 | ||
1962 | spin_lock_irqsave(&info->slock, flags); | |
e079f495 | 1963 | if (info->xmit_cnt && info->xmit_buf) { |
55b307da | 1964 | outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); |
037ad48b | 1965 | info->IER |= UART_IER_THRI; |
55b307da | 1966 | outb(info->IER, info->ioaddr + UART_IER); |
037ad48b JS |
1967 | } |
1968 | spin_unlock_irqrestore(&info->slock, flags); | |
1969 | } | |
1970 | ||
606d099c | 1971 | static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
a8dea4ec JS |
1972 | { |
1973 | struct mxser_port *info = tty->driver_data; | |
1974 | unsigned long flags; | |
1975 | ||
1976 | if ((tty->termios->c_cflag != old_termios->c_cflag) || | |
1977 | (RELEVANT_IFLAG(tty->termios->c_iflag) != RELEVANT_IFLAG(old_termios->c_iflag))) { | |
1978 | ||
1979 | mxser_change_speed(info, old_termios); | |
1980 | ||
1981 | if ((old_termios->c_cflag & CRTSCTS) && | |
1982 | !(tty->termios->c_cflag & CRTSCTS)) { | |
1983 | tty->hw_stopped = 0; | |
1984 | mxser_start(tty); | |
1985 | } | |
1986 | } | |
1987 | ||
e079f495 | 1988 | /* Handle sw stopped */ |
a8dea4ec JS |
1989 | if ((old_termios->c_iflag & IXON) && |
1990 | !(tty->termios->c_iflag & IXON)) { | |
1991 | tty->stopped = 0; | |
1992 | ||
a8dea4ec JS |
1993 | if (info->board->chip_flag) { |
1994 | spin_lock_irqsave(&info->slock, flags); | |
1995 | DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); | |
1996 | spin_unlock_irqrestore(&info->slock, flags); | |
1997 | } | |
a8dea4ec JS |
1998 | |
1999 | mxser_start(tty); | |
2000 | } | |
2001 | } | |
2002 | ||
037ad48b JS |
2003 | /* |
2004 | * mxser_wait_until_sent() --- wait until the transmitter is empty | |
2005 | */ | |
2006 | static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) | |
2007 | { | |
55b307da | 2008 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
2009 | unsigned long orig_jiffies, char_time; |
2010 | int lsr; | |
2011 | ||
2012 | if (info->type == PORT_UNKNOWN) | |
2013 | return; | |
2014 | ||
2015 | if (info->xmit_fifo_size == 0) | |
2016 | return; /* Just in case.... */ | |
2017 | ||
2018 | orig_jiffies = jiffies; | |
2019 | /* | |
2020 | * Set the check interval to be 1/5 of the estimated time to | |
2021 | * send a single character, and make it at least 1. The check | |
2022 | * interval should also be less than the timeout. | |
2023 | * | |
2024 | * Note: we have to use pretty tight timings here to satisfy | |
2025 | * the NIST-PCTS. | |
2026 | */ | |
2027 | char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; | |
2028 | char_time = char_time / 5; | |
2029 | if (char_time == 0) | |
2030 | char_time = 1; | |
2031 | if (timeout && timeout < char_time) | |
2032 | char_time = timeout; | |
2033 | /* | |
2034 | * If the transmitter hasn't cleared in twice the approximate | |
2035 | * amount of time to send the entire FIFO, it probably won't | |
2036 | * ever clear. This assumes the UART isn't doing flow | |
2037 | * control, which is currently the case. Hence, if it ever | |
2038 | * takes longer than info->timeout, this is probably due to a | |
2039 | * UART bug of some kind. So, we clamp the timeout parameter at | |
2040 | * 2*info->timeout. | |
2041 | */ | |
2042 | if (!timeout || timeout > 2 * info->timeout) | |
2043 | timeout = 2 * info->timeout; | |
2044 | #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT | |
2045 | printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...", | |
2046 | timeout, char_time); | |
2047 | printk("jiff=%lu...", jiffies); | |
2048 | #endif | |
55b307da | 2049 | while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) { |
037ad48b JS |
2050 | #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT |
2051 | printk("lsr = %d (jiff=%lu)...", lsr, jiffies); | |
2052 | #endif | |
2053 | schedule_timeout_interruptible(char_time); | |
2054 | if (signal_pending(current)) | |
2055 | break; | |
2056 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
2057 | break; | |
2058 | } | |
2059 | set_current_state(TASK_RUNNING); | |
2060 | ||
2061 | #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT | |
2062 | printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies); | |
a8dea4ec JS |
2063 | #endif |
2064 | } | |
037ad48b | 2065 | |
a8dea4ec JS |
2066 | /* |
2067 | * This routine is called by tty_hangup() when a hangup is signaled. | |
2068 | */ | |
2069 | void mxser_hangup(struct tty_struct *tty) | |
2070 | { | |
2071 | struct mxser_port *info = tty->driver_data; | |
037ad48b | 2072 | |
a8dea4ec JS |
2073 | mxser_flush_buffer(tty); |
2074 | mxser_shutdown(info); | |
2075 | info->event = 0; | |
2076 | info->count = 0; | |
2077 | info->flags &= ~ASYNC_NORMAL_ACTIVE; | |
2078 | info->tty = NULL; | |
2079 | wake_up_interruptible(&info->open_wait); | |
037ad48b JS |
2080 | } |
2081 | ||
a8dea4ec JS |
2082 | /* |
2083 | * mxser_rs_break() --- routine which turns the break handling on or off | |
2084 | */ | |
2085 | static void mxser_rs_break(struct tty_struct *tty, int break_state) | |
037ad48b | 2086 | { |
a8dea4ec | 2087 | struct mxser_port *info = tty->driver_data; |
037ad48b JS |
2088 | unsigned long flags; |
2089 | ||
a8dea4ec JS |
2090 | spin_lock_irqsave(&info->slock, flags); |
2091 | if (break_state == -1) | |
2092 | outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, | |
2093 | info->ioaddr + UART_LCR); | |
2094 | else | |
2095 | outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, | |
2096 | info->ioaddr + UART_LCR); | |
2097 | spin_unlock_irqrestore(&info->slock, flags); | |
2098 | } | |
037ad48b | 2099 | |
a8dea4ec JS |
2100 | static void mxser_receive_chars(struct mxser_port *port, int *status) |
2101 | { | |
2102 | struct tty_struct *tty = port->tty; | |
2103 | unsigned char ch, gdl; | |
2104 | int ignored = 0; | |
2105 | int cnt = 0; | |
2106 | int recv_room; | |
2107 | int max = 256; | |
2108 | unsigned long flags; | |
037ad48b | 2109 | |
a8dea4ec JS |
2110 | spin_lock_irqsave(&port->slock, flags); |
2111 | ||
2112 | recv_room = tty->receive_room; | |
e079f495 | 2113 | if ((recv_room == 0) && (!port->ldisc_stop_rx)) |
a8dea4ec | 2114 | mxser_stoprx(tty); |
037ad48b | 2115 | |
a8dea4ec | 2116 | if (port->board->chip_flag != MOXA_OTHER_UART) { |
037ad48b | 2117 | |
a8dea4ec JS |
2118 | if (*status & UART_LSR_SPECIAL) |
2119 | goto intr_old; | |
a8dea4ec JS |
2120 | if (port->board->chip_flag == MOXA_MUST_MU860_HWID && |
2121 | (*status & MOXA_MUST_LSR_RERR)) | |
2122 | goto intr_old; | |
a8dea4ec JS |
2123 | if (*status & MOXA_MUST_LSR_RERR) |
2124 | goto intr_old; | |
2125 | ||
2126 | gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); | |
2127 | ||
a8dea4ec JS |
2128 | if (port->board->chip_flag == MOXA_MUST_MU150_HWID) |
2129 | gdl &= MOXA_MUST_GDL_MASK; | |
2130 | if (gdl >= recv_room) { | |
e079f495 | 2131 | if (!port->ldisc_stop_rx) |
a8dea4ec | 2132 | mxser_stoprx(tty); |
a8dea4ec JS |
2133 | } |
2134 | while (gdl--) { | |
2135 | ch = inb(port->ioaddr + UART_RX); | |
2136 | tty_insert_flip_char(tty, ch, 0); | |
2137 | cnt++; | |
2138 | } | |
2139 | goto end_intr; | |
037ad48b | 2140 | } |
e079f495 | 2141 | intr_old: |
037ad48b | 2142 | |
a8dea4ec JS |
2143 | do { |
2144 | if (max-- < 0) | |
2145 | break; | |
037ad48b | 2146 | |
a8dea4ec | 2147 | ch = inb(port->ioaddr + UART_RX); |
e079f495 | 2148 | if (port->board->chip_flag && (*status & UART_LSR_OE)) |
a8dea4ec JS |
2149 | outb(0x23, port->ioaddr + UART_FCR); |
2150 | *status &= port->read_status_mask; | |
a8dea4ec JS |
2151 | if (*status & port->ignore_status_mask) { |
2152 | if (++ignored > 100) | |
2153 | break; | |
2154 | } else { | |
2155 | char flag = 0; | |
2156 | if (*status & UART_LSR_SPECIAL) { | |
2157 | if (*status & UART_LSR_BI) { | |
2158 | flag = TTY_BREAK; | |
a8dea4ec | 2159 | port->icount.brk++; |
037ad48b | 2160 | |
a8dea4ec JS |
2161 | if (port->flags & ASYNC_SAK) |
2162 | do_SAK(tty); | |
2163 | } else if (*status & UART_LSR_PE) { | |
2164 | flag = TTY_PARITY; | |
a8dea4ec JS |
2165 | port->icount.parity++; |
2166 | } else if (*status & UART_LSR_FE) { | |
2167 | flag = TTY_FRAME; | |
a8dea4ec JS |
2168 | port->icount.frame++; |
2169 | } else if (*status & UART_LSR_OE) { | |
2170 | flag = TTY_OVERRUN; | |
a8dea4ec | 2171 | port->icount.overrun++; |
925e9c1c JS |
2172 | } |
2173 | } | |
a8dea4ec JS |
2174 | tty_insert_flip_char(tty, ch, flag); |
2175 | cnt++; | |
2176 | if (cnt >= recv_room) { | |
e079f495 | 2177 | if (!port->ldisc_stop_rx) |
a8dea4ec | 2178 | mxser_stoprx(tty); |
a8dea4ec JS |
2179 | break; |
2180 | } | |
037ad48b | 2181 | |
a8dea4ec | 2182 | } |
037ad48b | 2183 | |
a8dea4ec JS |
2184 | if (port->board->chip_flag) |
2185 | break; | |
037ad48b | 2186 | |
a8dea4ec | 2187 | *status = inb(port->ioaddr + UART_LSR); |
a8dea4ec | 2188 | } while (*status & UART_LSR_DR); |
037ad48b | 2189 | |
e079f495 | 2190 | end_intr: |
a8dea4ec JS |
2191 | mxvar_log.rxcnt[port->tty->index] += cnt; |
2192 | port->mon_data.rxcnt += cnt; | |
2193 | port->mon_data.up_rxcnt += cnt; | |
2194 | spin_unlock_irqrestore(&port->slock, flags); | |
2195 | ||
2196 | tty_flip_buffer_push(tty); | |
037ad48b JS |
2197 | } |
2198 | ||
a8dea4ec | 2199 | static void mxser_transmit_chars(struct mxser_port *port) |
037ad48b | 2200 | { |
a8dea4ec JS |
2201 | int count, cnt; |
2202 | unsigned long flags; | |
037ad48b | 2203 | |
a8dea4ec | 2204 | spin_lock_irqsave(&port->slock, flags); |
037ad48b | 2205 | |
a8dea4ec JS |
2206 | if (port->x_char) { |
2207 | outb(port->x_char, port->ioaddr + UART_TX); | |
2208 | port->x_char = 0; | |
2209 | mxvar_log.txcnt[port->tty->index]++; | |
2210 | port->mon_data.txcnt++; | |
2211 | port->mon_data.up_txcnt++; | |
a8dea4ec JS |
2212 | port->icount.tx++; |
2213 | goto unlock; | |
037ad48b JS |
2214 | } |
2215 | ||
a8dea4ec JS |
2216 | if (port->xmit_buf == 0) |
2217 | goto unlock; | |
037ad48b | 2218 | |
925e9c1c JS |
2219 | if ((port->xmit_cnt <= 0) || port->tty->stopped || |
2220 | (port->tty->hw_stopped && | |
a8dea4ec JS |
2221 | (port->type != PORT_16550A) && |
2222 | (!port->board->chip_flag))) { | |
2223 | port->IER &= ~UART_IER_THRI; | |
2224 | outb(port->IER, port->ioaddr + UART_IER); | |
2225 | goto unlock; | |
2226 | } | |
037ad48b | 2227 | |
a8dea4ec JS |
2228 | cnt = port->xmit_cnt; |
2229 | count = port->xmit_fifo_size; | |
2230 | do { | |
2231 | outb(port->xmit_buf[port->xmit_tail++], | |
2232 | port->ioaddr + UART_TX); | |
2233 | port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1); | |
2234 | if (--port->xmit_cnt <= 0) | |
2235 | break; | |
2236 | } while (--count > 0); | |
2237 | mxvar_log.txcnt[port->tty->index] += (cnt - port->xmit_cnt); | |
55b307da | 2238 | |
a8dea4ec JS |
2239 | port->mon_data.txcnt += (cnt - port->xmit_cnt); |
2240 | port->mon_data.up_txcnt += (cnt - port->xmit_cnt); | |
a8dea4ec | 2241 | port->icount.tx += (cnt - port->xmit_cnt); |
037ad48b | 2242 | |
a8dea4ec JS |
2243 | if (port->xmit_cnt < WAKEUP_CHARS) { |
2244 | set_bit(MXSER_EVENT_TXLOW, &port->event); | |
2245 | schedule_work(&port->tqueue); | |
2246 | } | |
2247 | if (port->xmit_cnt <= 0) { | |
2248 | port->IER &= ~UART_IER_THRI; | |
2249 | outb(port->IER, port->ioaddr + UART_IER); | |
2250 | } | |
2251 | unlock: | |
2252 | spin_unlock_irqrestore(&port->slock, flags); | |
037ad48b JS |
2253 | } |
2254 | ||
2255 | /* | |
a8dea4ec | 2256 | * This is the serial driver's generic interrupt routine |
037ad48b | 2257 | */ |
b1d1c8dd | 2258 | static irqreturn_t mxser_interrupt(int irq, void *dev_id) |
037ad48b | 2259 | { |
a8dea4ec JS |
2260 | int status, iir, i; |
2261 | struct mxser_board *brd = NULL; | |
2262 | struct mxser_port *port; | |
2263 | int max, irqbits, bits, msr; | |
2264 | int pass_counter = 0; | |
2265 | unsigned int int_cnt; | |
2266 | int handled = IRQ_NONE; | |
037ad48b | 2267 | |
a8dea4ec JS |
2268 | for (i = 0; i < MXSER_BOARDS; i++) |
2269 | if (dev_id == &mxser_boards[i]) { | |
2270 | brd = dev_id; | |
2271 | break; | |
2272 | } | |
037ad48b | 2273 | |
a8dea4ec JS |
2274 | if (i == MXSER_BOARDS) |
2275 | goto irq_stop; | |
2276 | if (brd == NULL) | |
2277 | goto irq_stop; | |
cd7ed64e | 2278 | max = brd->info->nports; |
a8dea4ec JS |
2279 | while (1) { |
2280 | irqbits = inb(brd->vector) & brd->vector_mask; | |
2281 | if (irqbits == brd->vector_mask) | |
2282 | break; | |
037ad48b | 2283 | |
a8dea4ec JS |
2284 | handled = IRQ_HANDLED; |
2285 | for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { | |
2286 | if (irqbits == brd->vector_mask) | |
2287 | break; | |
2288 | if (bits & irqbits) | |
2289 | continue; | |
2290 | port = &brd->ports[i]; | |
037ad48b | 2291 | |
a8dea4ec JS |
2292 | int_cnt = 0; |
2293 | do { | |
a8dea4ec JS |
2294 | iir = inb(port->ioaddr + UART_IIR); |
2295 | if (iir & UART_IIR_NO_INT) | |
2296 | break; | |
2297 | iir &= MOXA_MUST_IIR_MASK; | |
2298 | if (!port->tty) { | |
2299 | status = inb(port->ioaddr + UART_LSR); | |
2300 | outb(0x27, port->ioaddr + UART_FCR); | |
2301 | inb(port->ioaddr + UART_MSR); | |
2302 | break; | |
2303 | } | |
037ad48b | 2304 | |
a8dea4ec JS |
2305 | status = inb(port->ioaddr + UART_LSR); |
2306 | ||
2307 | if (status & UART_LSR_PE) | |
2308 | port->err_shadow |= NPPI_NOTIFY_PARITY; | |
2309 | if (status & UART_LSR_FE) | |
2310 | port->err_shadow |= NPPI_NOTIFY_FRAMING; | |
2311 | if (status & UART_LSR_OE) | |
2312 | port->err_shadow |= | |
2313 | NPPI_NOTIFY_HW_OVERRUN; | |
2314 | if (status & UART_LSR_BI) | |
2315 | port->err_shadow |= NPPI_NOTIFY_BREAK; | |
2316 | ||
2317 | if (port->board->chip_flag) { | |
a8dea4ec JS |
2318 | if (iir == MOXA_MUST_IIR_GDA || |
2319 | iir == MOXA_MUST_IIR_RDA || | |
2320 | iir == MOXA_MUST_IIR_RTO || | |
2321 | iir == MOXA_MUST_IIR_LSR) | |
2322 | mxser_receive_chars(port, | |
2323 | &status); | |
2324 | ||
2325 | } else { | |
a8dea4ec JS |
2326 | status &= port->read_status_mask; |
2327 | if (status & UART_LSR_DR) | |
2328 | mxser_receive_chars(port, | |
2329 | &status); | |
2330 | } | |
2331 | msr = inb(port->ioaddr + UART_MSR); | |
2332 | if (msr & UART_MSR_ANY_DELTA) | |
2333 | mxser_check_modem_status(port, msr); | |
2334 | ||
a8dea4ec JS |
2335 | if (port->board->chip_flag) { |
2336 | if (iir == 0x02 && (status & | |
2337 | UART_LSR_THRE)) | |
2338 | mxser_transmit_chars(port); | |
2339 | } else { | |
a8dea4ec JS |
2340 | if (status & UART_LSR_THRE) |
2341 | mxser_transmit_chars(port); | |
2342 | } | |
2343 | } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); | |
2344 | } | |
2345 | if (pass_counter++ > MXSER_ISR_PASS_LIMIT) | |
2346 | break; /* Prevent infinite loops */ | |
2347 | } | |
2348 | ||
e079f495 | 2349 | irq_stop: |
a8dea4ec | 2350 | return handled; |
037ad48b JS |
2351 | } |
2352 | ||
a8dea4ec JS |
2353 | static const struct tty_operations mxser_ops = { |
2354 | .open = mxser_open, | |
2355 | .close = mxser_close, | |
2356 | .write = mxser_write, | |
2357 | .put_char = mxser_put_char, | |
2358 | .flush_chars = mxser_flush_chars, | |
2359 | .write_room = mxser_write_room, | |
2360 | .chars_in_buffer = mxser_chars_in_buffer, | |
2361 | .flush_buffer = mxser_flush_buffer, | |
2362 | .ioctl = mxser_ioctl, | |
2363 | .throttle = mxser_throttle, | |
2364 | .unthrottle = mxser_unthrottle, | |
2365 | .set_termios = mxser_set_termios, | |
2366 | .stop = mxser_stop, | |
2367 | .start = mxser_start, | |
2368 | .hangup = mxser_hangup, | |
2369 | .break_ctl = mxser_rs_break, | |
2370 | .wait_until_sent = mxser_wait_until_sent, | |
2371 | .tiocmget = mxser_tiocmget, | |
2372 | .tiocmset = mxser_tiocmset, | |
2373 | }; | |
2374 | ||
2375 | /* | |
2376 | * The MOXA Smartio/Industio serial driver boot-time initialization code! | |
2377 | */ | |
2378 | ||
2094e757 JS |
2379 | static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev, |
2380 | unsigned int irq) | |
171d3a86 | 2381 | { |
171d3a86 JS |
2382 | if (irq) |
2383 | free_irq(brd->irq, brd); | |
2384 | if (pdev != NULL) { /* PCI */ | |
fb0c9295 | 2385 | #ifdef CONFIG_PCI |
171d3a86 JS |
2386 | pci_release_region(pdev, 2); |
2387 | pci_release_region(pdev, 3); | |
2388 | pci_dev_put(pdev); | |
fb0c9295 | 2389 | #endif |
171d3a86 | 2390 | } else { |
cd7ed64e | 2391 | release_region(brd->ports[0].ioaddr, 8 * brd->info->nports); |
171d3a86 JS |
2392 | release_region(brd->vector, 1); |
2393 | } | |
2394 | } | |
2395 | ||
2094e757 JS |
2396 | static int __devinit mxser_initbrd(struct mxser_board *brd, |
2397 | struct pci_dev *pdev) | |
037ad48b | 2398 | { |
a8dea4ec JS |
2399 | struct mxser_port *info; |
2400 | unsigned int i; | |
2401 | int retval; | |
2402 | ||
2403 | printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud); | |
2404 | ||
cd7ed64e | 2405 | for (i = 0; i < brd->info->nports; i++) { |
a8dea4ec JS |
2406 | info = &brd->ports[i]; |
2407 | info->board = brd; | |
2408 | info->stop_rx = 0; | |
2409 | info->ldisc_stop_rx = 0; | |
037ad48b | 2410 | |
a8dea4ec JS |
2411 | /* Enhance mode enabled here */ |
2412 | if (brd->chip_flag != MOXA_OTHER_UART) | |
2413 | ENABLE_MOXA_MUST_ENCHANCE_MODE(info->ioaddr); | |
037ad48b | 2414 | |
a8dea4ec JS |
2415 | info->flags = ASYNC_SHARE_IRQ; |
2416 | info->type = brd->uart_type; | |
037ad48b | 2417 | |
a8dea4ec | 2418 | process_txrx_fifo(info); |
037ad48b | 2419 | |
a8dea4ec JS |
2420 | info->custom_divisor = info->baud_base * 16; |
2421 | info->close_delay = 5 * HZ / 10; | |
2422 | info->closing_wait = 30 * HZ; | |
95a7b8b9 | 2423 | INIT_WORK(&info->tqueue, mxser_do_softint); |
a8dea4ec JS |
2424 | info->normal_termios = mxvar_sdriver->init_termios; |
2425 | init_waitqueue_head(&info->open_wait); | |
2426 | init_waitqueue_head(&info->close_wait); | |
2427 | init_waitqueue_head(&info->delta_msr_wait); | |
2428 | memset(&info->mon_data, 0, sizeof(struct mxser_mon)); | |
2429 | info->err_shadow = 0; | |
2430 | spin_lock_init(&info->slock); | |
037ad48b | 2431 | |
a8dea4ec JS |
2432 | /* before set INT ISR, disable all int */ |
2433 | outb(inb(info->ioaddr + UART_IER) & 0xf0, | |
2434 | info->ioaddr + UART_IER); | |
2435 | } | |
2436 | /* | |
2437 | * Allocate the IRQ if necessary | |
2438 | */ | |
037ad48b | 2439 | |
a8dea4ec JS |
2440 | retval = request_irq(brd->irq, mxser_interrupt, |
2441 | (brd->ports[0].flags & ASYNC_SHARE_IRQ) ? IRQF_SHARED : | |
2442 | IRQF_DISABLED, "mxser", brd); | |
2443 | if (retval) { | |
2444 | printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may " | |
2445 | "conflict with another device.\n", | |
cd7ed64e | 2446 | brd->info->name, brd->irq); |
171d3a86 | 2447 | /* We hold resources, we need to release them. */ |
2094e757 | 2448 | mxser_release_res(brd, pdev, 0); |
a8dea4ec JS |
2449 | return retval; |
2450 | } | |
037ad48b JS |
2451 | return 0; |
2452 | } | |
2453 | ||
943f2959 | 2454 | static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd) |
037ad48b JS |
2455 | { |
2456 | int id, i, bits; | |
2457 | unsigned short regs[16], irq; | |
2458 | unsigned char scratch, scratch2; | |
2459 | ||
55b307da | 2460 | brd->chip_flag = MOXA_OTHER_UART; |
037ad48b JS |
2461 | |
2462 | id = mxser_read_register(cap, regs); | |
cd7ed64e JS |
2463 | switch (id) { |
2464 | case C168_ASIC_ID: | |
2465 | brd->info = &mxser_cards[0]; | |
2466 | break; | |
2467 | case C104_ASIC_ID: | |
2468 | brd->info = &mxser_cards[1]; | |
2469 | break; | |
2470 | case CI104J_ASIC_ID: | |
2471 | brd->info = &mxser_cards[2]; | |
2472 | break; | |
2473 | case C102_ASIC_ID: | |
2474 | brd->info = &mxser_cards[5]; | |
2475 | break; | |
2476 | case CI132_ASIC_ID: | |
2477 | brd->info = &mxser_cards[6]; | |
2478 | break; | |
2479 | case CI134_ASIC_ID: | |
2480 | brd->info = &mxser_cards[7]; | |
2481 | break; | |
2482 | default: | |
037ad48b | 2483 | return 0; |
cd7ed64e | 2484 | } |
037ad48b JS |
2485 | |
2486 | irq = 0; | |
cd7ed64e JS |
2487 | /* some ISA cards have 2 ports, but we want to see them as 4-port (why?) |
2488 | Flag-hack checks if configuration should be read as 2-port here. */ | |
2489 | if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) { | |
037ad48b JS |
2490 | irq = regs[9] & 0xF000; |
2491 | irq = irq | (irq >> 4); | |
2492 | if (irq != (regs[9] & 0xFF00)) | |
2493 | return MXSER_ERR_IRQ_CONFLIT; | |
cd7ed64e | 2494 | } else if (brd->info->nports == 4) { |
037ad48b JS |
2495 | irq = regs[9] & 0xF000; |
2496 | irq = irq | (irq >> 4); | |
2497 | irq = irq | (irq >> 8); | |
2498 | if (irq != regs[9]) | |
2499 | return MXSER_ERR_IRQ_CONFLIT; | |
cd7ed64e | 2500 | } else if (brd->info->nports == 8) { |
037ad48b JS |
2501 | irq = regs[9] & 0xF000; |
2502 | irq = irq | (irq >> 4); | |
2503 | irq = irq | (irq >> 8); | |
2504 | if ((irq != regs[9]) || (irq != regs[10])) | |
2505 | return MXSER_ERR_IRQ_CONFLIT; | |
2506 | } | |
2507 | ||
a8dea4ec JS |
2508 | if (!irq) |
2509 | return MXSER_ERR_IRQ; | |
2510 | brd->irq = ((int)(irq & 0xF000) >> 12); | |
2511 | for (i = 0; i < 8; i++) | |
2512 | brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8; | |
2513 | if ((regs[12] & 0x80) == 0) | |
2514 | return MXSER_ERR_VECTOR; | |
2515 | brd->vector = (int)regs[11]; /* interrupt vector */ | |
2516 | if (id == 1) | |
2517 | brd->vector_mask = 0x00FF; | |
2518 | else | |
2519 | brd->vector_mask = 0x000F; | |
2520 | for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) { | |
2521 | if (regs[12] & bits) { | |
2522 | brd->ports[i].baud_base = 921600; | |
e079f495 | 2523 | brd->ports[i].max_baud = 921600; |
a8dea4ec JS |
2524 | } else { |
2525 | brd->ports[i].baud_base = 115200; | |
e079f495 | 2526 | brd->ports[i].max_baud = 115200; |
a8dea4ec JS |
2527 | } |
2528 | } | |
2529 | scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB); | |
2530 | outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR); | |
2531 | outb(0, cap + UART_EFR); /* EFR is the same as FCR */ | |
2532 | outb(scratch2, cap + UART_LCR); | |
2533 | outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR); | |
2534 | scratch = inb(cap + UART_IIR); | |
2535 | ||
2536 | if (scratch & 0xC0) | |
2537 | brd->uart_type = PORT_16550A; | |
2538 | else | |
2539 | brd->uart_type = PORT_16450; | |
cd7ed64e JS |
2540 | if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports, |
2541 | "mxser(IO)")) | |
a8dea4ec JS |
2542 | return MXSER_ERR_IOADDR; |
2543 | if (!request_region(brd->vector, 1, "mxser(vector)")) { | |
cd7ed64e | 2544 | release_region(brd->ports[0].ioaddr, 8 * brd->info->nports); |
a8dea4ec JS |
2545 | return MXSER_ERR_VECTOR; |
2546 | } | |
cd7ed64e | 2547 | return brd->info->nports; |
a8dea4ec JS |
2548 | } |
2549 | ||
2094e757 JS |
2550 | static int __devinit mxser_probe(struct pci_dev *pdev, |
2551 | const struct pci_device_id *ent) | |
a8dea4ec | 2552 | { |
fb0c9295 | 2553 | #ifdef CONFIG_PCI |
2094e757 | 2554 | struct mxser_board *brd; |
a8dea4ec JS |
2555 | unsigned int i, j; |
2556 | unsigned long ioaddress; | |
2094e757 JS |
2557 | int retval = -EINVAL; |
2558 | ||
2559 | for (i = 0; i < MXSER_BOARDS; i++) | |
2560 | if (mxser_boards[i].info == NULL) | |
2561 | break; | |
2562 | ||
2563 | if (i >= MXSER_BOARDS) { | |
2564 | printk(KERN_ERR "Too many Smartio/Industio family boards found " | |
2565 | "(maximum %d), board not configured\n", MXSER_BOARDS); | |
2566 | goto err; | |
2567 | } | |
2568 | ||
2569 | brd = &mxser_boards[i]; | |
2570 | brd->idx = i * MXSER_PORTS_PER_BOARD; | |
2571 | printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n", | |
2572 | mxser_cards[ent->driver_data].name, | |
2573 | pdev->bus->number, PCI_SLOT(pdev->devfn)); | |
2574 | ||
2575 | retval = pci_enable_device(pdev); | |
2576 | if (retval) { | |
2577 | printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n"); | |
2578 | goto err; | |
2579 | } | |
a8dea4ec JS |
2580 | |
2581 | /* io address */ | |
a8dea4ec JS |
2582 | ioaddress = pci_resource_start(pdev, 2); |
2583 | retval = pci_request_region(pdev, 2, "mxser(IO)"); | |
2584 | if (retval) | |
2585 | goto err; | |
2586 | ||
2094e757 | 2587 | brd->info = &mxser_cards[ent->driver_data]; |
cd7ed64e | 2588 | for (i = 0; i < brd->info->nports; i++) |
a8dea4ec JS |
2589 | brd->ports[i].ioaddr = ioaddress + 8 * i; |
2590 | ||
2591 | /* vector */ | |
2592 | ioaddress = pci_resource_start(pdev, 3); | |
2593 | retval = pci_request_region(pdev, 3, "mxser(vector)"); | |
2594 | if (retval) | |
2595 | goto err_relio; | |
2596 | brd->vector = ioaddress; | |
2597 | ||
2598 | /* irq */ | |
2599 | brd->irq = pdev->irq; | |
2600 | ||
2601 | brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr); | |
2602 | brd->uart_type = PORT_16550A; | |
2603 | brd->vector_mask = 0; | |
2604 | ||
cd7ed64e | 2605 | for (i = 0; i < brd->info->nports; i++) { |
a8dea4ec JS |
2606 | for (j = 0; j < UART_INFO_NUM; j++) { |
2607 | if (Gpci_uart_info[j].type == brd->chip_flag) { | |
2608 | brd->ports[i].max_baud = | |
2609 | Gpci_uart_info[j].max_baud; | |
2610 | ||
2611 | /* exception....CP-102 */ | |
cd7ed64e | 2612 | if (brd->info->flags & MXSER_HIGHBAUD) |
a8dea4ec JS |
2613 | brd->ports[i].max_baud = 921600; |
2614 | break; | |
2615 | } | |
2616 | } | |
2617 | } | |
2618 | ||
2619 | if (brd->chip_flag == MOXA_MUST_MU860_HWID) { | |
cd7ed64e | 2620 | for (i = 0; i < brd->info->nports; i++) { |
a8dea4ec JS |
2621 | if (i < 4) |
2622 | brd->ports[i].opmode_ioaddr = ioaddress + 4; | |
2623 | else | |
2624 | brd->ports[i].opmode_ioaddr = ioaddress + 0x0c; | |
2625 | } | |
2626 | outb(0, ioaddress + 4); /* default set to RS232 mode */ | |
2627 | outb(0, ioaddress + 0x0c); /* default set to RS232 mode */ | |
2628 | } | |
2629 | ||
cd7ed64e | 2630 | for (i = 0; i < brd->info->nports; i++) { |
a8dea4ec JS |
2631 | brd->vector_mask |= (1 << i); |
2632 | brd->ports[i].baud_base = 921600; | |
2633 | } | |
2094e757 JS |
2634 | |
2635 | /* mxser_initbrd will hook ISR. */ | |
2636 | if (mxser_initbrd(brd, pdev) < 0) | |
2637 | goto err_relvec; | |
2638 | ||
2639 | for (i = 0; i < brd->info->nports; i++) | |
2640 | tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev); | |
2641 | ||
2642 | pci_set_drvdata(pdev, brd); | |
2643 | ||
a8dea4ec | 2644 | return 0; |
2094e757 JS |
2645 | err_relvec: |
2646 | pci_release_region(pdev, 3); | |
a8dea4ec JS |
2647 | err_relio: |
2648 | pci_release_region(pdev, 2); | |
2094e757 | 2649 | brd->info = NULL; |
a8dea4ec JS |
2650 | err: |
2651 | return retval; | |
fb0c9295 JS |
2652 | #else |
2653 | return -ENODEV; | |
2654 | #endif | |
a8dea4ec JS |
2655 | } |
2656 | ||
2094e757 JS |
2657 | static void __devexit mxser_remove(struct pci_dev *pdev) |
2658 | { | |
2659 | struct mxser_board *brd = pci_get_drvdata(pdev); | |
2660 | unsigned int i; | |
2661 | ||
2662 | for (i = 0; i < brd->info->nports; i++) | |
2663 | tty_unregister_device(mxvar_sdriver, brd->idx + i); | |
2664 | ||
2665 | mxser_release_res(brd, pdev, 1); | |
2666 | } | |
2667 | ||
2668 | static struct pci_driver mxser_driver = { | |
2669 | .name = "mxser", | |
2670 | .id_table = mxser_pcibrds, | |
2671 | .probe = mxser_probe, | |
2672 | .remove = __devexit_p(mxser_remove) | |
2673 | }; | |
2674 | ||
a8dea4ec JS |
2675 | static int __init mxser_module_init(void) |
2676 | { | |
a8dea4ec | 2677 | struct mxser_board *brd; |
eae4436a JS |
2678 | unsigned long cap; |
2679 | unsigned int i, m, isaloop; | |
2094e757 | 2680 | int retval, b; |
a8dea4ec JS |
2681 | |
2682 | pr_debug("Loading module mxser ...\n"); | |
2683 | ||
2684 | mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1); | |
2685 | if (!mxvar_sdriver) | |
2686 | return -ENOMEM; | |
2687 | spin_lock_init(&gm_lock); | |
2688 | ||
a8dea4ec JS |
2689 | printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n", |
2690 | MXSER_VERSION); | |
2691 | ||
2692 | /* Initialize the tty_driver structure */ | |
31f87cf4 | 2693 | mxvar_sdriver->owner = THIS_MODULE; |
a8dea4ec | 2694 | mxvar_sdriver->magic = TTY_DRIVER_MAGIC; |
e930790d | 2695 | mxvar_sdriver->name = "ttyMI"; |
a8dea4ec JS |
2696 | mxvar_sdriver->major = ttymajor; |
2697 | mxvar_sdriver->minor_start = 0; | |
2698 | mxvar_sdriver->num = MXSER_PORTS + 1; | |
2699 | mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; | |
2700 | mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; | |
2701 | mxvar_sdriver->init_termios = tty_std_termios; | |
2702 | mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; | |
938ef180 | 2703 | mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV; |
a8dea4ec | 2704 | tty_set_operations(mxvar_sdriver, &mxser_ops); |
a8dea4ec | 2705 | |
938ef180 JS |
2706 | retval = tty_register_driver(mxvar_sdriver); |
2707 | if (retval) { | |
2708 | printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " | |
2709 | "tty driver !\n"); | |
2710 | goto err_put; | |
2711 | } | |
2712 | ||
a8dea4ec JS |
2713 | mxvar_diagflag = 0; |
2714 | ||
2715 | m = 0; | |
2716 | /* Start finding ISA boards here */ | |
eae4436a JS |
2717 | for (isaloop = 0; isaloop < 2; isaloop++) |
2718 | for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) { | |
2719 | if (!isaloop) | |
2720 | cap = mxserBoardCAP[b]; /* predefined */ | |
2721 | else | |
2722 | cap = ioaddr[b]; /* module param */ | |
a8dea4ec | 2723 | |
eae4436a JS |
2724 | if (!cap) |
2725 | continue; | |
a8dea4ec | 2726 | |
eae4436a JS |
2727 | brd = &mxser_boards[m]; |
2728 | retval = mxser_get_ISA_conf(cap, brd); | |
2729 | ||
2730 | if (retval != 0) | |
2731 | printk(KERN_INFO "Found MOXA %s board " | |
2732 | "(CAP=0x%x)\n", | |
cd7ed64e | 2733 | brd->info->name, ioaddr[b]); |
eae4436a JS |
2734 | |
2735 | if (retval <= 0) { | |
2736 | if (retval == MXSER_ERR_IRQ) | |
2737 | printk(KERN_ERR "Invalid interrupt " | |
2738 | "number, board not " | |
2739 | "configured\n"); | |
2740 | else if (retval == MXSER_ERR_IRQ_CONFLIT) | |
2741 | printk(KERN_ERR "Invalid interrupt " | |
2742 | "number, board not " | |
2743 | "configured\n"); | |
2744 | else if (retval == MXSER_ERR_VECTOR) | |
2745 | printk(KERN_ERR "Invalid interrupt " | |
2746 | "vector, board not " | |
2747 | "configured\n"); | |
2748 | else if (retval == MXSER_ERR_IOADDR) | |
2749 | printk(KERN_ERR "Invalid I/O address, " | |
2750 | "board not configured\n"); | |
a8dea4ec | 2751 | |
2094e757 | 2752 | brd->info = NULL; |
eae4436a JS |
2753 | continue; |
2754 | } | |
a8dea4ec | 2755 | |
eae4436a | 2756 | /* mxser_initbrd will hook ISR. */ |
2094e757 JS |
2757 | if (mxser_initbrd(brd, NULL) < 0) { |
2758 | brd->info = NULL; | |
a8dea4ec JS |
2759 | continue; |
2760 | } | |
2094e757 JS |
2761 | |
2762 | brd->idx = m * MXSER_PORTS_PER_BOARD; | |
cd7ed64e | 2763 | for (i = 0; i < brd->info->nports; i++) |
2094e757 JS |
2764 | tty_register_device(mxvar_sdriver, brd->idx + i, |
2765 | NULL); | |
938ef180 | 2766 | |
a8dea4ec | 2767 | m++; |
a8dea4ec | 2768 | } |
037ad48b | 2769 | |
2094e757 JS |
2770 | retval = pci_register_driver(&mxser_driver); |
2771 | if (retval) { | |
2772 | printk(KERN_ERR "Can't register pci driver\n"); | |
2773 | if (!m) { | |
2774 | retval = -ENODEV; | |
2775 | goto err_unr; | |
2776 | } /* else: we have some ISA cards under control */ | |
037ad48b | 2777 | } |
a8dea4ec JS |
2778 | |
2779 | pr_debug("Done.\n"); | |
2780 | ||
938ef180 JS |
2781 | return 0; |
2782 | err_unr: | |
2783 | tty_unregister_driver(mxvar_sdriver); | |
2784 | err_put: | |
2785 | put_tty_driver(mxvar_sdriver); | |
a8dea4ec | 2786 | return retval; |
037ad48b JS |
2787 | } |
2788 | ||
a8dea4ec | 2789 | static void __exit mxser_module_exit(void) |
037ad48b | 2790 | { |
2094e757 | 2791 | unsigned int i, j; |
037ad48b | 2792 | |
a8dea4ec | 2793 | pr_debug("Unloading module mxser ...\n"); |
037ad48b | 2794 | |
2094e757 JS |
2795 | pci_unregister_driver(&mxser_driver); |
2796 | ||
2797 | for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */ | |
2798 | if (mxser_boards[i].info != NULL) | |
2799 | for (j = 0; j < mxser_boards[i].info->nports; j++) | |
2800 | tty_unregister_device(mxvar_sdriver, | |
2801 | mxser_boards[i].idx + j); | |
ead568c9 JS |
2802 | tty_unregister_driver(mxvar_sdriver); |
2803 | put_tty_driver(mxvar_sdriver); | |
037ad48b | 2804 | |
171d3a86 | 2805 | for (i = 0; i < MXSER_BOARDS; i++) |
cd7ed64e | 2806 | if (mxser_boards[i].info != NULL) |
2094e757 | 2807 | mxser_release_res(&mxser_boards[i], NULL, 1); |
037ad48b | 2808 | |
a8dea4ec | 2809 | pr_debug("Done.\n"); |
037ad48b JS |
2810 | } |
2811 | ||
2812 | module_init(mxser_module_init); | |
2813 | module_exit(mxser_module_exit); |