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1da177e4 LT |
1 | /******************************************************************************* |
2 | * | |
3 | * (c) 1998 by Computone Corporation | |
4 | * | |
5 | ******************************************************************************** | |
6 | * | |
7 | * | |
8 | * PACKAGE: Linux tty Device Driver for IntelliPort family of multiport | |
9 | * serial I/O controllers. | |
10 | * | |
11 | * DESCRIPTION: Low-level interface code for the device driver | |
12 | * (This is included source code, not a separate compilation | |
13 | * module.) | |
14 | * | |
15 | *******************************************************************************/ | |
16 | //--------------------------------------------- | |
17 | // Function declarations private to this module | |
18 | //--------------------------------------------- | |
19 | // Functions called only indirectly through i2eBordStr entries. | |
20 | ||
21 | static int iiWriteBuf16(i2eBordStrPtr, unsigned char *, int); | |
22 | static int iiWriteBuf8(i2eBordStrPtr, unsigned char *, int); | |
23 | static int iiReadBuf16(i2eBordStrPtr, unsigned char *, int); | |
24 | static int iiReadBuf8(i2eBordStrPtr, unsigned char *, int); | |
25 | ||
26 | static unsigned short iiReadWord16(i2eBordStrPtr); | |
27 | static unsigned short iiReadWord8(i2eBordStrPtr); | |
28 | static void iiWriteWord16(i2eBordStrPtr, unsigned short); | |
29 | static void iiWriteWord8(i2eBordStrPtr, unsigned short); | |
30 | ||
31 | static int iiWaitForTxEmptyII(i2eBordStrPtr, int); | |
32 | static int iiWaitForTxEmptyIIEX(i2eBordStrPtr, int); | |
33 | static int iiTxMailEmptyII(i2eBordStrPtr); | |
34 | static int iiTxMailEmptyIIEX(i2eBordStrPtr); | |
35 | static int iiTrySendMailII(i2eBordStrPtr, unsigned char); | |
36 | static int iiTrySendMailIIEX(i2eBordStrPtr, unsigned char); | |
37 | ||
38 | static unsigned short iiGetMailII(i2eBordStrPtr); | |
39 | static unsigned short iiGetMailIIEX(i2eBordStrPtr); | |
40 | ||
41 | static void iiEnableMailIrqII(i2eBordStrPtr); | |
42 | static void iiEnableMailIrqIIEX(i2eBordStrPtr); | |
43 | static void iiWriteMaskII(i2eBordStrPtr, unsigned char); | |
44 | static void iiWriteMaskIIEX(i2eBordStrPtr, unsigned char); | |
45 | ||
46 | static void ii2DelayTimer(unsigned int); | |
47 | static void ii2DelayWakeup(unsigned long id); | |
48 | static void ii2Nop(void); | |
49 | ||
50 | //*************** | |
51 | //* Static Data * | |
52 | //*************** | |
53 | ||
54 | static int ii2Safe; // Safe I/O address for delay routine | |
55 | ||
56 | static int iiDelayed; // Set when the iiResetDelay function is | |
57 | // called. Cleared when ANY board is reset. | |
58 | static struct timer_list * pDelayTimer; // Used by iiDelayTimer | |
59 | static wait_queue_head_t pDelayWait; // Used by iiDelayTimer | |
60 | static rwlock_t Dl_spinlock; | |
61 | ||
62 | //******** | |
63 | //* Code * | |
64 | //******** | |
65 | ||
66 | //======================================================= | |
67 | // Initialization Routines | |
68 | // | |
69 | // iiSetAddress | |
70 | // iiReset | |
71 | // iiResetDelay | |
72 | // iiInitialize | |
73 | //======================================================= | |
74 | ||
75 | //****************************************************************************** | |
76 | // Function: iiEllisInit() | |
77 | // Parameters: None | |
78 | // | |
79 | // Returns: Nothing | |
80 | // | |
81 | // Description: | |
82 | // | |
83 | // This routine performs any required initialization of the iiEllis subsystem. | |
84 | // | |
85 | //****************************************************************************** | |
86 | static void | |
87 | iiEllisInit(void) | |
88 | { | |
89 | pDelayTimer = kmalloc ( sizeof (struct timer_list), GFP_KERNEL ); | |
90 | init_timer(pDelayTimer); | |
91 | init_waitqueue_head(&pDelayWait); | |
92 | LOCK_INIT(&Dl_spinlock); | |
93 | } | |
94 | ||
95 | //****************************************************************************** | |
96 | // Function: iiEllisCleanup() | |
97 | // Parameters: None | |
98 | // | |
99 | // Returns: Nothing | |
100 | // | |
101 | // Description: | |
102 | // | |
103 | // This routine performs any required cleanup of the iiEllis subsystem. | |
104 | // | |
105 | //****************************************************************************** | |
106 | static void | |
107 | iiEllisCleanup(void) | |
108 | { | |
735d5661 | 109 | kfree(pDelayTimer); |
1da177e4 LT |
110 | } |
111 | ||
112 | //****************************************************************************** | |
113 | // Function: iiSetAddress(pB, address, delay) | |
114 | // Parameters: pB - pointer to the board structure | |
115 | // address - the purported I/O address of the board | |
116 | // delay - pointer to the 1-ms delay function to use | |
117 | // in this and any future operations to this board | |
118 | // | |
119 | // Returns: True if everything appears copacetic. | |
120 | // False if there is any error: the pB->i2eError field has the error | |
121 | // | |
122 | // Description: | |
123 | // | |
124 | // This routine (roughly) checks for address validity, sets the i2eValid OK and | |
125 | // sets the state to II_STATE_COLD which means that we haven't even sent a reset | |
126 | // yet. | |
127 | // | |
128 | //****************************************************************************** | |
129 | static int | |
130 | iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay ) | |
131 | { | |
132 | // Should any failure occur before init is finished... | |
133 | pB->i2eValid = I2E_INCOMPLETE; | |
134 | ||
135 | // Cannot check upper limit except extremely: Might be microchannel | |
136 | // Address must be on an 8-byte boundary | |
137 | ||
138 | if ((unsigned int)address <= 0x100 | |
139 | || (unsigned int)address >= 0xfff8 | |
140 | || (address & 0x7) | |
141 | ) | |
142 | { | |
143 | COMPLETE(pB,I2EE_BADADDR); | |
144 | } | |
145 | ||
146 | // Initialize accelerators | |
147 | pB->i2eBase = address; | |
148 | pB->i2eData = address + FIFO_DATA; | |
149 | pB->i2eStatus = address + FIFO_STATUS; | |
150 | pB->i2ePointer = address + FIFO_PTR; | |
151 | pB->i2eXMail = address + FIFO_MAIL; | |
152 | pB->i2eXMask = address + FIFO_MASK; | |
153 | ||
154 | // Initialize i/o address for ii2DelayIO | |
155 | ii2Safe = address + FIFO_NOP; | |
156 | ||
157 | // Initialize the delay routine | |
158 | pB->i2eDelay = ((delay != (delayFunc_t)NULL) ? delay : (delayFunc_t)ii2Nop); | |
159 | ||
160 | pB->i2eValid = I2E_MAGIC; | |
161 | pB->i2eState = II_STATE_COLD; | |
162 | ||
163 | COMPLETE(pB, I2EE_GOOD); | |
164 | } | |
165 | ||
166 | //****************************************************************************** | |
167 | // Function: iiReset(pB) | |
168 | // Parameters: pB - pointer to the board structure | |
169 | // | |
170 | // Returns: True if everything appears copacetic. | |
171 | // False if there is any error: the pB->i2eError field has the error | |
172 | // | |
173 | // Description: | |
174 | // | |
175 | // Attempts to reset the board (see also i2hw.h). Normally, we would use this to | |
176 | // reset a board immediately after iiSetAddress(), but it is valid to reset a | |
177 | // board from any state, say, in order to change or re-load loadware. (Under | |
178 | // such circumstances, no reason to re-run iiSetAddress(), which is why it is a | |
179 | // separate routine and not included in this routine. | |
180 | // | |
181 | //****************************************************************************** | |
182 | static int | |
183 | iiReset(i2eBordStrPtr pB) | |
184 | { | |
185 | // Magic number should be set, else even the address is suspect | |
186 | if (pB->i2eValid != I2E_MAGIC) | |
187 | { | |
188 | COMPLETE(pB, I2EE_BADMAGIC); | |
189 | } | |
190 | ||
191 | OUTB(pB->i2eBase + FIFO_RESET, 0); // Any data will do | |
192 | iiDelay(pB, 50); // Pause between resets | |
193 | OUTB(pB->i2eBase + FIFO_RESET, 0); // Second reset | |
194 | ||
195 | // We must wait before even attempting to read anything from the FIFO: the | |
196 | // board's P.O.S.T may actually attempt to read and write its end of the | |
197 | // FIFO in order to check flags, loop back (where supported), etc. On | |
198 | // completion of this testing it would reset the FIFO, and on completion | |
199 | // of all // P.O.S.T., write the message. We must not mistake data which | |
200 | // might have been sent for testing as part of the reset message. To | |
201 | // better utilize time, say, when resetting several boards, we allow the | |
202 | // delay to be performed externally; in this way the caller can reset | |
203 | // several boards, delay a single time, then call the initialization | |
204 | // routine for all. | |
205 | ||
206 | pB->i2eState = II_STATE_RESET; | |
207 | ||
208 | iiDelayed = 0; // i.e., the delay routine hasn't been called since the most | |
209 | // recent reset. | |
210 | ||
211 | // Ensure anything which would have been of use to standard loadware is | |
212 | // blanked out, since board has now forgotten everything!. | |
213 | ||
214 | pB->i2eUsingIrq = IRQ_UNDEFINED; // Not set up to use an interrupt yet | |
215 | pB->i2eWaitingForEmptyFifo = 0; | |
216 | pB->i2eOutMailWaiting = 0; | |
217 | pB->i2eChannelPtr = NULL; | |
218 | pB->i2eChannelCnt = 0; | |
219 | ||
220 | pB->i2eLeadoffWord[0] = 0; | |
221 | pB->i2eFifoInInts = 0; | |
222 | pB->i2eFifoOutInts = 0; | |
223 | pB->i2eFatalTrap = NULL; | |
224 | pB->i2eFatal = 0; | |
225 | ||
226 | COMPLETE(pB, I2EE_GOOD); | |
227 | } | |
228 | ||
229 | //****************************************************************************** | |
230 | // Function: iiResetDelay(pB) | |
231 | // Parameters: pB - pointer to the board structure | |
232 | // | |
233 | // Returns: True if everything appears copacetic. | |
234 | // False if there is any error: the pB->i2eError field has the error | |
235 | // | |
236 | // Description: | |
237 | // | |
238 | // Using the delay defined in board structure, waits two seconds (for board to | |
239 | // reset). | |
240 | // | |
241 | //****************************************************************************** | |
242 | static int | |
243 | iiResetDelay(i2eBordStrPtr pB) | |
244 | { | |
245 | if (pB->i2eValid != I2E_MAGIC) { | |
246 | COMPLETE(pB, I2EE_BADMAGIC); | |
247 | } | |
248 | if (pB->i2eState != II_STATE_RESET) { | |
249 | COMPLETE(pB, I2EE_BADSTATE); | |
250 | } | |
251 | iiDelay(pB,2000); /* Now we wait for two seconds. */ | |
252 | iiDelayed = 1; /* Delay has been called: ok to initialize */ | |
253 | COMPLETE(pB, I2EE_GOOD); | |
254 | } | |
255 | ||
256 | //****************************************************************************** | |
257 | // Function: iiInitialize(pB) | |
258 | // Parameters: pB - pointer to the board structure | |
259 | // | |
260 | // Returns: True if everything appears copacetic. | |
261 | // False if there is any error: the pB->i2eError field has the error | |
262 | // | |
263 | // Description: | |
264 | // | |
265 | // Attempts to read the Power-on reset message. Initializes any remaining fields | |
266 | // in the pB structure. | |
267 | // | |
268 | // This should be called as the third step of a process beginning with | |
269 | // iiReset(), then iiResetDelay(). This routine checks to see that the structure | |
270 | // is "valid" and in the reset state, also confirms that the delay routine has | |
271 | // been called since the latest reset (to any board! overly strong!). | |
272 | // | |
273 | //****************************************************************************** | |
274 | static int | |
275 | iiInitialize(i2eBordStrPtr pB) | |
276 | { | |
277 | int itemp; | |
278 | unsigned char c; | |
279 | unsigned short utemp; | |
280 | unsigned int ilimit; | |
281 | ||
282 | if (pB->i2eValid != I2E_MAGIC) | |
283 | { | |
284 | COMPLETE(pB, I2EE_BADMAGIC); | |
285 | } | |
286 | ||
287 | if (pB->i2eState != II_STATE_RESET || !iiDelayed) | |
288 | { | |
289 | COMPLETE(pB, I2EE_BADSTATE); | |
290 | } | |
291 | ||
292 | // In case there is a failure short of our completely reading the power-up | |
293 | // message. | |
294 | pB->i2eValid = I2E_INCOMPLETE; | |
295 | ||
296 | ||
297 | // Now attempt to read the message. | |
298 | ||
299 | for (itemp = 0; itemp < sizeof(porStr); itemp++) | |
300 | { | |
301 | // We expect the entire message is ready. | |
302 | if (HAS_NO_INPUT(pB)) | |
303 | { | |
304 | pB->i2ePomSize = itemp; | |
305 | COMPLETE(pB, I2EE_PORM_SHORT); | |
306 | } | |
307 | ||
308 | pB->i2ePom.c[itemp] = c = BYTE_FROM(pB); | |
309 | ||
310 | // We check the magic numbers as soon as they are supposed to be read | |
311 | // (rather than after) to minimize effect of reading something we | |
312 | // already suspect can't be "us". | |
313 | if ( (itemp == POR_1_INDEX && c != POR_MAGIC_1) || | |
314 | (itemp == POR_2_INDEX && c != POR_MAGIC_2)) | |
315 | { | |
316 | pB->i2ePomSize = itemp+1; | |
317 | COMPLETE(pB, I2EE_BADMAGIC); | |
318 | } | |
319 | } | |
320 | ||
321 | pB->i2ePomSize = itemp; | |
322 | ||
323 | // Ensure that this was all the data... | |
324 | if (HAS_INPUT(pB)) | |
325 | COMPLETE(pB, I2EE_PORM_LONG); | |
326 | ||
327 | // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper: | |
328 | // Implying we will not be able to download any code either: That's ok: the | |
329 | // condition is pretty explicit. | |
330 | if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER) | |
331 | { | |
332 | COMPLETE(pB, I2EE_POSTERR); | |
333 | } | |
334 | ||
335 | // Determine anything which must be done differently depending on the family | |
336 | // of boards! | |
337 | switch (pB->i2ePom.e.porID & POR_ID_FAMILY) | |
338 | { | |
339 | case POR_ID_FII: // IntelliPort-II | |
340 | ||
341 | pB->i2eFifoStyle = FIFO_II; | |
342 | pB->i2eFifoSize = 512; // 512 bytes, always | |
343 | pB->i2eDataWidth16 = NO; | |
344 | ||
345 | pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit | |
346 | // slot, we do allow it to be done (documentation!) | |
347 | ||
348 | pB->i2eGoodMap[1] = | |
349 | pB->i2eGoodMap[2] = | |
350 | pB->i2eGoodMap[3] = | |
351 | pB->i2eChannelMap[1] = | |
352 | pB->i2eChannelMap[2] = | |
353 | pB->i2eChannelMap[3] = 0; | |
354 | ||
355 | switch (pB->i2ePom.e.porID & POR_ID_SIZE) | |
356 | { | |
357 | case POR_ID_II_4: | |
358 | pB->i2eGoodMap[0] = | |
359 | pB->i2eChannelMap[0] = 0x0f; // four-port | |
360 | ||
361 | // Since porPorts1 is based on the Hardware ID register, the numbers | |
362 | // should always be consistent for IntelliPort-II. Ditto below... | |
363 | if (pB->i2ePom.e.porPorts1 != 4) | |
364 | { | |
365 | COMPLETE(pB, I2EE_INCONSIST); | |
366 | } | |
367 | break; | |
368 | ||
369 | case POR_ID_II_8: | |
370 | case POR_ID_II_8R: | |
371 | pB->i2eGoodMap[0] = | |
372 | pB->i2eChannelMap[0] = 0xff; // Eight port | |
373 | if (pB->i2ePom.e.porPorts1 != 8) | |
374 | { | |
375 | COMPLETE(pB, I2EE_INCONSIST); | |
376 | } | |
377 | break; | |
378 | ||
379 | case POR_ID_II_6: | |
380 | pB->i2eGoodMap[0] = | |
381 | pB->i2eChannelMap[0] = 0x3f; // Six Port | |
382 | if (pB->i2ePom.e.porPorts1 != 6) | |
383 | { | |
384 | COMPLETE(pB, I2EE_INCONSIST); | |
385 | } | |
386 | break; | |
387 | } | |
388 | ||
389 | // Fix up the "good channel list based on any errors reported. | |
390 | if (pB->i2ePom.e.porDiag1 & POR_BAD_UART1) | |
391 | { | |
392 | pB->i2eGoodMap[0] &= ~0x0f; | |
393 | } | |
394 | ||
395 | if (pB->i2ePom.e.porDiag1 & POR_BAD_UART2) | |
396 | { | |
397 | pB->i2eGoodMap[0] &= ~0xf0; | |
398 | } | |
399 | ||
400 | break; // POR_ID_FII case | |
401 | ||
402 | case POR_ID_FIIEX: // IntelliPort-IIEX | |
403 | ||
404 | pB->i2eFifoStyle = FIFO_IIEX; | |
405 | ||
406 | itemp = pB->i2ePom.e.porFifoSize; | |
407 | ||
408 | // Implicit assumption that fifo would not grow beyond 32k, | |
409 | // nor would ever be less than 256. | |
410 | ||
411 | if (itemp < 8 || itemp > 15) | |
412 | { | |
413 | COMPLETE(pB, I2EE_INCONSIST); | |
414 | } | |
415 | pB->i2eFifoSize = (1 << itemp); | |
416 | ||
417 | // These are based on what P.O.S.T thinks should be there, based on | |
418 | // box ID registers | |
419 | ilimit = pB->i2ePom.e.porNumBoxes; | |
420 | if (ilimit > ABS_MAX_BOXES) | |
421 | { | |
422 | ilimit = ABS_MAX_BOXES; | |
423 | } | |
424 | ||
425 | // For as many boxes as EXIST, gives the type of box. | |
426 | // Added 8/6/93: check for the ISA-4 (asic) which looks like an | |
427 | // expandable but for whom "8 or 16?" is not the right question. | |
428 | ||
429 | utemp = pB->i2ePom.e.porFlags; | |
430 | if (utemp & POR_CEX4) | |
431 | { | |
432 | pB->i2eChannelMap[0] = 0x000f; | |
433 | } else { | |
434 | utemp &= POR_BOXES; | |
435 | for (itemp = 0; itemp < ilimit; itemp++) | |
436 | { | |
437 | pB->i2eChannelMap[itemp] = | |
438 | ((utemp & POR_BOX_16) ? 0xffff : 0x00ff); | |
439 | utemp >>= 1; | |
440 | } | |
441 | } | |
442 | ||
443 | // These are based on what P.O.S.T actually found. | |
444 | ||
445 | utemp = (pB->i2ePom.e.porPorts2 << 8) + pB->i2ePom.e.porPorts1; | |
446 | ||
447 | for (itemp = 0; itemp < ilimit; itemp++) | |
448 | { | |
449 | pB->i2eGoodMap[itemp] = 0; | |
450 | if (utemp & 1) pB->i2eGoodMap[itemp] |= 0x000f; | |
451 | if (utemp & 2) pB->i2eGoodMap[itemp] |= 0x00f0; | |
452 | if (utemp & 4) pB->i2eGoodMap[itemp] |= 0x0f00; | |
453 | if (utemp & 8) pB->i2eGoodMap[itemp] |= 0xf000; | |
454 | utemp >>= 4; | |
455 | } | |
456 | ||
457 | // Now determine whether we should transfer in 8 or 16-bit mode. | |
458 | switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) ) | |
459 | { | |
460 | case POR_BUS_SLOT16 | POR_BUS_DIP16: | |
461 | pB->i2eDataWidth16 = YES; | |
462 | pB->i2eMaxIrq = 15; | |
463 | break; | |
464 | ||
465 | case POR_BUS_SLOT16: | |
466 | pB->i2eDataWidth16 = NO; | |
467 | pB->i2eMaxIrq = 15; | |
468 | break; | |
469 | ||
470 | case 0: | |
471 | case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care. | |
472 | default: | |
473 | pB->i2eDataWidth16 = NO; | |
474 | pB->i2eMaxIrq = 7; | |
475 | break; | |
476 | } | |
477 | break; // POR_ID_FIIEX case | |
478 | ||
479 | default: // Unknown type of board | |
480 | COMPLETE(pB, I2EE_BAD_FAMILY); | |
481 | break; | |
482 | } // End the switch based on family | |
483 | ||
484 | // Temporarily, claim there is no room in the outbound fifo. | |
485 | // We will maintain this whenever we check for an empty outbound FIFO. | |
486 | pB->i2eFifoRemains = 0; | |
487 | ||
488 | // Now, based on the bus type, should we expect to be able to re-configure | |
489 | // interrupts (say, for testing purposes). | |
490 | switch (pB->i2ePom.e.porBus & POR_BUS_TYPE) | |
491 | { | |
492 | case POR_BUS_T_ISA: | |
493 | case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok. | |
494 | pB->i2eChangeIrq = YES; | |
495 | break; | |
496 | case POR_BUS_T_MCA: | |
497 | case POR_BUS_T_EISA: | |
498 | pB->i2eChangeIrq = NO; | |
499 | break; | |
500 | default: | |
501 | COMPLETE(pB, I2EE_BADBUS); | |
502 | } | |
503 | ||
504 | if (pB->i2eDataWidth16 == YES) | |
505 | { | |
506 | pB->i2eWriteBuf = iiWriteBuf16; | |
507 | pB->i2eReadBuf = iiReadBuf16; | |
508 | pB->i2eWriteWord = iiWriteWord16; | |
509 | pB->i2eReadWord = iiReadWord16; | |
510 | } else { | |
511 | pB->i2eWriteBuf = iiWriteBuf8; | |
512 | pB->i2eReadBuf = iiReadBuf8; | |
513 | pB->i2eWriteWord = iiWriteWord8; | |
514 | pB->i2eReadWord = iiReadWord8; | |
515 | } | |
516 | ||
517 | switch(pB->i2eFifoStyle) | |
518 | { | |
519 | case FIFO_II: | |
520 | pB->i2eWaitForTxEmpty = iiWaitForTxEmptyII; | |
521 | pB->i2eTxMailEmpty = iiTxMailEmptyII; | |
522 | pB->i2eTrySendMail = iiTrySendMailII; | |
523 | pB->i2eGetMail = iiGetMailII; | |
524 | pB->i2eEnableMailIrq = iiEnableMailIrqII; | |
525 | pB->i2eWriteMask = iiWriteMaskII; | |
526 | ||
527 | break; | |
528 | ||
529 | case FIFO_IIEX: | |
530 | pB->i2eWaitForTxEmpty = iiWaitForTxEmptyIIEX; | |
531 | pB->i2eTxMailEmpty = iiTxMailEmptyIIEX; | |
532 | pB->i2eTrySendMail = iiTrySendMailIIEX; | |
533 | pB->i2eGetMail = iiGetMailIIEX; | |
534 | pB->i2eEnableMailIrq = iiEnableMailIrqIIEX; | |
535 | pB->i2eWriteMask = iiWriteMaskIIEX; | |
536 | ||
537 | break; | |
538 | ||
539 | default: | |
540 | COMPLETE(pB, I2EE_INCONSIST); | |
541 | } | |
542 | ||
543 | // Initialize state information. | |
544 | pB->i2eState = II_STATE_READY; // Ready to load loadware. | |
545 | ||
546 | // Some Final cleanup: | |
547 | // For some boards, the bootstrap firmware may perform some sort of test | |
548 | // resulting in a stray character pending in the incoming mailbox. If one is | |
549 | // there, it should be read and discarded, especially since for the standard | |
550 | // firmware, it's the mailbox that interrupts the host. | |
551 | ||
552 | pB->i2eStartMail = iiGetMail(pB); | |
553 | ||
554 | // Throw it away and clear the mailbox structure element | |
555 | pB->i2eStartMail = NO_MAIL_HERE; | |
556 | ||
557 | // Everything is ok now, return with good status/ | |
558 | ||
559 | pB->i2eValid = I2E_MAGIC; | |
560 | COMPLETE(pB, I2EE_GOOD); | |
561 | } | |
562 | ||
563 | //======================================================= | |
564 | // Delay Routines | |
565 | // | |
566 | // iiDelayIO | |
567 | // iiNop | |
568 | //======================================================= | |
569 | ||
570 | static void | |
571 | ii2DelayWakeup(unsigned long id) | |
572 | { | |
573 | wake_up_interruptible ( &pDelayWait ); | |
574 | } | |
575 | ||
576 | //****************************************************************************** | |
577 | // Function: ii2DelayTimer(mseconds) | |
578 | // Parameters: mseconds - number of milliseconds to delay | |
579 | // | |
580 | // Returns: Nothing | |
581 | // | |
582 | // Description: | |
583 | // | |
584 | // This routine delays for approximately mseconds milliseconds and is intended | |
585 | // to be called indirectly through i2Delay field in i2eBordStr. It uses the | |
586 | // Linux timer_list mechanism. | |
587 | // | |
588 | // The Linux timers use a unit called "jiffies" which are 10mS in the Intel | |
589 | // architecture. This function rounds the delay period up to the next "jiffy". | |
590 | // In the Alpha architecture the "jiffy" is 1mS, but this driver is not intended | |
591 | // for Alpha platforms at this time. | |
592 | // | |
593 | //****************************************************************************** | |
594 | static void | |
595 | ii2DelayTimer(unsigned int mseconds) | |
596 | { | |
597 | wait_queue_t wait; | |
598 | ||
599 | init_waitqueue_entry(&wait, current); | |
600 | ||
601 | init_timer ( pDelayTimer ); | |
602 | ||
603 | add_wait_queue(&pDelayWait, &wait); | |
604 | ||
605 | set_current_state( TASK_INTERRUPTIBLE ); | |
606 | ||
607 | pDelayTimer->expires = jiffies + ( mseconds + 9 ) / 10; | |
608 | pDelayTimer->function = ii2DelayWakeup; | |
609 | pDelayTimer->data = 0; | |
610 | ||
611 | add_timer ( pDelayTimer ); | |
612 | ||
613 | schedule(); | |
614 | ||
615 | set_current_state( TASK_RUNNING ); | |
616 | remove_wait_queue(&pDelayWait, &wait); | |
617 | ||
618 | del_timer ( pDelayTimer ); | |
619 | } | |
620 | ||
621 | #if 0 | |
622 | //static void ii2DelayIO(unsigned int); | |
623 | //****************************************************************************** | |
624 | // !!! Not Used, this is DOS crap, some of you young folks may be interested in | |
625 | // in how things were done in the stone age of caculating machines !!! | |
626 | // Function: ii2DelayIO(mseconds) | |
627 | // Parameters: mseconds - number of milliseconds to delay | |
628 | // | |
629 | // Returns: Nothing | |
630 | // | |
631 | // Description: | |
632 | // | |
633 | // This routine delays for approximately mseconds milliseconds and is intended | |
634 | // to be called indirectly through i2Delay field in i2eBordStr. It is intended | |
635 | // for use where a clock-based function is impossible: for example, DOS drivers. | |
636 | // | |
637 | // This function uses the IN instruction to place bounds on the timing and | |
638 | // assumes that ii2Safe has been set. This is because I/O instructions are not | |
639 | // subject to caching and will therefore take a certain minimum time. To ensure | |
640 | // the delay is at least long enough on fast machines, it is based on some | |
641 | // fastest-case calculations. On slower machines this may cause VERY long | |
642 | // delays. (3 x fastest case). In the fastest case, everything is cached except | |
643 | // the I/O instruction itself. | |
644 | // | |
645 | // Timing calculations: | |
646 | // The fastest bus speed for I/O operations is likely to be 10 MHz. The I/O | |
647 | // operation in question is a byte operation to an odd address. For 8-bit | |
648 | // operations, the architecture generally enforces two wait states. At 10 MHz, a | |
649 | // single cycle time is 100nS. A read operation at two wait states takes 6 | |
650 | // cycles for a total time of 600nS. Therefore approximately 1666 iterations | |
651 | // would be required to generate a single millisecond delay. The worst | |
652 | // (reasonable) case would be an 8MHz system with no cacheing. In this case, the | |
653 | // I/O instruction would take 125nS x 6 cyles = 750 nS. More importantly, code | |
654 | // fetch of other instructions in the loop would take time (zero wait states, | |
655 | // however) and would be hard to estimate. This is minimized by using in-line | |
656 | // assembler for the in inner loop of IN instructions. This consists of just a | |
657 | // few bytes. So we'll guess about four code fetches per loop. Each code fetch | |
658 | // should take four cycles, so we have 125nS * 8 = 1000nS. Worst case then is | |
659 | // that what should have taken 1 mS takes instead 1666 * (1750) = 2.9 mS. | |
660 | // | |
661 | // So much for theoretical timings: results using 1666 value on some actual | |
662 | // machines: | |
663 | // IBM 286 6MHz 3.15 mS | |
664 | // Zenith 386 33MHz 2.45 mS | |
665 | // (brandX) 386 33MHz 1.90 mS (has cache) | |
666 | // (brandY) 486 33MHz 2.35 mS | |
667 | // NCR 486 ?? 1.65 mS (microchannel) | |
668 | // | |
669 | // For most machines, it is probably safe to scale this number back (remember, | |
670 | // for robust operation use an actual timed delay if possible), so we are using | |
671 | // a value of 1190. This yields 1.17 mS for the fastest machine in our sample, | |
672 | // 1.75 mS for typical 386 machines, and 2.25 mS the absolute slowest machine. | |
673 | // | |
674 | // 1/29/93: | |
675 | // The above timings are too slow. Actual cycle times might be faster. ISA cycle | |
676 | // times could approach 500 nS, and ... | |
677 | // The IBM model 77 being microchannel has no wait states for 8-bit reads and | |
678 | // seems to be accessing the I/O at 440 nS per access (from start of one to | |
679 | // start of next). This would imply we need 1000/.440 = 2272 iterations to | |
680 | // guarantee we are fast enough. In actual testing, we see that 2 * 1190 are in | |
681 | // fact enough. For diagnostics, we keep the level at 1190, but developers note | |
682 | // this needs tuning. | |
683 | // | |
684 | // Safe assumption: 2270 i/o reads = 1 millisecond | |
685 | // | |
686 | //****************************************************************************** | |
687 | ||
688 | ||
689 | static int ii2DelValue = 1190; // See timing calculations below | |
690 | // 1666 for fastest theoretical machine | |
691 | // 1190 safe for most fast 386 machines | |
692 | // 1000 for fastest machine tested here | |
693 | // 540 (sic) for AT286/6Mhz | |
694 | static void | |
695 | ii2DelayIO(unsigned int mseconds) | |
696 | { | |
697 | if (!ii2Safe) | |
698 | return; /* Do nothing if this variable uninitialized */ | |
699 | ||
700 | while(mseconds--) { | |
701 | int i = ii2DelValue; | |
702 | while ( i-- ) { | |
703 | INB ( ii2Safe ); | |
704 | } | |
705 | } | |
706 | } | |
707 | #endif | |
708 | ||
709 | //****************************************************************************** | |
710 | // Function: ii2Nop() | |
711 | // Parameters: None | |
712 | // | |
713 | // Returns: Nothing | |
714 | // | |
715 | // Description: | |
716 | // | |
717 | // iiInitialize will set i2eDelay to this if the delay parameter is NULL. This | |
718 | // saves checking for a NULL pointer at every call. | |
719 | //****************************************************************************** | |
720 | static void | |
721 | ii2Nop(void) | |
722 | { | |
723 | return; // no mystery here | |
724 | } | |
725 | ||
726 | //======================================================= | |
727 | // Routines which are available in 8/16-bit versions, or | |
728 | // in different fifo styles. These are ALL called | |
729 | // indirectly through the board structure. | |
730 | //======================================================= | |
731 | ||
732 | //****************************************************************************** | |
733 | // Function: iiWriteBuf16(pB, address, count) | |
734 | // Parameters: pB - pointer to board structure | |
735 | // address - address of data to write | |
736 | // count - number of data bytes to write | |
737 | // | |
738 | // Returns: True if everything appears copacetic. | |
739 | // False if there is any error: the pB->i2eError field has the error | |
740 | // | |
741 | // Description: | |
742 | // | |
743 | // Writes 'count' bytes from 'address' to the data fifo specified by the board | |
744 | // structure pointer pB. Should count happen to be odd, an extra pad byte is | |
745 | // sent (identity unknown...). Uses 16-bit (word) operations. Is called | |
746 | // indirectly through pB->i2eWriteBuf. | |
747 | // | |
748 | //****************************************************************************** | |
749 | static int | |
750 | iiWriteBuf16(i2eBordStrPtr pB, unsigned char *address, int count) | |
751 | { | |
752 | // Rudimentary sanity checking here. | |
753 | if (pB->i2eValid != I2E_MAGIC) | |
754 | COMPLETE(pB, I2EE_INVALID); | |
755 | ||
756 | OUTSW ( pB->i2eData, address, count); | |
757 | ||
758 | COMPLETE(pB, I2EE_GOOD); | |
759 | } | |
760 | ||
761 | //****************************************************************************** | |
762 | // Function: iiWriteBuf8(pB, address, count) | |
763 | // Parameters: pB - pointer to board structure | |
764 | // address - address of data to write | |
765 | // count - number of data bytes to write | |
766 | // | |
767 | // Returns: True if everything appears copacetic. | |
768 | // False if there is any error: the pB->i2eError field has the error | |
769 | // | |
770 | // Description: | |
771 | // | |
772 | // Writes 'count' bytes from 'address' to the data fifo specified by the board | |
773 | // structure pointer pB. Should count happen to be odd, an extra pad byte is | |
774 | // sent (identity unknown...). This is to be consistent with the 16-bit version. | |
775 | // Uses 8-bit (byte) operations. Is called indirectly through pB->i2eWriteBuf. | |
776 | // | |
777 | //****************************************************************************** | |
778 | static int | |
779 | iiWriteBuf8(i2eBordStrPtr pB, unsigned char *address, int count) | |
780 | { | |
781 | /* Rudimentary sanity checking here */ | |
782 | if (pB->i2eValid != I2E_MAGIC) | |
783 | COMPLETE(pB, I2EE_INVALID); | |
784 | ||
785 | OUTSB ( pB->i2eData, address, count ); | |
786 | ||
787 | COMPLETE(pB, I2EE_GOOD); | |
788 | } | |
789 | ||
790 | //****************************************************************************** | |
791 | // Function: iiReadBuf16(pB, address, count) | |
792 | // Parameters: pB - pointer to board structure | |
793 | // address - address to put data read | |
794 | // count - number of data bytes to read | |
795 | // | |
796 | // Returns: True if everything appears copacetic. | |
797 | // False if there is any error: the pB->i2eError field has the error | |
798 | // | |
799 | // Description: | |
800 | // | |
801 | // Reads 'count' bytes into 'address' from the data fifo specified by the board | |
802 | // structure pointer pB. Should count happen to be odd, an extra pad byte is | |
803 | // received (identity unknown...). Uses 16-bit (word) operations. Is called | |
804 | // indirectly through pB->i2eReadBuf. | |
805 | // | |
806 | //****************************************************************************** | |
807 | static int | |
808 | iiReadBuf16(i2eBordStrPtr pB, unsigned char *address, int count) | |
809 | { | |
810 | // Rudimentary sanity checking here. | |
811 | if (pB->i2eValid != I2E_MAGIC) | |
812 | COMPLETE(pB, I2EE_INVALID); | |
813 | ||
814 | INSW ( pB->i2eData, address, count); | |
815 | ||
816 | COMPLETE(pB, I2EE_GOOD); | |
817 | } | |
818 | ||
819 | //****************************************************************************** | |
820 | // Function: iiReadBuf8(pB, address, count) | |
821 | // Parameters: pB - pointer to board structure | |
822 | // address - address to put data read | |
823 | // count - number of data bytes to read | |
824 | // | |
825 | // Returns: True if everything appears copacetic. | |
826 | // False if there is any error: the pB->i2eError field has the error | |
827 | // | |
828 | // Description: | |
829 | // | |
830 | // Reads 'count' bytes into 'address' from the data fifo specified by the board | |
831 | // structure pointer pB. Should count happen to be odd, an extra pad byte is | |
832 | // received (identity unknown...). This to match the 16-bit behaviour. Uses | |
833 | // 8-bit (byte) operations. Is called indirectly through pB->i2eReadBuf. | |
834 | // | |
835 | //****************************************************************************** | |
836 | static int | |
837 | iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count) | |
838 | { | |
839 | // Rudimentary sanity checking here. | |
840 | if (pB->i2eValid != I2E_MAGIC) | |
841 | COMPLETE(pB, I2EE_INVALID); | |
842 | ||
843 | INSB ( pB->i2eData, address, count); | |
844 | ||
845 | COMPLETE(pB, I2EE_GOOD); | |
846 | } | |
847 | ||
848 | //****************************************************************************** | |
849 | // Function: iiReadWord16(pB) | |
850 | // Parameters: pB - pointer to board structure | |
851 | // | |
852 | // Returns: True if everything appears copacetic. | |
853 | // False if there is any error: the pB->i2eError field has the error | |
854 | // | |
855 | // Description: | |
856 | // | |
857 | // Returns the word read from the data fifo specified by the board-structure | |
858 | // pointer pB. Uses a 16-bit operation. Is called indirectly through | |
859 | // pB->i2eReadWord. | |
860 | // | |
861 | //****************************************************************************** | |
862 | static unsigned short | |
863 | iiReadWord16(i2eBordStrPtr pB) | |
864 | { | |
865 | return (unsigned short)( INW(pB->i2eData) ); | |
866 | } | |
867 | ||
868 | //****************************************************************************** | |
869 | // Function: iiReadWord8(pB) | |
870 | // Parameters: pB - pointer to board structure | |
871 | // | |
872 | // Returns: True if everything appears copacetic. | |
873 | // False if there is any error: the pB->i2eError field has the error | |
874 | // | |
875 | // Description: | |
876 | // | |
877 | // Returns the word read from the data fifo specified by the board-structure | |
878 | // pointer pB. Uses two 8-bit operations. Bytes are assumed to be LSB first. Is | |
879 | // called indirectly through pB->i2eReadWord. | |
880 | // | |
881 | //****************************************************************************** | |
882 | static unsigned short | |
883 | iiReadWord8(i2eBordStrPtr pB) | |
884 | { | |
885 | unsigned short urs; | |
886 | ||
887 | urs = INB ( pB->i2eData ); | |
888 | ||
889 | return ( ( INB ( pB->i2eData ) << 8 ) | urs ); | |
890 | } | |
891 | ||
892 | //****************************************************************************** | |
893 | // Function: iiWriteWord16(pB, value) | |
894 | // Parameters: pB - pointer to board structure | |
895 | // value - data to write | |
896 | // | |
897 | // Returns: True if everything appears copacetic. | |
898 | // False if there is any error: the pB->i2eError field has the error | |
899 | // | |
900 | // Description: | |
901 | // | |
902 | // Writes the word 'value' to the data fifo specified by the board-structure | |
903 | // pointer pB. Uses 16-bit operation. Is called indirectly through | |
904 | // pB->i2eWriteWord. | |
905 | // | |
906 | //****************************************************************************** | |
907 | static void | |
908 | iiWriteWord16(i2eBordStrPtr pB, unsigned short value) | |
909 | { | |
910 | WORD_TO(pB, (int)value); | |
911 | } | |
912 | ||
913 | //****************************************************************************** | |
914 | // Function: iiWriteWord8(pB, value) | |
915 | // Parameters: pB - pointer to board structure | |
916 | // value - data to write | |
917 | // | |
918 | // Returns: True if everything appears copacetic. | |
919 | // False if there is any error: the pB->i2eError field has the error | |
920 | // | |
921 | // Description: | |
922 | // | |
923 | // Writes the word 'value' to the data fifo specified by the board-structure | |
924 | // pointer pB. Uses two 8-bit operations (writes LSB first). Is called | |
925 | // indirectly through pB->i2eWriteWord. | |
926 | // | |
927 | //****************************************************************************** | |
928 | static void | |
929 | iiWriteWord8(i2eBordStrPtr pB, unsigned short value) | |
930 | { | |
931 | BYTE_TO(pB, (char)value); | |
932 | BYTE_TO(pB, (char)(value >> 8) ); | |
933 | } | |
934 | ||
935 | //****************************************************************************** | |
936 | // Function: iiWaitForTxEmptyII(pB, mSdelay) | |
937 | // Parameters: pB - pointer to board structure | |
938 | // mSdelay - period to wait before returning | |
939 | // | |
940 | // Returns: True if the FIFO is empty. | |
941 | // False if it not empty in the required time: the pB->i2eError | |
942 | // field has the error. | |
943 | // | |
944 | // Description: | |
945 | // | |
946 | // Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if | |
947 | // not empty by the required time, returns false and error in pB->i2eError, | |
948 | // otherwise returns true. | |
949 | // | |
950 | // mSdelay == 0 is taken to mean must be empty on the first test. | |
951 | // | |
952 | // This version operates on IntelliPort-II - style FIFO's | |
953 | // | |
954 | // Note this routine is organized so that if status is ok there is no delay at | |
955 | // all called either before or after the test. Is called indirectly through | |
956 | // pB->i2eWaitForTxEmpty. | |
957 | // | |
958 | //****************************************************************************** | |
959 | static int | |
960 | iiWaitForTxEmptyII(i2eBordStrPtr pB, int mSdelay) | |
961 | { | |
962 | unsigned long flags; | |
963 | int itemp; | |
964 | ||
965 | for (;;) | |
966 | { | |
967 | // This routine hinges on being able to see the "other" status register | |
968 | // (as seen by the local processor). His incoming fifo is our outgoing | |
969 | // FIFO. | |
970 | // | |
971 | // By the nature of this routine, you would be using this as part of a | |
972 | // larger atomic context: i.e., you would use this routine to ensure the | |
973 | // fifo empty, then act on this information. Between these two halves, | |
974 | // you will generally not want to service interrupts or in any way | |
975 | // disrupt the assumptions implicit in the larger context. | |
976 | // | |
977 | // Even worse, however, this routine "shifts" the status register to | |
978 | // point to the local status register which is not the usual situation. | |
979 | // Therefore for extra safety, we force the critical section to be | |
980 | // completely atomic, and pick up after ourselves before allowing any | |
981 | // interrupts of any kind. | |
982 | ||
983 | ||
984 | WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags) | |
985 | OUTB(pB->i2ePointer, SEL_COMMAND); | |
986 | OUTB(pB->i2ePointer, SEL_CMD_SH); | |
987 | ||
988 | itemp = INB(pB->i2eStatus); | |
989 | ||
990 | OUTB(pB->i2ePointer, SEL_COMMAND); | |
991 | OUTB(pB->i2ePointer, SEL_CMD_UNSH); | |
992 | ||
993 | if (itemp & ST_IN_EMPTY) | |
994 | { | |
995 | UPDATE_FIFO_ROOM(pB); | |
996 | WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) | |
997 | COMPLETE(pB, I2EE_GOOD); | |
998 | } | |
999 | ||
1000 | WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) | |
1001 | ||
1002 | if (mSdelay-- == 0) | |
1003 | break; | |
1004 | ||
1005 | iiDelay(pB, 1); /* 1 mS granularity on checking condition */ | |
1006 | } | |
1007 | COMPLETE(pB, I2EE_TXE_TIME); | |
1008 | } | |
1009 | ||
1010 | //****************************************************************************** | |
1011 | // Function: iiWaitForTxEmptyIIEX(pB, mSdelay) | |
1012 | // Parameters: pB - pointer to board structure | |
1013 | // mSdelay - period to wait before returning | |
1014 | // | |
1015 | // Returns: True if the FIFO is empty. | |
1016 | // False if it not empty in the required time: the pB->i2eError | |
1017 | // field has the error. | |
1018 | // | |
1019 | // Description: | |
1020 | // | |
1021 | // Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if | |
1022 | // not empty by the required time, returns false and error in pB->i2eError, | |
1023 | // otherwise returns true. | |
1024 | // | |
1025 | // mSdelay == 0 is taken to mean must be empty on the first test. | |
1026 | // | |
1027 | // This version operates on IntelliPort-IIEX - style FIFO's | |
1028 | // | |
1029 | // Note this routine is organized so that if status is ok there is no delay at | |
1030 | // all called either before or after the test. Is called indirectly through | |
1031 | // pB->i2eWaitForTxEmpty. | |
1032 | // | |
1033 | //****************************************************************************** | |
1034 | static int | |
1035 | iiWaitForTxEmptyIIEX(i2eBordStrPtr pB, int mSdelay) | |
1036 | { | |
1037 | unsigned long flags; | |
1038 | ||
1039 | for (;;) | |
1040 | { | |
1041 | // By the nature of this routine, you would be using this as part of a | |
1042 | // larger atomic context: i.e., you would use this routine to ensure the | |
1043 | // fifo empty, then act on this information. Between these two halves, | |
1044 | // you will generally not want to service interrupts or in any way | |
1045 | // disrupt the assumptions implicit in the larger context. | |
1046 | ||
1047 | WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags) | |
1048 | ||
1049 | if (INB(pB->i2eStatus) & STE_OUT_MT) { | |
1050 | UPDATE_FIFO_ROOM(pB); | |
1051 | WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) | |
1052 | COMPLETE(pB, I2EE_GOOD); | |
1053 | } | |
1054 | WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) | |
1055 | ||
1056 | if (mSdelay-- == 0) | |
1057 | break; | |
1058 | ||
1059 | iiDelay(pB, 1); // 1 mS granularity on checking condition | |
1060 | } | |
1061 | COMPLETE(pB, I2EE_TXE_TIME); | |
1062 | } | |
1063 | ||
1064 | //****************************************************************************** | |
1065 | // Function: iiTxMailEmptyII(pB) | |
1066 | // Parameters: pB - pointer to board structure | |
1067 | // | |
1068 | // Returns: True if the transmit mailbox is empty. | |
1069 | // False if it not empty. | |
1070 | // | |
1071 | // Description: | |
1072 | // | |
1073 | // Returns true or false according to whether the transmit mailbox is empty (and | |
1074 | // therefore able to accept more mail) | |
1075 | // | |
1076 | // This version operates on IntelliPort-II - style FIFO's | |
1077 | // | |
1078 | //****************************************************************************** | |
1079 | static int | |
1080 | iiTxMailEmptyII(i2eBordStrPtr pB) | |
1081 | { | |
1082 | int port = pB->i2ePointer; | |
1083 | OUTB ( port, SEL_OUTMAIL ); | |
1084 | return ( INB(port) == 0 ); | |
1085 | } | |
1086 | ||
1087 | //****************************************************************************** | |
1088 | // Function: iiTxMailEmptyIIEX(pB) | |
1089 | // Parameters: pB - pointer to board structure | |
1090 | // | |
1091 | // Returns: True if the transmit mailbox is empty. | |
1092 | // False if it not empty. | |
1093 | // | |
1094 | // Description: | |
1095 | // | |
1096 | // Returns true or false according to whether the transmit mailbox is empty (and | |
1097 | // therefore able to accept more mail) | |
1098 | // | |
1099 | // This version operates on IntelliPort-IIEX - style FIFO's | |
1100 | // | |
1101 | //****************************************************************************** | |
1102 | static int | |
1103 | iiTxMailEmptyIIEX(i2eBordStrPtr pB) | |
1104 | { | |
1105 | return !(INB(pB->i2eStatus) & STE_OUT_MAIL); | |
1106 | } | |
1107 | ||
1108 | //****************************************************************************** | |
1109 | // Function: iiTrySendMailII(pB,mail) | |
1110 | // Parameters: pB - pointer to board structure | |
1111 | // mail - value to write to mailbox | |
1112 | // | |
1113 | // Returns: True if the transmit mailbox is empty, and mail is sent. | |
1114 | // False if it not empty. | |
1115 | // | |
1116 | // Description: | |
1117 | // | |
1118 | // If outgoing mailbox is empty, sends mail and returns true. If outgoing | |
1119 | // mailbox is not empty, returns false. | |
1120 | // | |
1121 | // This version operates on IntelliPort-II - style FIFO's | |
1122 | // | |
1123 | //****************************************************************************** | |
1124 | static int | |
1125 | iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail) | |
1126 | { | |
1127 | int port = pB->i2ePointer; | |
1128 | ||
1129 | OUTB(port, SEL_OUTMAIL); | |
1130 | if (INB(port) == 0) { | |
1131 | OUTB(port, SEL_OUTMAIL); | |
1132 | OUTB(port, mail); | |
1133 | return 1; | |
1134 | } | |
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | //****************************************************************************** | |
1139 | // Function: iiTrySendMailIIEX(pB,mail) | |
1140 | // Parameters: pB - pointer to board structure | |
1141 | // mail - value to write to mailbox | |
1142 | // | |
1143 | // Returns: True if the transmit mailbox is empty, and mail is sent. | |
1144 | // False if it not empty. | |
1145 | // | |
1146 | // Description: | |
1147 | // | |
1148 | // If outgoing mailbox is empty, sends mail and returns true. If outgoing | |
1149 | // mailbox is not empty, returns false. | |
1150 | // | |
1151 | // This version operates on IntelliPort-IIEX - style FIFO's | |
1152 | // | |
1153 | //****************************************************************************** | |
1154 | static int | |
1155 | iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail) | |
1156 | { | |
1157 | if(INB(pB->i2eStatus) & STE_OUT_MAIL) { | |
1158 | return 0; | |
1159 | } | |
1160 | OUTB(pB->i2eXMail, mail); | |
1161 | return 1; | |
1162 | } | |
1163 | ||
1164 | //****************************************************************************** | |
1165 | // Function: iiGetMailII(pB,mail) | |
1166 | // Parameters: pB - pointer to board structure | |
1167 | // | |
1168 | // Returns: Mailbox data or NO_MAIL_HERE. | |
1169 | // | |
1170 | // Description: | |
1171 | // | |
1172 | // If no mail available, returns NO_MAIL_HERE otherwise returns the data from | |
1173 | // the mailbox, which is guaranteed != NO_MAIL_HERE. | |
1174 | // | |
1175 | // This version operates on IntelliPort-II - style FIFO's | |
1176 | // | |
1177 | //****************************************************************************** | |
1178 | static unsigned short | |
1179 | iiGetMailII(i2eBordStrPtr pB) | |
1180 | { | |
1181 | if (HAS_MAIL(pB)) { | |
1182 | OUTB(pB->i2ePointer, SEL_INMAIL); | |
1183 | return INB(pB->i2ePointer); | |
1184 | } else { | |
1185 | return NO_MAIL_HERE; | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | //****************************************************************************** | |
1190 | // Function: iiGetMailIIEX(pB,mail) | |
1191 | // Parameters: pB - pointer to board structure | |
1192 | // | |
1193 | // Returns: Mailbox data or NO_MAIL_HERE. | |
1194 | // | |
1195 | // Description: | |
1196 | // | |
1197 | // If no mail available, returns NO_MAIL_HERE otherwise returns the data from | |
1198 | // the mailbox, which is guaranteed != NO_MAIL_HERE. | |
1199 | // | |
1200 | // This version operates on IntelliPort-IIEX - style FIFO's | |
1201 | // | |
1202 | //****************************************************************************** | |
1203 | static unsigned short | |
1204 | iiGetMailIIEX(i2eBordStrPtr pB) | |
1205 | { | |
1206 | if (HAS_MAIL(pB)) { | |
1207 | return INB(pB->i2eXMail); | |
1208 | } else { | |
1209 | return NO_MAIL_HERE; | |
1210 | } | |
1211 | } | |
1212 | ||
1213 | //****************************************************************************** | |
1214 | // Function: iiEnableMailIrqII(pB) | |
1215 | // Parameters: pB - pointer to board structure | |
1216 | // | |
1217 | // Returns: Nothing | |
1218 | // | |
1219 | // Description: | |
1220 | // | |
1221 | // Enables board to interrupt host (only) by writing to host's in-bound mailbox. | |
1222 | // | |
1223 | // This version operates on IntelliPort-II - style FIFO's | |
1224 | // | |
1225 | //****************************************************************************** | |
1226 | static void | |
1227 | iiEnableMailIrqII(i2eBordStrPtr pB) | |
1228 | { | |
1229 | OUTB(pB->i2ePointer, SEL_MASK); | |
1230 | OUTB(pB->i2ePointer, ST_IN_MAIL); | |
1231 | } | |
1232 | ||
1233 | //****************************************************************************** | |
1234 | // Function: iiEnableMailIrqIIEX(pB) | |
1235 | // Parameters: pB - pointer to board structure | |
1236 | // | |
1237 | // Returns: Nothing | |
1238 | // | |
1239 | // Description: | |
1240 | // | |
1241 | // Enables board to interrupt host (only) by writing to host's in-bound mailbox. | |
1242 | // | |
1243 | // This version operates on IntelliPort-IIEX - style FIFO's | |
1244 | // | |
1245 | //****************************************************************************** | |
1246 | static void | |
1247 | iiEnableMailIrqIIEX(i2eBordStrPtr pB) | |
1248 | { | |
1249 | OUTB(pB->i2eXMask, MX_IN_MAIL); | |
1250 | } | |
1251 | ||
1252 | //****************************************************************************** | |
1253 | // Function: iiWriteMaskII(pB) | |
1254 | // Parameters: pB - pointer to board structure | |
1255 | // | |
1256 | // Returns: Nothing | |
1257 | // | |
1258 | // Description: | |
1259 | // | |
1260 | // Writes arbitrary value to the mask register. | |
1261 | // | |
1262 | // This version operates on IntelliPort-II - style FIFO's | |
1263 | // | |
1264 | //****************************************************************************** | |
1265 | static void | |
1266 | iiWriteMaskII(i2eBordStrPtr pB, unsigned char value) | |
1267 | { | |
1268 | OUTB(pB->i2ePointer, SEL_MASK); | |
1269 | OUTB(pB->i2ePointer, value); | |
1270 | } | |
1271 | ||
1272 | //****************************************************************************** | |
1273 | // Function: iiWriteMaskIIEX(pB) | |
1274 | // Parameters: pB - pointer to board structure | |
1275 | // | |
1276 | // Returns: Nothing | |
1277 | // | |
1278 | // Description: | |
1279 | // | |
1280 | // Writes arbitrary value to the mask register. | |
1281 | // | |
1282 | // This version operates on IntelliPort-IIEX - style FIFO's | |
1283 | // | |
1284 | //****************************************************************************** | |
1285 | static void | |
1286 | iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value) | |
1287 | { | |
1288 | OUTB(pB->i2eXMask, value); | |
1289 | } | |
1290 | ||
1291 | //****************************************************************************** | |
1292 | // Function: iiDownloadBlock(pB, pSource, isStandard) | |
1293 | // Parameters: pB - pointer to board structure | |
1294 | // pSource - loadware block to download | |
1295 | // isStandard - True if "standard" loadware, else false. | |
1296 | // | |
1297 | // Returns: Success or Failure | |
1298 | // | |
1299 | // Description: | |
1300 | // | |
1301 | // Downloads a single block (at pSource)to the board referenced by pB. Caller | |
1302 | // sets isStandard to true/false according to whether the "standard" loadware is | |
1303 | // what's being loaded. The normal process, then, is to perform an iiInitialize | |
1304 | // to the board, then perform some number of iiDownloadBlocks using the returned | |
1305 | // state to determine when download is complete. | |
1306 | // | |
1307 | // Possible return values: (see I2ELLIS.H) | |
1308 | // II_DOWN_BADVALID | |
1309 | // II_DOWN_BADFILE | |
1310 | // II_DOWN_CONTINUING | |
1311 | // II_DOWN_GOOD | |
1312 | // II_DOWN_BAD | |
1313 | // II_DOWN_BADSTATE | |
1314 | // II_DOWN_TIMEOUT | |
1315 | // | |
1316 | // Uses the i2eState and i2eToLoad fields (initialized at iiInitialize) to | |
1317 | // determine whether this is the first block, whether to check for magic | |
1318 | // numbers, how many blocks there are to go... | |
1319 | // | |
1320 | //****************************************************************************** | |
1321 | static int | |
1322 | iiDownloadBlock ( i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard) | |
1323 | { | |
1324 | int itemp; | |
1325 | int loadedFirst; | |
1326 | ||
1327 | if (pB->i2eValid != I2E_MAGIC) return II_DOWN_BADVALID; | |
1328 | ||
1329 | switch(pB->i2eState) | |
1330 | { | |
1331 | case II_STATE_READY: | |
1332 | ||
1333 | // Loading the first block after reset. Must check the magic number of the | |
1334 | // loadfile, store the number of blocks we expect to load. | |
1335 | if (pSource->e.loadMagic != MAGIC_LOADFILE) | |
1336 | { | |
1337 | return II_DOWN_BADFILE; | |
1338 | } | |
1339 | ||
1340 | // Next we store the total number of blocks to load, including this one. | |
1341 | pB->i2eToLoad = 1 + pSource->e.loadBlocksMore; | |
1342 | ||
1343 | // Set the state, store the version numbers. ('Cause this may have come | |
1344 | // from a file - we might want to report these versions and revisions in | |
1345 | // case of an error! | |
1346 | pB->i2eState = II_STATE_LOADING; | |
1347 | pB->i2eLVersion = pSource->e.loadVersion; | |
1348 | pB->i2eLRevision = pSource->e.loadRevision; | |
1349 | pB->i2eLSub = pSource->e.loadSubRevision; | |
1350 | ||
1351 | // The time and date of compilation is also available but don't bother | |
1352 | // storing it for normal purposes. | |
1353 | loadedFirst = 1; | |
1354 | break; | |
1355 | ||
1356 | case II_STATE_LOADING: | |
1357 | loadedFirst = 0; | |
1358 | break; | |
1359 | ||
1360 | default: | |
1361 | return II_DOWN_BADSTATE; | |
1362 | } | |
1363 | ||
1364 | // Now we must be in the II_STATE_LOADING state, and we assume i2eToLoad | |
1365 | // must be positive still, because otherwise we would have cleaned up last | |
1366 | // time and set the state to II_STATE_LOADED. | |
1367 | if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) { | |
1368 | return II_DOWN_TIMEOUT; | |
1369 | } | |
1370 | ||
1371 | if (!iiWriteBuf(pB, pSource->c, LOADWARE_BLOCK_SIZE)) { | |
1372 | return II_DOWN_BADVALID; | |
1373 | } | |
1374 | ||
1375 | // If we just loaded the first block, wait for the fifo to empty an extra | |
1376 | // long time to allow for any special startup code in the firmware, like | |
1377 | // sending status messages to the LCD's. | |
1378 | ||
1379 | if (loadedFirst) { | |
1380 | if (!iiWaitForTxEmpty(pB, MAX_DLOAD_START_TIME)) { | |
1381 | return II_DOWN_TIMEOUT; | |
1382 | } | |
1383 | } | |
1384 | ||
1385 | // Determine whether this was our last block! | |
1386 | if (--(pB->i2eToLoad)) { | |
1387 | return II_DOWN_CONTINUING; // more to come... | |
1388 | } | |
1389 | ||
1390 | // It WAS our last block: Clean up operations... | |
1391 | // ...Wait for last buffer to drain from the board... | |
1392 | if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) { | |
1393 | return II_DOWN_TIMEOUT; | |
1394 | } | |
1395 | // If there were only a single block written, this would come back | |
1396 | // immediately and be harmless, though not strictly necessary. | |
1397 | itemp = MAX_DLOAD_ACK_TIME/10; | |
1398 | while (--itemp) { | |
1399 | if (HAS_INPUT(pB)) { | |
1400 | switch(BYTE_FROM(pB)) | |
1401 | { | |
1402 | case LOADWARE_OK: | |
1403 | pB->i2eState = | |
1404 | isStandard ? II_STATE_STDLOADED :II_STATE_LOADED; | |
1405 | ||
1406 | // Some revisions of the bootstrap firmware (e.g. ISA-8 1.0.2) | |
1407 | // will, // if there is a debug port attached, require some | |
1408 | // time to send information to the debug port now. It will do | |
1409 | // this before // executing any of the code we just downloaded. | |
1410 | // It may take up to 700 milliseconds. | |
1411 | if (pB->i2ePom.e.porDiag2 & POR_DEBUG_PORT) { | |
1412 | iiDelay(pB, 700); | |
1413 | } | |
1414 | ||
1415 | return II_DOWN_GOOD; | |
1416 | ||
1417 | case LOADWARE_BAD: | |
1418 | default: | |
1419 | return II_DOWN_BAD; | |
1420 | } | |
1421 | } | |
1422 | ||
1423 | iiDelay(pB, 10); // 10 mS granularity on checking condition | |
1424 | } | |
1425 | ||
1426 | // Drop-through --> timed out waiting for firmware confirmation | |
1427 | ||
1428 | pB->i2eState = II_STATE_BADLOAD; | |
1429 | return II_DOWN_TIMEOUT; | |
1430 | } | |
1431 | ||
1432 | //****************************************************************************** | |
1433 | // Function: iiDownloadAll(pB, pSource, isStandard, size) | |
1434 | // Parameters: pB - pointer to board structure | |
1435 | // pSource - loadware block to download | |
1436 | // isStandard - True if "standard" loadware, else false. | |
1437 | // size - size of data to download (in bytes) | |
1438 | // | |
1439 | // Returns: Success or Failure | |
1440 | // | |
1441 | // Description: | |
1442 | // | |
1443 | // Given a pointer to a board structure, a pointer to the beginning of some | |
1444 | // loadware, whether it is considered the "standard loadware", and the size of | |
1445 | // the array in bytes loads the entire array to the board as loadware. | |
1446 | // | |
1447 | // Assumes the board has been freshly reset and the power-up reset message read. | |
1448 | // (i.e., in II_STATE_READY). Complains if state is bad, or if there seems to be | |
1449 | // too much or too little data to load, or if iiDownloadBlock complains. | |
1450 | //****************************************************************************** | |
1451 | static int | |
1452 | iiDownloadAll(i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard, int size) | |
1453 | { | |
1454 | int status; | |
1455 | ||
1456 | // We know (from context) board should be ready for the first block of | |
1457 | // download. Complain if not. | |
1458 | if (pB->i2eState != II_STATE_READY) return II_DOWN_BADSTATE; | |
1459 | ||
1460 | while (size > 0) { | |
1461 | size -= LOADWARE_BLOCK_SIZE; // How much data should there be left to | |
1462 | // load after the following operation ? | |
1463 | ||
1464 | // Note we just bump pSource by "one", because its size is actually that | |
1465 | // of an entire block, same as LOADWARE_BLOCK_SIZE. | |
1466 | status = iiDownloadBlock(pB, pSource++, isStandard); | |
1467 | ||
1468 | switch(status) | |
1469 | { | |
1470 | case II_DOWN_GOOD: | |
1471 | return ( (size > 0) ? II_DOWN_OVER : II_DOWN_GOOD); | |
1472 | ||
1473 | case II_DOWN_CONTINUING: | |
1474 | break; | |
1475 | ||
1476 | default: | |
1477 | return status; | |
1478 | } | |
1479 | } | |
1480 | ||
1481 | // We shouldn't drop out: it means "while" caught us with nothing left to | |
1482 | // download, yet the previous DownloadBlock did not return complete. Ergo, | |
1483 | // not enough data to match the size byte in the header. | |
1484 | return II_DOWN_UNDER; | |
1485 | } |