[linux-2.6-block.git] / drivers / char / hw_random.c

/*
        Added support for the AMD Geode LX RNG
	(c) Copyright 2004-2005 Advanced Micro Devices, Inc.

	derived from

 	Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
	(c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
 
 	derived from
 
        Hardware driver for the AMD 768 Random Number Generator (RNG)
        (c) Copyright 2001 Red Hat Inc <alan@redhat.com>

 	derived from
 
	Hardware driver for Intel i810 Random Number Generator (RNG)
	Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
	Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>

	Please read Documentation/hw_random.txt for details on use.

	----------------------------------------------------------
	This software may be used and distributed according to the terms
        of the GNU General Public License, incorporated herein by reference.

 */


#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/random.h>
#include <linux/miscdevice.h>
#include <linux/smp_lock.h>
#include <linux/mm.h>
#include <linux/delay.h>

#ifdef __i386__
#include <asm/msr.h>
#include <asm/cpufeature.h>
#endif

#include <asm/io.h>
#include <asm/uaccess.h>


/*
 * core module and version information
 */
#define RNG_VERSION "1.0.0"
#define RNG_MODULE_NAME "hw_random"
#define RNG_DRIVER_NAME   RNG_MODULE_NAME " hardware driver " RNG_VERSION
#define PFX RNG_MODULE_NAME ": "


/*
 * debugging macros
 */

/* pr_debug() collapses to a no-op if DEBUG is not defined */
#define DPRINTK(fmt, args...) pr_debug(PFX "%s: " fmt, __FUNCTION__ , ## args)


#undef RNG_NDEBUG        /* define to enable lightweight runtime checks */
#ifdef RNG_NDEBUG
#define assert(expr)							\
		if(!(expr)) {						\
		printk(KERN_DEBUG PFX "Assertion failed! %s,%s,%s,"	\
		"line=%d\n", #expr, __FILE__, __FUNCTION__, __LINE__);	\
		}
#else
#define assert(expr)
#endif

#define RNG_MISCDEV_MINOR		183 /* official */

static int rng_dev_open (struct inode *inode, struct file *filp);
static ssize_t rng_dev_read (struct file *filp, char __user *buf, size_t size,
				loff_t * offp);

static int __init intel_init (struct pci_dev *dev);
static void intel_cleanup(void);
static unsigned int intel_data_present (void);
static u32 intel_data_read (void);

static int __init amd_init (struct pci_dev *dev);
static void amd_cleanup(void);
static unsigned int amd_data_present (void);
static u32 amd_data_read (void);

#ifdef __i386__
static int __init via_init(struct pci_dev *dev);
static void via_cleanup(void);
static unsigned int via_data_present (void);
static u32 via_data_read (void);
#endif

static int __init geode_init(struct pci_dev *dev);
static void geode_cleanup(void);
static unsigned int geode_data_present (void);
static u32 geode_data_read (void);

struct rng_operations {
	int (*init) (struct pci_dev *dev);
	void (*cleanup) (void);
	unsigned int (*data_present) (void);
	u32 (*data_read) (void);
	unsigned int n_bytes; /* number of bytes per ->data_read */
};
static struct rng_operations *rng_ops;

static struct file_operations rng_chrdev_ops = {
	.owner		= THIS_MODULE,
	.open		= rng_dev_open,
	.read		= rng_dev_read,
};


static struct miscdevice rng_miscdev = {
	RNG_MISCDEV_MINOR,
	RNG_MODULE_NAME,
	&rng_chrdev_ops,
};

enum {
	rng_hw_none,
	rng_hw_intel,
	rng_hw_amd,
	rng_hw_via,
	rng_hw_geode,
};

static struct rng_operations rng_vendor_ops[] = {
	/* rng_hw_none */
	{ },

	/* rng_hw_intel */
	{ intel_init, intel_cleanup, intel_data_present,
	  intel_data_read, 1 },

	/* rng_hw_amd */
	{ amd_init, amd_cleanup, amd_data_present, amd_data_read, 4 },

#ifdef __i386__
	/* rng_hw_via */
	{ via_init, via_cleanup, via_data_present, via_data_read, 1 },
#endif

	/* rng_hw_geode */
	{ geode_init, geode_cleanup, geode_data_present, geode_data_read, 4 }
};

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because someone else might one day
 * want to register another driver on the same PCI id.
 */
static struct pci_device_id rng_pci_tbl[] = {
	{ 0x1022, 0x7443, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_amd },
	{ 0x1022, 0x746b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_amd },

	{ 0x8086, 0x2418, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	{ 0x8086, 0x2428, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	{ 0x8086, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	{ 0x8086, 0x2448, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	{ 0x8086, 0x244e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	{ 0x8086, 0x245e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },

	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LX_AES,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_geode },

	{ 0, },	/* terminate list */
};
MODULE_DEVICE_TABLE (pci, rng_pci_tbl);


/***********************************************************************
 *
 * Intel RNG operations
 *
 */

/*
 * RNG registers (offsets from rng_mem)
 */
#define INTEL_RNG_HW_STATUS			0
#define         INTEL_RNG_PRESENT		0x40
#define         INTEL_RNG_ENABLED		0x01
#define INTEL_RNG_STATUS			1
#define         INTEL_RNG_DATA_PRESENT		0x01
#define INTEL_RNG_DATA				2

/*
 * Magic address at which Intel PCI bridges locate the RNG
 */
#define INTEL_RNG_ADDR				0xFFBC015F
#define INTEL_RNG_ADDR_LEN			3

/* token to our ioremap'd RNG register area */
static void __iomem *rng_mem;

static inline u8 intel_hwstatus (void)
{
	assert (rng_mem != NULL);
	return readb (rng_mem + INTEL_RNG_HW_STATUS);
}

static inline u8 intel_hwstatus_set (u8 hw_status)
{
	assert (rng_mem != NULL);
	writeb (hw_status, rng_mem + INTEL_RNG_HW_STATUS);
	return intel_hwstatus ();
}

static unsigned int intel_data_present(void)
{
	assert (rng_mem != NULL);

	return (readb (rng_mem + INTEL_RNG_STATUS) & INTEL_RNG_DATA_PRESENT) ?
		1 : 0;
}

static u32 intel_data_read(void)
{
	assert (rng_mem != NULL);

	return readb (rng_mem + INTEL_RNG_DATA);
}

static int __init intel_init (struct pci_dev *dev)
{
	int rc;
	u8 hw_status;

	DPRINTK ("ENTER\n");

	rng_mem = ioremap (INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
	if (rng_mem == NULL) {
		printk (KERN_ERR PFX "cannot ioremap RNG Memory\n");
		rc = -EBUSY;
		goto err_out;
	}

	/* Check for Intel 82802 */
	hw_status = intel_hwstatus ();
	if ((hw_status & INTEL_RNG_PRESENT) == 0) {
		printk (KERN_ERR PFX "RNG not detected\n");
		rc = -ENODEV;
		goto err_out_free_map;
	}

	/* turn RNG h/w on, if it's off */
	if ((hw_status & INTEL_RNG_ENABLED) == 0)
		hw_status = intel_hwstatus_set (hw_status | INTEL_RNG_ENABLED);
	if ((hw_status & INTEL_RNG_ENABLED) == 0) {
		printk (KERN_ERR PFX "cannot enable RNG, aborting\n");
		rc = -EIO;
		goto err_out_free_map;
	}

	DPRINTK ("EXIT, returning 0\n");
	return 0;

err_out_free_map:
	iounmap (rng_mem);
	rng_mem = NULL;
err_out:
	DPRINTK ("EXIT, returning %d\n", rc);
	return rc;
}

static void intel_cleanup(void)
{
	u8 hw_status;

	hw_status = intel_hwstatus ();
	if (hw_status & INTEL_RNG_ENABLED)
		intel_hwstatus_set (hw_status & ~INTEL_RNG_ENABLED);
	else
		printk(KERN_WARNING PFX "unusual: RNG already disabled\n");
	iounmap(rng_mem);
	rng_mem = NULL;
}

/***********************************************************************
 *
 * AMD RNG operations
 *
 */

static u32 pmbase;			/* PMxx I/O base */
static struct pci_dev *amd_dev;

static unsigned int amd_data_present (void)
{
      	return inl(pmbase + 0xF4) & 1;
}


static u32 amd_data_read (void)
{
	return inl(pmbase + 0xF0);
}

static int __init amd_init (struct pci_dev *dev)
{
	int rc;
	u8 rnen;

	DPRINTK ("ENTER\n");

	pci_read_config_dword(dev, 0x58, &pmbase);

	pmbase &= 0x0000FF00;

	if (pmbase == 0)
	{
		printk (KERN_ERR PFX "power management base not set\n");
		rc = -EIO;
		goto err_out;
	}

	pci_read_config_byte(dev, 0x40, &rnen);
	rnen |= (1 << 7);	/* RNG on */
	pci_write_config_byte(dev, 0x40, rnen);

	pci_read_config_byte(dev, 0x41, &rnen);
	rnen |= (1 << 7);	/* PMIO enable */
	pci_write_config_byte(dev, 0x41, rnen);

	pr_info( PFX "AMD768 system management I/O registers at 0x%X.\n",
			pmbase);

	amd_dev = dev;

	DPRINTK ("EXIT, returning 0\n");
	return 0;

err_out:
	DPRINTK ("EXIT, returning %d\n", rc);
	return rc;
}

static void amd_cleanup(void)
{
	u8 rnen;

	pci_read_config_byte(amd_dev, 0x40, &rnen);
	rnen &= ~(1 << 7);	/* RNG off */
	pci_write_config_byte(amd_dev, 0x40, rnen);

	/* FIXME: twiddle pmio, also? */
}

#ifdef __i386__
/***********************************************************************
 *
 * VIA RNG operations
 *
 */

enum {
	VIA_STRFILT_CNT_SHIFT	= 16,
	VIA_STRFILT_FAIL	= (1 << 15),
	VIA_STRFILT_ENABLE	= (1 << 14),
	VIA_RAWBITS_ENABLE	= (1 << 13),
	VIA_RNG_ENABLE		= (1 << 6),
	VIA_XSTORE_CNT_MASK	= 0x0F,

	VIA_RNG_CHUNK_8		= 0x00,	/* 64 rand bits, 64 stored bits */
	VIA_RNG_CHUNK_4		= 0x01,	/* 32 rand bits, 32 stored bits */
	VIA_RNG_CHUNK_4_MASK	= 0xFFFFFFFF,
	VIA_RNG_CHUNK_2		= 0x02,	/* 16 rand bits, 32 stored bits */
	VIA_RNG_CHUNK_2_MASK	= 0xFFFF,
	VIA_RNG_CHUNK_1		= 0x03,	/* 8 rand bits, 32 stored bits */
	VIA_RNG_CHUNK_1_MASK	= 0xFF,
};

static u32 via_rng_datum;

/*
 * Investigate using the 'rep' prefix to obtain 32 bits of random data
 * in one insn.  The upside is potentially better performance.  The
 * downside is that the instruction becomes no longer atomic.  Due to
 * this, just like familiar issues with /dev/random itself, the worst
 * case of a 'rep xstore' could potentially pause a cpu for an
 * unreasonably long time.  In practice, this condition would likely
 * only occur when the hardware is failing.  (or so we hope :))
 *
 * Another possible performance boost may come from simply buffering
 * until we have 4 bytes, thus returning a u32 at a time,
 * instead of the current u8-at-a-time.
 */

static inline u32 xstore(u32 *addr, u32 edx_in)
{
	u32 eax_out;

	asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
		:"=m"(*addr), "=a"(eax_out)
		:"D"(addr), "d"(edx_in));

	return eax_out;
}

static unsigned int via_data_present(void)
{
	u32 bytes_out;

	/* We choose the recommended 1-byte-per-instruction RNG rate,
	 * for greater randomness at the expense of speed.  Larger
	 * values 2, 4, or 8 bytes-per-instruction yield greater
	 * speed at lesser randomness.
	 *
	 * If you change this to another VIA_CHUNK_n, you must also
	 * change the ->n_bytes values in rng_vendor_ops[] tables.
	 * VIA_CHUNK_8 requires further code changes.
	 *
	 * A copy of MSR_VIA_RNG is placed in eax_out when xstore
	 * completes.
	 */
	via_rng_datum = 0; /* paranoia, not really necessary */
	bytes_out = xstore(&via_rng_datum, VIA_RNG_CHUNK_1) & VIA_XSTORE_CNT_MASK;
	if (bytes_out == 0)
		return 0;

	return 1;
}

static u32 via_data_read(void)
{
	return via_rng_datum;
}

static int __init via_init(struct pci_dev *dev)
{
	u32 lo, hi, old_lo;

	/* Control the RNG via MSR.  Tread lightly and pay very close
	 * close attention to values written, as the reserved fields
	 * are documented to be "undefined and unpredictable"; but it
	 * does not say to write them as zero, so I make a guess that
	 * we restore the values we find in the register.
	 */
	rdmsr(MSR_VIA_RNG, lo, hi);

	old_lo = lo;
	lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
	lo &= ~VIA_XSTORE_CNT_MASK;
	lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
	lo |= VIA_RNG_ENABLE;

	if (lo != old_lo)
		wrmsr(MSR_VIA_RNG, lo, hi);

	/* perhaps-unnecessary sanity check; remove after testing if
	   unneeded */
	rdmsr(MSR_VIA_RNG, lo, hi);
	if ((lo & VIA_RNG_ENABLE) == 0) {
		printk(KERN_ERR PFX "cannot enable VIA C3 RNG, aborting\n");
		return -ENODEV;
	}

	return 0;
}

static void via_cleanup(void)
{
	/* do nothing */
}
#endif

/***********************************************************************
 *
 * AMD Geode RNG operations
 *
 */

static void __iomem *geode_rng_base = NULL;

#define GEODE_RNG_DATA_REG   0x50
#define GEODE_RNG_STATUS_REG 0x54

static u32 geode_data_read(void)
{
	u32 val;

	assert(geode_rng_base != NULL);
	val = readl(geode_rng_base + GEODE_RNG_DATA_REG);
	return val;
}

static unsigned int geode_data_present(void)
{
	u32 val;

	assert(geode_rng_base != NULL);
	val = readl(geode_rng_base + GEODE_RNG_STATUS_REG);
	return val;
}

static void geode_cleanup(void)
{
	iounmap(geode_rng_base);
  	geode_rng_base = NULL;
}

static int geode_init(struct pci_dev *dev)
{
	unsigned long rng_base = pci_resource_start(dev, 0);

	if (rng_base == 0)
		return 1;

	geode_rng_base = ioremap(rng_base, 0x58);

	if (geode_rng_base == NULL) {
		printk(KERN_ERR PFX "Cannot ioremap RNG memory\n");
		return -EBUSY;
	}

	return 0;
}

/***********************************************************************
 *
 * /dev/hwrandom character device handling (major 10, minor 183)
 *
 */

static int rng_dev_open (struct inode *inode, struct file *filp)
{
	/* enforce read-only access to this chrdev */
	if ((filp->f_mode & FMODE_READ) == 0)
		return -EINVAL;
	if (filp->f_mode & FMODE_WRITE)
		return -EINVAL;

	return 0;
}


static ssize_t rng_dev_read (struct file *filp, char __user *buf, size_t size,
				loff_t * offp)
{
	static DEFINE_SPINLOCK(rng_lock);
	unsigned int have_data;
	u32 data = 0;
	ssize_t ret = 0;

	while (size) {
		spin_lock(&rng_lock);

		have_data = 0;
		if (rng_ops->data_present()) {
			data = rng_ops->data_read();
			have_data = rng_ops->n_bytes;
		}

		spin_unlock (&rng_lock);

		while (have_data && size) {
			if (put_user((u8)data, buf++)) {
				ret = ret ? : -EFAULT;
				break;
			}
			size--;
			ret++;
			have_data--;
			data>>=8;
		}

		if (filp->f_flags & O_NONBLOCK)
			return ret ? : -EAGAIN;

		if(need_resched())
			schedule_timeout_interruptible(1);
		else
			udelay(200);	/* FIXME: We could poll for 250uS ?? */

		if (signal_pending (current))
			return ret ? : -ERESTARTSYS;
	}
	return ret;
}


/*
 * rng_init_one - look for and attempt to init a single RNG
 */
static int __init rng_init_one (struct pci_dev *dev)
{
	int rc;

	DPRINTK ("ENTER\n");

	assert(rng_ops != NULL);

	rc = rng_ops->init(dev);
	if (rc)
		goto err_out;

	rc = misc_register (&rng_miscdev);
	if (rc) {
		printk (KERN_ERR PFX "misc device register failed\n");
		goto err_out_cleanup_hw;
	}

	DPRINTK ("EXIT, returning 0\n");
	return 0;

err_out_cleanup_hw:
	rng_ops->cleanup();
err_out:
	DPRINTK ("EXIT, returning %d\n", rc);
	return rc;
}


MODULE_AUTHOR("The Linux Kernel team");
MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver");
MODULE_LICENSE("GPL");


/*
 * rng_init - initialize RNG module
 */
static int __init rng_init (void)
{
	int rc;
	struct pci_dev *pdev = NULL;
	const struct pci_device_id *ent;

	DPRINTK ("ENTER\n");

	/* Probe for Intel, AMD, Geode RNGs */
	for_each_pci_dev(pdev) {
		ent = pci_match_id(rng_pci_tbl, pdev);
		if (ent) {
			rng_ops = &rng_vendor_ops[ent->driver_data];
			goto match;
		}
	}

#ifdef __i386__
	/* Probe for VIA RNG */
	if (cpu_has_xstore) {
		rng_ops = &rng_vendor_ops[rng_hw_via];
		pdev = NULL;
		goto match;
	}
#endif

	DPRINTK ("EXIT, returning -ENODEV\n");
	return -ENODEV;

match:
	rc = rng_init_one (pdev);
	if (rc)
		return rc;

	pr_info( RNG_DRIVER_NAME " loaded\n");

	DPRINTK ("EXIT, returning 0\n");
	return 0;
}


/*
 * rng_init - shutdown RNG module
 */
static void __exit rng_cleanup (void)
{
	DPRINTK ("ENTER\n");

	misc_deregister (&rng_miscdev);

	if (rng_ops->cleanup)
		rng_ops->cleanup();

	DPRINTK ("EXIT\n");
}


module_init (rng_init);
module_exit (rng_cleanup);
Commit	Line	Data
1da177e4	1	/*
a7a4ad09 JC	2	Added support for the AMD Geode LX RNG
	3	(c) Copyright 2004-2005 Advanced Micro Devices, Inc.
	4
	5	derived from
	6
1da177e4 LT	7	Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
	8	(c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
	9
	10	derived from
	11
	12	Hardware driver for the AMD 768 Random Number Generator (RNG)
	13	(c) Copyright 2001 Red Hat Inc <alan@redhat.com>
	14
	15	derived from
	16
	17	Hardware driver for Intel i810 Random Number Generator (RNG)
	18	Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
	19	Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
	20
	21	Please read Documentation/hw_random.txt for details on use.
	22
	23	----------------------------------------------------------
	24	This software may be used and distributed according to the terms
	25	of the GNU General Public License, incorporated herein by reference.
	26
	27	*/
	28
	29
	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
	32	#include <linux/fs.h>
	33	#include <linux/init.h>
	34	#include <linux/pci.h>
	35	#include <linux/interrupt.h>
	36	#include <linux/spinlock.h>
	37	#include <linux/random.h>
	38	#include <linux/miscdevice.h>
	39	#include <linux/smp_lock.h>
	40	#include <linux/mm.h>
	41	#include <linux/delay.h>
	42
	43	#ifdef __i386__
	44	#include <asm/msr.h>
	45	#include <asm/cpufeature.h>
	46	#endif
	47
	48	#include <asm/io.h>
	49	#include <asm/uaccess.h>
	50
	51
	52	/*
	53	* core module and version information
	54	*/
	55	#define RNG_VERSION "1.0.0"
	56	#define RNG_MODULE_NAME "hw_random"
	57	#define RNG_DRIVER_NAME RNG_MODULE_NAME " hardware driver " RNG_VERSION
	58	#define PFX RNG_MODULE_NAME ": "
	59
	60
	61	/*
	62	* debugging macros
	63	*/
	64
	65	/* pr_debug() collapses to a no-op if DEBUG is not defined */
	66	#define DPRINTK(fmt, args...) pr_debug(PFX "%s: " fmt, __FUNCTION__ , ## args)
	67
	68
	69	#undef RNG_NDEBUG /* define to enable lightweight runtime checks */
	70	#ifdef RNG_NDEBUG
71	#define assert(expr) \
72	if(!(expr)) { \
73	printk(KERN_DEBUG PFX "Assertion failed! %s,%s,%s," \
74	"line=%d\n", #expr, __FILE__, __FUNCTION__, __LINE__); \
75	}
76	#else
77	#define assert(expr)
78	#endif
79
80	#define RNG_MISCDEV_MINOR 183 /* official */
81
82	static int rng_dev_open (struct inode inode, struct file filp);
83	static ssize_t rng_dev_read (struct file filp, char __user buf, size_t size,
84	loff_t * offp);
85
86	static int __init intel_init (struct pci_dev *dev);
87	static void intel_cleanup(void);
88	static unsigned int intel_data_present (void);
89	static u32 intel_data_read (void);
90
91	static int __init amd_init (struct pci_dev *dev);
92	static void amd_cleanup(void);
93	static unsigned int amd_data_present (void);
94	static u32 amd_data_read (void);
95
96	#ifdef __i386__
97	static int __init via_init(struct pci_dev *dev);
98	static void via_cleanup(void);
99	static unsigned int via_data_present (void);
100	static u32 via_data_read (void);
101	#endif
102
a7a4ad09 JC	103	static int __init geode_init(struct pci_dev *dev);
	104	static void geode_cleanup(void);
	105	static unsigned int geode_data_present (void);
	106	static u32 geode_data_read (void);
	107
1da177e4 LT	108	struct rng_operations {
	109	int (init) (struct pci_dev dev);
	110	void (*cleanup) (void);
	111	unsigned int (*data_present) (void);
	112	u32 (*data_read) (void);
	113	unsigned int n_bytes; /* number of bytes per ->data_read */
	114	};
	115	static struct rng_operations *rng_ops;
	116
	117	static struct file_operations rng_chrdev_ops = {
	118	.owner = THIS_MODULE,
	119	.open = rng_dev_open,
	120	.read = rng_dev_read,
	121	};
	122
	123
	124	static struct miscdevice rng_miscdev = {
	125	RNG_MISCDEV_MINOR,
	126	RNG_MODULE_NAME,
	127	&rng_chrdev_ops,
	128	};
	129
	130	enum {
	131	rng_hw_none,
	132	rng_hw_intel,
	133	rng_hw_amd,
	134	rng_hw_via,
a7a4ad09	135	rng_hw_geode,
1da177e4 LT	136	};
	137
	138	static struct rng_operations rng_vendor_ops[] = {
	139	/* rng_hw_none */
	140	{ },
	141
	142	/* rng_hw_intel */
	143	{ intel_init, intel_cleanup, intel_data_present,
	144	intel_data_read, 1 },
	145
	146	/* rng_hw_amd */
	147	{ amd_init, amd_cleanup, amd_data_present, amd_data_read, 4 },
	148
	149	#ifdef __i386__
	150	/* rng_hw_via */
	151	{ via_init, via_cleanup, via_data_present, via_data_read, 1 },
	152	#endif
a7a4ad09 JC	153
	154	/* rng_hw_geode */
	155	{ geode_init, geode_cleanup, geode_data_present, geode_data_read, 4 }
1da177e4 LT	156	};
	157
	158	/*
	159	* Data for PCI driver interface
	160	*
	161	* This data only exists for exporting the supported
	162	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
	163	* register a pci_driver, because someone else might one day
	164	* want to register another driver on the same PCI id.
	165	*/
	166	static struct pci_device_id rng_pci_tbl[] = {
	167	{ 0x1022, 0x7443, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_amd },
	168	{ 0x1022, 0x746b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_amd },
	169
	170	{ 0x8086, 0x2418, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	171	{ 0x8086, 0x2428, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
e0804b17	172	{ 0x8086, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
1da177e4 LT	173	{ 0x8086, 0x2448, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	174	{ 0x8086, 0x244e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	175	{ 0x8086, 0x245e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
	176
a7a4ad09 JC	177	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LX_AES,
	178	PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_geode },
	179
1da177e4 LT	180	{ 0, }, /* terminate list */
	181	};
	182	MODULE_DEVICE_TABLE (pci, rng_pci_tbl);
	183
	184
	185	/***********************************************************************
	186	*
	187	* Intel RNG operations
	188	*
	189	*/
	190
	191	/*
	192	* RNG registers (offsets from rng_mem)
	193	*/
	194	#define INTEL_RNG_HW_STATUS 0
	195	#define INTEL_RNG_PRESENT 0x40
	196	#define INTEL_RNG_ENABLED 0x01
	197	#define INTEL_RNG_STATUS 1
	198	#define INTEL_RNG_DATA_PRESENT 0x01
	199	#define INTEL_RNG_DATA 2
	200
	201	/*
	202	* Magic address at which Intel PCI bridges locate the RNG
	203	*/
	204	#define INTEL_RNG_ADDR 0xFFBC015F
	205	#define INTEL_RNG_ADDR_LEN 3
	206
	207	/* token to our ioremap'd RNG register area */
	208	static void __iomem *rng_mem;
	209
	210	static inline u8 intel_hwstatus (void)
	211	{
	212	assert (rng_mem != NULL);
	213	return readb (rng_mem + INTEL_RNG_HW_STATUS);
	214	}
	215
	216	static inline u8 intel_hwstatus_set (u8 hw_status)
	217	{
	218	assert (rng_mem != NULL);
	219	writeb (hw_status, rng_mem + INTEL_RNG_HW_STATUS);
	220	return intel_hwstatus ();
	221	}
	222
	223	static unsigned int intel_data_present(void)
	224	{
	225	assert (rng_mem != NULL);
	226
	227	return (readb (rng_mem + INTEL_RNG_STATUS) & INTEL_RNG_DATA_PRESENT) ?
	228	1 : 0;
	229	}
	230
	231	static u32 intel_data_read(void)
	232	{
	233	assert (rng_mem != NULL);
	234
	235	return readb (rng_mem + INTEL_RNG_DATA);
	236	}
	237
	238	static int __init intel_init (struct pci_dev *dev)
	239	{
	240	int rc;
	241	u8 hw_status;
	242
	243	DPRINTK ("ENTER\n");
244
245	rng_mem = ioremap (INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
246	if (rng_mem == NULL) {
247	printk (KERN_ERR PFX "cannot ioremap RNG Memory\n");
248	rc = -EBUSY;
249	goto err_out;
250	}
251
252	/* Check for Intel 82802 */
253	hw_status = intel_hwstatus ();
254	if ((hw_status & INTEL_RNG_PRESENT) == 0) {
255	printk (KERN_ERR PFX "RNG not detected\n");
256	rc = -ENODEV;
257	goto err_out_free_map;
258	}
259
260	/* turn RNG h/w on, if it's off */
261	if ((hw_status & INTEL_RNG_ENABLED) == 0)
262	hw_status = intel_hwstatus_set (hw_status \| INTEL_RNG_ENABLED);
263	if ((hw_status & INTEL_RNG_ENABLED) == 0) {
264	printk (KERN_ERR PFX "cannot enable RNG, aborting\n");
265	rc = -EIO;
266	goto err_out_free_map;
267	}
268
269	DPRINTK ("EXIT, returning 0\n");
270	return 0;
271
272	err_out_free_map:
273	iounmap (rng_mem);
274	rng_mem = NULL;
275	err_out:
276	DPRINTK ("EXIT, returning %d\n", rc);
277	return rc;
278	}
279
280	static void intel_cleanup(void)
281	{
282	u8 hw_status;
283
284	hw_status = intel_hwstatus ();
285	if (hw_status & INTEL_RNG_ENABLED)
286	intel_hwstatus_set (hw_status & ~INTEL_RNG_ENABLED);
287	else
288	printk(KERN_WARNING PFX "unusual: RNG already disabled\n");
289	iounmap(rng_mem);
290	rng_mem = NULL;
291	}
292
293	/***********************************************************************
294	*
295	* AMD RNG operations
296	*
297	*/
298
299	static u32 pmbase; /* PMxx I/O base */
300	static struct pci_dev *amd_dev;
301
302	static unsigned int amd_data_present (void)
303	{
304	return inl(pmbase + 0xF4) & 1;
305	}
306
307
308	static u32 amd_data_read (void)
309	{
310	return inl(pmbase + 0xF0);
311	}
312
313	static int __init amd_init (struct pci_dev *dev)
314	{
315	int rc;
316	u8 rnen;
317
318	DPRINTK ("ENTER\n");
319
320	pci_read_config_dword(dev, 0x58, &pmbase);
321
322	pmbase &= 0x0000FF00;
323
324	if (pmbase == 0)
325	{
326	printk (KERN_ERR PFX "power management base not set\n");
327	rc = -EIO;
328	goto err_out;
329	}
330
331	pci_read_config_byte(dev, 0x40, &rnen);
332	rnen \|= (1 << 7); /* RNG on */
333	pci_write_config_byte(dev, 0x40, rnen);
334
335	pci_read_config_byte(dev, 0x41, &rnen);
336	rnen \|= (1 << 7); /* PMIO enable */
337	pci_write_config_byte(dev, 0x41, rnen);
338
339	pr_info( PFX "AMD768 system management I/O registers at 0x%X.\n",
340	pmbase);
341
342	amd_dev = dev;
343
344	DPRINTK ("EXIT, returning 0\n");
345	return 0;
346
347	err_out:
348	DPRINTK ("EXIT, returning %d\n", rc);
349	return rc;
350	}
351
352	static void amd_cleanup(void)
353	{
354	u8 rnen;
355
356	pci_read_config_byte(amd_dev, 0x40, &rnen);
357	rnen &= ~(1 << 7); /* RNG off */
358	pci_write_config_byte(amd_dev, 0x40, rnen);
359
360	/* FIXME: twiddle pmio, also? */
361	}
362
363	#ifdef __i386__
364	/***********************************************************************
365	*
366	* VIA RNG operations
367	*
368	*/
369
370	enum {
371	VIA_STRFILT_CNT_SHIFT = 16,
372	VIA_STRFILT_FAIL = (1 << 15),
373	VIA_STRFILT_ENABLE = (1 << 14),
374	VIA_RAWBITS_ENABLE = (1 << 13),
375	VIA_RNG_ENABLE = (1 << 6),
376	VIA_XSTORE_CNT_MASK = 0x0F,
377
378	VIA_RNG_CHUNK_8 = 0x00, /* 64 rand bits, 64 stored bits */
379	VIA_RNG_CHUNK_4 = 0x01, /* 32 rand bits, 32 stored bits */
380	VIA_RNG_CHUNK_4_MASK = 0xFFFFFFFF,
381	VIA_RNG_CHUNK_2 = 0x02, /* 16 rand bits, 32 stored bits */
382	VIA_RNG_CHUNK_2_MASK = 0xFFFF,
383	VIA_RNG_CHUNK_1 = 0x03, /* 8 rand bits, 32 stored bits */
384	VIA_RNG_CHUNK_1_MASK = 0xFF,
385	};
386
387	static u32 via_rng_datum;
388
389	/*
390	* Investigate using the 'rep' prefix to obtain 32 bits of random data
391	* in one insn. The upside is potentially better performance. The
392	* downside is that the instruction becomes no longer atomic. Due to
393	* this, just like familiar issues with /dev/random itself, the worst
394	* case of a 'rep xstore' could potentially pause a cpu for an
395	* unreasonably long time. In practice, this condition would likely
396	* only occur when the hardware is failing. (or so we hope :))
397	*
398	* Another possible performance boost may come from simply buffering
399	* until we have 4 bytes, thus returning a u32 at a time,
400	* instead of the current u8-at-a-time.
401	*/
402
403	static inline u32 xstore(u32 *addr, u32 edx_in)
404	{
405	u32 eax_out;
406
407	asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
408	:"=m"(*addr), "=a"(eax_out)
409	:"D"(addr), "d"(edx_in));
410
411	return eax_out;
412	}
413
414	static unsigned int via_data_present(void)
415	{
416	u32 bytes_out;
417
418	/* We choose the recommended 1-byte-per-instruction RNG rate,
419	* for greater randomness at the expense of speed. Larger
420	* values 2, 4, or 8 bytes-per-instruction yield greater
421	* speed at lesser randomness.
422	*
423	* If you change this to another VIA_CHUNK_n, you must also
424	* change the ->n_bytes values in rng_vendor_ops[] tables.
425	* VIA_CHUNK_8 requires further code changes.
426	*
427	* A copy of MSR_VIA_RNG is placed in eax_out when xstore
428	* completes.
429	*/
430	via_rng_datum = 0; /* paranoia, not really necessary */
431	bytes_out = xstore(&via_rng_datum, VIA_RNG_CHUNK_1) & VIA_XSTORE_CNT_MASK;
432	if (bytes_out == 0)
433	return 0;
434
435	return 1;
436	}
437
438	static u32 via_data_read(void)
439	{
440	return via_rng_datum;
441	}
442
443	static int __init via_init(struct pci_dev *dev)
444	{
445	u32 lo, hi, old_lo;
446
447	/* Control the RNG via MSR. Tread lightly and pay very close
448	* close attention to values written, as the reserved fields
449	* are documented to be "undefined and unpredictable"; but it
450	* does not say to write them as zero, so I make a guess that
451	* we restore the values we find in the register.
452	*/
453	rdmsr(MSR_VIA_RNG, lo, hi);
454
455	old_lo = lo;
456	lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
457	lo &= ~VIA_XSTORE_CNT_MASK;
458	lo &= ~(VIA_STRFILT_ENABLE \| VIA_STRFILT_FAIL \| VIA_RAWBITS_ENABLE);
459	lo \|= VIA_RNG_ENABLE;
460
461	if (lo != old_lo)
462	wrmsr(MSR_VIA_RNG, lo, hi);
463
464	/* perhaps-unnecessary sanity check; remove after testing if
465	unneeded */
466	rdmsr(MSR_VIA_RNG, lo, hi);
467	if ((lo & VIA_RNG_ENABLE) == 0) {
468	printk(KERN_ERR PFX "cannot enable VIA C3 RNG, aborting\n");
469	return -ENODEV;
470	}
471
472	return 0;
473	}
474
475	static void via_cleanup(void)
476	{
477	/* do nothing */
478	}
479	#endif
480
a7a4ad09 JC	481	/***********************************************************************
	482	*
	483	* AMD Geode RNG operations
	484	*
	485	*/
	486
	487	static void __iomem *geode_rng_base = NULL;
	488
	489	#define GEODE_RNG_DATA_REG 0x50
	490	#define GEODE_RNG_STATUS_REG 0x54
	491
	492	static u32 geode_data_read(void)
	493	{
	494	u32 val;
	495
	496	assert(geode_rng_base != NULL);
	497	val = readl(geode_rng_base + GEODE_RNG_DATA_REG);
	498	return val;
	499	}
	500
	501	static unsigned int geode_data_present(void)
	502	{
	503	u32 val;
	504
	505	assert(geode_rng_base != NULL);
	506	val = readl(geode_rng_base + GEODE_RNG_STATUS_REG);
	507	return val;
	508	}
	509
	510	static void geode_cleanup(void)
	511	{
	512	iounmap(geode_rng_base);
	513	geode_rng_base = NULL;
	514	}
	515
	516	static int geode_init(struct pci_dev *dev)
	517	{
	518	unsigned long rng_base = pci_resource_start(dev, 0);
	519
	520	if (rng_base == 0)
	521	return 1;
	522
	523	geode_rng_base = ioremap(rng_base, 0x58);
	524
	525	if (geode_rng_base == NULL) {
	526	printk(KERN_ERR PFX "Cannot ioremap RNG memory\n");
	527	return -EBUSY;
	528	}
	529
	530	return 0;
	531	}
1da177e4 LT	532
	533	/***********************************************************************
	534	*
	535	* /dev/hwrandom character device handling (major 10, minor 183)
	536	*
	537	*/
	538
	539	static int rng_dev_open (struct inode inode, struct file filp)
	540	{
	541	/* enforce read-only access to this chrdev */
	542	if ((filp->f_mode & FMODE_READ) == 0)
	543	return -EINVAL;
	544	if (filp->f_mode & FMODE_WRITE)
	545	return -EINVAL;
	546
	547	return 0;
	548	}
	549
	550
	551	static ssize_t rng_dev_read (struct file filp, char __user buf, size_t size,
	552	loff_t * offp)
	553	{
	554	static DEFINE_SPINLOCK(rng_lock);
	555	unsigned int have_data;
	556	u32 data = 0;
	557	ssize_t ret = 0;
	558
	559	while (size) {
	560	spin_lock(&rng_lock);
	561
	562	have_data = 0;
	563	if (rng_ops->data_present()) {
	564	data = rng_ops->data_read();
	565	have_data = rng_ops->n_bytes;
	566	}
	567
	568	spin_unlock (&rng_lock);
	569
	570	while (have_data && size) {
	571	if (put_user((u8)data, buf++)) {
	572	ret = ret ? : -EFAULT;
	573	break;
	574	}
	575	size--;
	576	ret++;
	577	have_data--;
	578	data>>=8;
	579	}
	580
	581	if (filp->f_flags & O_NONBLOCK)
	582	return ret ? : -EAGAIN;
	583
	584	if(need_resched())
da4cd8df	585	schedule_timeout_interruptible(1);
1da177e4 LT	586	else
	587	udelay(200); /* FIXME: We could poll for 250uS ?? */
	588
	589	if (signal_pending (current))
	590	return ret ? : -ERESTARTSYS;
	591	}
	592	return ret;
	593	}
	594
	595
	596
	597	/*
	598	* rng_init_one - look for and attempt to init a single RNG
	599	*/
	600	static int __init rng_init_one (struct pci_dev *dev)
	601	{
	602	int rc;
	603
	604	DPRINTK ("ENTER\n");
	605
	606	assert(rng_ops != NULL);
	607
	608	rc = rng_ops->init(dev);
	609	if (rc)
	610	goto err_out;
	611
	612	rc = misc_register (&rng_miscdev);
	613	if (rc) {
	614	printk (KERN_ERR PFX "misc device register failed\n");
	615	goto err_out_cleanup_hw;
	616	}
	617
	618	DPRINTK ("EXIT, returning 0\n");
	619	return 0;
	620
	621	err_out_cleanup_hw:
	622	rng_ops->cleanup();
	623	err_out:
	624	DPRINTK ("EXIT, returning %d\n", rc);
	625	return rc;
	626	}
	627
	628
	629
	630	MODULE_AUTHOR("The Linux Kernel team");
	631	MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver");
	632	MODULE_LICENSE("GPL");
	633
	634
	635	/*
	636	* rng_init - initialize RNG module
	637	*/
	638	static int __init rng_init (void)
	639	{
	640	int rc;
	641	struct pci_dev *pdev = NULL;
	642	const struct pci_device_id *ent;
	643
	644	DPRINTK ("ENTER\n");
	645
a7a4ad09	646	/* Probe for Intel, AMD, Geode RNGs */
1da177e4	647	for_each_pci_dev(pdev) {
75865858	648	ent = pci_match_id(rng_pci_tbl, pdev);
1da177e4 LT	649	if (ent) {
	650	rng_ops = &rng_vendor_ops[ent->driver_data];
	651	goto match;
	652	}
	653	}
	654
	655	#ifdef __i386__
	656	/* Probe for VIA RNG */
	657	if (cpu_has_xstore) {
	658	rng_ops = &rng_vendor_ops[rng_hw_via];
	659	pdev = NULL;
	660	goto match;
	661	}
	662	#endif
	663
	664	DPRINTK ("EXIT, returning -ENODEV\n");
	665	return -ENODEV;
	666
	667	match:
	668	rc = rng_init_one (pdev);
	669	if (rc)
	670	return rc;
	671
	672	pr_info( RNG_DRIVER_NAME " loaded\n");
	673
	674	DPRINTK ("EXIT, returning 0\n");
	675	return 0;
	676	}
	677
	678
	679	/*
	680	* rng_init - shutdown RNG module
	681	*/
	682	static void __exit rng_cleanup (void)
	683	{
	684	DPRINTK ("ENTER\n");
	685
	686	misc_deregister (&rng_miscdev);
	687
	688	if (rng_ops->cleanup)
	689	rng_ops->cleanup();
	690
	691	DPRINTK ("EXIT\n");
	692	}
	693
	694
	695	module_init (rng_init);
	696	module_exit (rng_cleanup);