[linux-2.6-block.git] / drivers / char / hw_random / via-rng.c

/*
 * RNG driver for VIA RNGs
 *
 * Copyright 2005 (c) MontaVista Software, Inc.
 *
 * with the majority of the code coming from:
 *
 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
 *
 * derived from
 *
 * Hardware driver for the AMD 768 Random Number Generator (RNG)
 * (c) Copyright 2001 Red Hat Inc
 *
 * derived from
 *
 * Hardware driver for Intel i810 Random Number Generator (RNG)
 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
 *
 * This file is licensed under  the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <crypto/padlock.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/hw_random.h>
#include <linux/delay.h>
#include <asm/cpu_device_id.h>
#include <asm/io.h>
#include <asm/msr.h>
#include <asm/cpufeature.h>
#include <asm/fpu/api.h>


enum {
	VIA_STRFILT_CNT_SHIFT	= 16,
	VIA_STRFILT_FAIL	= (1 << 15),
	VIA_STRFILT_ENABLE	= (1 << 14),
	VIA_RAWBITS_ENABLE	= (1 << 13),
	VIA_RNG_ENABLE		= (1 << 6),
	VIA_NOISESRC1		= (1 << 8),
	VIA_NOISESRC2		= (1 << 9),
	VIA_XSTORE_CNT_MASK	= 0x0F,

	VIA_RNG_CHUNK_8		= 0x00,	/* 64 rand bits, 64 stored bits */
	VIA_RNG_CHUNK_4		= 0x01,	/* 32 rand bits, 32 stored bits */
	VIA_RNG_CHUNK_4_MASK	= 0xFFFFFFFF,
	VIA_RNG_CHUNK_2		= 0x02,	/* 16 rand bits, 32 stored bits */
	VIA_RNG_CHUNK_2_MASK	= 0xFFFF,
	VIA_RNG_CHUNK_1		= 0x03,	/* 8 rand bits, 32 stored bits */
	VIA_RNG_CHUNK_1_MASK	= 0xFF,
};

/*
 * Investigate using the 'rep' prefix to obtain 32 bits of random data
 * in one insn.  The upside is potentially better performance.  The
 * downside is that the instruction becomes no longer atomic.  Due to
 * this, just like familiar issues with /dev/random itself, the worst
 * case of a 'rep xstore' could potentially pause a cpu for an
 * unreasonably long time.  In practice, this condition would likely
 * only occur when the hardware is failing.  (or so we hope :))
 *
 * Another possible performance boost may come from simply buffering
 * until we have 4 bytes, thus returning a u32 at a time,
 * instead of the current u8-at-a-time.
 *
 * Padlock instructions can generate a spurious DNA fault, so
 * we have to call them in the context of irq_ts_save/restore()
 */

static inline u32 xstore(u32 *addr, u32 edx_in)
{
	u32 eax_out;
	int ts_state;

	ts_state = irq_ts_save();

	asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
		: "=m" (*addr), "=a" (eax_out), "+d" (edx_in), "+D" (addr));

	irq_ts_restore(ts_state);
	return eax_out;
}

static int via_rng_data_present(struct hwrng *rng, int wait)
{
	char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	u32 *via_rng_datum = (u32 *)PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	u32 bytes_out;
	int i;

	/* We choose the recommended 1-byte-per-instruction RNG rate,
	 * for greater randomness at the expense of speed.  Larger
	 * values 2, 4, or 8 bytes-per-instruction yield greater
	 * speed at lesser randomness.
	 *
	 * If you change this to another VIA_CHUNK_n, you must also
	 * change the ->n_bytes values in rng_vendor_ops[] tables.
	 * VIA_CHUNK_8 requires further code changes.
	 *
	 * A copy of MSR_VIA_RNG is placed in eax_out when xstore
	 * completes.
	 */

	for (i = 0; i < 20; i++) {
		*via_rng_datum = 0; /* paranoia, not really necessary */
		bytes_out = xstore(via_rng_datum, VIA_RNG_CHUNK_1);
		bytes_out &= VIA_XSTORE_CNT_MASK;
		if (bytes_out || !wait)
			break;
		udelay(10);
	}
	rng->priv = *via_rng_datum;
	return bytes_out ? 1 : 0;
}

static int via_rng_data_read(struct hwrng *rng, u32 *data)
{
	u32 via_rng_datum = (u32)rng->priv;

	*data = via_rng_datum;

	return 1;
}

static int via_rng_init(struct hwrng *rng)
{
	struct cpuinfo_x86 *c = &cpu_data(0);
	u32 lo, hi, old_lo;

	/* VIA Nano CPUs don't have the MSR_VIA_RNG anymore.  The RNG
	 * is always enabled if CPUID rng_en is set.  There is no
	 * RNG configuration like it used to be the case in this
	 * register */
	if ((c->x86 == 6) && (c->x86_model >= 0x0f)) {
		if (!boot_cpu_has(X86_FEATURE_XSTORE_EN)) {
			pr_err(PFX "can't enable hardware RNG "
				"if XSTORE is not enabled\n");
			return -ENODEV;
		}
		return 0;
	}

	/* Control the RNG via MSR.  Tread lightly and pay very close
	 * close attention to values written, as the reserved fields
	 * are documented to be "undefined and unpredictable"; but it
	 * does not say to write them as zero, so I make a guess that
	 * we restore the values we find in the register.
	 */
	rdmsr(MSR_VIA_RNG, lo, hi);

	old_lo = lo;
	lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
	lo &= ~VIA_XSTORE_CNT_MASK;
	lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
	lo |= VIA_RNG_ENABLE;
	lo |= VIA_NOISESRC1;

	/* Enable secondary noise source on CPUs where it is present. */

	/* Nehemiah stepping 8 and higher */
	if ((c->x86_model == 9) && (c->x86_mask > 7))
		lo |= VIA_NOISESRC2;

	/* Esther */
	if (c->x86_model >= 10)
		lo |= VIA_NOISESRC2;

	if (lo != old_lo)
		wrmsr(MSR_VIA_RNG, lo, hi);

	/* perhaps-unnecessary sanity check; remove after testing if
	   unneeded */
	rdmsr(MSR_VIA_RNG, lo, hi);
	if ((lo & VIA_RNG_ENABLE) == 0) {
		pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");
		return -ENODEV;
	}

	return 0;
}


static struct hwrng via_rng = {
	.name		= "via",
	.init		= via_rng_init,
	.data_present	= via_rng_data_present,
	.data_read	= via_rng_data_read,
};


static int __init mod_init(void)
{
	int err;

	if (!boot_cpu_has(X86_FEATURE_XSTORE))
		return -ENODEV;

	pr_info("VIA RNG detected\n");
	err = hwrng_register(&via_rng);
	if (err) {
		pr_err(PFX "RNG registering failed (%d)\n",
		       err);
		goto out;
	}
out:
	return err;
}

static void __exit mod_exit(void)
{
	hwrng_unregister(&via_rng);
}

module_init(mod_init);
module_exit(mod_exit);

static struct x86_cpu_id __maybe_unused via_rng_cpu_id[] = {
	X86_FEATURE_MATCH(X86_FEATURE_XSTORE),
	{}
};

MODULE_DESCRIPTION("H/W RNG driver for VIA CPU with PadLock");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(x86cpu, via_rng_cpu_id);
Commit	Line	Data
13523363 MB	1	/*
	2	* RNG driver for VIA RNGs
	3	*
	4	* Copyright 2005 (c) MontaVista Software, Inc.
	5	*
	6	* with the majority of the code coming from:
	7	*
	8	* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
	9	* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
	10	*
	11	* derived from
	12	*
	13	* Hardware driver for the AMD 768 Random Number Generator (RNG)
77122d0b	14	* (c) Copyright 2001 Red Hat Inc
13523363 MB	15	*
	16	* derived from
	17	*
	18	* Hardware driver for Intel i810 Random Number Generator (RNG)
	19	* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
	20	* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
	21	*
	22	* This file is licensed under the terms of the GNU General Public
	23	* License version 2. This program is licensed "as is" without any
	24	* warranty of any kind, whether express or implied.
	25	*/
	26
55db8387	27	#include <crypto/padlock.h>
13523363 MB	28	#include <linux/module.h>
13523363 MB	29	#include <linux/kernel.h>
13523363	30	#include <linux/hw_random.h>
984e976f	31	#include <linux/delay.h>
ff6f83fc	32	#include <asm/cpu_device_id.h>
13523363 MB	33	#include <asm/io.h>
	34	#include <asm/msr.h>
	35	#include <asm/cpufeature.h>
df6b35f4	36	#include <asm/fpu/api.h>
13523363 MB	37
13523363 MB	38
13523363 MB	39
	40
	41	enum {
	42	VIA_STRFILT_CNT_SHIFT = 16,
	43	VIA_STRFILT_FAIL = (1 << 15),
	44	VIA_STRFILT_ENABLE = (1 << 14),
	45	VIA_RAWBITS_ENABLE = (1 << 13),
	46	VIA_RNG_ENABLE = (1 << 6),
11025e85 DJ	47	VIA_NOISESRC1 = (1 << 8),
11025e85 DJ	48	VIA_NOISESRC2 = (1 << 9),
13523363 MB	49	VIA_XSTORE_CNT_MASK = 0x0F,
	50
	51	VIA_RNG_CHUNK_8 = 0x00, /* 64 rand bits, 64 stored bits */
	52	VIA_RNG_CHUNK_4 = 0x01, /* 32 rand bits, 32 stored bits */
	53	VIA_RNG_CHUNK_4_MASK = 0xFFFFFFFF,
	54	VIA_RNG_CHUNK_2 = 0x02, /* 16 rand bits, 32 stored bits */
	55	VIA_RNG_CHUNK_2_MASK = 0xFFFF,
	56	VIA_RNG_CHUNK_1 = 0x03, /* 8 rand bits, 32 stored bits */
	57	VIA_RNG_CHUNK_1_MASK = 0xFF,
	58	};
	59
	60	/*
	61	* Investigate using the 'rep' prefix to obtain 32 bits of random data
	62	* in one insn. The upside is potentially better performance. The
	63	* downside is that the instruction becomes no longer atomic. Due to
	64	* this, just like familiar issues with /dev/random itself, the worst
	65	* case of a 'rep xstore' could potentially pause a cpu for an
	66	* unreasonably long time. In practice, this condition would likely
	67	* only occur when the hardware is failing. (or so we hope :))
	68	*
	69	* Another possible performance boost may come from simply buffering
	70	* until we have 4 bytes, thus returning a u32 at a time,
	71	* instead of the current u8-at-a-time.
e4914012 SS	72	*
	73	* Padlock instructions can generate a spurious DNA fault, so
	74	* we have to call them in the context of irq_ts_save/restore()
13523363 MB	75	*/
	76
	77	static inline u32 xstore(u32 *addr, u32 edx_in)
	78	{
	79	u32 eax_out;
e4914012 SS	80	int ts_state;
	81
	82	ts_state = irq_ts_save();
13523363 MB	83
13523363 MB	84	asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
0735ac1f	85	: "=m" (*addr), "=a" (eax_out), "+d" (edx_in), "+D" (addr));
13523363	86
e4914012	87	irq_ts_restore(ts_state);
13523363 MB	88	return eax_out;
	89	}
	90
984e976f	91	static int via_rng_data_present(struct hwrng *rng, int wait)
13523363	92	{
55db8387 HX	93	char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	94	((aligned(STACK_ALIGN)));
	95	u32 via_rng_datum = (u32 )PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
13523363	96	u32 bytes_out;
984e976f	97	int i;
13523363 MB	98
	99	/* We choose the recommended 1-byte-per-instruction RNG rate,
	100	* for greater randomness at the expense of speed. Larger
	101	* values 2, 4, or 8 bytes-per-instruction yield greater
	102	* speed at lesser randomness.
	103	*
	104	* If you change this to another VIA_CHUNK_n, you must also
	105	* change the ->n_bytes values in rng_vendor_ops[] tables.
	106	* VIA_CHUNK_8 requires further code changes.
	107	*
	108	* A copy of MSR_VIA_RNG is placed in eax_out when xstore
	109	* completes.
	110	*/
	111
984e976f PM	112	for (i = 0; i < 20; i++) {
	113	via_rng_datum = 0; / paranoia, not really necessary */
	114	bytes_out = xstore(via_rng_datum, VIA_RNG_CHUNK_1);
	115	bytes_out &= VIA_XSTORE_CNT_MASK;
	116	if (bytes_out \|\| !wait)
	117	break;
	118	udelay(10);
	119	}
55db8387	120	rng->priv = *via_rng_datum;
984e976f	121	return bytes_out ? 1 : 0;
13523363 MB	122	}
	123
	124	static int via_rng_data_read(struct hwrng rng, u32 data)
	125	{
	126	u32 via_rng_datum = (u32)rng->priv;
	127
	128	*data = via_rng_datum;
	129
	130	return 1;
	131	}
	132
	133	static int via_rng_init(struct hwrng *rng)
	134	{
11025e85	135	struct cpuinfo_x86 *c = &cpu_data(0);
13523363 MB	136	u32 lo, hi, old_lo;
13523363 MB	137
858576bd HW	138	/* VIA Nano CPUs don't have the MSR_VIA_RNG anymore. The RNG
	139	* is always enabled if CPUID rng_en is set. There is no
	140	* RNG configuration like it used to be the case in this
	141	* register */
	142	if ((c->x86 == 6) && (c->x86_model >= 0x0f)) {
362f924b	143	if (!boot_cpu_has(X86_FEATURE_XSTORE_EN)) {
7a1ae9c0	144	pr_err(PFX "can't enable hardware RNG "
858576bd HW	145	"if XSTORE is not enabled\n");
	146	return -ENODEV;
	147	}
	148	return 0;
	149	}
	150
13523363 MB	151	/* Control the RNG via MSR. Tread lightly and pay very close
	152	* close attention to values written, as the reserved fields
	153	* are documented to be "undefined and unpredictable"; but it
	154	* does not say to write them as zero, so I make a guess that
	155	* we restore the values we find in the register.
	156	*/
	157	rdmsr(MSR_VIA_RNG, lo, hi);
	158
	159	old_lo = lo;
	160	lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
	161	lo &= ~VIA_XSTORE_CNT_MASK;
	162	lo &= ~(VIA_STRFILT_ENABLE \| VIA_STRFILT_FAIL \| VIA_RAWBITS_ENABLE);
	163	lo \|= VIA_RNG_ENABLE;
11025e85 DJ	164	lo \|= VIA_NOISESRC1;
	165
	166	/* Enable secondary noise source on CPUs where it is present. */
	167
	168	/* Nehemiah stepping 8 and higher */
	169	if ((c->x86_model == 9) && (c->x86_mask > 7))
	170	lo \|= VIA_NOISESRC2;
	171
	172	/* Esther */
	173	if (c->x86_model >= 10)
	174	lo \|= VIA_NOISESRC2;
13523363 MB	175
	176	if (lo != old_lo)
	177	wrmsr(MSR_VIA_RNG, lo, hi);
	178
	179	/* perhaps-unnecessary sanity check; remove after testing if
	180	unneeded */
	181	rdmsr(MSR_VIA_RNG, lo, hi);
	182	if ((lo & VIA_RNG_ENABLE) == 0) {
7a1ae9c0	183	pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");
13523363 MB	184	return -ENODEV;
	185	}
	186
	187	return 0;
	188	}
	189
	190
	191	static struct hwrng via_rng = {
	192	.name = "via",
	193	.init = via_rng_init,
	194	.data_present = via_rng_data_present,
	195	.data_read = via_rng_data_read,
	196	};
	197
	198
	199	static int __init mod_init(void)
	200	{
	201	int err;
	202
362f924b	203	if (!boot_cpu_has(X86_FEATURE_XSTORE))
13523363	204	return -ENODEV;
362f924b	205
7a1ae9c0	206	pr_info("VIA RNG detected\n");
13523363 MB	207	err = hwrng_register(&via_rng);
13523363 MB	208	if (err) {
7a1ae9c0	209	pr_err(PFX "RNG registering failed (%d)\n",
13523363 MB	210	err);
	211	goto out;
	212	}
	213	out:
	214	return err;
	215	}
	216
	217	static void __exit mod_exit(void)
	218	{
	219	hwrng_unregister(&via_rng);
	220	}
	221
56fb5fe9	222	module_init(mod_init);
13523363 MB	223	module_exit(mod_exit);
13523363 MB	224
a44bc80e	225	static struct x86_cpu_id __maybe_unused via_rng_cpu_id[] = {
ff6f83fc BH	226	X86_FEATURE_MATCH(X86_FEATURE_XSTORE),
	227	{}
	228	};
	229
608d1cd5	230	MODULE_DESCRIPTION("H/W RNG driver for VIA CPU with PadLock");
13523363	231	MODULE_LICENSE("GPL");
ff6f83fc	232	MODULE_DEVICE_TABLE(x86cpu, via_rng_cpu_id);