Commit | Line | Data |
---|---|---|
ebc915ad | 1 | /* |
c49a7f18 | 2 | * omap-rng.c - RNG driver for TI OMAP CPU family |
ebc915ad MB |
3 | * |
4 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
5 | * | |
6 | * Copyright 2005 (c) MontaVista Software, Inc. | |
7 | * | |
8 | * Mostly based on original driver: | |
9 | * | |
10 | * Copyright (C) 2005 Nokia Corporation | |
96de0e25 | 11 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> |
ebc915ad MB |
12 | * |
13 | * This file is licensed under the terms of the GNU General Public | |
14 | * License version 2. This program is licensed "as is" without any | |
15 | * warranty of any kind, whether express or implied. | |
ebc915ad MB |
16 | */ |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/random.h> | |
21 | #include <linux/err.h> | |
af2bc7d2 | 22 | #include <linux/platform_device.h> |
ebc915ad | 23 | #include <linux/hw_random.h> |
984e976f | 24 | #include <linux/delay.h> |
02666360 | 25 | #include <linux/slab.h> |
665d92fa | 26 | #include <linux/pm_runtime.h> |
ebc915ad MB |
27 | |
28 | #include <asm/io.h> | |
ebc915ad MB |
29 | |
30 | #define RNG_OUT_REG 0x00 /* Output register */ | |
31 | #define RNG_STAT_REG 0x04 /* Status register | |
32 | [0] = STAT_BUSY */ | |
33 | #define RNG_ALARM_REG 0x24 /* Alarm register | |
34 | [7:0] = ALARM_COUNTER */ | |
35 | #define RNG_CONFIG_REG 0x28 /* Configuration register | |
36 | [11:6] = RESET_COUNT | |
37 | [5:3] = RING2_DELAY | |
38 | [2:0] = RING1_DELAY */ | |
39 | #define RNG_REV_REG 0x3c /* Revision register | |
40 | [7:0] = REV_NB */ | |
41 | #define RNG_MASK_REG 0x40 /* Mask and reset register | |
42 | [2] = IT_EN | |
43 | [1] = SOFTRESET | |
44 | [0] = AUTOIDLE */ | |
45 | #define RNG_SYSSTATUS 0x44 /* System status | |
46 | [0] = RESETDONE */ | |
47 | ||
02666360 PW |
48 | /** |
49 | * struct omap_rng_private_data - RNG IP block-specific data | |
50 | * @base: virtual address of the beginning of the RNG IP block registers | |
02666360 PW |
51 | * @mem_res: struct resource * for the IP block registers physical memory |
52 | */ | |
53 | struct omap_rng_private_data { | |
54 | void __iomem *base; | |
02666360 PW |
55 | struct resource *mem_res; |
56 | }; | |
ebc915ad | 57 | |
02666360 | 58 | static inline u32 omap_rng_read_reg(struct omap_rng_private_data *priv, int reg) |
ebc915ad | 59 | { |
02666360 | 60 | return __raw_readl(priv->base + reg); |
ebc915ad MB |
61 | } |
62 | ||
02666360 PW |
63 | static inline void omap_rng_write_reg(struct omap_rng_private_data *priv, |
64 | int reg, u32 val) | |
ebc915ad | 65 | { |
02666360 | 66 | __raw_writel(val, priv->base + reg); |
ebc915ad MB |
67 | } |
68 | ||
984e976f | 69 | static int omap_rng_data_present(struct hwrng *rng, int wait) |
ebc915ad | 70 | { |
02666360 | 71 | struct omap_rng_private_data *priv; |
984e976f PM |
72 | int data, i; |
73 | ||
02666360 PW |
74 | priv = (struct omap_rng_private_data *)rng->priv; |
75 | ||
984e976f | 76 | for (i = 0; i < 20; i++) { |
02666360 | 77 | data = omap_rng_read_reg(priv, RNG_STAT_REG) ? 0 : 1; |
984e976f PM |
78 | if (data || !wait) |
79 | break; | |
c49a7f18 DB |
80 | /* RNG produces data fast enough (2+ MBit/sec, even |
81 | * during "rngtest" loads, that these delays don't | |
82 | * seem to trigger. We *could* use the RNG IRQ, but | |
83 | * that'd be higher overhead ... so why bother? | |
84 | */ | |
984e976f PM |
85 | udelay(10); |
86 | } | |
87 | return data; | |
ebc915ad MB |
88 | } |
89 | ||
90 | static int omap_rng_data_read(struct hwrng *rng, u32 *data) | |
91 | { | |
02666360 PW |
92 | struct omap_rng_private_data *priv; |
93 | ||
94 | priv = (struct omap_rng_private_data *)rng->priv; | |
95 | ||
96 | *data = omap_rng_read_reg(priv, RNG_OUT_REG); | |
ebc915ad | 97 | |
02666360 | 98 | return sizeof(u32); |
ebc915ad MB |
99 | } |
100 | ||
101 | static struct hwrng omap_rng_ops = { | |
102 | .name = "omap", | |
103 | .data_present = omap_rng_data_present, | |
104 | .data_read = omap_rng_data_read, | |
105 | }; | |
106 | ||
bcd2982a | 107 | static int omap_rng_probe(struct platform_device *pdev) |
ebc915ad | 108 | { |
02666360 | 109 | struct omap_rng_private_data *priv; |
ebc915ad MB |
110 | int ret; |
111 | ||
d52dc81e LV |
112 | priv = devm_kzalloc(&pdev->dev, sizeof(struct omap_rng_private_data), |
113 | GFP_KERNEL); | |
02666360 PW |
114 | if (!priv) { |
115 | dev_err(&pdev->dev, "could not allocate memory\n"); | |
116 | return -ENOMEM; | |
117 | }; | |
118 | ||
119 | omap_rng_ops.priv = (unsigned long)priv; | |
1f539bcb | 120 | platform_set_drvdata(pdev, priv); |
ebc915ad | 121 | |
02666360 | 122 | priv->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
c7c9e1c3 TR |
123 | priv->base = devm_ioremap_resource(&pdev->dev, priv->mem_res); |
124 | if (IS_ERR(priv->base)) { | |
125 | ret = PTR_ERR(priv->base); | |
55c381e4 RK |
126 | goto err_ioremap; |
127 | } | |
ebc915ad | 128 | |
665d92fa PW |
129 | pm_runtime_enable(&pdev->dev); |
130 | pm_runtime_get_sync(&pdev->dev); | |
131 | ||
ebc915ad | 132 | ret = hwrng_register(&omap_rng_ops); |
55c381e4 RK |
133 | if (ret) |
134 | goto err_register; | |
ebc915ad | 135 | |
af2bc7d2 | 136 | dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n", |
02666360 PW |
137 | omap_rng_read_reg(priv, RNG_REV_REG)); |
138 | ||
02666360 | 139 | omap_rng_write_reg(priv, RNG_MASK_REG, 0x1); |
ebc915ad MB |
140 | |
141 | return 0; | |
55c381e4 RK |
142 | |
143 | err_register: | |
02666360 | 144 | priv->base = NULL; |
665d92fa | 145 | pm_runtime_disable(&pdev->dev); |
55c381e4 | 146 | err_ioremap: |
55c381e4 | 147 | return ret; |
ebc915ad MB |
148 | } |
149 | ||
af2bc7d2 | 150 | static int __exit omap_rng_remove(struct platform_device *pdev) |
ebc915ad | 151 | { |
1f539bcb | 152 | struct omap_rng_private_data *priv = platform_get_drvdata(pdev); |
02666360 | 153 | |
ebc915ad MB |
154 | hwrng_unregister(&omap_rng_ops); |
155 | ||
02666360 PW |
156 | omap_rng_write_reg(priv, RNG_MASK_REG, 0x0); |
157 | ||
665d92fa PW |
158 | pm_runtime_put_sync(&pdev->dev); |
159 | pm_runtime_disable(&pdev->dev); | |
ebc915ad | 160 | |
ebc915ad MB |
161 | return 0; |
162 | } | |
163 | ||
59596df6 | 164 | #ifdef CONFIG_PM_SLEEP |
ebc915ad | 165 | |
7650572a | 166 | static int omap_rng_suspend(struct device *dev) |
ebc915ad | 167 | { |
02666360 PW |
168 | struct omap_rng_private_data *priv = dev_get_drvdata(dev); |
169 | ||
170 | omap_rng_write_reg(priv, RNG_MASK_REG, 0x0); | |
665d92fa | 171 | pm_runtime_put_sync(dev); |
02666360 | 172 | |
ebc915ad MB |
173 | return 0; |
174 | } | |
175 | ||
7650572a | 176 | static int omap_rng_resume(struct device *dev) |
ebc915ad | 177 | { |
02666360 PW |
178 | struct omap_rng_private_data *priv = dev_get_drvdata(dev); |
179 | ||
665d92fa | 180 | pm_runtime_get_sync(dev); |
02666360 PW |
181 | omap_rng_write_reg(priv, RNG_MASK_REG, 0x1); |
182 | ||
af2bc7d2 | 183 | return 0; |
ebc915ad MB |
184 | } |
185 | ||
7650572a RW |
186 | static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume); |
187 | #define OMAP_RNG_PM (&omap_rng_pm) | |
188 | ||
ebc915ad MB |
189 | #else |
190 | ||
7650572a | 191 | #define OMAP_RNG_PM NULL |
ebc915ad MB |
192 | |
193 | #endif | |
194 | ||
af2bc7d2 DB |
195 | static struct platform_driver omap_rng_driver = { |
196 | .driver = { | |
197 | .name = "omap_rng", | |
198 | .owner = THIS_MODULE, | |
7650572a | 199 | .pm = OMAP_RNG_PM, |
af2bc7d2 | 200 | }, |
ebc915ad MB |
201 | .probe = omap_rng_probe, |
202 | .remove = __exit_p(omap_rng_remove), | |
ebc915ad MB |
203 | }; |
204 | ||
4390f77b LV |
205 | module_platform_driver(omap_rng_driver); |
206 | MODULE_ALIAS("platform:omap_rng"); | |
ebc915ad MB |
207 | MODULE_AUTHOR("Deepak Saxena (and others)"); |
208 | MODULE_LICENSE("GPL"); |