Commit | Line | Data |
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22f579c6 | 1 | /* via_dma.c -- DMA support for the VIA Unichrome/Pro |
b5e89ed5 | 2 | * |
22f579c6 DA |
3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. | |
7 | * All Rights Reserved. | |
b5e89ed5 | 8 | * |
22f579c6 DA |
9 | * Copyright 2004 The Unichrome project. |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the | |
20 | * next paragraph) shall be included in all copies or substantial portions | |
21 | * of the Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
b5e89ed5 DA |
26 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
27 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
28 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
22f579c6 DA |
29 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
30 | * | |
b5e89ed5 DA |
31 | * Authors: |
32 | * Tungsten Graphics, | |
33 | * Erdi Chen, | |
22f579c6 DA |
34 | * Thomas Hellstrom. |
35 | */ | |
36 | ||
37 | #include "drmP.h" | |
38 | #include "drm.h" | |
39 | #include "via_drm.h" | |
40 | #include "via_drv.h" | |
41 | #include "via_3d_reg.h" | |
42 | ||
43 | #define CMDBUF_ALIGNMENT_SIZE (0x100) | |
44 | #define CMDBUF_ALIGNMENT_MASK (0x0ff) | |
45 | ||
46 | /* defines for VIA 3D registers */ | |
47 | #define VIA_REG_STATUS 0x400 | |
48 | #define VIA_REG_TRANSET 0x43C | |
49 | #define VIA_REG_TRANSPACE 0x440 | |
50 | ||
51 | /* VIA_REG_STATUS(0x400): Engine Status */ | |
52 | #define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ | |
53 | #define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ | |
54 | #define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ | |
55 | #define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ | |
56 | ||
57 | #define SetReg2DAGP(nReg, nData) { \ | |
58 | *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \ | |
59 | *((uint32_t *)(vb) + 1) = (nData); \ | |
60 | vb = ((uint32_t *)vb) + 2; \ | |
61 | dev_priv->dma_low +=8; \ | |
62 | } | |
63 | ||
b5e89ed5 | 64 | #define via_flush_write_combine() DRM_MEMORYBARRIER() |
22f579c6 DA |
65 | |
66 | #define VIA_OUT_RING_QW(w1,w2) \ | |
67 | *vb++ = (w1); \ | |
68 | *vb++ = (w2); \ | |
b5e89ed5 | 69 | dev_priv->dma_low += 8; |
22f579c6 DA |
70 | |
71 | static void via_cmdbuf_start(drm_via_private_t * dev_priv); | |
72 | static void via_cmdbuf_pause(drm_via_private_t * dev_priv); | |
73 | static void via_cmdbuf_reset(drm_via_private_t * dev_priv); | |
74 | static void via_cmdbuf_rewind(drm_via_private_t * dev_priv); | |
75 | static int via_wait_idle(drm_via_private_t * dev_priv); | |
b5e89ed5 | 76 | static void via_pad_cache(drm_via_private_t * dev_priv, int qwords); |
22f579c6 DA |
77 | |
78 | /* | |
79 | * Free space in command buffer. | |
80 | */ | |
81 | ||
b5e89ed5 | 82 | static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv) |
22f579c6 | 83 | { |
b5e89ed5 | 84 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
22f579c6 | 85 | uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; |
b5e89ed5 DA |
86 | |
87 | return ((hw_addr <= dev_priv->dma_low) ? | |
88 | (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : | |
22f579c6 DA |
89 | (hw_addr - dev_priv->dma_low)); |
90 | } | |
91 | ||
92 | /* | |
93 | * How much does the command regulator lag behind? | |
94 | */ | |
95 | ||
b5e89ed5 | 96 | static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv) |
22f579c6 | 97 | { |
b5e89ed5 | 98 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
22f579c6 | 99 | uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; |
b5e89ed5 DA |
100 | |
101 | return ((hw_addr <= dev_priv->dma_low) ? | |
102 | (dev_priv->dma_low - hw_addr) : | |
22f579c6 DA |
103 | (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); |
104 | } | |
105 | ||
106 | /* | |
107 | * Check that the given size fits in the buffer, otherwise wait. | |
108 | */ | |
109 | ||
110 | static inline int | |
111 | via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size) | |
112 | { | |
113 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
114 | uint32_t cur_addr, hw_addr, next_addr; | |
115 | volatile uint32_t *hw_addr_ptr; | |
116 | uint32_t count; | |
117 | hw_addr_ptr = dev_priv->hw_addr_ptr; | |
118 | cur_addr = dev_priv->dma_low; | |
b5e89ed5 | 119 | next_addr = cur_addr + size + 512 * 1024; |
22f579c6 DA |
120 | count = 1000000; |
121 | do { | |
b5e89ed5 | 122 | hw_addr = *hw_addr_ptr - agp_base; |
22f579c6 | 123 | if (count-- == 0) { |
b5e89ed5 DA |
124 | DRM_ERROR |
125 | ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n", | |
126 | hw_addr, cur_addr, next_addr); | |
22f579c6 DA |
127 | return -1; |
128 | } | |
129 | } while ((cur_addr < hw_addr) && (next_addr >= hw_addr)); | |
130 | return 0; | |
131 | } | |
132 | ||
22f579c6 DA |
133 | /* |
134 | * Checks whether buffer head has reach the end. Rewind the ring buffer | |
135 | * when necessary. | |
136 | * | |
137 | * Returns virtual pointer to ring buffer. | |
138 | */ | |
139 | ||
140 | static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, | |
141 | unsigned int size) | |
142 | { | |
b5e89ed5 DA |
143 | if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) > |
144 | dev_priv->dma_high) { | |
22f579c6 DA |
145 | via_cmdbuf_rewind(dev_priv); |
146 | } | |
147 | if (via_cmdbuf_wait(dev_priv, size) != 0) { | |
148 | return NULL; | |
149 | } | |
150 | ||
151 | return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); | |
152 | } | |
153 | ||
84b1fd10 | 154 | int via_dma_cleanup(struct drm_device * dev) |
22f579c6 DA |
155 | { |
156 | if (dev->dev_private) { | |
157 | drm_via_private_t *dev_priv = | |
b5e89ed5 | 158 | (drm_via_private_t *) dev->dev_private; |
22f579c6 DA |
159 | |
160 | if (dev_priv->ring.virtual_start) { | |
161 | via_cmdbuf_reset(dev_priv); | |
162 | ||
163 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
164 | dev_priv->ring.virtual_start = NULL; | |
165 | } | |
166 | ||
167 | } | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
84b1fd10 | 172 | static int via_initialize(struct drm_device * dev, |
22f579c6 DA |
173 | drm_via_private_t * dev_priv, |
174 | drm_via_dma_init_t * init) | |
175 | { | |
176 | if (!dev_priv || !dev_priv->mmio) { | |
177 | DRM_ERROR("via_dma_init called before via_map_init\n"); | |
178 | return DRM_ERR(EFAULT); | |
179 | } | |
180 | ||
181 | if (dev_priv->ring.virtual_start != NULL) { | |
182 | DRM_ERROR("%s called again without calling cleanup\n", | |
183 | __FUNCTION__); | |
184 | return DRM_ERR(EFAULT); | |
185 | } | |
186 | ||
187 | if (!dev->agp || !dev->agp->base) { | |
b5e89ed5 | 188 | DRM_ERROR("%s called with no agp memory available\n", |
22f579c6 DA |
189 | __FUNCTION__); |
190 | return DRM_ERR(EFAULT); | |
191 | } | |
192 | ||
756db73d TH |
193 | if (dev_priv->chipset == VIA_DX9_0) { |
194 | DRM_ERROR("AGP DMA is not supported on this chip\n"); | |
195 | return DRM_ERR(EINVAL); | |
196 | } | |
197 | ||
22f579c6 DA |
198 | dev_priv->ring.map.offset = dev->agp->base + init->offset; |
199 | dev_priv->ring.map.size = init->size; | |
200 | dev_priv->ring.map.type = 0; | |
201 | dev_priv->ring.map.flags = 0; | |
202 | dev_priv->ring.map.mtrr = 0; | |
203 | ||
204 | drm_core_ioremap(&dev_priv->ring.map, dev); | |
205 | ||
206 | if (dev_priv->ring.map.handle == NULL) { | |
207 | via_dma_cleanup(dev); | |
208 | DRM_ERROR("can not ioremap virtual address for" | |
209 | " ring buffer\n"); | |
210 | return DRM_ERR(ENOMEM); | |
211 | } | |
212 | ||
213 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
214 | ||
215 | dev_priv->dma_ptr = dev_priv->ring.virtual_start; | |
216 | dev_priv->dma_low = 0; | |
217 | dev_priv->dma_high = init->size; | |
218 | dev_priv->dma_wrap = init->size; | |
219 | dev_priv->dma_offset = init->offset; | |
220 | dev_priv->last_pause_ptr = NULL; | |
92514243 DA |
221 | dev_priv->hw_addr_ptr = |
222 | (volatile uint32_t *)((char *)dev_priv->mmio->handle + | |
223 | init->reg_pause_addr); | |
22f579c6 DA |
224 | |
225 | via_cmdbuf_start(dev_priv); | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
ce60fe02 | 230 | static int via_dma_init(DRM_IOCTL_ARGS) |
22f579c6 DA |
231 | { |
232 | DRM_DEVICE; | |
233 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
234 | drm_via_dma_init_t init; | |
235 | int retcode = 0; | |
236 | ||
bbaf3641 | 237 | DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data, |
22f579c6 DA |
238 | sizeof(init)); |
239 | ||
240 | switch (init.func) { | |
241 | case VIA_INIT_DMA: | |
92514243 | 242 | if (!DRM_SUSER(DRM_CURPROC)) |
22f579c6 DA |
243 | retcode = DRM_ERR(EPERM); |
244 | else | |
245 | retcode = via_initialize(dev, dev_priv, &init); | |
246 | break; | |
247 | case VIA_CLEANUP_DMA: | |
92514243 | 248 | if (!DRM_SUSER(DRM_CURPROC)) |
22f579c6 DA |
249 | retcode = DRM_ERR(EPERM); |
250 | else | |
251 | retcode = via_dma_cleanup(dev); | |
252 | break; | |
b5e89ed5 DA |
253 | case VIA_DMA_INITIALIZED: |
254 | retcode = (dev_priv->ring.virtual_start != NULL) ? | |
a0a6dd0b | 255 | 0 : DRM_ERR(EFAULT); |
b5e89ed5 | 256 | break; |
22f579c6 DA |
257 | default: |
258 | retcode = DRM_ERR(EINVAL); | |
259 | break; | |
260 | } | |
261 | ||
262 | return retcode; | |
263 | } | |
264 | ||
84b1fd10 | 265 | static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd) |
22f579c6 DA |
266 | { |
267 | drm_via_private_t *dev_priv; | |
268 | uint32_t *vb; | |
269 | int ret; | |
270 | ||
271 | dev_priv = (drm_via_private_t *) dev->dev_private; | |
272 | ||
273 | if (dev_priv->ring.virtual_start == NULL) { | |
274 | DRM_ERROR("%s called without initializing AGP ring buffer.\n", | |
275 | __FUNCTION__); | |
276 | return DRM_ERR(EFAULT); | |
277 | } | |
278 | ||
279 | if (cmd->size > VIA_PCI_BUF_SIZE) { | |
280 | return DRM_ERR(ENOMEM); | |
b5e89ed5 | 281 | } |
22f579c6 DA |
282 | |
283 | if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) | |
284 | return DRM_ERR(EFAULT); | |
285 | ||
286 | /* | |
287 | * Running this function on AGP memory is dead slow. Therefore | |
288 | * we run it on a temporary cacheable system memory buffer and | |
289 | * copy it to AGP memory when ready. | |
290 | */ | |
291 | ||
b5e89ed5 DA |
292 | if ((ret = |
293 | via_verify_command_stream((uint32_t *) dev_priv->pci_buf, | |
294 | cmd->size, dev, 1))) { | |
22f579c6 DA |
295 | return ret; |
296 | } | |
b5e89ed5 | 297 | |
22f579c6 DA |
298 | vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); |
299 | if (vb == NULL) { | |
300 | return DRM_ERR(EAGAIN); | |
301 | } | |
302 | ||
303 | memcpy(vb, dev_priv->pci_buf, cmd->size); | |
b5e89ed5 | 304 | |
22f579c6 DA |
305 | dev_priv->dma_low += cmd->size; |
306 | ||
307 | /* | |
308 | * Small submissions somehow stalls the CPU. (AGP cache effects?) | |
309 | * pad to greater size. | |
310 | */ | |
311 | ||
312 | if (cmd->size < 0x100) | |
b5e89ed5 | 313 | via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3); |
22f579c6 DA |
314 | via_cmdbuf_pause(dev_priv); |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
84b1fd10 | 319 | int via_driver_dma_quiescent(struct drm_device * dev) |
22f579c6 DA |
320 | { |
321 | drm_via_private_t *dev_priv = dev->dev_private; | |
322 | ||
323 | if (!via_wait_idle(dev_priv)) { | |
324 | return DRM_ERR(EBUSY); | |
325 | } | |
326 | return 0; | |
327 | } | |
328 | ||
ce60fe02 | 329 | static int via_flush_ioctl(DRM_IOCTL_ARGS) |
22f579c6 DA |
330 | { |
331 | DRM_DEVICE; | |
332 | ||
b5e89ed5 | 333 | LOCK_TEST_WITH_RETURN(dev, filp); |
22f579c6 DA |
334 | |
335 | return via_driver_dma_quiescent(dev); | |
336 | } | |
337 | ||
ce60fe02 | 338 | static int via_cmdbuffer(DRM_IOCTL_ARGS) |
22f579c6 DA |
339 | { |
340 | DRM_DEVICE; | |
341 | drm_via_cmdbuffer_t cmdbuf; | |
342 | int ret; | |
343 | ||
b5e89ed5 | 344 | LOCK_TEST_WITH_RETURN(dev, filp); |
22f579c6 | 345 | |
bbaf3641 | 346 | DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, |
22f579c6 DA |
347 | sizeof(cmdbuf)); |
348 | ||
349 | DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size); | |
350 | ||
351 | ret = via_dispatch_cmdbuffer(dev, &cmdbuf); | |
352 | if (ret) { | |
353 | return ret; | |
354 | } | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
84b1fd10 | 359 | static int via_dispatch_pci_cmdbuffer(struct drm_device * dev, |
22f579c6 DA |
360 | drm_via_cmdbuffer_t * cmd) |
361 | { | |
362 | drm_via_private_t *dev_priv = dev->dev_private; | |
363 | int ret; | |
364 | ||
365 | if (cmd->size > VIA_PCI_BUF_SIZE) { | |
366 | return DRM_ERR(ENOMEM); | |
b5e89ed5 | 367 | } |
22f579c6 DA |
368 | if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) |
369 | return DRM_ERR(EFAULT); | |
b5e89ed5 DA |
370 | |
371 | if ((ret = | |
372 | via_verify_command_stream((uint32_t *) dev_priv->pci_buf, | |
373 | cmd->size, dev, 0))) { | |
22f579c6 DA |
374 | return ret; |
375 | } | |
b5e89ed5 DA |
376 | |
377 | ret = | |
378 | via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, | |
379 | cmd->size); | |
22f579c6 DA |
380 | return ret; |
381 | } | |
382 | ||
ce60fe02 | 383 | static int via_pci_cmdbuffer(DRM_IOCTL_ARGS) |
22f579c6 DA |
384 | { |
385 | DRM_DEVICE; | |
386 | drm_via_cmdbuffer_t cmdbuf; | |
387 | int ret; | |
388 | ||
b5e89ed5 | 389 | LOCK_TEST_WITH_RETURN(dev, filp); |
22f579c6 | 390 | |
bbaf3641 | 391 | DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, |
22f579c6 DA |
392 | sizeof(cmdbuf)); |
393 | ||
394 | DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf, | |
395 | cmdbuf.size); | |
396 | ||
397 | ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf); | |
398 | if (ret) { | |
399 | return ret; | |
400 | } | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
22f579c6 DA |
405 | static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv, |
406 | uint32_t * vb, int qw_count) | |
407 | { | |
b5e89ed5 | 408 | for (; qw_count > 0; --qw_count) { |
22f579c6 DA |
409 | VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY); |
410 | } | |
411 | return vb; | |
412 | } | |
413 | ||
22f579c6 DA |
414 | /* |
415 | * This function is used internally by ring buffer mangement code. | |
416 | * | |
417 | * Returns virtual pointer to ring buffer. | |
418 | */ | |
419 | static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv) | |
420 | { | |
421 | return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); | |
422 | } | |
423 | ||
424 | /* | |
425 | * Hooks a segment of data into the tail of the ring-buffer by | |
426 | * modifying the pause address stored in the buffer itself. If | |
427 | * the regulator has already paused, restart it. | |
428 | */ | |
b5e89ed5 | 429 | static int via_hook_segment(drm_via_private_t * dev_priv, |
22f579c6 DA |
430 | uint32_t pause_addr_hi, uint32_t pause_addr_lo, |
431 | int no_pci_fire) | |
432 | { | |
433 | int paused, count; | |
434 | volatile uint32_t *paused_at = dev_priv->last_pause_ptr; | |
a0a6dd0b | 435 | uint32_t reader,ptr; |
22f579c6 | 436 | |
a0a6dd0b | 437 | paused = 0; |
22f579c6 | 438 | via_flush_write_combine(); |
ef68d295 TH |
439 | (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1); |
440 | *paused_at = pause_addr_lo; | |
22f579c6 | 441 | via_flush_write_combine(); |
ef68d295 | 442 | (void) *paused_at; |
a0a6dd0b TH |
443 | reader = *(dev_priv->hw_addr_ptr); |
444 | ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) + | |
445 | dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; | |
22f579c6 | 446 | dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; |
22f579c6 | 447 | |
a0a6dd0b TH |
448 | if ((ptr - reader) <= dev_priv->dma_diff ) { |
449 | count = 10000000; | |
450 | while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--); | |
22f579c6 | 451 | } |
b5e89ed5 | 452 | |
22f579c6 | 453 | if (paused && !no_pci_fire) { |
a0a6dd0b TH |
454 | reader = *(dev_priv->hw_addr_ptr); |
455 | if ((ptr - reader) == dev_priv->dma_diff) { | |
22f579c6 | 456 | |
a0a6dd0b TH |
457 | /* |
458 | * There is a concern that these writes may stall the PCI bus | |
459 | * if the GPU is not idle. However, idling the GPU first | |
460 | * doesn't make a difference. | |
461 | */ | |
b5e89ed5 | 462 | |
22f579c6 DA |
463 | VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); |
464 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); | |
465 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); | |
76f62551 | 466 | VIA_READ(VIA_REG_TRANSPACE); |
b5e89ed5 | 467 | } |
22f579c6 DA |
468 | } |
469 | return paused; | |
470 | } | |
471 | ||
22f579c6 DA |
472 | static int via_wait_idle(drm_via_private_t * dev_priv) |
473 | { | |
474 | int count = 10000000; | |
a0a6dd0b TH |
475 | |
476 | while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--); | |
477 | ||
22f579c6 DA |
478 | while (count-- && (VIA_READ(VIA_REG_STATUS) & |
479 | (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | | |
480 | VIA_3D_ENG_BUSY))) ; | |
481 | return count; | |
482 | } | |
483 | ||
484 | static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type, | |
b5e89ed5 DA |
485 | uint32_t addr, uint32_t * cmd_addr_hi, |
486 | uint32_t * cmd_addr_lo, int skip_wait) | |
22f579c6 DA |
487 | { |
488 | uint32_t agp_base; | |
489 | uint32_t cmd_addr, addr_lo, addr_hi; | |
490 | uint32_t *vb; | |
491 | uint32_t qw_pad_count; | |
492 | ||
493 | if (!skip_wait) | |
b5e89ed5 | 494 | via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE); |
22f579c6 DA |
495 | |
496 | vb = via_get_dma(dev_priv); | |
b5e89ed5 DA |
497 | VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) | |
498 | (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16); | |
22f579c6 DA |
499 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
500 | qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) - | |
b5e89ed5 | 501 | ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3); |
22f579c6 | 502 | |
b5e89ed5 DA |
503 | cmd_addr = (addr) ? addr : |
504 | agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3); | |
22f579c6 DA |
505 | addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) | |
506 | (cmd_addr & HC_HAGPBpL_MASK)); | |
507 | addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24)); | |
508 | ||
509 | vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1); | |
b5e89ed5 | 510 | VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo); |
22f579c6 DA |
511 | return vb; |
512 | } | |
513 | ||
22f579c6 DA |
514 | static void via_cmdbuf_start(drm_via_private_t * dev_priv) |
515 | { | |
516 | uint32_t pause_addr_lo, pause_addr_hi; | |
517 | uint32_t start_addr, start_addr_lo; | |
518 | uint32_t end_addr, end_addr_lo; | |
519 | uint32_t command; | |
520 | uint32_t agp_base; | |
a0a6dd0b TH |
521 | uint32_t ptr; |
522 | uint32_t reader; | |
523 | int count; | |
22f579c6 | 524 | |
22f579c6 DA |
525 | dev_priv->dma_low = 0; |
526 | ||
527 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
528 | start_addr = agp_base; | |
529 | end_addr = agp_base + dev_priv->dma_high; | |
530 | ||
531 | start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF)); | |
532 | end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF)); | |
533 | command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) | | |
534 | ((end_addr & 0xff000000) >> 16)); | |
535 | ||
b5e89ed5 DA |
536 | dev_priv->last_pause_ptr = |
537 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, | |
538 | &pause_addr_hi, &pause_addr_lo, 1) - 1; | |
22f579c6 DA |
539 | |
540 | via_flush_write_combine(); | |
ef68d295 | 541 | (void) *(volatile uint32_t *)dev_priv->last_pause_ptr; |
22f579c6 DA |
542 | |
543 | VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); | |
544 | VIA_WRITE(VIA_REG_TRANSPACE, command); | |
545 | VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo); | |
546 | VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo); | |
547 | ||
548 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); | |
549 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); | |
76f62551 | 550 | DRM_WRITEMEMORYBARRIER(); |
22f579c6 | 551 | VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); |
76f62551 | 552 | VIA_READ(VIA_REG_TRANSPACE); |
a0a6dd0b TH |
553 | |
554 | dev_priv->dma_diff = 0; | |
555 | ||
556 | count = 10000000; | |
557 | while (!(VIA_READ(0x41c) & 0x80000000) && count--); | |
558 | ||
559 | reader = *(dev_priv->hw_addr_ptr); | |
560 | ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) + | |
561 | dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; | |
562 | ||
563 | /* | |
564 | * This is the difference between where we tell the | |
565 | * command reader to pause and where it actually pauses. | |
566 | * This differs between hw implementation so we need to | |
567 | * detect it. | |
568 | */ | |
569 | ||
570 | dev_priv->dma_diff = ptr - reader; | |
22f579c6 DA |
571 | } |
572 | ||
b5e89ed5 | 573 | static void via_pad_cache(drm_via_private_t * dev_priv, int qwords) |
22f579c6 DA |
574 | { |
575 | uint32_t *vb; | |
576 | ||
577 | via_cmdbuf_wait(dev_priv, qwords + 2); | |
578 | vb = via_get_dma(dev_priv); | |
b5e89ed5 DA |
579 | VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16); |
580 | via_align_buffer(dev_priv, vb, qwords); | |
22f579c6 DA |
581 | } |
582 | ||
583 | static inline void via_dummy_bitblt(drm_via_private_t * dev_priv) | |
584 | { | |
585 | uint32_t *vb = via_get_dma(dev_priv); | |
586 | SetReg2DAGP(0x0C, (0 | (0 << 16))); | |
587 | SetReg2DAGP(0x10, 0 | (0 << 16)); | |
b5e89ed5 | 588 | SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); |
22f579c6 DA |
589 | } |
590 | ||
22f579c6 DA |
591 | static void via_cmdbuf_jump(drm_via_private_t * dev_priv) |
592 | { | |
593 | uint32_t agp_base; | |
594 | uint32_t pause_addr_lo, pause_addr_hi; | |
595 | uint32_t jump_addr_lo, jump_addr_hi; | |
596 | volatile uint32_t *last_pause_ptr; | |
22f579c6 DA |
597 | |
598 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
b5e89ed5 | 599 | via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, |
22f579c6 | 600 | &jump_addr_lo, 0); |
22f579c6 | 601 | |
b5e89ed5 | 602 | dev_priv->dma_wrap = dev_priv->dma_low; |
22f579c6 DA |
603 | |
604 | /* | |
605 | * Wrap command buffer to the beginning. | |
606 | */ | |
607 | ||
608 | dev_priv->dma_low = 0; | |
609 | if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) { | |
610 | DRM_ERROR("via_cmdbuf_jump failed\n"); | |
611 | } | |
612 | ||
613 | via_dummy_bitblt(dev_priv); | |
b5e89ed5 | 614 | via_dummy_bitblt(dev_priv); |
22f579c6 | 615 | |
b5e89ed5 DA |
616 | last_pause_ptr = |
617 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
618 | &pause_addr_lo, 0) - 1; | |
619 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
22f579c6 DA |
620 | &pause_addr_lo, 0); |
621 | ||
622 | *last_pause_ptr = pause_addr_lo; | |
22f579c6 | 623 | |
a0a6dd0b | 624 | via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0); |
22f579c6 DA |
625 | } |
626 | ||
a0a6dd0b | 627 | |
22f579c6 DA |
628 | static void via_cmdbuf_rewind(drm_via_private_t * dev_priv) |
629 | { | |
b5e89ed5 | 630 | via_cmdbuf_jump(dev_priv); |
22f579c6 DA |
631 | } |
632 | ||
633 | static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type) | |
634 | { | |
635 | uint32_t pause_addr_lo, pause_addr_hi; | |
636 | ||
637 | via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0); | |
b5e89ed5 | 638 | via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); |
22f579c6 DA |
639 | } |
640 | ||
22f579c6 DA |
641 | static void via_cmdbuf_pause(drm_via_private_t * dev_priv) |
642 | { | |
643 | via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE); | |
644 | } | |
645 | ||
646 | static void via_cmdbuf_reset(drm_via_private_t * dev_priv) | |
647 | { | |
648 | via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP); | |
649 | via_wait_idle(dev_priv); | |
650 | } | |
651 | ||
652 | /* | |
653 | * User interface to the space and lag functions. | |
654 | */ | |
655 | ||
ce60fe02 | 656 | static int via_cmdbuf_size(DRM_IOCTL_ARGS) |
22f579c6 DA |
657 | { |
658 | DRM_DEVICE; | |
659 | drm_via_cmdbuf_size_t d_siz; | |
660 | int ret = 0; | |
661 | uint32_t tmp_size, count; | |
662 | drm_via_private_t *dev_priv; | |
663 | ||
664 | DRM_DEBUG("via cmdbuf_size\n"); | |
b5e89ed5 | 665 | LOCK_TEST_WITH_RETURN(dev, filp); |
22f579c6 DA |
666 | |
667 | dev_priv = (drm_via_private_t *) dev->dev_private; | |
668 | ||
669 | if (dev_priv->ring.virtual_start == NULL) { | |
670 | DRM_ERROR("%s called without initializing AGP ring buffer.\n", | |
671 | __FUNCTION__); | |
672 | return DRM_ERR(EFAULT); | |
673 | } | |
674 | ||
bbaf3641 | 675 | DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data, |
22f579c6 DA |
676 | sizeof(d_siz)); |
677 | ||
22f579c6 DA |
678 | count = 1000000; |
679 | tmp_size = d_siz.size; | |
b5e89ed5 | 680 | switch (d_siz.func) { |
22f579c6 | 681 | case VIA_CMDBUF_SPACE: |
b5e89ed5 DA |
682 | while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size) |
683 | && count--) { | |
22f579c6 DA |
684 | if (!d_siz.wait) { |
685 | break; | |
686 | } | |
687 | } | |
688 | if (!count) { | |
689 | DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n"); | |
690 | ret = DRM_ERR(EAGAIN); | |
691 | } | |
692 | break; | |
693 | case VIA_CMDBUF_LAG: | |
b5e89ed5 DA |
694 | while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size) |
695 | && count--) { | |
22f579c6 DA |
696 | if (!d_siz.wait) { |
697 | break; | |
698 | } | |
699 | } | |
700 | if (!count) { | |
701 | DRM_ERROR("VIA_CMDBUF_LAG timed out.\n"); | |
702 | ret = DRM_ERR(EAGAIN); | |
703 | } | |
704 | break; | |
705 | default: | |
706 | ret = DRM_ERR(EFAULT); | |
707 | } | |
708 | d_siz.size = tmp_size; | |
709 | ||
bbaf3641 | 710 | DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz, |
22f579c6 DA |
711 | sizeof(d_siz)); |
712 | return ret; | |
713 | } | |
92514243 DA |
714 | |
715 | drm_ioctl_desc_t via_ioctls[] = { | |
a7a2cc31 DA |
716 | [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH}, |
717 | [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH}, | |
718 | [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER}, | |
719 | [DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, DRM_AUTH|DRM_MASTER}, | |
720 | [DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, DRM_AUTH|DRM_MASTER}, | |
721 | [DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, DRM_AUTH}, | |
722 | [DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, DRM_AUTH}, | |
723 | [DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, DRM_AUTH}, | |
724 | [DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, DRM_AUTH}, | |
725 | [DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, DRM_AUTH}, | |
726 | [DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, DRM_AUTH}, | |
443448d0 DA |
727 | [DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, DRM_AUTH}, |
728 | [DRM_IOCTL_NR(DRM_VIA_DMA_BLIT)] = {via_dma_blit, DRM_AUTH}, | |
729 | [DRM_IOCTL_NR(DRM_VIA_BLIT_SYNC)] = {via_dma_blit_sync, DRM_AUTH} | |
92514243 DA |
730 | }; |
731 | ||
732 | int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls); |