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drm: Replace filp in ioctl arguments with drm_file *file_priv.
[linux-2.6-block.git] / drivers / char / drm / radeon_drv.h
CommitLineData
1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
d6fece05 41#define DRIVER_DATE "20060524"
1da177e4
LT		 42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
b5e89ed5 71 * clients use to tell the DRM where they think the framebuffer is
1da177e4
LT		 72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
d985c108 76 * (No 3D support yet - just microcode loading).
1da177e4
LT		 77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
414ed537 85 * 1.17- Add initial support for R300 (3D).
9d17601c
DA		 86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
ea98a92f 90 * 1.19- Add support for gart table in FB memory and PCIE r300
d985c108
DA		 91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
4e5e2e25 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
d5ea702f 94 * 1.23- Add new radeon memory map work from benh
ee4621f0 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
d6fece05
DA		 96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
f2b04cd2
DA		 98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
ddbee333 100 * 1.28- Add support for VBL on CRTC2
1da177e4
LT		 101 */
102#define DRIVER_MAJOR 1
ddbee333 103#define DRIVER_MINOR 28
1da177e4
LT		 104#define DRIVER_PATCHLEVEL 0
105
1da177e4
LT		 106/*
107 * Radeon chip families
108 */
109enum radeon_family {
110 CHIP_R100,
1da177e4 111 CHIP_RV100,
dfab1154 112 CHIP_RS100,
1da177e4
LT		 113 CHIP_RV200,
114 CHIP_RS200,
dfab1154 115 CHIP_R200,
1da177e4 116 CHIP_RV250,
dfab1154 117 CHIP_RS300,
1da177e4
LT		 118 CHIP_RV280,
119 CHIP_R300,
414ed537 120 CHIP_R350,
1da177e4 121 CHIP_RV350,
dfab1154 122 CHIP_RV380,
414ed537 123 CHIP_R420,
dfab1154
DA		 124 CHIP_RV410,
125 CHIP_RS400,
1da177e4
LT		 126 CHIP_LAST,
127};
128
129enum radeon_cp_microcode_version {
130 UCODE_R100,
131 UCODE_R200,
132 UCODE_R300,
133};
134
135/*
136 * Chip flags
137 */
138enum radeon_chip_flags {
54a56ac5
DA		 139 RADEON_FAMILY_MASK = 0x0000ffffUL,
140 RADEON_FLAGS_MASK = 0xffff0000UL,
141 RADEON_IS_MOBILITY = 0x00010000UL,
142 RADEON_IS_IGP = 0x00020000UL,
143 RADEON_SINGLE_CRTC = 0x00040000UL,
144 RADEON_IS_AGP = 0x00080000UL,
145 RADEON_HAS_HIERZ = 0x00100000UL,
146 RADEON_IS_PCIE = 0x00200000UL,
147 RADEON_NEW_MEMMAP = 0x00400000UL,
148 RADEON_IS_PCI = 0x00800000UL,
f2b04cd2 149 RADEON_IS_IGPGART = 0x01000000UL,
1da177e4
LT		 150};
151
d5ea702f
DA		 152#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
153 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
d985c108
DA		 154#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
155
1da177e4 156typedef struct drm_radeon_freelist {
b5e89ed5 157 unsigned int age;
056219e2 158 struct drm_buf *buf;
b5e89ed5
DA		 159 struct drm_radeon_freelist *next;
160 struct drm_radeon_freelist *prev;
1da177e4
LT		 161} drm_radeon_freelist_t;
162
163typedef struct drm_radeon_ring_buffer {
164 u32 *start;
165 u32 *end;
166 int size;
167 int size_l2qw;
168
169 u32 tail;
170 u32 tail_mask;
171 int space;
172
173 int high_mark;
174} drm_radeon_ring_buffer_t;
175
176typedef struct drm_radeon_depth_clear_t {
177 u32 rb3d_cntl;
178 u32 rb3d_zstencilcntl;
179 u32 se_cntl;
180} drm_radeon_depth_clear_t;
181
182struct drm_radeon_driver_file_fields {
183 int64_t radeon_fb_delta;
184};
185
186struct mem_block {
187 struct mem_block *next;
188 struct mem_block *prev;
189 int start;
190 int size;
6c340eac 191 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 192};
193
194struct radeon_surface {
195 int refcount;
196 u32 lower;
197 u32 upper;
198 u32 flags;
199};
200
201struct radeon_virt_surface {
202 int surface_index;
203 u32 lower;
204 u32 upper;
205 u32 flags;
6c340eac 206 struct drm_file *file_priv;
1da177e4
LT		 207};
208
209typedef struct drm_radeon_private {
210 drm_radeon_ring_buffer_t ring;
211 drm_radeon_sarea_t *sarea_priv;
212
213 u32 fb_location;
d5ea702f
DA		 214 u32 fb_size;
215 int new_memmap;
1da177e4
LT		 216
217 int gart_size;
218 u32 gart_vm_start;
219 unsigned long gart_buffers_offset;
220
221 int cp_mode;
222 int cp_running;
223
b5e89ed5
DA		 224 drm_radeon_freelist_t *head;
225 drm_radeon_freelist_t *tail;
1da177e4
LT		 226 int last_buf;
227 volatile u32 *scratch;
228 int writeback_works;
229
230 int usec_timeout;
231
232 int microcode_version;
233
1da177e4
LT		 234 struct {
235 u32 boxes;
236 int freelist_timeouts;
237 int freelist_loops;
238 int requested_bufs;
239 int last_frame_reads;
240 int last_clear_reads;
241 int clears;
242 int texture_uploads;
243 } stats;
244
245 int do_boxes;
246 int page_flipping;
1da177e4
LT		 247
248 u32 color_fmt;
249 unsigned int front_offset;
250 unsigned int front_pitch;
251 unsigned int back_offset;
252 unsigned int back_pitch;
253
254 u32 depth_fmt;
255 unsigned int depth_offset;
256 unsigned int depth_pitch;
257
258 u32 front_pitch_offset;
259 u32 back_pitch_offset;
260 u32 depth_pitch_offset;
261
262 drm_radeon_depth_clear_t depth_clear;
b5e89ed5 263
1da177e4
LT		 264 unsigned long ring_offset;
265 unsigned long ring_rptr_offset;
266 unsigned long buffers_offset;
267 unsigned long gart_textures_offset;
268
269 drm_local_map_t *sarea;
270 drm_local_map_t *mmio;
271 drm_local_map_t *cp_ring;
272 drm_local_map_t *ring_rptr;
273 drm_local_map_t *gart_textures;
274
275 struct mem_block *gart_heap;
276 struct mem_block *fb_heap;
277
278 /* SW interrupt */
b5e89ed5
DA		 279 wait_queue_head_t swi_queue;
280 atomic_t swi_emitted;
ddbee333
DA		 281 int vblank_crtc;
282 uint32_t irq_enable_reg;
283 int irq_enabled;
1da177e4
LT		 284
285 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
b5e89ed5 286 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
1da177e4 287
b5e89ed5 288 unsigned long pcigart_offset;
f2b04cd2 289 unsigned int pcigart_offset_set;
55910517 290 struct drm_ati_pcigart_info gart_info;
ea98a92f 291
ee4621f0
DA		 292 u32 scratch_ages[5];
293
1da177e4
LT		 294 /* starting from here on, data is preserved accross an open */
295 uint32_t flags; /* see radeon_chip_flags */
296} drm_radeon_private_t;
297
298typedef struct drm_radeon_buf_priv {
299 u32 age;
300} drm_radeon_buf_priv_t;
301
b3a83639
DA		 302typedef struct drm_radeon_kcmd_buffer {
303 int bufsz;
304 char *buf;
305 int nbox;
c60ce623 306 struct drm_clip_rect __user *boxes;
b3a83639
DA		 307} drm_radeon_kcmd_buffer_t;
308
689b9d74 309extern int radeon_no_wb;
b3a83639
DA		 310extern drm_ioctl_desc_t radeon_ioctls[];
311extern int radeon_max_ioctl;
312
1d6bb8e5
MCA		 313/* Check whether the given hardware address is inside the framebuffer or the
314 * GART area.
315 */
316static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
317 u64 off)
318{
319 u32 fb_start = dev_priv->fb_location;
320 u32 fb_end = fb_start + dev_priv->fb_size - 1;
321 u32 gart_start = dev_priv->gart_vm_start;
322 u32 gart_end = gart_start + dev_priv->gart_size - 1;
323
324 return ((off >= fb_start && off <= fb_end) ||
325 (off >= gart_start && off <= gart_end));
326}
327
1da177e4 328 /* radeon_cp.c */
b5e89ed5
DA		 329extern int radeon_cp_init(DRM_IOCTL_ARGS);
330extern int radeon_cp_start(DRM_IOCTL_ARGS);
331extern int radeon_cp_stop(DRM_IOCTL_ARGS);
332extern int radeon_cp_reset(DRM_IOCTL_ARGS);
333extern int radeon_cp_idle(DRM_IOCTL_ARGS);
334extern int radeon_cp_resume(DRM_IOCTL_ARGS);
335extern int radeon_engine_reset(DRM_IOCTL_ARGS);
336extern int radeon_fullscreen(DRM_IOCTL_ARGS);
337extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
1da177e4 338
84b1fd10 339extern void radeon_freelist_reset(struct drm_device * dev);
056219e2 340extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
1da177e4 341
b5e89ed5 342extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
1da177e4 343
b5e89ed5 344extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
1da177e4
LT		 345
346extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 347extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 348extern int radeon_driver_postcleanup(struct drm_device *dev);
349
b5e89ed5
DA		 350extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
351extern int radeon_mem_free(DRM_IOCTL_ARGS);
352extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
353extern void radeon_mem_takedown(struct mem_block **heap);
6c340eac
EA		 354extern void radeon_mem_release(struct drm_file *file_priv,
355 struct mem_block *heap);
1da177e4
LT		 356
357 /* radeon_irq.c */
b5e89ed5
DA		 358extern int radeon_irq_emit(DRM_IOCTL_ARGS);
359extern int radeon_irq_wait(DRM_IOCTL_ARGS);
360
84b1fd10
DA		 361extern void radeon_do_release(struct drm_device * dev);
362extern int radeon_driver_vblank_wait(struct drm_device * dev,
b5e89ed5 363 unsigned int *sequence);
84b1fd10 364extern int radeon_driver_vblank_wait2(struct drm_device * dev,
ddbee333 365 unsigned int *sequence);
b5e89ed5 366extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10
DA		 367extern void radeon_driver_irq_preinstall(struct drm_device * dev);
368extern void radeon_driver_irq_postinstall(struct drm_device * dev);
369extern void radeon_driver_irq_uninstall(struct drm_device * dev);
370extern int radeon_vblank_crtc_get(struct drm_device *dev);
371extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
1da177e4 372
22eae947
DA		 373extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
374extern int radeon_driver_unload(struct drm_device *dev);
375extern int radeon_driver_firstopen(struct drm_device *dev);
6c340eac 376extern void radeon_driver_preclose(struct drm_device * dev, struct drm_file *file_priv);
84b1fd10
DA		 377extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp);
378extern void radeon_driver_lastclose(struct drm_device * dev);
379extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv);
9a186645
DA		 380extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
381 unsigned long arg);
382
414ed537
DA		 383/* r300_cmdbuf.c */
384extern void r300_init_reg_flags(void);
385
6c340eac
EA		 386extern int r300_do_cp_cmdbuf(struct drm_device * dev,
387 struct drm_file *file_priv,
b3a83639 388 drm_radeon_kcmd_buffer_t * cmdbuf);
414ed537 389
1da177e4
LT		 390/* Flags for stats.boxes
391 */
392#define RADEON_BOX_DMA_IDLE 0x1
393#define RADEON_BOX_RING_FULL 0x2
394#define RADEON_BOX_FLIP 0x4
395#define RADEON_BOX_WAIT_IDLE 0x8
396#define RADEON_BOX_TEXTURE_LOAD 0x10
397
1da177e4
LT		 398/* Register definitions, register access macros and drmAddMap constants
399 * for Radeon kernel driver.
400 */
401
402#define RADEON_AGP_COMMAND 0x0f60
d985c108
DA		 403#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
404# define RADEON_AGP_ENABLE (1<<8)
1da177e4
LT		 405#define RADEON_AUX_SCISSOR_CNTL 0x26f0
406# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
407# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
408# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
409# define RADEON_SCISSOR_0_ENABLE (1 << 28)
410# define RADEON_SCISSOR_1_ENABLE (1 << 29)
411# define RADEON_SCISSOR_2_ENABLE (1 << 30)
412
413#define RADEON_BUS_CNTL 0x0030
414# define RADEON_BUS_MASTER_DIS (1 << 6)
415
416#define RADEON_CLOCK_CNTL_DATA 0x000c
417# define RADEON_PLL_WR_EN (1 << 7)
418#define RADEON_CLOCK_CNTL_INDEX 0x0008
419#define RADEON_CONFIG_APER_SIZE 0x0108
d985c108 420#define RADEON_CONFIG_MEMSIZE 0x00f8
1da177e4
LT		 421#define RADEON_CRTC_OFFSET 0x0224
422#define RADEON_CRTC_OFFSET_CNTL 0x0228
423# define RADEON_CRTC_TILE_EN (1 << 15)
424# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
425#define RADEON_CRTC2_OFFSET 0x0324
426#define RADEON_CRTC2_OFFSET_CNTL 0x0328
427
ea98a92f
DA		 428#define RADEON_PCIE_INDEX 0x0030
429#define RADEON_PCIE_DATA 0x0034
430#define RADEON_PCIE_TX_GART_CNTL 0x10
431# define RADEON_PCIE_TX_GART_EN (1 << 0)
432# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
433# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
434# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
435# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
436# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
437# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
438# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
439#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
440#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
441#define RADEON_PCIE_TX_GART_BASE 0x13
442#define RADEON_PCIE_TX_GART_START_LO 0x14
443#define RADEON_PCIE_TX_GART_START_HI 0x15
444#define RADEON_PCIE_TX_GART_END_LO 0x16
445#define RADEON_PCIE_TX_GART_END_HI 0x17
446
f2b04cd2
DA		 447#define RADEON_IGPGART_INDEX 0x168
448#define RADEON_IGPGART_DATA 0x16c
449#define RADEON_IGPGART_UNK_18 0x18
450#define RADEON_IGPGART_CTRL 0x2b
451#define RADEON_IGPGART_BASE_ADDR 0x2c
452#define RADEON_IGPGART_FLUSH 0x2e
453#define RADEON_IGPGART_ENABLE 0x38
454#define RADEON_IGPGART_UNK_39 0x39
455
414ed537
DA		 456#define RADEON_MPP_TB_CONFIG 0x01c0
457#define RADEON_MEM_CNTL 0x0140
458#define RADEON_MEM_SDRAM_MODE_REG 0x0158
459#define RADEON_AGP_BASE 0x0170
460
1da177e4
LT		 461#define RADEON_RB3D_COLOROFFSET 0x1c40
462#define RADEON_RB3D_COLORPITCH 0x1c48
463
3e14a286
MD		 464#define RADEON_SRC_X_Y 0x1590
465
1da177e4
LT		 466#define RADEON_DP_GUI_MASTER_CNTL 0x146c
467# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
468# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
469# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
470# define RADEON_GMC_BRUSH_NONE (15 << 4)
471# define RADEON_GMC_DST_16BPP (4 << 8)
472# define RADEON_GMC_DST_24BPP (5 << 8)
473# define RADEON_GMC_DST_32BPP (6 << 8)
474# define RADEON_GMC_DST_DATATYPE_SHIFT 8
475# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
476# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
477# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
478# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
479# define RADEON_GMC_WR_MSK_DIS (1 << 30)
480# define RADEON_ROP3_S 0x00cc0000
481# define RADEON_ROP3_P 0x00f00000
482#define RADEON_DP_WRITE_MASK 0x16cc
3e14a286 483#define RADEON_SRC_PITCH_OFFSET 0x1428
1da177e4
LT		 484#define RADEON_DST_PITCH_OFFSET 0x142c
485#define RADEON_DST_PITCH_OFFSET_C 0x1c80
486# define RADEON_DST_TILE_LINEAR (0 << 30)
487# define RADEON_DST_TILE_MACRO (1 << 30)
488# define RADEON_DST_TILE_MICRO (2 << 30)
489# define RADEON_DST_TILE_BOTH (3 << 30)
490
491#define RADEON_SCRATCH_REG0 0x15e0
492#define RADEON_SCRATCH_REG1 0x15e4
493#define RADEON_SCRATCH_REG2 0x15e8
494#define RADEON_SCRATCH_REG3 0x15ec
495#define RADEON_SCRATCH_REG4 0x15f0
496#define RADEON_SCRATCH_REG5 0x15f4
497#define RADEON_SCRATCH_UMSK 0x0770
498#define RADEON_SCRATCH_ADDR 0x0774
499
500#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
501
502#define GET_SCRATCH( x ) (dev_priv->writeback_works \
503 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
504 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
505
1da177e4
LT		 506#define RADEON_GEN_INT_CNTL 0x0040
507# define RADEON_CRTC_VBLANK_MASK (1 << 0)
ddbee333 508# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
1da177e4
LT		 509# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
510# define RADEON_SW_INT_ENABLE (1 << 25)
511
512#define RADEON_GEN_INT_STATUS 0x0044
513# define RADEON_CRTC_VBLANK_STAT (1 << 0)
514# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
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DA		 515# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
516# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
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LT		 517# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
518# define RADEON_SW_INT_TEST (1 << 25)
519# define RADEON_SW_INT_TEST_ACK (1 << 25)
520# define RADEON_SW_INT_FIRE (1 << 26)
521
522#define RADEON_HOST_PATH_CNTL 0x0130
523# define RADEON_HDP_SOFT_RESET (1 << 26)
524# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
525# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
526
527#define RADEON_ISYNC_CNTL 0x1724
528# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
529# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
530# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
531# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
532# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
533# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
534
535#define RADEON_RBBM_GUICNTL 0x172c
536# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
537# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
538# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
539# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
540
541#define RADEON_MC_AGP_LOCATION 0x014c
542#define RADEON_MC_FB_LOCATION 0x0148
543#define RADEON_MCLK_CNTL 0x0012
544# define RADEON_FORCEON_MCLKA (1 << 16)
545# define RADEON_FORCEON_MCLKB (1 << 17)
546# define RADEON_FORCEON_YCLKA (1 << 18)
547# define RADEON_FORCEON_YCLKB (1 << 19)
548# define RADEON_FORCEON_MC (1 << 20)
549# define RADEON_FORCEON_AIC (1 << 21)
550
551#define RADEON_PP_BORDER_COLOR_0 0x1d40
552#define RADEON_PP_BORDER_COLOR_1 0x1d44
553#define RADEON_PP_BORDER_COLOR_2 0x1d48
554#define RADEON_PP_CNTL 0x1c38
555# define RADEON_SCISSOR_ENABLE (1 << 1)
556#define RADEON_PP_LUM_MATRIX 0x1d00
557#define RADEON_PP_MISC 0x1c14
558#define RADEON_PP_ROT_MATRIX_0 0x1d58
559#define RADEON_PP_TXFILTER_0 0x1c54
560#define RADEON_PP_TXOFFSET_0 0x1c5c
561#define RADEON_PP_TXFILTER_1 0x1c6c
562#define RADEON_PP_TXFILTER_2 0x1c84
563
564#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
565# define RADEON_RB2D_DC_FLUSH (3 << 0)
566# define RADEON_RB2D_DC_FREE (3 << 2)
567# define RADEON_RB2D_DC_FLUSH_ALL 0xf
568# define RADEON_RB2D_DC_BUSY (1 << 31)
569#define RADEON_RB3D_CNTL 0x1c3c
570# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
571# define RADEON_PLANE_MASK_ENABLE (1 << 1)
572# define RADEON_DITHER_ENABLE (1 << 2)
573# define RADEON_ROUND_ENABLE (1 << 3)
574# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
575# define RADEON_DITHER_INIT (1 << 5)
576# define RADEON_ROP_ENABLE (1 << 6)
577# define RADEON_STENCIL_ENABLE (1 << 7)
578# define RADEON_Z_ENABLE (1 << 8)
579# define RADEON_ZBLOCK16 (1 << 15)
580#define RADEON_RB3D_DEPTHOFFSET 0x1c24
581#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
582#define RADEON_RB3D_DEPTHPITCH 0x1c28
583#define RADEON_RB3D_PLANEMASK 0x1d84
584#define RADEON_RB3D_STENCILREFMASK 0x1d7c
585#define RADEON_RB3D_ZCACHE_MODE 0x3250
586#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
587# define RADEON_RB3D_ZC_FLUSH (1 << 0)
588# define RADEON_RB3D_ZC_FREE (1 << 2)
589# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
590# define RADEON_RB3D_ZC_BUSY (1 << 31)
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MD		 591#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
592# define RADEON_RB3D_DC_FLUSH (3 << 0)
593# define RADEON_RB3D_DC_FREE (3 << 2)
594# define RADEON_RB3D_DC_FLUSH_ALL 0xf
595# define RADEON_RB3D_DC_BUSY (1 << 31)
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LT		 596#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
597# define RADEON_Z_TEST_MASK (7 << 4)
598# define RADEON_Z_TEST_ALWAYS (7 << 4)
599# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
600# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
601# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
602# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
603# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
604# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
605# define RADEON_FORCE_Z_DIRTY (1 << 29)
606# define RADEON_Z_WRITE_ENABLE (1 << 30)
607# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
608#define RADEON_RBBM_SOFT_RESET 0x00f0
609# define RADEON_SOFT_RESET_CP (1 << 0)
610# define RADEON_SOFT_RESET_HI (1 << 1)
611# define RADEON_SOFT_RESET_SE (1 << 2)
612# define RADEON_SOFT_RESET_RE (1 << 3)
613# define RADEON_SOFT_RESET_PP (1 << 4)
614# define RADEON_SOFT_RESET_E2 (1 << 5)
615# define RADEON_SOFT_RESET_RB (1 << 6)
616# define RADEON_SOFT_RESET_HDP (1 << 7)
617#define RADEON_RBBM_STATUS 0x0e40
618# define RADEON_RBBM_FIFOCNT_MASK 0x007f
619# define RADEON_RBBM_ACTIVE (1 << 31)
620#define RADEON_RE_LINE_PATTERN 0x1cd0
621#define RADEON_RE_MISC 0x26c4
622#define RADEON_RE_TOP_LEFT 0x26c0
623#define RADEON_RE_WIDTH_HEIGHT 0x1c44
624#define RADEON_RE_STIPPLE_ADDR 0x1cc8
625#define RADEON_RE_STIPPLE_DATA 0x1ccc
626
627#define RADEON_SCISSOR_TL_0 0x1cd8
628#define RADEON_SCISSOR_BR_0 0x1cdc
629#define RADEON_SCISSOR_TL_1 0x1ce0
630#define RADEON_SCISSOR_BR_1 0x1ce4
631#define RADEON_SCISSOR_TL_2 0x1ce8
632#define RADEON_SCISSOR_BR_2 0x1cec
633#define RADEON_SE_COORD_FMT 0x1c50
634#define RADEON_SE_CNTL 0x1c4c
635# define RADEON_FFACE_CULL_CW (0 << 0)
636# define RADEON_BFACE_SOLID (3 << 1)
637# define RADEON_FFACE_SOLID (3 << 3)
638# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
639# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
640# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
641# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
642# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
643# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
644# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
645# define RADEON_FOG_SHADE_FLAT (1 << 14)
646# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
647# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
648# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
649# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
650# define RADEON_ROUND_MODE_TRUNC (0 << 28)
651# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
652#define RADEON_SE_CNTL_STATUS 0x2140
653#define RADEON_SE_LINE_WIDTH 0x1db8
654#define RADEON_SE_VPORT_XSCALE 0x1d98
655#define RADEON_SE_ZBIAS_FACTOR 0x1db0
656#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
657#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
658#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
659# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
660# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
661#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
662#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
663# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
664#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
665#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
666#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
667#define RADEON_SURFACE_CNTL 0x0b00
668# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
669# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
670# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
671# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
672# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
673# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
674# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
675# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
676# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
677#define RADEON_SURFACE0_INFO 0x0b0c
678# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
679# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
680# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
681# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
682# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
683# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
684#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
685#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
686# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
687#define RADEON_SURFACE1_INFO 0x0b1c
688#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
689#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
690#define RADEON_SURFACE2_INFO 0x0b2c
691#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
692#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
693#define RADEON_SURFACE3_INFO 0x0b3c
694#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
695#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
696#define RADEON_SURFACE4_INFO 0x0b4c
697#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
698#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
699#define RADEON_SURFACE5_INFO 0x0b5c
700#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
701#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
702#define RADEON_SURFACE6_INFO 0x0b6c
703#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
704#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
705#define RADEON_SURFACE7_INFO 0x0b7c
706#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
707#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
708#define RADEON_SW_SEMAPHORE 0x013c
709
710#define RADEON_WAIT_UNTIL 0x1720
711# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
d985c108
DA		 712# define RADEON_WAIT_2D_IDLE (1 << 14)
713# define RADEON_WAIT_3D_IDLE (1 << 15)
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LT		 714# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
715# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
716# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
717
718#define RADEON_RB3D_ZMASKOFFSET 0x3234
719#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
720# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
721# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
722
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LT		 723/* CP registers */
724#define RADEON_CP_ME_RAM_ADDR 0x07d4
725#define RADEON_CP_ME_RAM_RADDR 0x07d8
726#define RADEON_CP_ME_RAM_DATAH 0x07dc
727#define RADEON_CP_ME_RAM_DATAL 0x07e0
728
729#define RADEON_CP_RB_BASE 0x0700
730#define RADEON_CP_RB_CNTL 0x0704
731# define RADEON_BUF_SWAP_32BIT (2 << 16)
ae1b1a48 732# define RADEON_RB_NO_UPDATE (1 << 27)
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LT		 733#define RADEON_CP_RB_RPTR_ADDR 0x070c
734#define RADEON_CP_RB_RPTR 0x0710
735#define RADEON_CP_RB_WPTR 0x0714
736
737#define RADEON_CP_RB_WPTR_DELAY 0x0718
738# define RADEON_PRE_WRITE_TIMER_SHIFT 0
739# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
740
741#define RADEON_CP_IB_BASE 0x0738
742
743#define RADEON_CP_CSQ_CNTL 0x0740
744# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
745# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
746# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
747# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
748# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
749# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
750# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
751
752#define RADEON_AIC_CNTL 0x01d0
753# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
754#define RADEON_AIC_STAT 0x01d4
755#define RADEON_AIC_PT_BASE 0x01d8
756#define RADEON_AIC_LO_ADDR 0x01dc
757#define RADEON_AIC_HI_ADDR 0x01e0
758#define RADEON_AIC_TLB_ADDR 0x01e4
759#define RADEON_AIC_TLB_DATA 0x01e8
760
761/* CP command packets */
762#define RADEON_CP_PACKET0 0x00000000
763# define RADEON_ONE_REG_WR (1 << 15)
764#define RADEON_CP_PACKET1 0x40000000
765#define RADEON_CP_PACKET2 0x80000000
766#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 767# define RADEON_CP_NOP 0x00001000
768# define RADEON_CP_NEXT_CHAR 0x00001900
769# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
770# define RADEON_CP_SET_SCISSORS 0x00001E00
b5e89ed5 771 /* GEN_INDX_PRIM is unsupported starting with R300 */
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LT		 772# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
773# define RADEON_WAIT_FOR_IDLE 0x00002600
774# define RADEON_3D_DRAW_VBUF 0x00002800
775# define RADEON_3D_DRAW_IMMD 0x00002900
776# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 777# define RADEON_CP_LOAD_PALETTE 0x00002C00
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LT		 778# define RADEON_3D_LOAD_VBPNTR 0x00002F00
779# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
780# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
781# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 782# define RADEON_CP_INDX_BUFFER 0x00003300
783# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
784# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
785# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 786# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 787# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
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LT		 788# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
789# define RADEON_CNTL_PAINT_MULTI 0x00009A00
790# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
791# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
792
793#define RADEON_CP_PACKET_MASK 0xC0000000
794#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
795#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
796#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
797#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
798
799#define RADEON_VTX_Z_PRESENT (1 << 31)
800#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
801
802#define RADEON_PRIM_TYPE_NONE (0 << 0)
803#define RADEON_PRIM_TYPE_POINT (1 << 0)
804#define RADEON_PRIM_TYPE_LINE (2 << 0)
805#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
806#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
807#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
808#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
809#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
810#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
811#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
812#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
813#define RADEON_PRIM_TYPE_MASK 0xf
814#define RADEON_PRIM_WALK_IND (1 << 4)
815#define RADEON_PRIM_WALK_LIST (2 << 4)
816#define RADEON_PRIM_WALK_RING (3 << 4)
817#define RADEON_COLOR_ORDER_BGRA (0 << 6)
818#define RADEON_COLOR_ORDER_RGBA (1 << 6)
819#define RADEON_MAOS_ENABLE (1 << 7)
820#define RADEON_VTX_FMT_R128_MODE (0 << 8)
821#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
822#define RADEON_NUM_VERTICES_SHIFT 16
823
824#define RADEON_COLOR_FORMAT_CI8 2
825#define RADEON_COLOR_FORMAT_ARGB1555 3
826#define RADEON_COLOR_FORMAT_RGB565 4
827#define RADEON_COLOR_FORMAT_ARGB8888 6
828#define RADEON_COLOR_FORMAT_RGB332 7
829#define RADEON_COLOR_FORMAT_RGB8 9
830#define RADEON_COLOR_FORMAT_ARGB4444 15
831
832#define RADEON_TXFORMAT_I8 0
833#define RADEON_TXFORMAT_AI88 1
834#define RADEON_TXFORMAT_RGB332 2
835#define RADEON_TXFORMAT_ARGB1555 3
836#define RADEON_TXFORMAT_RGB565 4
837#define RADEON_TXFORMAT_ARGB4444 5
838#define RADEON_TXFORMAT_ARGB8888 6
839#define RADEON_TXFORMAT_RGBA8888 7
840#define RADEON_TXFORMAT_Y8 8
841#define RADEON_TXFORMAT_VYUY422 10
842#define RADEON_TXFORMAT_YVYU422 11
843#define RADEON_TXFORMAT_DXT1 12
844#define RADEON_TXFORMAT_DXT23 14
845#define RADEON_TXFORMAT_DXT45 15
846
847#define R200_PP_TXCBLEND_0 0x2f00
848#define R200_PP_TXCBLEND_1 0x2f10
849#define R200_PP_TXCBLEND_2 0x2f20
850#define R200_PP_TXCBLEND_3 0x2f30
851#define R200_PP_TXCBLEND_4 0x2f40
852#define R200_PP_TXCBLEND_5 0x2f50
853#define R200_PP_TXCBLEND_6 0x2f60
854#define R200_PP_TXCBLEND_7 0x2f70
b5e89ed5 855#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
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LT		 856#define R200_PP_TFACTOR_0 0x2ee0
857#define R200_SE_VTX_FMT_0 0x2088
858#define R200_SE_VAP_CNTL 0x2080
859#define R200_SE_TCL_MATRIX_SEL_0 0x2230
b5e89ed5
DA		 860#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
861#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
862#define R200_PP_TXFILTER_5 0x2ca0
863#define R200_PP_TXFILTER_4 0x2c80
864#define R200_PP_TXFILTER_3 0x2c60
865#define R200_PP_TXFILTER_2 0x2c40
866#define R200_PP_TXFILTER_1 0x2c20
867#define R200_PP_TXFILTER_0 0x2c00
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LT		 868#define R200_PP_TXOFFSET_5 0x2d78
869#define R200_PP_TXOFFSET_4 0x2d60
870#define R200_PP_TXOFFSET_3 0x2d48
871#define R200_PP_TXOFFSET_2 0x2d30
872#define R200_PP_TXOFFSET_1 0x2d18
873#define R200_PP_TXOFFSET_0 0x2d00
874
875#define R200_PP_CUBIC_FACES_0 0x2c18
876#define R200_PP_CUBIC_FACES_1 0x2c38
877#define R200_PP_CUBIC_FACES_2 0x2c58
878#define R200_PP_CUBIC_FACES_3 0x2c78
879#define R200_PP_CUBIC_FACES_4 0x2c98
880#define R200_PP_CUBIC_FACES_5 0x2cb8
881#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
882#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
883#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
884#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
885#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
886#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
887#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
888#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
889#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
890#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
891#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
892#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
893#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
894#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
895#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
896#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
897#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
898#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
899#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
900#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
901#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
902#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
903#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
904#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
905#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
906#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
907#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
908#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
909#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
910#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
911
912#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
913#define R200_SE_VTE_CNTL 0x20b0
914#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
915#define R200_PP_TAM_DEBUG3 0x2d9c
916#define R200_PP_CNTL_X 0x2cc4
917#define R200_SE_VAP_CNTL_STATUS 0x2140
918#define R200_RE_SCISSOR_TL_0 0x1cd8
919#define R200_RE_SCISSOR_TL_1 0x1ce0
920#define R200_RE_SCISSOR_TL_2 0x1ce8
b5e89ed5 921#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1da177e4
LT		 922#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
923#define R200_SE_VTX_STATE_CNTL 0x2180
924#define R200_RE_POINTSIZE 0x2648
925#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
926
b5e89ed5 927#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1da177e4
LT		 928#define RADEON_PP_TEX_SIZE_1 0x1d0c
929#define RADEON_PP_TEX_SIZE_2 0x1d14
930
931#define RADEON_PP_CUBIC_FACES_0 0x1d24
932#define RADEON_PP_CUBIC_FACES_1 0x1d28
933#define RADEON_PP_CUBIC_FACES_2 0x1d2c
934#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
935#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
936#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
937
f2a2279f
DA		 938#define RADEON_SE_TCL_STATE_FLUSH 0x2284
939
1da177e4
LT		 940#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
941#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
942#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
943#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
944#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
945#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
946#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
947#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
948#define R200_3D_DRAW_IMMD_2 0xC0003500
949#define R200_SE_VTX_FMT_1 0x208c
b5e89ed5 950#define R200_RE_CNTL 0x1c50
1da177e4
LT		 951
952#define R200_RB3D_BLENDCOLOR 0x3218
953
954#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
955
956#define R200_PP_TRI_PERF 0x2cf8
957
9d17601c 958#define R200_PP_AFS_0 0x2f80
b5e89ed5 959#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
9d17601c 960
d6fece05
DA		 961#define R200_VAP_PVS_CNTL_1 0x22D0
962
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LT		 963/* Constants */
964#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
965
966#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
967#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
968#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
969#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
970#define RADEON_LAST_DISPATCH 1
971
972#define RADEON_MAX_VB_AGE 0x7fffffff
973#define RADEON_MAX_VB_VERTS (0xffff)
974
975#define RADEON_RING_HIGH_MARK 128
976
ea98a92f
DA		 977#define RADEON_PCIGART_TABLE_SIZE (32*1024)
978
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LT		 979#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
980#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
981#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
982#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
983
984#define RADEON_WRITE_PLL( addr, val ) \
985do { \
986 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
987 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
988 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
989} while (0)
990
f2b04cd2
DA		 991#define RADEON_WRITE_IGPGART( addr, val ) \
992do { \
993 RADEON_WRITE( RADEON_IGPGART_INDEX, \
994 ((addr) & 0x7f) | (1 << 8)); \
995 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
996 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
997} while (0)
998
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DA		 999#define RADEON_WRITE_PCIE( addr, val ) \
1000do { \
1001 RADEON_WRITE8( RADEON_PCIE_INDEX, \
1002 ((addr) & 0xff)); \
1003 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
1004} while (0)
1005
1da177e4
LT		 1006#define CP_PACKET0( reg, n ) \
1007 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1008#define CP_PACKET0_TABLE( reg, n ) \
1009 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1010#define CP_PACKET1( reg0, reg1 ) \
1011 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1012#define CP_PACKET2() \
1013 (RADEON_CP_PACKET2)
1014#define CP_PACKET3( pkt, n ) \
1015 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1016
1da177e4
LT		 1017/* ================================================================
1018 * Engine control helper macros
1019 */
1020
1021#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1022 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1023 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1024 RADEON_WAIT_HOST_IDLECLEAN) ); \
1025} while (0)
1026
1027#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1028 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1029 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1030 RADEON_WAIT_HOST_IDLECLEAN) ); \
1031} while (0)
1032
1033#define RADEON_WAIT_UNTIL_IDLE() do { \
1034 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1035 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1036 RADEON_WAIT_3D_IDLECLEAN | \
1037 RADEON_WAIT_HOST_IDLECLEAN) ); \
1038} while (0)
1039
1040#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1041 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1042 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1043} while (0)
1044
1045#define RADEON_FLUSH_CACHE() do { \
b9b603dd 1046 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
b15ec368 1047 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1da177e4
LT		 1048} while (0)
1049
1050#define RADEON_PURGE_CACHE() do { \
b9b603dd 1051 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
b15ec368 1052 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1da177e4
LT		 1053} while (0)
1054
1055#define RADEON_FLUSH_ZCACHE() do { \
1056 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1057 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1058} while (0)
1059
1060#define RADEON_PURGE_ZCACHE() do { \
1061 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1062 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1063} while (0)
1064
1da177e4
LT		 1065/* ================================================================
1066 * Misc helper macros
1067 */
1068
b5e89ed5 1069/* Perfbox functionality only.
1da177e4
LT		 1070 */
1071#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1072do { \
1073 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1074 u32 head = GET_RING_HEAD( dev_priv ); \
1075 if (head == dev_priv->ring.tail) \
1076 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1077 } \
1078} while (0)
1079
1080#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1081do { \
1082 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1083 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1084 int __ret = radeon_do_cp_idle( dev_priv ); \
1085 if ( __ret ) return __ret; \
1086 sarea_priv->last_dispatch = 0; \
1087 radeon_freelist_reset( dev ); \
1088 } \
1089} while (0)
1090
1091#define RADEON_DISPATCH_AGE( age ) do { \
1092 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1093 OUT_RING( age ); \
1094} while (0)
1095
1096#define RADEON_FRAME_AGE( age ) do { \
1097 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1098 OUT_RING( age ); \
1099} while (0)
1100
1101#define RADEON_CLEAR_AGE( age ) do { \
1102 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1103 OUT_RING( age ); \
1104} while (0)
1105
1da177e4
LT		 1106/* ================================================================
1107 * Ring control
1108 */
1109
1110#define RADEON_VERBOSE 0
1111
1112#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1113
1114#define BEGIN_RING( n ) do { \
1115 if ( RADEON_VERBOSE ) { \
1116 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1117 n, __FUNCTION__ ); \
1118 } \
1119 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1120 COMMIT_RING(); \
1121 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1122 } \
1123 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1124 ring = dev_priv->ring.start; \
1125 write = dev_priv->ring.tail; \
1126 mask = dev_priv->ring.tail_mask; \
1127} while (0)
1128
1129#define ADVANCE_RING() do { \
1130 if ( RADEON_VERBOSE ) { \
1131 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1132 write, dev_priv->ring.tail ); \
1133 } \
1134 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1135 DRM_ERROR( \
1136 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1137 ((dev_priv->ring.tail + _nr) & mask), \
1138 write, __LINE__); \
1139 } else \
1140 dev_priv->ring.tail = write; \
1141} while (0)
1142
1143#define COMMIT_RING() do { \
1144 /* Flush writes to ring */ \
1145 DRM_MEMORYBARRIER(); \
1146 GET_RING_HEAD( dev_priv ); \
1147 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1148 /* read from PCI bus to ensure correct posting */ \
1149 RADEON_READ( RADEON_CP_RB_RPTR ); \
1150} while (0)
1151
1152#define OUT_RING( x ) do { \
1153 if ( RADEON_VERBOSE ) { \
1154 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1155 (unsigned int)(x), write ); \
1156 } \
1157 ring[write++] = (x); \
1158 write &= mask; \
1159} while (0)
1160
1161#define OUT_RING_REG( reg, val ) do { \
1162 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1163 OUT_RING( val ); \
1164} while (0)
1165
1da177e4
LT		 1166#define OUT_RING_TABLE( tab, sz ) do { \
1167 int _size = (sz); \
1168 int *_tab = (int *)(tab); \
1169 \
1170 if (write + _size > mask) { \
1171 int _i = (mask+1) - write; \
1172 _size -= _i; \
1173 while (_i > 0 ) { \
1174 *(int *)(ring + write) = *_tab++; \
1175 write++; \
1176 _i--; \
1177 } \
1178 write = 0; \
1179 _tab += _i; \
1180 } \
1da177e4
LT		 1181 while (_size > 0) { \
1182 *(ring + write) = *_tab++; \
1183 write++; \
1184 _size--; \
1185 } \
1186 write &= mask; \
1187} while (0)
1188
b5e89ed5 1189#endif /* __RADEON_DRV_H__ */
Linux 6.x block layer and io_uring tree(s)