projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm: rework radeon memory map (radeon 1.23)
[linux-2.6-block.git] / drivers / char / drm / radeon_cp.c
CommitLineData
f26c473c
DA		 1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
1da177e4
LT		 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#include "drmP.h"
32#include "drm.h"
33#include "radeon_drm.h"
34#include "radeon_drv.h"
414ed537 35#include "r300_reg.h"
1da177e4
LT		 36
37#define RADEON_FIFO_DEBUG 0
38
b5e89ed5 39static int radeon_do_cleanup_cp(drm_device_t * dev);
1da177e4
LT		 40
41/* CP microcode (from ATI) */
42static u32 R200_cp_microcode[][2] = {
b5e89ed5
DA		 43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
1da177e4
LT		 299};
300
1da177e4 301static u32 radeon_cp_microcode[][2] = {
b5e89ed5
DA		 302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
1da177e4
LT		 558};
559
560static u32 R300_cp_microcode[][2] = {
b5e89ed5
DA		 561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
1da177e4
LT		 817};
818
b5e89ed5 819static int RADEON_READ_PLL(drm_device_t * dev, int addr)
1da177e4
LT		 820{
821 drm_radeon_private_t *dev_priv = dev->dev_private;
822
823 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
825}
826
d985c108 827static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
ea98a92f
DA		 828{
829 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
830 return RADEON_READ(RADEON_PCIE_DATA);
831}
832
1da177e4 833#if RADEON_FIFO_DEBUG
b5e89ed5 834static void radeon_status(drm_radeon_private_t * dev_priv)
1da177e4 835{
b5e89ed5
DA		 836 printk("%s:\n", __FUNCTION__);
837 printk("RBBM_STATUS = 0x%08x\n",
838 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
839 printk("CP_RB_RTPR = 0x%08x\n",
840 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
841 printk("CP_RB_WTPR = 0x%08x\n",
842 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
843 printk("AIC_CNTL = 0x%08x\n",
844 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
845 printk("AIC_STAT = 0x%08x\n",
846 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
847 printk("AIC_PT_BASE = 0x%08x\n",
848 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
849 printk("TLB_ADDR = 0x%08x\n",
850 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
851 printk("TLB_DATA = 0x%08x\n",
852 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
1da177e4
LT		 853}
854#endif
855
1da177e4
LT		 856/* ================================================================
857 * Engine, FIFO control
858 */
859
b5e89ed5 860static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
1da177e4
LT		 861{
862 u32 tmp;
863 int i;
864
865 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
866
b5e89ed5 867 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
1da177e4 868 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
b5e89ed5 869 RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
1da177e4 870
b5e89ed5
DA		 871 for (i = 0; i < dev_priv->usec_timeout; i++) {
872 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
873 & RADEON_RB2D_DC_BUSY)) {
1da177e4
LT		 874 return 0;
875 }
b5e89ed5 876 DRM_UDELAY(1);
1da177e4
LT		 877 }
878
879#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 880 DRM_ERROR("failed!\n");
881 radeon_status(dev_priv);
1da177e4
LT		 882#endif
883 return DRM_ERR(EBUSY);
884}
885
b5e89ed5 886static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
1da177e4
LT		 887{
888 int i;
889
890 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
891
b5e89ed5
DA		 892 for (i = 0; i < dev_priv->usec_timeout; i++) {
893 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
894 & RADEON_RBBM_FIFOCNT_MASK);
895 if (slots >= entries)
896 return 0;
897 DRM_UDELAY(1);
1da177e4
LT		 898 }
899
900#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 901 DRM_ERROR("failed!\n");
902 radeon_status(dev_priv);
1da177e4
LT		 903#endif
904 return DRM_ERR(EBUSY);
905}
906
b5e89ed5 907static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 908{
909 int i, ret;
910
911 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
912
b5e89ed5
DA		 913 ret = radeon_do_wait_for_fifo(dev_priv, 64);
914 if (ret)
915 return ret;
1da177e4 916
b5e89ed5
DA		 917 for (i = 0; i < dev_priv->usec_timeout; i++) {
918 if (!(RADEON_READ(RADEON_RBBM_STATUS)
919 & RADEON_RBBM_ACTIVE)) {
920 radeon_do_pixcache_flush(dev_priv);
1da177e4
LT		 921 return 0;
922 }
b5e89ed5 923 DRM_UDELAY(1);
1da177e4
LT		 924 }
925
926#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 927 DRM_ERROR("failed!\n");
928 radeon_status(dev_priv);
1da177e4
LT		 929#endif
930 return DRM_ERR(EBUSY);
931}
932
1da177e4
LT		 933/* ================================================================
934 * CP control, initialization
935 */
936
937/* Load the microcode for the CP */
b5e89ed5 938static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1da177e4
LT		 939{
940 int i;
b5e89ed5 941 DRM_DEBUG("\n");
1da177e4 942
b5e89ed5 943 radeon_do_wait_for_idle(dev_priv);
1da177e4 944
b5e89ed5 945 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1da177e4 946
b5e89ed5 947 if (dev_priv->microcode_version == UCODE_R200) {
1da177e4 948 DRM_INFO("Loading R200 Microcode\n");
b5e89ed5
DA		 949 for (i = 0; i < 256; i++) {
950 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
951 R200_cp_microcode[i][1]);
952 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
953 R200_cp_microcode[i][0]);
1da177e4 954 }
b5e89ed5 955 } else if (dev_priv->microcode_version == UCODE_R300) {
1da177e4 956 DRM_INFO("Loading R300 Microcode\n");
b5e89ed5
DA		 957 for (i = 0; i < 256; i++) {
958 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
959 R300_cp_microcode[i][1]);
960 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
961 R300_cp_microcode[i][0]);
1da177e4
LT		 962 }
963 } else {
b5e89ed5
DA		 964 for (i = 0; i < 256; i++) {
965 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
966 radeon_cp_microcode[i][1]);
967 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
968 radeon_cp_microcode[i][0]);
1da177e4
LT		 969 }
970 }
971}
972
973/* Flush any pending commands to the CP. This should only be used just
974 * prior to a wait for idle, as it informs the engine that the command
975 * stream is ending.
976 */
b5e89ed5 977static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1da177e4 978{
b5e89ed5 979 DRM_DEBUG("\n");
1da177e4
LT		 980#if 0
981 u32 tmp;
982
b5e89ed5
DA		 983 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
984 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1da177e4
LT		 985#endif
986}
987
988/* Wait for the CP to go idle.
989 */
b5e89ed5 990int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 991{
992 RING_LOCALS;
b5e89ed5 993 DRM_DEBUG("\n");
1da177e4 994
b5e89ed5 995 BEGIN_RING(6);
1da177e4
LT		 996
997 RADEON_PURGE_CACHE();
998 RADEON_PURGE_ZCACHE();
999 RADEON_WAIT_UNTIL_IDLE();
1000
1001 ADVANCE_RING();
1002 COMMIT_RING();
1003
b5e89ed5 1004 return radeon_do_wait_for_idle(dev_priv);
1da177e4
LT		 1005}
1006
1007/* Start the Command Processor.
1008 */
b5e89ed5 1009static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1010{
1011 RING_LOCALS;
b5e89ed5 1012 DRM_DEBUG("\n");
1da177e4 1013
b5e89ed5 1014 radeon_do_wait_for_idle(dev_priv);
1da177e4 1015
b5e89ed5 1016 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1da177e4
LT		 1017
1018 dev_priv->cp_running = 1;
1019
b5e89ed5 1020 BEGIN_RING(6);
1da177e4
LT		 1021
1022 RADEON_PURGE_CACHE();
1023 RADEON_PURGE_ZCACHE();
1024 RADEON_WAIT_UNTIL_IDLE();
1025
1026 ADVANCE_RING();
1027 COMMIT_RING();
1028}
1029
1030/* Reset the Command Processor. This will not flush any pending
1031 * commands, so you must wait for the CP command stream to complete
1032 * before calling this routine.
1033 */
b5e89ed5 1034static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1035{
1036 u32 cur_read_ptr;
b5e89ed5 1037 DRM_DEBUG("\n");
1da177e4 1038
b5e89ed5
DA		 1039 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1040 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1041 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 1042 dev_priv->ring.tail = cur_read_ptr;
1043}
1044
1045/* Stop the Command Processor. This will not flush any pending
1046 * commands, so you must flush the command stream and wait for the CP
1047 * to go idle before calling this routine.
1048 */
b5e89ed5 1049static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1da177e4 1050{
b5e89ed5 1051 DRM_DEBUG("\n");
1da177e4 1052
b5e89ed5 1053 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1da177e4
LT		 1054
1055 dev_priv->cp_running = 0;
1056}
1057
1058/* Reset the engine. This will stop the CP if it is running.
1059 */
b5e89ed5 1060static int radeon_do_engine_reset(drm_device_t * dev)
1da177e4
LT		 1061{
1062 drm_radeon_private_t *dev_priv = dev->dev_private;
1063 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
b5e89ed5 1064 DRM_DEBUG("\n");
1da177e4 1065
b5e89ed5
DA		 1066 radeon_do_pixcache_flush(dev_priv);
1067
1068 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1069 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1070
1071 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1072 RADEON_FORCEON_MCLKA |
1073 RADEON_FORCEON_MCLKB |
1074 RADEON_FORCEON_YCLKA |
1075 RADEON_FORCEON_YCLKB |
1076 RADEON_FORCEON_MC |
1077 RADEON_FORCEON_AIC));
1078
1079 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1080
1081 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1082 RADEON_SOFT_RESET_CP |
1083 RADEON_SOFT_RESET_HI |
1084 RADEON_SOFT_RESET_SE |
1085 RADEON_SOFT_RESET_RE |
1086 RADEON_SOFT_RESET_PP |
1087 RADEON_SOFT_RESET_E2 |
1088 RADEON_SOFT_RESET_RB));
1089 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1090 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1091 ~(RADEON_SOFT_RESET_CP |
1da177e4
LT		 1092 RADEON_SOFT_RESET_HI |
1093 RADEON_SOFT_RESET_SE |
1094 RADEON_SOFT_RESET_RE |
1095 RADEON_SOFT_RESET_PP |
1096 RADEON_SOFT_RESET_E2 |
b5e89ed5
DA		 1097 RADEON_SOFT_RESET_RB)));
1098 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1099
1100 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1101 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1102 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1da177e4
LT		 1103
1104 /* Reset the CP ring */
b5e89ed5 1105 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1106
1107 /* The CP is no longer running after an engine reset */
1108 dev_priv->cp_running = 0;
1109
1110 /* Reset any pending vertex, indirect buffers */
b5e89ed5 1111 radeon_freelist_reset(dev);
1da177e4
LT		 1112
1113 return 0;
1114}
1115
b5e89ed5
DA		 1116static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1117 drm_radeon_private_t * dev_priv)
1da177e4
LT		 1118{
1119 u32 ring_start, cur_read_ptr;
1120 u32 tmp;
d5ea702f
DA		 1121
1122 /* Initialize the memory controller. With new memory map, the fb location
1123 * is not changed, it should have been properly initialized already. Part
1124 * of the problem is that the code below is bogus, assuming the GART is
1125 * always appended to the fb which is not necessarily the case
1126 */
1127 if (!dev_priv->new_memmap)
1128 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1129 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1130 | (dev_priv->fb_location >> 16));
1da177e4
LT		 1131
1132#if __OS_HAS_AGP
d985c108 1133 if (dev_priv->flags & CHIP_IS_AGP) {
d5ea702f 1134 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
b5e89ed5
DA		 1135 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1136 (((dev_priv->gart_vm_start - 1 +
1137 dev_priv->gart_size) & 0xffff0000) |
1138 (dev_priv->gart_vm_start >> 16)));
1da177e4
LT		 1139
1140 ring_start = (dev_priv->cp_ring->offset
1141 - dev->agp->base
1142 + dev_priv->gart_vm_start);
b0917bd9 1143 } else
1da177e4
LT		 1144#endif
1145 ring_start = (dev_priv->cp_ring->offset
b0917bd9 1146 - (unsigned long)dev->sg->virtual
1da177e4
LT		 1147 + dev_priv->gart_vm_start);
1148
b5e89ed5 1149 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1da177e4
LT		 1150
1151 /* Set the write pointer delay */
b5e89ed5 1152 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1da177e4
LT		 1153
1154 /* Initialize the ring buffer's read and write pointers */
b5e89ed5
DA		 1155 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1156 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1157 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 1158 dev_priv->ring.tail = cur_read_ptr;
1159
1160#if __OS_HAS_AGP
d985c108 1161 if (dev_priv->flags & CHIP_IS_AGP) {
b5e89ed5
DA		 1162 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1163 dev_priv->ring_rptr->offset
1164 - dev->agp->base + dev_priv->gart_vm_start);
1da177e4
LT		 1165 } else
1166#endif
1167 {
1168 drm_sg_mem_t *entry = dev->sg;
1169 unsigned long tmp_ofs, page_ofs;
1170
b0917bd9
IK		 1171 tmp_ofs = dev_priv->ring_rptr->offset -
1172 (unsigned long)dev->sg->virtual;
1da177e4
LT		 1173 page_ofs = tmp_ofs >> PAGE_SHIFT;
1174
b5e89ed5
DA		 1175 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1176 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1177 (unsigned long)entry->busaddr[page_ofs],
1178 entry->handle + tmp_ofs);
1da177e4
LT		 1179 }
1180
d5ea702f
DA		 1181 /* Set ring buffer size */
1182#ifdef __BIG_ENDIAN
1183 RADEON_WRITE(RADEON_CP_RB_CNTL,
1184 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1185#else
1186 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1187#endif
1188
1189 /* Start with assuming that writeback doesn't work */
1190 dev_priv->writeback_works = 0;
1191
1da177e4
LT		 1192 /* Initialize the scratch register pointer. This will cause
1193 * the scratch register values to be written out to memory
1194 * whenever they are updated.
1195 *
1196 * We simply put this behind the ring read pointer, this works
1197 * with PCI GART as well as (whatever kind of) AGP GART
1198 */
b5e89ed5
DA		 1199 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1200 + RADEON_SCRATCH_REG_OFFSET);
1da177e4
LT		 1201
1202 dev_priv->scratch = ((__volatile__ u32 *)
1203 dev_priv->ring_rptr->handle +
1204 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1205
b5e89ed5 1206 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1da177e4 1207
d5ea702f
DA		 1208 /* Turn on bus mastering */
1209 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1210 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1da177e4
LT		 1211
1212 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
b5e89ed5 1213 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1da177e4
LT		 1214
1215 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
b5e89ed5
DA		 1216 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1217 dev_priv->sarea_priv->last_dispatch);
1da177e4
LT		 1218
1219 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
b5e89ed5 1220 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1da177e4 1221
b5e89ed5 1222 radeon_do_wait_for_idle(dev_priv);
1da177e4 1223
1da177e4 1224 /* Sync everything up */
b5e89ed5
DA		 1225 RADEON_WRITE(RADEON_ISYNC_CNTL,
1226 (RADEON_ISYNC_ANY2D_IDLE3D |
1227 RADEON_ISYNC_ANY3D_IDLE2D |
1228 RADEON_ISYNC_WAIT_IDLEGUI |
1229 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
d5ea702f
DA		 1230
1231}
1232
1233static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1234{
1235 u32 tmp;
1236
1237 /* Writeback doesn't seem to work everywhere, test it here and possibly
1238 * enable it if it appears to work
1239 */
1240 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1241 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1242
1243 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1244 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1245 0xdeadbeef)
1246 break;
1247 DRM_UDELAY(1);
1248 }
1249
1250 if (tmp < dev_priv->usec_timeout) {
1251 dev_priv->writeback_works = 1;
1252 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1253 } else {
1254 dev_priv->writeback_works = 0;
1255 DRM_INFO("writeback test failed\n");
1256 }
1257 if (radeon_no_wb == 1) {
1258 dev_priv->writeback_works = 0;
1259 DRM_INFO("writeback forced off\n");
1260 }
1da177e4
LT		 1261}
1262
ea98a92f
DA		 1263/* Enable or disable PCI-E GART on the chip */
1264static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1265{
1266 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1267 if (on) {
1268
1269 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
b5e89ed5
DA		 1270 dev_priv->gart_vm_start,
1271 (long)dev_priv->gart_info.bus_addr,
ea98a92f 1272 dev_priv->gart_size);
b5e89ed5
DA		 1273 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1274 dev_priv->gart_vm_start);
1275 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1276 dev_priv->gart_info.bus_addr);
1277 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1278 dev_priv->gart_vm_start);
1279 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1280 dev_priv->gart_vm_start +
1281 dev_priv->gart_size - 1);
1282
ea98a92f 1283 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
b5e89ed5
DA		 1284
1285 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1286 RADEON_PCIE_TX_GART_EN);
ea98a92f 1287 } else {
b5e89ed5
DA		 1288 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1289 tmp & ~RADEON_PCIE_TX_GART_EN);
ea98a92f 1290 }
1da177e4
LT		 1291}
1292
1293/* Enable or disable PCI GART on the chip */
b5e89ed5 1294static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1da177e4 1295{
d985c108 1296 u32 tmp;
1da177e4 1297
b5e89ed5 1298 if (dev_priv->flags & CHIP_IS_PCIE) {
ea98a92f
DA		 1299 radeon_set_pciegart(dev_priv, on);
1300 return;
1301 }
1da177e4 1302
d985c108
DA		 1303 tmp = RADEON_READ(RADEON_AIC_CNTL);
1304
b5e89ed5
DA		 1305 if (on) {
1306 RADEON_WRITE(RADEON_AIC_CNTL,
1307 tmp | RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1308
1309 /* set PCI GART page-table base address
1310 */
ea98a92f 1311 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1da177e4
LT		 1312
1313 /* set address range for PCI address translate
1314 */
b5e89ed5
DA		 1315 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1316 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1317 + dev_priv->gart_size - 1);
1da177e4
LT		 1318
1319 /* Turn off AGP aperture -- is this required for PCI GART?
1320 */
b5e89ed5
DA		 1321 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1322 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1da177e4 1323 } else {
b5e89ed5
DA		 1324 RADEON_WRITE(RADEON_AIC_CNTL,
1325 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1326 }
1327}
1328
b5e89ed5 1329static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1da177e4 1330{
d985c108
DA		 1331 drm_radeon_private_t *dev_priv = dev->dev_private;
1332
b5e89ed5 1333 DRM_DEBUG("\n");
1da177e4 1334
d985c108
DA		 1335 if (init->is_pci && (dev_priv->flags & CHIP_IS_AGP))
1336 {
1337 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1338 dev_priv->flags &= ~CHIP_IS_AGP;
1339 }
1da177e4 1340
d985c108 1341 if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
b5e89ed5 1342 DRM_ERROR("PCI GART memory not allocated!\n");
1da177e4
LT		 1343 radeon_do_cleanup_cp(dev);
1344 return DRM_ERR(EINVAL);
1345 }
1346
1347 dev_priv->usec_timeout = init->usec_timeout;
b5e89ed5
DA		 1348 if (dev_priv->usec_timeout < 1 ||
1349 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1350 DRM_DEBUG("TIMEOUT problem!\n");
1da177e4
LT		 1351 radeon_do_cleanup_cp(dev);
1352 return DRM_ERR(EINVAL);
1353 }
1354
d985c108 1355 switch(init->func) {
1da177e4 1356 case RADEON_INIT_R200_CP:
b5e89ed5 1357 dev_priv->microcode_version = UCODE_R200;
1da177e4
LT		 1358 break;
1359 case RADEON_INIT_R300_CP:
b5e89ed5 1360 dev_priv->microcode_version = UCODE_R300;
1da177e4
LT		 1361 break;
1362 default:
b5e89ed5 1363 dev_priv->microcode_version = UCODE_R100;
1da177e4 1364 }
b5e89ed5 1365
1da177e4
LT		 1366 dev_priv->do_boxes = 0;
1367 dev_priv->cp_mode = init->cp_mode;
1368
1369 /* We don't support anything other than bus-mastering ring mode,
1370 * but the ring can be in either AGP or PCI space for the ring
1371 * read pointer.
1372 */
b5e89ed5
DA		 1373 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1374 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1375 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1da177e4
LT		 1376 radeon_do_cleanup_cp(dev);
1377 return DRM_ERR(EINVAL);
1378 }
1379
b5e89ed5 1380 switch (init->fb_bpp) {
1da177e4
LT		 1381 case 16:
1382 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1383 break;
1384 case 32:
1385 default:
1386 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1387 break;
1388 }
b5e89ed5
DA		 1389 dev_priv->front_offset = init->front_offset;
1390 dev_priv->front_pitch = init->front_pitch;
1391 dev_priv->back_offset = init->back_offset;
1392 dev_priv->back_pitch = init->back_pitch;
1da177e4 1393
b5e89ed5 1394 switch (init->depth_bpp) {
1da177e4
LT		 1395 case 16:
1396 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1397 break;
1398 case 32:
1399 default:
1400 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1401 break;
1402 }
b5e89ed5
DA		 1403 dev_priv->depth_offset = init->depth_offset;
1404 dev_priv->depth_pitch = init->depth_pitch;
1da177e4
LT		 1405
1406 /* Hardware state for depth clears. Remove this if/when we no
1407 * longer clear the depth buffer with a 3D rectangle. Hard-code
1408 * all values to prevent unwanted 3D state from slipping through
1409 * and screwing with the clear operation.
1410 */
1411 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1412 (dev_priv->color_fmt << 10) |
b5e89ed5
DA		 1413 (dev_priv->microcode_version ==
1414 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1da177e4 1415
b5e89ed5
DA		 1416 dev_priv->depth_clear.rb3d_zstencilcntl =
1417 (dev_priv->depth_fmt |
1418 RADEON_Z_TEST_ALWAYS |
1419 RADEON_STENCIL_TEST_ALWAYS |
1420 RADEON_STENCIL_S_FAIL_REPLACE |
1421 RADEON_STENCIL_ZPASS_REPLACE |
1422 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1da177e4
LT		 1423
1424 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1425 RADEON_BFACE_SOLID |
1426 RADEON_FFACE_SOLID |
1427 RADEON_FLAT_SHADE_VTX_LAST |
1428 RADEON_DIFFUSE_SHADE_FLAT |
1429 RADEON_ALPHA_SHADE_FLAT |
1430 RADEON_SPECULAR_SHADE_FLAT |
1431 RADEON_FOG_SHADE_FLAT |
1432 RADEON_VTX_PIX_CENTER_OGL |
1433 RADEON_ROUND_MODE_TRUNC |
1434 RADEON_ROUND_PREC_8TH_PIX);
1435
1436 DRM_GETSAREA();
1437
1da177e4
LT		 1438 dev_priv->ring_offset = init->ring_offset;
1439 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1440 dev_priv->buffers_offset = init->buffers_offset;
1441 dev_priv->gart_textures_offset = init->gart_textures_offset;
b5e89ed5
DA		 1442
1443 if (!dev_priv->sarea) {
1da177e4 1444 DRM_ERROR("could not find sarea!\n");
1da177e4
LT		 1445 radeon_do_cleanup_cp(dev);
1446 return DRM_ERR(EINVAL);
1447 }
1448
1da177e4 1449 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
b5e89ed5 1450 if (!dev_priv->cp_ring) {
1da177e4 1451 DRM_ERROR("could not find cp ring region!\n");
1da177e4
LT		 1452 radeon_do_cleanup_cp(dev);
1453 return DRM_ERR(EINVAL);
1454 }
1455 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
b5e89ed5 1456 if (!dev_priv->ring_rptr) {
1da177e4 1457 DRM_ERROR("could not find ring read pointer!\n");
1da177e4
LT		 1458 radeon_do_cleanup_cp(dev);
1459 return DRM_ERR(EINVAL);
1460 }
d1f2b55a 1461 dev->agp_buffer_token = init->buffers_offset;
1da177e4 1462 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
b5e89ed5 1463 if (!dev->agp_buffer_map) {
1da177e4 1464 DRM_ERROR("could not find dma buffer region!\n");
1da177e4
LT		 1465 radeon_do_cleanup_cp(dev);
1466 return DRM_ERR(EINVAL);
1467 }
1468
b5e89ed5
DA		 1469 if (init->gart_textures_offset) {
1470 dev_priv->gart_textures =
1471 drm_core_findmap(dev, init->gart_textures_offset);
1472 if (!dev_priv->gart_textures) {
1da177e4 1473 DRM_ERROR("could not find GART texture region!\n");
1da177e4
LT		 1474 radeon_do_cleanup_cp(dev);
1475 return DRM_ERR(EINVAL);
1476 }
1477 }
1478
1479 dev_priv->sarea_priv =
b5e89ed5
DA		 1480 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1481 init->sarea_priv_offset);
1da177e4
LT		 1482
1483#if __OS_HAS_AGP
d985c108 1484 if (dev_priv->flags & CHIP_IS_AGP) {
b5e89ed5
DA		 1485 drm_core_ioremap(dev_priv->cp_ring, dev);
1486 drm_core_ioremap(dev_priv->ring_rptr, dev);
1487 drm_core_ioremap(dev->agp_buffer_map, dev);
1488 if (!dev_priv->cp_ring->handle ||
1489 !dev_priv->ring_rptr->handle ||
1490 !dev->agp_buffer_map->handle) {
1da177e4 1491 DRM_ERROR("could not find ioremap agp regions!\n");
1da177e4
LT		 1492 radeon_do_cleanup_cp(dev);
1493 return DRM_ERR(EINVAL);
1494 }
1495 } else
1496#endif
1497 {
b5e89ed5 1498 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1da177e4 1499 dev_priv->ring_rptr->handle =
b5e89ed5
DA		 1500 (void *)dev_priv->ring_rptr->offset;
1501 dev->agp_buffer_map->handle =
1502 (void *)dev->agp_buffer_map->offset;
1503
1504 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1505 dev_priv->cp_ring->handle);
1506 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1507 dev_priv->ring_rptr->handle);
1508 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1509 dev->agp_buffer_map->handle);
1da177e4
LT		 1510 }
1511
b5e89ed5
DA		 1512 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1513 & 0xffff) << 16;
d5ea702f
DA		 1514 dev_priv->fb_size =
1515 ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
1516 - dev_priv->fb_location;
1da177e4 1517
b5e89ed5
DA		 1518 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1519 ((dev_priv->front_offset
1520 + dev_priv->fb_location) >> 10));
1da177e4 1521
b5e89ed5
DA		 1522 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1523 ((dev_priv->back_offset
1524 + dev_priv->fb_location) >> 10));
1da177e4 1525
b5e89ed5
DA		 1526 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1527 ((dev_priv->depth_offset
1528 + dev_priv->fb_location) >> 10));
1da177e4
LT		 1529
1530 dev_priv->gart_size = init->gart_size;
d5ea702f
DA		 1531
1532 /* New let's set the memory map ... */
1533 if (dev_priv->new_memmap) {
1534 u32 base = 0;
1535
1536 DRM_INFO("Setting GART location based on new memory map\n");
1537
1538 /* If using AGP, try to locate the AGP aperture at the same
1539 * location in the card and on the bus, though we have to
1540 * align it down.
1541 */
1542#if __OS_HAS_AGP
1543 if (dev_priv->flags & CHIP_IS_AGP) {
1544 base = dev->agp->base;
1545 /* Check if valid */
1546 if ((base + dev_priv->gart_size) > dev_priv->fb_location &&
1547 base < (dev_priv->fb_location + dev_priv->fb_size)) {
1548 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1549 dev->agp->base);
1550 base = 0;
1551 }
1552 }
1553#endif
1554 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1555 if (base == 0) {
1556 base = dev_priv->fb_location + dev_priv->fb_size;
1557 if (((base + dev_priv->gart_size) & 0xfffffffful)
1558 < base)
1559 base = dev_priv->fb_location
1560 - dev_priv->gart_size;
1561 }
1562 dev_priv->gart_vm_start = base & 0xffc00000u;
1563 if (dev_priv->gart_vm_start != base)
1564 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1565 base, dev_priv->gart_vm_start);
1566 } else {
1567 DRM_INFO("Setting GART location based on old memory map\n");
1568 dev_priv->gart_vm_start = dev_priv->fb_location +
1569 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1570 }
1da177e4
LT		 1571
1572#if __OS_HAS_AGP
d985c108 1573 if (dev_priv->flags & CHIP_IS_AGP)
1da177e4 1574 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b5e89ed5
DA		 1575 - dev->agp->base
1576 + dev_priv->gart_vm_start);
1da177e4
LT		 1577 else
1578#endif
1579 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b0917bd9
IK		 1580 - (unsigned long)dev->sg->virtual
1581 + dev_priv->gart_vm_start);
1da177e4 1582
b5e89ed5
DA		 1583 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1584 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1585 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1586 dev_priv->gart_buffers_offset);
1da177e4 1587
b5e89ed5
DA		 1588 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1589 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1da177e4
LT		 1590 + init->ring_size / sizeof(u32));
1591 dev_priv->ring.size = init->ring_size;
b5e89ed5 1592 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1da177e4 1593
b5e89ed5 1594 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1da177e4
LT		 1595
1596 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1597
1598#if __OS_HAS_AGP
d985c108 1599 if (dev_priv->flags & CHIP_IS_AGP) {
1da177e4 1600 /* Turn off PCI GART */
b5e89ed5 1601 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1602 } else
1603#endif
1604 {
ea98a92f
DA		 1605 /* if we have an offset set from userspace */
1606 if (dev_priv->pcigart_offset) {
b5e89ed5
DA		 1607 dev_priv->gart_info.bus_addr =
1608 dev_priv->pcigart_offset + dev_priv->fb_location;
f26c473c
DA		 1609 dev_priv->gart_info.mapping.offset =
1610 dev_priv->gart_info.bus_addr;
1611 dev_priv->gart_info.mapping.size =
1612 RADEON_PCIGART_TABLE_SIZE;
1613
1614 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
b5e89ed5 1615 dev_priv->gart_info.addr =
f26c473c 1616 dev_priv->gart_info.mapping.handle;
b5e89ed5
DA		 1617
1618 dev_priv->gart_info.is_pcie =
1619 !!(dev_priv->flags & CHIP_IS_PCIE);
1620 dev_priv->gart_info.gart_table_location =
1621 DRM_ATI_GART_FB;
1622
f26c473c 1623 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
b5e89ed5
DA		 1624 dev_priv->gart_info.addr,
1625 dev_priv->pcigart_offset);
1626 } else {
1627 dev_priv->gart_info.gart_table_location =
1628 DRM_ATI_GART_MAIN;
f26c473c
DA		 1629 dev_priv->gart_info.addr = NULL;
1630 dev_priv->gart_info.bus_addr = 0;
b5e89ed5
DA		 1631 if (dev_priv->flags & CHIP_IS_PCIE) {
1632 DRM_ERROR
1633 ("Cannot use PCI Express without GART in FB memory\n");
ea98a92f
DA		 1634 radeon_do_cleanup_cp(dev);
1635 return DRM_ERR(EINVAL);
1636 }
1637 }
1638
1639 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
b5e89ed5 1640 DRM_ERROR("failed to init PCI GART!\n");
1da177e4
LT		 1641 radeon_do_cleanup_cp(dev);
1642 return DRM_ERR(ENOMEM);
1643 }
1644
1645 /* Turn on PCI GART */
b5e89ed5 1646 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1647 }
1648
b5e89ed5
DA		 1649 radeon_cp_load_microcode(dev_priv);
1650 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4
LT		 1651
1652 dev_priv->last_buf = 0;
1653
b5e89ed5 1654 radeon_do_engine_reset(dev);
d5ea702f 1655 radeon_test_writeback(dev_priv);
1da177e4
LT		 1656
1657 return 0;
1658}
1659
b5e89ed5 1660static int radeon_do_cleanup_cp(drm_device_t * dev)
1da177e4
LT		 1661{
1662 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1663 DRM_DEBUG("\n");
1da177e4
LT		 1664
1665 /* Make sure interrupts are disabled here because the uninstall ioctl
1666 * may not have been called from userspace and after dev_private
1667 * is freed, it's too late.
1668 */
b5e89ed5
DA		 1669 if (dev->irq_enabled)
1670 drm_irq_uninstall(dev);
1da177e4
LT		 1671
1672#if __OS_HAS_AGP
d985c108
DA		 1673 if (dev_priv->flags & CHIP_IS_AGP) {
1674 if (dev_priv->cp_ring != NULL) {
b5e89ed5 1675 drm_core_ioremapfree(dev_priv->cp_ring, dev);
d985c108
DA		 1676 dev_priv->cp_ring = NULL;
1677 }
1678 if (dev_priv->ring_rptr != NULL) {
b5e89ed5 1679 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
d985c108
DA		 1680 dev_priv->ring_rptr = NULL;
1681 }
b5e89ed5
DA		 1682 if (dev->agp_buffer_map != NULL) {
1683 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1da177e4
LT		 1684 dev->agp_buffer_map = NULL;
1685 }
1686 } else
1687#endif
1688 {
d985c108
DA		 1689
1690 if (dev_priv->gart_info.bus_addr) {
1691 /* Turn off PCI GART */
1692 radeon_set_pcigart(dev_priv, 0);
ea98a92f
DA		 1693 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1694 DRM_ERROR("failed to cleanup PCI GART!\n");
d985c108 1695 }
b5e89ed5 1696
d985c108
DA		 1697 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1698 {
f26c473c 1699 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
d59cc22f 1700 dev_priv->gart_info.addr = NULL;
ea98a92f 1701 }
1da177e4 1702 }
1da177e4
LT		 1703 /* only clear to the start of flags */
1704 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1705
1706 return 0;
1707}
1708
b5e89ed5
DA		 1709/* This code will reinit the Radeon CP hardware after a resume from disc.
1710 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1da177e4
LT		 1711 * here we make sure that all Radeon hardware initialisation is re-done without
1712 * affecting running applications.
1713 *
1714 * Charl P. Botha <http://cpbotha.net>
1715 */
b5e89ed5 1716static int radeon_do_resume_cp(drm_device_t * dev)
1da177e4
LT		 1717{
1718 drm_radeon_private_t *dev_priv = dev->dev_private;
1719
b5e89ed5
DA		 1720 if (!dev_priv) {
1721 DRM_ERROR("Called with no initialization\n");
1722 return DRM_ERR(EINVAL);
1da177e4
LT		 1723 }
1724
1725 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1726
1727#if __OS_HAS_AGP
d985c108 1728 if (dev_priv->flags & CHIP_IS_AGP) {
1da177e4 1729 /* Turn off PCI GART */
b5e89ed5 1730 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1731 } else
1732#endif
1733 {
1734 /* Turn on PCI GART */
b5e89ed5 1735 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1736 }
1737
b5e89ed5
DA		 1738 radeon_cp_load_microcode(dev_priv);
1739 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4 1740
b5e89ed5 1741 radeon_do_engine_reset(dev);
1da177e4
LT		 1742
1743 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1744
1745 return 0;
1746}
1747
b5e89ed5 1748int radeon_cp_init(DRM_IOCTL_ARGS)
1da177e4
LT		 1749{
1750 DRM_DEVICE;
1751 drm_radeon_init_t init;
1752
b5e89ed5 1753 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1754
b5e89ed5
DA		 1755 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1756 sizeof(init));
1da177e4 1757
b5e89ed5 1758 if (init.func == RADEON_INIT_R300_CP)
414ed537
DA		 1759 r300_init_reg_flags();
1760
b5e89ed5 1761 switch (init.func) {
1da177e4
LT		 1762 case RADEON_INIT_CP:
1763 case RADEON_INIT_R200_CP:
1764 case RADEON_INIT_R300_CP:
b5e89ed5 1765 return radeon_do_init_cp(dev, &init);
1da177e4 1766 case RADEON_CLEANUP_CP:
b5e89ed5 1767 return radeon_do_cleanup_cp(dev);
1da177e4
LT		 1768 }
1769
1770 return DRM_ERR(EINVAL);
1771}
1772
b5e89ed5 1773int radeon_cp_start(DRM_IOCTL_ARGS)
1da177e4
LT		 1774{
1775 DRM_DEVICE;
1776 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1777 DRM_DEBUG("\n");
1da177e4 1778
b5e89ed5 1779 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1780
b5e89ed5
DA		 1781 if (dev_priv->cp_running) {
1782 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1da177e4
LT		 1783 return 0;
1784 }
b5e89ed5
DA		 1785 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1786 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1787 __FUNCTION__, dev_priv->cp_mode);
1da177e4
LT		 1788 return 0;
1789 }
1790
b5e89ed5 1791 radeon_do_cp_start(dev_priv);
1da177e4
LT		 1792
1793 return 0;
1794}
1795
1796/* Stop the CP. The engine must have been idled before calling this
1797 * routine.
1798 */
b5e89ed5 1799int radeon_cp_stop(DRM_IOCTL_ARGS)
1da177e4
LT		 1800{
1801 DRM_DEVICE;
1802 drm_radeon_private_t *dev_priv = dev->dev_private;
1803 drm_radeon_cp_stop_t stop;
1804 int ret;
b5e89ed5 1805 DRM_DEBUG("\n");
1da177e4 1806
b5e89ed5 1807 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1808
b5e89ed5
DA		 1809 DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1810 sizeof(stop));
1da177e4
LT		 1811
1812 if (!dev_priv->cp_running)
1813 return 0;
1814
1815 /* Flush any pending CP commands. This ensures any outstanding
1816 * commands are exectuted by the engine before we turn it off.
1817 */
b5e89ed5
DA		 1818 if (stop.flush) {
1819 radeon_do_cp_flush(dev_priv);
1da177e4
LT		 1820 }
1821
1822 /* If we fail to make the engine go idle, we return an error
1823 * code so that the DRM ioctl wrapper can try again.
1824 */
b5e89ed5
DA		 1825 if (stop.idle) {
1826 ret = radeon_do_cp_idle(dev_priv);
1827 if (ret)
1828 return ret;
1da177e4
LT		 1829 }
1830
1831 /* Finally, we can turn off the CP. If the engine isn't idle,
1832 * we will get some dropped triangles as they won't be fully
1833 * rendered before the CP is shut down.
1834 */
b5e89ed5 1835 radeon_do_cp_stop(dev_priv);
1da177e4
LT		 1836
1837 /* Reset the engine */
b5e89ed5 1838 radeon_do_engine_reset(dev);
1da177e4
LT		 1839
1840 return 0;
1841}
1842
b5e89ed5 1843void radeon_do_release(drm_device_t * dev)
1da177e4
LT		 1844{
1845 drm_radeon_private_t *dev_priv = dev->dev_private;
1846 int i, ret;
1847
1848 if (dev_priv) {
1849 if (dev_priv->cp_running) {
1850 /* Stop the cp */
b5e89ed5 1851 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1da177e4
LT		 1852 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1853#ifdef __linux__
1854 schedule();
1855#else
1856 tsleep(&ret, PZERO, "rdnrel", 1);
1857#endif
1858 }
b5e89ed5
DA		 1859 radeon_do_cp_stop(dev_priv);
1860 radeon_do_engine_reset(dev);
1da177e4
LT		 1861 }
1862
1863 /* Disable *all* interrupts */
1864 if (dev_priv->mmio) /* remove this after permanent addmaps */
b5e89ed5 1865 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1da177e4 1866
b5e89ed5 1867 if (dev_priv->mmio) { /* remove all surfaces */
1da177e4 1868 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
b5e89ed5
DA		 1869 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1870 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1871 16 * i, 0);
1872 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1873 16 * i, 0);
1da177e4
LT		 1874 }
1875 }
1876
1877 /* Free memory heap structures */
b5e89ed5
DA		 1878 radeon_mem_takedown(&(dev_priv->gart_heap));
1879 radeon_mem_takedown(&(dev_priv->fb_heap));
1da177e4
LT		 1880
1881 /* deallocate kernel resources */
b5e89ed5 1882 radeon_do_cleanup_cp(dev);
1da177e4
LT		 1883 }
1884}
1885
1886/* Just reset the CP ring. Called as part of an X Server engine reset.
1887 */
b5e89ed5 1888int radeon_cp_reset(DRM_IOCTL_ARGS)
1da177e4
LT		 1889{
1890 DRM_DEVICE;
1891 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1892 DRM_DEBUG("\n");
1da177e4 1893
b5e89ed5 1894 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1895
b5e89ed5
DA		 1896 if (!dev_priv) {
1897 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1da177e4
LT		 1898 return DRM_ERR(EINVAL);
1899 }
1900
b5e89ed5 1901 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1902
1903 /* The CP is no longer running after an engine reset */
1904 dev_priv->cp_running = 0;
1905
1906 return 0;
1907}
1908
b5e89ed5 1909int radeon_cp_idle(DRM_IOCTL_ARGS)
1da177e4
LT		 1910{
1911 DRM_DEVICE;
1912 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1913 DRM_DEBUG("\n");
1da177e4 1914
b5e89ed5 1915 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1916
b5e89ed5 1917 return radeon_do_cp_idle(dev_priv);
1da177e4
LT		 1918}
1919
1920/* Added by Charl P. Botha to call radeon_do_resume_cp().
1921 */
b5e89ed5 1922int radeon_cp_resume(DRM_IOCTL_ARGS)
1da177e4
LT		 1923{
1924 DRM_DEVICE;
1925
1926 return radeon_do_resume_cp(dev);
1927}
1928
b5e89ed5 1929int radeon_engine_reset(DRM_IOCTL_ARGS)
1da177e4
LT		 1930{
1931 DRM_DEVICE;
b5e89ed5 1932 DRM_DEBUG("\n");
1da177e4 1933
b5e89ed5 1934 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1935
b5e89ed5 1936 return radeon_do_engine_reset(dev);
1da177e4
LT		 1937}
1938
1da177e4
LT		 1939/* ================================================================
1940 * Fullscreen mode
1941 */
1942
1943/* KW: Deprecated to say the least:
1944 */
b5e89ed5 1945int radeon_fullscreen(DRM_IOCTL_ARGS)
1da177e4
LT		 1946{
1947 return 0;
1948}
1949
1da177e4
LT		 1950/* ================================================================
1951 * Freelist management
1952 */
1953
1954/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1955 * bufs until freelist code is used. Note this hides a problem with
1956 * the scratch register * (used to keep track of last buffer
1957 * completed) being written to before * the last buffer has actually
b5e89ed5 1958 * completed rendering.
1da177e4
LT		 1959 *
1960 * KW: It's also a good way to find free buffers quickly.
1961 *
1962 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1963 * sleep. However, bugs in older versions of radeon_accel.c mean that
1964 * we essentially have to do this, else old clients will break.
b5e89ed5 1965 *
1da177e4
LT		 1966 * However, it does leave open a potential deadlock where all the
1967 * buffers are held by other clients, which can't release them because
b5e89ed5 1968 * they can't get the lock.
1da177e4
LT		 1969 */
1970
b5e89ed5 1971drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1da177e4
LT		 1972{
1973 drm_device_dma_t *dma = dev->dma;
1974 drm_radeon_private_t *dev_priv = dev->dev_private;
1975 drm_radeon_buf_priv_t *buf_priv;
1976 drm_buf_t *buf;
1977 int i, t;
1978 int start;
1979
b5e89ed5 1980 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 1981 dev_priv->last_buf = 0;
1982
1983 start = dev_priv->last_buf;
1984
b5e89ed5
DA		 1985 for (t = 0; t < dev_priv->usec_timeout; t++) {
1986 u32 done_age = GET_SCRATCH(1);
1987 DRM_DEBUG("done_age = %d\n", done_age);
1988 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 1989 buf = dma->buflist[i];
1990 buf_priv = buf->dev_private;
b5e89ed5
DA		 1991 if (buf->filp == 0 || (buf->pending &&
1992 buf_priv->age <= done_age)) {
1da177e4
LT		 1993 dev_priv->stats.requested_bufs++;
1994 buf->pending = 0;
1995 return buf;
1996 }
1997 start = 0;
1998 }
1999
2000 if (t) {
b5e89ed5 2001 DRM_UDELAY(1);
1da177e4
LT		 2002 dev_priv->stats.freelist_loops++;
2003 }
2004 }
2005
b5e89ed5 2006 DRM_DEBUG("returning NULL!\n");
1da177e4
LT		 2007 return NULL;
2008}
b5e89ed5 2009
1da177e4 2010#if 0
b5e89ed5 2011drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1da177e4
LT		 2012{
2013 drm_device_dma_t *dma = dev->dma;
2014 drm_radeon_private_t *dev_priv = dev->dev_private;
2015 drm_radeon_buf_priv_t *buf_priv;
2016 drm_buf_t *buf;
2017 int i, t;
2018 int start;
2019 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2020
b5e89ed5 2021 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 2022 dev_priv->last_buf = 0;
2023
2024 start = dev_priv->last_buf;
2025 dev_priv->stats.freelist_loops++;
b5e89ed5
DA		 2026
2027 for (t = 0; t < 2; t++) {
2028 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 2029 buf = dma->buflist[i];
2030 buf_priv = buf->dev_private;
b5e89ed5
DA		 2031 if (buf->filp == 0 || (buf->pending &&
2032 buf_priv->age <= done_age)) {
1da177e4
LT		 2033 dev_priv->stats.requested_bufs++;
2034 buf->pending = 0;
2035 return buf;
2036 }
2037 }
2038 start = 0;
2039 }
2040
2041 return NULL;
2042}
2043#endif
2044
b5e89ed5 2045void radeon_freelist_reset(drm_device_t * dev)
1da177e4
LT		 2046{
2047 drm_device_dma_t *dma = dev->dma;
2048 drm_radeon_private_t *dev_priv = dev->dev_private;
2049 int i;
2050
2051 dev_priv->last_buf = 0;
b5e89ed5 2052 for (i = 0; i < dma->buf_count; i++) {
1da177e4
LT		 2053 drm_buf_t *buf = dma->buflist[i];
2054 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2055 buf_priv->age = 0;
2056 }
2057}
2058
1da177e4
LT		 2059/* ================================================================
2060 * CP command submission
2061 */
2062
b5e89ed5 2063int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1da177e4
LT		 2064{
2065 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2066 int i;
b5e89ed5 2067 u32 last_head = GET_RING_HEAD(dev_priv);
1da177e4 2068
b5e89ed5
DA		 2069 for (i = 0; i < dev_priv->usec_timeout; i++) {
2070 u32 head = GET_RING_HEAD(dev_priv);
1da177e4
LT		 2071
2072 ring->space = (head - ring->tail) * sizeof(u32);
b5e89ed5 2073 if (ring->space <= 0)
1da177e4 2074 ring->space += ring->size;
b5e89ed5 2075 if (ring->space > n)
1da177e4 2076 return 0;
b5e89ed5 2077
1da177e4
LT		 2078 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2079
2080 if (head != last_head)
2081 i = 0;
2082 last_head = head;
2083
b5e89ed5 2084 DRM_UDELAY(1);
1da177e4
LT		 2085 }
2086
2087 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2088#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 2089 radeon_status(dev_priv);
2090 DRM_ERROR("failed!\n");
1da177e4
LT		 2091#endif
2092 return DRM_ERR(EBUSY);
2093}
2094
b5e89ed5
DA		 2095static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
2096 drm_dma_t * d)
1da177e4
LT		 2097{
2098 int i;
2099 drm_buf_t *buf;
2100
b5e89ed5
DA		 2101 for (i = d->granted_count; i < d->request_count; i++) {
2102 buf = radeon_freelist_get(dev);
2103 if (!buf)
2104 return DRM_ERR(EBUSY); /* NOTE: broken client */
1da177e4
LT		 2105
2106 buf->filp = filp;
2107
b5e89ed5
DA		 2108 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2109 sizeof(buf->idx)))
1da177e4 2110 return DRM_ERR(EFAULT);
b5e89ed5
DA		 2111 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2112 sizeof(buf->total)))
1da177e4
LT		 2113 return DRM_ERR(EFAULT);
2114
2115 d->granted_count++;
2116 }
2117 return 0;
2118}
2119
b5e89ed5 2120int radeon_cp_buffers(DRM_IOCTL_ARGS)
1da177e4
LT		 2121{
2122 DRM_DEVICE;
2123 drm_device_dma_t *dma = dev->dma;
2124 int ret = 0;
2125 drm_dma_t __user *argp = (void __user *)data;
2126 drm_dma_t d;
2127
b5e89ed5 2128 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 2129
b5e89ed5 2130 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1da177e4
LT		 2131
2132 /* Please don't send us buffers.
2133 */
b5e89ed5
DA		 2134 if (d.send_count != 0) {
2135 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2136 DRM_CURRENTPID, d.send_count);
1da177e4
LT		 2137 return DRM_ERR(EINVAL);
2138 }
2139
2140 /* We'll send you buffers.
2141 */
b5e89ed5
DA		 2142 if (d.request_count < 0 || d.request_count > dma->buf_count) {
2143 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2144 DRM_CURRENTPID, d.request_count, dma->buf_count);
1da177e4
LT		 2145 return DRM_ERR(EINVAL);
2146 }
2147
2148 d.granted_count = 0;
2149
b5e89ed5
DA		 2150 if (d.request_count) {
2151 ret = radeon_cp_get_buffers(filp, dev, &d);
1da177e4
LT		 2152 }
2153
b5e89ed5 2154 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
1da177e4
LT		 2155
2156 return ret;
2157}
2158
22eae947 2159int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1da177e4
LT		 2160{
2161 drm_radeon_private_t *dev_priv;
2162 int ret = 0;
2163
2164 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2165 if (dev_priv == NULL)
2166 return DRM_ERR(ENOMEM);
2167
2168 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2169 dev->dev_private = (void *)dev_priv;
2170 dev_priv->flags = flags;
2171
2172 switch (flags & CHIP_FAMILY_MASK) {
2173 case CHIP_R100:
2174 case CHIP_RV200:
2175 case CHIP_R200:
2176 case CHIP_R300:
414ed537 2177 case CHIP_R420:
1da177e4
LT		 2178 dev_priv->flags |= CHIP_HAS_HIERZ;
2179 break;
2180 default:
b5e89ed5 2181 /* all other chips have no hierarchical z buffer */
1da177e4
LT		 2182 break;
2183 }
414ed537
DA		 2184
2185 if (drm_device_is_agp(dev))
2186 dev_priv->flags |= CHIP_IS_AGP;
b5e89ed5 2187
ea98a92f
DA		 2188 if (drm_device_is_pcie(dev))
2189 dev_priv->flags |= CHIP_IS_PCIE;
2190
414ed537 2191 DRM_DEBUG("%s card detected\n",
d985c108 2192 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags & CHIP_IS_PCIE) ? "PCIE" : "PCI"))));
1da177e4
LT		 2193 return ret;
2194}
2195
22eae947
DA		 2196/* Create mappings for registers and framebuffer so userland doesn't necessarily
2197 * have to find them.
2198 */
2199int radeon_driver_firstopen(struct drm_device *dev)
836cf046
DA		 2200{
2201 int ret;
2202 drm_local_map_t *map;
2203 drm_radeon_private_t *dev_priv = dev->dev_private;
2204
2205 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2206 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2207 _DRM_READ_ONLY, &dev_priv->mmio);
2208 if (ret != 0)
2209 return ret;
2210
2211 ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2212 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2213 _DRM_WRITE_COMBINING, &map);
2214 if (ret != 0)
2215 return ret;
2216
2217 return 0;
2218}
2219
22eae947 2220int radeon_driver_unload(struct drm_device *dev)
1da177e4
LT		 2221{
2222 drm_radeon_private_t *dev_priv = dev->dev_private;
2223
2224 DRM_DEBUG("\n");
1da177e4
LT		 2225 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2226
2227 dev->dev_private = NULL;
2228 return 0;
2229}
Linux 6.x block layer and io_uring tree(s)