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Merge git://git.infradead.org/~dwmw2/rbtree-2.6
[linux-2.6-block.git] / drivers / char / drm / radeon_cp.c
CommitLineData
f26c473c
DA		 1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
1da177e4
LT		 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#include "drmP.h"
32#include "drm.h"
33#include "radeon_drm.h"
34#include "radeon_drv.h"
414ed537 35#include "r300_reg.h"
1da177e4
LT		 36
37#define RADEON_FIFO_DEBUG 0
38
b5e89ed5 39static int radeon_do_cleanup_cp(drm_device_t * dev);
1da177e4
LT		 40
41/* CP microcode (from ATI) */
42static u32 R200_cp_microcode[][2] = {
b5e89ed5
DA		 43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
1da177e4
LT		 299};
300
1da177e4 301static u32 radeon_cp_microcode[][2] = {
b5e89ed5
DA		 302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
1da177e4
LT		 558};
559
560static u32 R300_cp_microcode[][2] = {
b5e89ed5
DA		 561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
1da177e4
LT		 817};
818
b5e89ed5 819static int RADEON_READ_PLL(drm_device_t * dev, int addr)
1da177e4
LT		 820{
821 drm_radeon_private_t *dev_priv = dev->dev_private;
822
823 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
825}
826
d985c108 827static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
ea98a92f
DA		 828{
829 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
830 return RADEON_READ(RADEON_PCIE_DATA);
831}
832
1da177e4 833#if RADEON_FIFO_DEBUG
b5e89ed5 834static void radeon_status(drm_radeon_private_t * dev_priv)
1da177e4 835{
b5e89ed5
DA		 836 printk("%s:\n", __FUNCTION__);
837 printk("RBBM_STATUS = 0x%08x\n",
838 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
839 printk("CP_RB_RTPR = 0x%08x\n",
840 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
841 printk("CP_RB_WTPR = 0x%08x\n",
842 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
843 printk("AIC_CNTL = 0x%08x\n",
844 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
845 printk("AIC_STAT = 0x%08x\n",
846 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
847 printk("AIC_PT_BASE = 0x%08x\n",
848 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
849 printk("TLB_ADDR = 0x%08x\n",
850 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
851 printk("TLB_DATA = 0x%08x\n",
852 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
1da177e4
LT		 853}
854#endif
855
1da177e4
LT		 856/* ================================================================
857 * Engine, FIFO control
858 */
859
b5e89ed5 860static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
1da177e4
LT		 861{
862 u32 tmp;
863 int i;
864
865 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
866
b5e89ed5 867 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
1da177e4 868 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
b5e89ed5 869 RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
1da177e4 870
b5e89ed5
DA		 871 for (i = 0; i < dev_priv->usec_timeout; i++) {
872 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
873 & RADEON_RB2D_DC_BUSY)) {
1da177e4
LT		 874 return 0;
875 }
b5e89ed5 876 DRM_UDELAY(1);
1da177e4
LT		 877 }
878
879#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 880 DRM_ERROR("failed!\n");
881 radeon_status(dev_priv);
1da177e4
LT		 882#endif
883 return DRM_ERR(EBUSY);
884}
885
b5e89ed5 886static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
1da177e4
LT		 887{
888 int i;
889
890 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
891
b5e89ed5
DA		 892 for (i = 0; i < dev_priv->usec_timeout; i++) {
893 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
894 & RADEON_RBBM_FIFOCNT_MASK);
895 if (slots >= entries)
896 return 0;
897 DRM_UDELAY(1);
1da177e4
LT		 898 }
899
900#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 901 DRM_ERROR("failed!\n");
902 radeon_status(dev_priv);
1da177e4
LT		 903#endif
904 return DRM_ERR(EBUSY);
905}
906
b5e89ed5 907static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 908{
909 int i, ret;
910
911 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
912
b5e89ed5
DA		 913 ret = radeon_do_wait_for_fifo(dev_priv, 64);
914 if (ret)
915 return ret;
1da177e4 916
b5e89ed5
DA		 917 for (i = 0; i < dev_priv->usec_timeout; i++) {
918 if (!(RADEON_READ(RADEON_RBBM_STATUS)
919 & RADEON_RBBM_ACTIVE)) {
920 radeon_do_pixcache_flush(dev_priv);
1da177e4
LT		 921 return 0;
922 }
b5e89ed5 923 DRM_UDELAY(1);
1da177e4
LT		 924 }
925
926#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 927 DRM_ERROR("failed!\n");
928 radeon_status(dev_priv);
1da177e4
LT		 929#endif
930 return DRM_ERR(EBUSY);
931}
932
1da177e4
LT		 933/* ================================================================
934 * CP control, initialization
935 */
936
937/* Load the microcode for the CP */
b5e89ed5 938static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1da177e4
LT		 939{
940 int i;
b5e89ed5 941 DRM_DEBUG("\n");
1da177e4 942
b5e89ed5 943 radeon_do_wait_for_idle(dev_priv);
1da177e4 944
b5e89ed5 945 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1da177e4 946
b5e89ed5 947 if (dev_priv->microcode_version == UCODE_R200) {
1da177e4 948 DRM_INFO("Loading R200 Microcode\n");
b5e89ed5
DA		 949 for (i = 0; i < 256; i++) {
950 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
951 R200_cp_microcode[i][1]);
952 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
953 R200_cp_microcode[i][0]);
1da177e4 954 }
b5e89ed5 955 } else if (dev_priv->microcode_version == UCODE_R300) {
1da177e4 956 DRM_INFO("Loading R300 Microcode\n");
b5e89ed5
DA		 957 for (i = 0; i < 256; i++) {
958 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
959 R300_cp_microcode[i][1]);
960 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
961 R300_cp_microcode[i][0]);
1da177e4
LT		 962 }
963 } else {
b5e89ed5
DA		 964 for (i = 0; i < 256; i++) {
965 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
966 radeon_cp_microcode[i][1]);
967 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
968 radeon_cp_microcode[i][0]);
1da177e4
LT		 969 }
970 }
971}
972
973/* Flush any pending commands to the CP. This should only be used just
974 * prior to a wait for idle, as it informs the engine that the command
975 * stream is ending.
976 */
b5e89ed5 977static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1da177e4 978{
b5e89ed5 979 DRM_DEBUG("\n");
1da177e4
LT		 980#if 0
981 u32 tmp;
982
b5e89ed5
DA		 983 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
984 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1da177e4
LT		 985#endif
986}
987
988/* Wait for the CP to go idle.
989 */
b5e89ed5 990int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 991{
992 RING_LOCALS;
b5e89ed5 993 DRM_DEBUG("\n");
1da177e4 994
b5e89ed5 995 BEGIN_RING(6);
1da177e4
LT		 996
997 RADEON_PURGE_CACHE();
998 RADEON_PURGE_ZCACHE();
999 RADEON_WAIT_UNTIL_IDLE();
1000
1001 ADVANCE_RING();
1002 COMMIT_RING();
1003
b5e89ed5 1004 return radeon_do_wait_for_idle(dev_priv);
1da177e4
LT		 1005}
1006
1007/* Start the Command Processor.
1008 */
b5e89ed5 1009static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1010{
1011 RING_LOCALS;
b5e89ed5 1012 DRM_DEBUG("\n");
1da177e4 1013
b5e89ed5 1014 radeon_do_wait_for_idle(dev_priv);
1da177e4 1015
b5e89ed5 1016 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1da177e4
LT		 1017
1018 dev_priv->cp_running = 1;
1019
b5e89ed5 1020 BEGIN_RING(6);
1da177e4
LT		 1021
1022 RADEON_PURGE_CACHE();
1023 RADEON_PURGE_ZCACHE();
1024 RADEON_WAIT_UNTIL_IDLE();
1025
1026 ADVANCE_RING();
1027 COMMIT_RING();
1028}
1029
1030/* Reset the Command Processor. This will not flush any pending
1031 * commands, so you must wait for the CP command stream to complete
1032 * before calling this routine.
1033 */
b5e89ed5 1034static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1035{
1036 u32 cur_read_ptr;
b5e89ed5 1037 DRM_DEBUG("\n");
1da177e4 1038
b5e89ed5
DA		 1039 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1040 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1041 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 1042 dev_priv->ring.tail = cur_read_ptr;
1043}
1044
1045/* Stop the Command Processor. This will not flush any pending
1046 * commands, so you must flush the command stream and wait for the CP
1047 * to go idle before calling this routine.
1048 */
b5e89ed5 1049static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1da177e4 1050{
b5e89ed5 1051 DRM_DEBUG("\n");
1da177e4 1052
b5e89ed5 1053 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1da177e4
LT		 1054
1055 dev_priv->cp_running = 0;
1056}
1057
1058/* Reset the engine. This will stop the CP if it is running.
1059 */
b5e89ed5 1060static int radeon_do_engine_reset(drm_device_t * dev)
1da177e4
LT		 1061{
1062 drm_radeon_private_t *dev_priv = dev->dev_private;
1063 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
b5e89ed5 1064 DRM_DEBUG("\n");
1da177e4 1065
b5e89ed5
DA		 1066 radeon_do_pixcache_flush(dev_priv);
1067
1068 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1069 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1070
1071 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1072 RADEON_FORCEON_MCLKA |
1073 RADEON_FORCEON_MCLKB |
1074 RADEON_FORCEON_YCLKA |
1075 RADEON_FORCEON_YCLKB |
1076 RADEON_FORCEON_MC |
1077 RADEON_FORCEON_AIC));
1078
1079 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1080
1081 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1082 RADEON_SOFT_RESET_CP |
1083 RADEON_SOFT_RESET_HI |
1084 RADEON_SOFT_RESET_SE |
1085 RADEON_SOFT_RESET_RE |
1086 RADEON_SOFT_RESET_PP |
1087 RADEON_SOFT_RESET_E2 |
1088 RADEON_SOFT_RESET_RB));
1089 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1090 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1091 ~(RADEON_SOFT_RESET_CP |
1da177e4
LT		 1092 RADEON_SOFT_RESET_HI |
1093 RADEON_SOFT_RESET_SE |
1094 RADEON_SOFT_RESET_RE |
1095 RADEON_SOFT_RESET_PP |
1096 RADEON_SOFT_RESET_E2 |
b5e89ed5
DA		 1097 RADEON_SOFT_RESET_RB)));
1098 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1099
1100 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1101 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1102 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1da177e4
LT		 1103
1104 /* Reset the CP ring */
b5e89ed5 1105 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1106
1107 /* The CP is no longer running after an engine reset */
1108 dev_priv->cp_running = 0;
1109
1110 /* Reset any pending vertex, indirect buffers */
b5e89ed5 1111 radeon_freelist_reset(dev);
1da177e4
LT		 1112
1113 return 0;
1114}
1115
b5e89ed5
DA		 1116static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1117 drm_radeon_private_t * dev_priv)
1da177e4
LT		 1118{
1119 u32 ring_start, cur_read_ptr;
1120 u32 tmp;
d5ea702f
DA		 1121
1122 /* Initialize the memory controller. With new memory map, the fb location
1123 * is not changed, it should have been properly initialized already. Part
1124 * of the problem is that the code below is bogus, assuming the GART is
1125 * always appended to the fb which is not necessarily the case
1126 */
1127 if (!dev_priv->new_memmap)
1128 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1129 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1130 | (dev_priv->fb_location >> 16));
1da177e4
LT		 1131
1132#if __OS_HAS_AGP
d985c108 1133 if (dev_priv->flags & CHIP_IS_AGP) {
d5ea702f 1134 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
b5e89ed5
DA		 1135 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1136 (((dev_priv->gart_vm_start - 1 +
1137 dev_priv->gart_size) & 0xffff0000) |
1138 (dev_priv->gart_vm_start >> 16)));
1da177e4
LT		 1139
1140 ring_start = (dev_priv->cp_ring->offset
1141 - dev->agp->base
1142 + dev_priv->gart_vm_start);
b0917bd9 1143 } else
1da177e4
LT		 1144#endif
1145 ring_start = (dev_priv->cp_ring->offset
b0917bd9 1146 - (unsigned long)dev->sg->virtual
1da177e4
LT		 1147 + dev_priv->gart_vm_start);
1148
b5e89ed5 1149 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1da177e4
LT		 1150
1151 /* Set the write pointer delay */
b5e89ed5 1152 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1da177e4
LT		 1153
1154 /* Initialize the ring buffer's read and write pointers */
b5e89ed5
DA		 1155 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1156 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1157 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 1158 dev_priv->ring.tail = cur_read_ptr;
1159
1160#if __OS_HAS_AGP
d985c108 1161 if (dev_priv->flags & CHIP_IS_AGP) {
b5e89ed5
DA		 1162 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1163 dev_priv->ring_rptr->offset
1164 - dev->agp->base + dev_priv->gart_vm_start);
1da177e4
LT		 1165 } else
1166#endif
1167 {
1168 drm_sg_mem_t *entry = dev->sg;
1169 unsigned long tmp_ofs, page_ofs;
1170
b0917bd9
IK		 1171 tmp_ofs = dev_priv->ring_rptr->offset -
1172 (unsigned long)dev->sg->virtual;
1da177e4
LT		 1173 page_ofs = tmp_ofs >> PAGE_SHIFT;
1174
b5e89ed5
DA		 1175 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1176 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1177 (unsigned long)entry->busaddr[page_ofs],
1178 entry->handle + tmp_ofs);
1da177e4
LT		 1179 }
1180
d5ea702f
DA		 1181 /* Set ring buffer size */
1182#ifdef __BIG_ENDIAN
1183 RADEON_WRITE(RADEON_CP_RB_CNTL,
1184 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1185#else
1186 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1187#endif
1188
1189 /* Start with assuming that writeback doesn't work */
1190 dev_priv->writeback_works = 0;
1191
1da177e4
LT		 1192 /* Initialize the scratch register pointer. This will cause
1193 * the scratch register values to be written out to memory
1194 * whenever they are updated.
1195 *
1196 * We simply put this behind the ring read pointer, this works
1197 * with PCI GART as well as (whatever kind of) AGP GART
1198 */
b5e89ed5
DA		 1199 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1200 + RADEON_SCRATCH_REG_OFFSET);
1da177e4
LT		 1201
1202 dev_priv->scratch = ((__volatile__ u32 *)
1203 dev_priv->ring_rptr->handle +
1204 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1205
b5e89ed5 1206 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1da177e4 1207
d5ea702f
DA		 1208 /* Turn on bus mastering */
1209 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1210 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1da177e4
LT		 1211
1212 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
b5e89ed5 1213 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1da177e4
LT		 1214
1215 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
b5e89ed5
DA		 1216 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1217 dev_priv->sarea_priv->last_dispatch);
1da177e4
LT		 1218
1219 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
b5e89ed5 1220 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1da177e4 1221
b5e89ed5 1222 radeon_do_wait_for_idle(dev_priv);
1da177e4 1223
1da177e4 1224 /* Sync everything up */
b5e89ed5
DA		 1225 RADEON_WRITE(RADEON_ISYNC_CNTL,
1226 (RADEON_ISYNC_ANY2D_IDLE3D |
1227 RADEON_ISYNC_ANY3D_IDLE2D |
1228 RADEON_ISYNC_WAIT_IDLEGUI |
1229 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
d5ea702f
DA		 1230
1231}
1232
1233static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1234{
1235 u32 tmp;
1236
1237 /* Writeback doesn't seem to work everywhere, test it here and possibly
1238 * enable it if it appears to work
1239 */
1240 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1241 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1242
1243 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1244 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1245 0xdeadbeef)
1246 break;
1247 DRM_UDELAY(1);
1248 }
1249
1250 if (tmp < dev_priv->usec_timeout) {
1251 dev_priv->writeback_works = 1;
1252 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1253 } else {
1254 dev_priv->writeback_works = 0;
1255 DRM_INFO("writeback test failed\n");
1256 }
1257 if (radeon_no_wb == 1) {
1258 dev_priv->writeback_works = 0;
1259 DRM_INFO("writeback forced off\n");
1260 }
1da177e4
LT		 1261}
1262
ea98a92f
DA		 1263/* Enable or disable PCI-E GART on the chip */
1264static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1265{
1266 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1267 if (on) {
1268
1269 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
b5e89ed5
DA		 1270 dev_priv->gart_vm_start,
1271 (long)dev_priv->gart_info.bus_addr,
ea98a92f 1272 dev_priv->gart_size);
b5e89ed5
DA		 1273 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1274 dev_priv->gart_vm_start);
1275 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1276 dev_priv->gart_info.bus_addr);
1277 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1278 dev_priv->gart_vm_start);
1279 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1280 dev_priv->gart_vm_start +
1281 dev_priv->gart_size - 1);
1282
ea98a92f 1283 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
b5e89ed5
DA		 1284
1285 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1286 RADEON_PCIE_TX_GART_EN);
ea98a92f 1287 } else {
b5e89ed5
DA		 1288 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1289 tmp & ~RADEON_PCIE_TX_GART_EN);
ea98a92f 1290 }
1da177e4
LT		 1291}
1292
1293/* Enable or disable PCI GART on the chip */
b5e89ed5 1294static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1da177e4 1295{
d985c108 1296 u32 tmp;
1da177e4 1297
b5e89ed5 1298 if (dev_priv->flags & CHIP_IS_PCIE) {
ea98a92f
DA		 1299 radeon_set_pciegart(dev_priv, on);
1300 return;
1301 }
1da177e4 1302
d985c108
DA		 1303 tmp = RADEON_READ(RADEON_AIC_CNTL);
1304
b5e89ed5
DA		 1305 if (on) {
1306 RADEON_WRITE(RADEON_AIC_CNTL,
1307 tmp | RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1308
1309 /* set PCI GART page-table base address
1310 */
ea98a92f 1311 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1da177e4
LT		 1312
1313 /* set address range for PCI address translate
1314 */
b5e89ed5
DA		 1315 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1316 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1317 + dev_priv->gart_size - 1);
1da177e4
LT		 1318
1319 /* Turn off AGP aperture -- is this required for PCI GART?
1320 */
b5e89ed5
DA		 1321 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1322 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1da177e4 1323 } else {
b5e89ed5
DA		 1324 RADEON_WRITE(RADEON_AIC_CNTL,
1325 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1326 }
1327}
1328
b5e89ed5 1329static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1da177e4 1330{
d985c108
DA		 1331 drm_radeon_private_t *dev_priv = dev->dev_private;
1332
b5e89ed5 1333 DRM_DEBUG("\n");
1da177e4 1334
f3dd5c37
DA		 1335 /* if we require new memory map but we don't have it fail */
1336 if ((dev_priv->flags & CHIP_NEW_MEMMAP) && !dev_priv->new_memmap)
1337 {
1338 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX\n");
1339 radeon_do_cleanup_cp(dev);
1340 return DRM_ERR(EINVAL);
1341 }
1342
d985c108
DA		 1343 if (init->is_pci && (dev_priv->flags & CHIP_IS_AGP))
1344 {
1345 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1346 dev_priv->flags &= ~CHIP_IS_AGP;
1347 }
1da177e4 1348
d985c108 1349 if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
b5e89ed5 1350 DRM_ERROR("PCI GART memory not allocated!\n");
1da177e4
LT		 1351 radeon_do_cleanup_cp(dev);
1352 return DRM_ERR(EINVAL);
1353 }
1354
1355 dev_priv->usec_timeout = init->usec_timeout;
b5e89ed5
DA		 1356 if (dev_priv->usec_timeout < 1 ||
1357 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1358 DRM_DEBUG("TIMEOUT problem!\n");
1da177e4
LT		 1359 radeon_do_cleanup_cp(dev);
1360 return DRM_ERR(EINVAL);
1361 }
1362
d985c108 1363 switch(init->func) {
1da177e4 1364 case RADEON_INIT_R200_CP:
b5e89ed5 1365 dev_priv->microcode_version = UCODE_R200;
1da177e4
LT		 1366 break;
1367 case RADEON_INIT_R300_CP:
b5e89ed5 1368 dev_priv->microcode_version = UCODE_R300;
1da177e4
LT		 1369 break;
1370 default:
b5e89ed5 1371 dev_priv->microcode_version = UCODE_R100;
1da177e4 1372 }
b5e89ed5 1373
1da177e4
LT		 1374 dev_priv->do_boxes = 0;
1375 dev_priv->cp_mode = init->cp_mode;
1376
1377 /* We don't support anything other than bus-mastering ring mode,
1378 * but the ring can be in either AGP or PCI space for the ring
1379 * read pointer.
1380 */
b5e89ed5
DA		 1381 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1382 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1383 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1da177e4
LT		 1384 radeon_do_cleanup_cp(dev);
1385 return DRM_ERR(EINVAL);
1386 }
1387
b5e89ed5 1388 switch (init->fb_bpp) {
1da177e4
LT		 1389 case 16:
1390 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1391 break;
1392 case 32:
1393 default:
1394 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1395 break;
1396 }
b5e89ed5
DA		 1397 dev_priv->front_offset = init->front_offset;
1398 dev_priv->front_pitch = init->front_pitch;
1399 dev_priv->back_offset = init->back_offset;
1400 dev_priv->back_pitch = init->back_pitch;
1da177e4 1401
b5e89ed5 1402 switch (init->depth_bpp) {
1da177e4
LT		 1403 case 16:
1404 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1405 break;
1406 case 32:
1407 default:
1408 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1409 break;
1410 }
b5e89ed5
DA		 1411 dev_priv->depth_offset = init->depth_offset;
1412 dev_priv->depth_pitch = init->depth_pitch;
1da177e4
LT		 1413
1414 /* Hardware state for depth clears. Remove this if/when we no
1415 * longer clear the depth buffer with a 3D rectangle. Hard-code
1416 * all values to prevent unwanted 3D state from slipping through
1417 * and screwing with the clear operation.
1418 */
1419 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1420 (dev_priv->color_fmt << 10) |
b5e89ed5
DA		 1421 (dev_priv->microcode_version ==
1422 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1da177e4 1423
b5e89ed5
DA		 1424 dev_priv->depth_clear.rb3d_zstencilcntl =
1425 (dev_priv->depth_fmt |
1426 RADEON_Z_TEST_ALWAYS |
1427 RADEON_STENCIL_TEST_ALWAYS |
1428 RADEON_STENCIL_S_FAIL_REPLACE |
1429 RADEON_STENCIL_ZPASS_REPLACE |
1430 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1da177e4
LT		 1431
1432 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1433 RADEON_BFACE_SOLID |
1434 RADEON_FFACE_SOLID |
1435 RADEON_FLAT_SHADE_VTX_LAST |
1436 RADEON_DIFFUSE_SHADE_FLAT |
1437 RADEON_ALPHA_SHADE_FLAT |
1438 RADEON_SPECULAR_SHADE_FLAT |
1439 RADEON_FOG_SHADE_FLAT |
1440 RADEON_VTX_PIX_CENTER_OGL |
1441 RADEON_ROUND_MODE_TRUNC |
1442 RADEON_ROUND_PREC_8TH_PIX);
1443
1444 DRM_GETSAREA();
1445
1da177e4
LT		 1446 dev_priv->ring_offset = init->ring_offset;
1447 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1448 dev_priv->buffers_offset = init->buffers_offset;
1449 dev_priv->gart_textures_offset = init->gart_textures_offset;
b5e89ed5
DA		 1450
1451 if (!dev_priv->sarea) {
1da177e4 1452 DRM_ERROR("could not find sarea!\n");
1da177e4
LT		 1453 radeon_do_cleanup_cp(dev);
1454 return DRM_ERR(EINVAL);
1455 }
1456
1da177e4 1457 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
b5e89ed5 1458 if (!dev_priv->cp_ring) {
1da177e4 1459 DRM_ERROR("could not find cp ring region!\n");
1da177e4
LT		 1460 radeon_do_cleanup_cp(dev);
1461 return DRM_ERR(EINVAL);
1462 }
1463 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
b5e89ed5 1464 if (!dev_priv->ring_rptr) {
1da177e4 1465 DRM_ERROR("could not find ring read pointer!\n");
1da177e4
LT		 1466 radeon_do_cleanup_cp(dev);
1467 return DRM_ERR(EINVAL);
1468 }
d1f2b55a 1469 dev->agp_buffer_token = init->buffers_offset;
1da177e4 1470 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
b5e89ed5 1471 if (!dev->agp_buffer_map) {
1da177e4 1472 DRM_ERROR("could not find dma buffer region!\n");
1da177e4
LT		 1473 radeon_do_cleanup_cp(dev);
1474 return DRM_ERR(EINVAL);
1475 }
1476
b5e89ed5
DA		 1477 if (init->gart_textures_offset) {
1478 dev_priv->gart_textures =
1479 drm_core_findmap(dev, init->gart_textures_offset);
1480 if (!dev_priv->gart_textures) {
1da177e4 1481 DRM_ERROR("could not find GART texture region!\n");
1da177e4
LT		 1482 radeon_do_cleanup_cp(dev);
1483 return DRM_ERR(EINVAL);
1484 }
1485 }
1486
1487 dev_priv->sarea_priv =
b5e89ed5
DA		 1488 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1489 init->sarea_priv_offset);
1da177e4
LT		 1490
1491#if __OS_HAS_AGP
d985c108 1492 if (dev_priv->flags & CHIP_IS_AGP) {
b5e89ed5
DA		 1493 drm_core_ioremap(dev_priv->cp_ring, dev);
1494 drm_core_ioremap(dev_priv->ring_rptr, dev);
1495 drm_core_ioremap(dev->agp_buffer_map, dev);
1496 if (!dev_priv->cp_ring->handle ||
1497 !dev_priv->ring_rptr->handle ||
1498 !dev->agp_buffer_map->handle) {
1da177e4 1499 DRM_ERROR("could not find ioremap agp regions!\n");
1da177e4
LT		 1500 radeon_do_cleanup_cp(dev);
1501 return DRM_ERR(EINVAL);
1502 }
1503 } else
1504#endif
1505 {
b5e89ed5 1506 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1da177e4 1507 dev_priv->ring_rptr->handle =
b5e89ed5
DA		 1508 (void *)dev_priv->ring_rptr->offset;
1509 dev->agp_buffer_map->handle =
1510 (void *)dev->agp_buffer_map->offset;
1511
1512 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1513 dev_priv->cp_ring->handle);
1514 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1515 dev_priv->ring_rptr->handle);
1516 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1517 dev->agp_buffer_map->handle);
1da177e4
LT		 1518 }
1519
b5e89ed5
DA		 1520 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1521 & 0xffff) << 16;
d5ea702f
DA		 1522 dev_priv->fb_size =
1523 ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
1524 - dev_priv->fb_location;
1da177e4 1525
b5e89ed5
DA		 1526 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1527 ((dev_priv->front_offset
1528 + dev_priv->fb_location) >> 10));
1da177e4 1529
b5e89ed5
DA		 1530 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1531 ((dev_priv->back_offset
1532 + dev_priv->fb_location) >> 10));
1da177e4 1533
b5e89ed5
DA		 1534 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1535 ((dev_priv->depth_offset
1536 + dev_priv->fb_location) >> 10));
1da177e4
LT		 1537
1538 dev_priv->gart_size = init->gart_size;
d5ea702f
DA		 1539
1540 /* New let's set the memory map ... */
1541 if (dev_priv->new_memmap) {
1542 u32 base = 0;
1543
1544 DRM_INFO("Setting GART location based on new memory map\n");
1545
1546 /* If using AGP, try to locate the AGP aperture at the same
1547 * location in the card and on the bus, though we have to
1548 * align it down.
1549 */
1550#if __OS_HAS_AGP
1551 if (dev_priv->flags & CHIP_IS_AGP) {
1552 base = dev->agp->base;
1553 /* Check if valid */
1554 if ((base + dev_priv->gart_size) > dev_priv->fb_location &&
1555 base < (dev_priv->fb_location + dev_priv->fb_size)) {
1556 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1557 dev->agp->base);
1558 base = 0;
1559 }
1560 }
1561#endif
1562 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1563 if (base == 0) {
1564 base = dev_priv->fb_location + dev_priv->fb_size;
1565 if (((base + dev_priv->gart_size) & 0xfffffffful)
1566 < base)
1567 base = dev_priv->fb_location
1568 - dev_priv->gart_size;
1569 }
1570 dev_priv->gart_vm_start = base & 0xffc00000u;
1571 if (dev_priv->gart_vm_start != base)
1572 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1573 base, dev_priv->gart_vm_start);
1574 } else {
1575 DRM_INFO("Setting GART location based on old memory map\n");
1576 dev_priv->gart_vm_start = dev_priv->fb_location +
1577 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1578 }
1da177e4
LT		 1579
1580#if __OS_HAS_AGP
d985c108 1581 if (dev_priv->flags & CHIP_IS_AGP)
1da177e4 1582 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b5e89ed5
DA		 1583 - dev->agp->base
1584 + dev_priv->gart_vm_start);
1da177e4
LT		 1585 else
1586#endif
1587 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b0917bd9
IK		 1588 - (unsigned long)dev->sg->virtual
1589 + dev_priv->gart_vm_start);
1da177e4 1590
b5e89ed5
DA		 1591 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1592 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1593 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1594 dev_priv->gart_buffers_offset);
1da177e4 1595
b5e89ed5
DA		 1596 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1597 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1da177e4
LT		 1598 + init->ring_size / sizeof(u32));
1599 dev_priv->ring.size = init->ring_size;
b5e89ed5 1600 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1da177e4 1601
b5e89ed5 1602 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1da177e4
LT		 1603
1604 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1605
1606#if __OS_HAS_AGP
d985c108 1607 if (dev_priv->flags & CHIP_IS_AGP) {
1da177e4 1608 /* Turn off PCI GART */
b5e89ed5 1609 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1610 } else
1611#endif
1612 {
ea98a92f
DA		 1613 /* if we have an offset set from userspace */
1614 if (dev_priv->pcigart_offset) {
b5e89ed5
DA		 1615 dev_priv->gart_info.bus_addr =
1616 dev_priv->pcigart_offset + dev_priv->fb_location;
f26c473c
DA		 1617 dev_priv->gart_info.mapping.offset =
1618 dev_priv->gart_info.bus_addr;
1619 dev_priv->gart_info.mapping.size =
1620 RADEON_PCIGART_TABLE_SIZE;
1621
1622 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
b5e89ed5 1623 dev_priv->gart_info.addr =
f26c473c 1624 dev_priv->gart_info.mapping.handle;
b5e89ed5
DA		 1625
1626 dev_priv->gart_info.is_pcie =
1627 !!(dev_priv->flags & CHIP_IS_PCIE);
1628 dev_priv->gart_info.gart_table_location =
1629 DRM_ATI_GART_FB;
1630
f26c473c 1631 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
b5e89ed5
DA		 1632 dev_priv->gart_info.addr,
1633 dev_priv->pcigart_offset);
1634 } else {
1635 dev_priv->gart_info.gart_table_location =
1636 DRM_ATI_GART_MAIN;
f26c473c
DA		 1637 dev_priv->gart_info.addr = NULL;
1638 dev_priv->gart_info.bus_addr = 0;
b5e89ed5
DA		 1639 if (dev_priv->flags & CHIP_IS_PCIE) {
1640 DRM_ERROR
1641 ("Cannot use PCI Express without GART in FB memory\n");
ea98a92f
DA		 1642 radeon_do_cleanup_cp(dev);
1643 return DRM_ERR(EINVAL);
1644 }
1645 }
1646
1647 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
b5e89ed5 1648 DRM_ERROR("failed to init PCI GART!\n");
1da177e4
LT		 1649 radeon_do_cleanup_cp(dev);
1650 return DRM_ERR(ENOMEM);
1651 }
1652
1653 /* Turn on PCI GART */
b5e89ed5 1654 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1655 }
1656
b5e89ed5
DA		 1657 radeon_cp_load_microcode(dev_priv);
1658 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4
LT		 1659
1660 dev_priv->last_buf = 0;
1661
b5e89ed5 1662 radeon_do_engine_reset(dev);
d5ea702f 1663 radeon_test_writeback(dev_priv);
1da177e4
LT		 1664
1665 return 0;
1666}
1667
b5e89ed5 1668static int radeon_do_cleanup_cp(drm_device_t * dev)
1da177e4
LT		 1669{
1670 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1671 DRM_DEBUG("\n");
1da177e4
LT		 1672
1673 /* Make sure interrupts are disabled here because the uninstall ioctl
1674 * may not have been called from userspace and after dev_private
1675 * is freed, it's too late.
1676 */
b5e89ed5
DA		 1677 if (dev->irq_enabled)
1678 drm_irq_uninstall(dev);
1da177e4
LT		 1679
1680#if __OS_HAS_AGP
d985c108
DA		 1681 if (dev_priv->flags & CHIP_IS_AGP) {
1682 if (dev_priv->cp_ring != NULL) {
b5e89ed5 1683 drm_core_ioremapfree(dev_priv->cp_ring, dev);
d985c108
DA		 1684 dev_priv->cp_ring = NULL;
1685 }
1686 if (dev_priv->ring_rptr != NULL) {
b5e89ed5 1687 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
d985c108
DA		 1688 dev_priv->ring_rptr = NULL;
1689 }
b5e89ed5
DA		 1690 if (dev->agp_buffer_map != NULL) {
1691 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1da177e4
LT		 1692 dev->agp_buffer_map = NULL;
1693 }
1694 } else
1695#endif
1696 {
d985c108
DA		 1697
1698 if (dev_priv->gart_info.bus_addr) {
1699 /* Turn off PCI GART */
1700 radeon_set_pcigart(dev_priv, 0);
ea98a92f
DA		 1701 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1702 DRM_ERROR("failed to cleanup PCI GART!\n");
d985c108 1703 }
b5e89ed5 1704
d985c108
DA		 1705 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1706 {
f26c473c 1707 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
d59cc22f 1708 dev_priv->gart_info.addr = NULL;
ea98a92f 1709 }
1da177e4 1710 }
1da177e4
LT		 1711 /* only clear to the start of flags */
1712 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1713
1714 return 0;
1715}
1716
b5e89ed5
DA		 1717/* This code will reinit the Radeon CP hardware after a resume from disc.
1718 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1da177e4
LT		 1719 * here we make sure that all Radeon hardware initialisation is re-done without
1720 * affecting running applications.
1721 *
1722 * Charl P. Botha <http://cpbotha.net>
1723 */
b5e89ed5 1724static int radeon_do_resume_cp(drm_device_t * dev)
1da177e4
LT		 1725{
1726 drm_radeon_private_t *dev_priv = dev->dev_private;
1727
b5e89ed5
DA		 1728 if (!dev_priv) {
1729 DRM_ERROR("Called with no initialization\n");
1730 return DRM_ERR(EINVAL);
1da177e4
LT		 1731 }
1732
1733 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1734
1735#if __OS_HAS_AGP
d985c108 1736 if (dev_priv->flags & CHIP_IS_AGP) {
1da177e4 1737 /* Turn off PCI GART */
b5e89ed5 1738 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1739 } else
1740#endif
1741 {
1742 /* Turn on PCI GART */
b5e89ed5 1743 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1744 }
1745
b5e89ed5
DA		 1746 radeon_cp_load_microcode(dev_priv);
1747 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4 1748
b5e89ed5 1749 radeon_do_engine_reset(dev);
1da177e4
LT		 1750
1751 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1752
1753 return 0;
1754}
1755
b5e89ed5 1756int radeon_cp_init(DRM_IOCTL_ARGS)
1da177e4
LT		 1757{
1758 DRM_DEVICE;
1759 drm_radeon_init_t init;
1760
b5e89ed5 1761 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1762
b5e89ed5
DA		 1763 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1764 sizeof(init));
1da177e4 1765
b5e89ed5 1766 if (init.func == RADEON_INIT_R300_CP)
414ed537
DA		 1767 r300_init_reg_flags();
1768
b5e89ed5 1769 switch (init.func) {
1da177e4
LT		 1770 case RADEON_INIT_CP:
1771 case RADEON_INIT_R200_CP:
1772 case RADEON_INIT_R300_CP:
b5e89ed5 1773 return radeon_do_init_cp(dev, &init);
1da177e4 1774 case RADEON_CLEANUP_CP:
b5e89ed5 1775 return radeon_do_cleanup_cp(dev);
1da177e4
LT		 1776 }
1777
1778 return DRM_ERR(EINVAL);
1779}
1780
b5e89ed5 1781int radeon_cp_start(DRM_IOCTL_ARGS)
1da177e4
LT		 1782{
1783 DRM_DEVICE;
1784 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1785 DRM_DEBUG("\n");
1da177e4 1786
b5e89ed5 1787 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1788
b5e89ed5
DA		 1789 if (dev_priv->cp_running) {
1790 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1da177e4
LT		 1791 return 0;
1792 }
b5e89ed5
DA		 1793 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1794 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1795 __FUNCTION__, dev_priv->cp_mode);
1da177e4
LT		 1796 return 0;
1797 }
1798
b5e89ed5 1799 radeon_do_cp_start(dev_priv);
1da177e4
LT		 1800
1801 return 0;
1802}
1803
1804/* Stop the CP. The engine must have been idled before calling this
1805 * routine.
1806 */
b5e89ed5 1807int radeon_cp_stop(DRM_IOCTL_ARGS)
1da177e4
LT		 1808{
1809 DRM_DEVICE;
1810 drm_radeon_private_t *dev_priv = dev->dev_private;
1811 drm_radeon_cp_stop_t stop;
1812 int ret;
b5e89ed5 1813 DRM_DEBUG("\n");
1da177e4 1814
b5e89ed5 1815 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1816
b5e89ed5
DA		 1817 DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1818 sizeof(stop));
1da177e4
LT		 1819
1820 if (!dev_priv->cp_running)
1821 return 0;
1822
1823 /* Flush any pending CP commands. This ensures any outstanding
1824 * commands are exectuted by the engine before we turn it off.
1825 */
b5e89ed5
DA		 1826 if (stop.flush) {
1827 radeon_do_cp_flush(dev_priv);
1da177e4
LT		 1828 }
1829
1830 /* If we fail to make the engine go idle, we return an error
1831 * code so that the DRM ioctl wrapper can try again.
1832 */
b5e89ed5
DA		 1833 if (stop.idle) {
1834 ret = radeon_do_cp_idle(dev_priv);
1835 if (ret)
1836 return ret;
1da177e4
LT		 1837 }
1838
1839 /* Finally, we can turn off the CP. If the engine isn't idle,
1840 * we will get some dropped triangles as they won't be fully
1841 * rendered before the CP is shut down.
1842 */
b5e89ed5 1843 radeon_do_cp_stop(dev_priv);
1da177e4
LT		 1844
1845 /* Reset the engine */
b5e89ed5 1846 radeon_do_engine_reset(dev);
1da177e4
LT		 1847
1848 return 0;
1849}
1850
b5e89ed5 1851void radeon_do_release(drm_device_t * dev)
1da177e4
LT		 1852{
1853 drm_radeon_private_t *dev_priv = dev->dev_private;
1854 int i, ret;
1855
1856 if (dev_priv) {
1857 if (dev_priv->cp_running) {
1858 /* Stop the cp */
b5e89ed5 1859 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1da177e4
LT		 1860 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1861#ifdef __linux__
1862 schedule();
1863#else
1864 tsleep(&ret, PZERO, "rdnrel", 1);
1865#endif
1866 }
b5e89ed5
DA		 1867 radeon_do_cp_stop(dev_priv);
1868 radeon_do_engine_reset(dev);
1da177e4
LT		 1869 }
1870
1871 /* Disable *all* interrupts */
1872 if (dev_priv->mmio) /* remove this after permanent addmaps */
b5e89ed5 1873 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1da177e4 1874
b5e89ed5 1875 if (dev_priv->mmio) { /* remove all surfaces */
1da177e4 1876 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
b5e89ed5
DA		 1877 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1878 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1879 16 * i, 0);
1880 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1881 16 * i, 0);
1da177e4
LT		 1882 }
1883 }
1884
1885 /* Free memory heap structures */
b5e89ed5
DA		 1886 radeon_mem_takedown(&(dev_priv->gart_heap));
1887 radeon_mem_takedown(&(dev_priv->fb_heap));
1da177e4
LT		 1888
1889 /* deallocate kernel resources */
b5e89ed5 1890 radeon_do_cleanup_cp(dev);
1da177e4
LT		 1891 }
1892}
1893
1894/* Just reset the CP ring. Called as part of an X Server engine reset.
1895 */
b5e89ed5 1896int radeon_cp_reset(DRM_IOCTL_ARGS)
1da177e4
LT		 1897{
1898 DRM_DEVICE;
1899 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1900 DRM_DEBUG("\n");
1da177e4 1901
b5e89ed5 1902 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1903
b5e89ed5
DA		 1904 if (!dev_priv) {
1905 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1da177e4
LT		 1906 return DRM_ERR(EINVAL);
1907 }
1908
b5e89ed5 1909 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1910
1911 /* The CP is no longer running after an engine reset */
1912 dev_priv->cp_running = 0;
1913
1914 return 0;
1915}
1916
b5e89ed5 1917int radeon_cp_idle(DRM_IOCTL_ARGS)
1da177e4
LT		 1918{
1919 DRM_DEVICE;
1920 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1921 DRM_DEBUG("\n");
1da177e4 1922
b5e89ed5 1923 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1924
b5e89ed5 1925 return radeon_do_cp_idle(dev_priv);
1da177e4
LT		 1926}
1927
1928/* Added by Charl P. Botha to call radeon_do_resume_cp().
1929 */
b5e89ed5 1930int radeon_cp_resume(DRM_IOCTL_ARGS)
1da177e4
LT		 1931{
1932 DRM_DEVICE;
1933
1934 return radeon_do_resume_cp(dev);
1935}
1936
b5e89ed5 1937int radeon_engine_reset(DRM_IOCTL_ARGS)
1da177e4
LT		 1938{
1939 DRM_DEVICE;
b5e89ed5 1940 DRM_DEBUG("\n");
1da177e4 1941
b5e89ed5 1942 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 1943
b5e89ed5 1944 return radeon_do_engine_reset(dev);
1da177e4
LT		 1945}
1946
1da177e4
LT		 1947/* ================================================================
1948 * Fullscreen mode
1949 */
1950
1951/* KW: Deprecated to say the least:
1952 */
b5e89ed5 1953int radeon_fullscreen(DRM_IOCTL_ARGS)
1da177e4
LT		 1954{
1955 return 0;
1956}
1957
1da177e4
LT		 1958/* ================================================================
1959 * Freelist management
1960 */
1961
1962/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1963 * bufs until freelist code is used. Note this hides a problem with
1964 * the scratch register * (used to keep track of last buffer
1965 * completed) being written to before * the last buffer has actually
b5e89ed5 1966 * completed rendering.
1da177e4
LT		 1967 *
1968 * KW: It's also a good way to find free buffers quickly.
1969 *
1970 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1971 * sleep. However, bugs in older versions of radeon_accel.c mean that
1972 * we essentially have to do this, else old clients will break.
b5e89ed5 1973 *
1da177e4
LT		 1974 * However, it does leave open a potential deadlock where all the
1975 * buffers are held by other clients, which can't release them because
b5e89ed5 1976 * they can't get the lock.
1da177e4
LT		 1977 */
1978
b5e89ed5 1979drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1da177e4
LT		 1980{
1981 drm_device_dma_t *dma = dev->dma;
1982 drm_radeon_private_t *dev_priv = dev->dev_private;
1983 drm_radeon_buf_priv_t *buf_priv;
1984 drm_buf_t *buf;
1985 int i, t;
1986 int start;
1987
b5e89ed5 1988 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 1989 dev_priv->last_buf = 0;
1990
1991 start = dev_priv->last_buf;
1992
b5e89ed5
DA		 1993 for (t = 0; t < dev_priv->usec_timeout; t++) {
1994 u32 done_age = GET_SCRATCH(1);
1995 DRM_DEBUG("done_age = %d\n", done_age);
1996 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 1997 buf = dma->buflist[i];
1998 buf_priv = buf->dev_private;
b5e89ed5
DA		 1999 if (buf->filp == 0 || (buf->pending &&
2000 buf_priv->age <= done_age)) {
1da177e4
LT		 2001 dev_priv->stats.requested_bufs++;
2002 buf->pending = 0;
2003 return buf;
2004 }
2005 start = 0;
2006 }
2007
2008 if (t) {
b5e89ed5 2009 DRM_UDELAY(1);
1da177e4
LT		 2010 dev_priv->stats.freelist_loops++;
2011 }
2012 }
2013
b5e89ed5 2014 DRM_DEBUG("returning NULL!\n");
1da177e4
LT		 2015 return NULL;
2016}
b5e89ed5 2017
1da177e4 2018#if 0
b5e89ed5 2019drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1da177e4
LT		 2020{
2021 drm_device_dma_t *dma = dev->dma;
2022 drm_radeon_private_t *dev_priv = dev->dev_private;
2023 drm_radeon_buf_priv_t *buf_priv;
2024 drm_buf_t *buf;
2025 int i, t;
2026 int start;
2027 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2028
b5e89ed5 2029 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 2030 dev_priv->last_buf = 0;
2031
2032 start = dev_priv->last_buf;
2033 dev_priv->stats.freelist_loops++;
b5e89ed5
DA		 2034
2035 for (t = 0; t < 2; t++) {
2036 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 2037 buf = dma->buflist[i];
2038 buf_priv = buf->dev_private;
b5e89ed5
DA		 2039 if (buf->filp == 0 || (buf->pending &&
2040 buf_priv->age <= done_age)) {
1da177e4
LT		 2041 dev_priv->stats.requested_bufs++;
2042 buf->pending = 0;
2043 return buf;
2044 }
2045 }
2046 start = 0;
2047 }
2048
2049 return NULL;
2050}
2051#endif
2052
b5e89ed5 2053void radeon_freelist_reset(drm_device_t * dev)
1da177e4
LT		 2054{
2055 drm_device_dma_t *dma = dev->dma;
2056 drm_radeon_private_t *dev_priv = dev->dev_private;
2057 int i;
2058
2059 dev_priv->last_buf = 0;
b5e89ed5 2060 for (i = 0; i < dma->buf_count; i++) {
1da177e4
LT		 2061 drm_buf_t *buf = dma->buflist[i];
2062 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2063 buf_priv->age = 0;
2064 }
2065}
2066
1da177e4
LT		 2067/* ================================================================
2068 * CP command submission
2069 */
2070
b5e89ed5 2071int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1da177e4
LT		 2072{
2073 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2074 int i;
b5e89ed5 2075 u32 last_head = GET_RING_HEAD(dev_priv);
1da177e4 2076
b5e89ed5
DA		 2077 for (i = 0; i < dev_priv->usec_timeout; i++) {
2078 u32 head = GET_RING_HEAD(dev_priv);
1da177e4
LT		 2079
2080 ring->space = (head - ring->tail) * sizeof(u32);
b5e89ed5 2081 if (ring->space <= 0)
1da177e4 2082 ring->space += ring->size;
b5e89ed5 2083 if (ring->space > n)
1da177e4 2084 return 0;
b5e89ed5 2085
1da177e4
LT		 2086 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2087
2088 if (head != last_head)
2089 i = 0;
2090 last_head = head;
2091
b5e89ed5 2092 DRM_UDELAY(1);
1da177e4
LT		 2093 }
2094
2095 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2096#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 2097 radeon_status(dev_priv);
2098 DRM_ERROR("failed!\n");
1da177e4
LT		 2099#endif
2100 return DRM_ERR(EBUSY);
2101}
2102
b5e89ed5
DA		 2103static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
2104 drm_dma_t * d)
1da177e4
LT		 2105{
2106 int i;
2107 drm_buf_t *buf;
2108
b5e89ed5
DA		 2109 for (i = d->granted_count; i < d->request_count; i++) {
2110 buf = radeon_freelist_get(dev);
2111 if (!buf)
2112 return DRM_ERR(EBUSY); /* NOTE: broken client */
1da177e4
LT		 2113
2114 buf->filp = filp;
2115
b5e89ed5
DA		 2116 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2117 sizeof(buf->idx)))
1da177e4 2118 return DRM_ERR(EFAULT);
b5e89ed5
DA		 2119 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2120 sizeof(buf->total)))
1da177e4
LT		 2121 return DRM_ERR(EFAULT);
2122
2123 d->granted_count++;
2124 }
2125 return 0;
2126}
2127
b5e89ed5 2128int radeon_cp_buffers(DRM_IOCTL_ARGS)
1da177e4
LT		 2129{
2130 DRM_DEVICE;
2131 drm_device_dma_t *dma = dev->dma;
2132 int ret = 0;
2133 drm_dma_t __user *argp = (void __user *)data;
2134 drm_dma_t d;
2135
b5e89ed5 2136 LOCK_TEST_WITH_RETURN(dev, filp);
1da177e4 2137
b5e89ed5 2138 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1da177e4
LT		 2139
2140 /* Please don't send us buffers.
2141 */
b5e89ed5
DA		 2142 if (d.send_count != 0) {
2143 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2144 DRM_CURRENTPID, d.send_count);
1da177e4
LT		 2145 return DRM_ERR(EINVAL);
2146 }
2147
2148 /* We'll send you buffers.
2149 */
b5e89ed5
DA		 2150 if (d.request_count < 0 || d.request_count > dma->buf_count) {
2151 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2152 DRM_CURRENTPID, d.request_count, dma->buf_count);
1da177e4
LT		 2153 return DRM_ERR(EINVAL);
2154 }
2155
2156 d.granted_count = 0;
2157
b5e89ed5
DA		 2158 if (d.request_count) {
2159 ret = radeon_cp_get_buffers(filp, dev, &d);
1da177e4
LT		 2160 }
2161
b5e89ed5 2162 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
1da177e4
LT		 2163
2164 return ret;
2165}
2166
22eae947 2167int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1da177e4
LT		 2168{
2169 drm_radeon_private_t *dev_priv;
2170 int ret = 0;
2171
2172 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2173 if (dev_priv == NULL)
2174 return DRM_ERR(ENOMEM);
2175
2176 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2177 dev->dev_private = (void *)dev_priv;
2178 dev_priv->flags = flags;
2179
2180 switch (flags & CHIP_FAMILY_MASK) {
2181 case CHIP_R100:
2182 case CHIP_RV200:
2183 case CHIP_R200:
2184 case CHIP_R300:
414ed537 2185 case CHIP_R420:
1da177e4
LT		 2186 dev_priv->flags |= CHIP_HAS_HIERZ;
2187 break;
2188 default:
b5e89ed5 2189 /* all other chips have no hierarchical z buffer */
1da177e4
LT		 2190 break;
2191 }
414ed537
DA		 2192
2193 if (drm_device_is_agp(dev))
2194 dev_priv->flags |= CHIP_IS_AGP;
b5e89ed5 2195
ea98a92f
DA		 2196 if (drm_device_is_pcie(dev))
2197 dev_priv->flags |= CHIP_IS_PCIE;
2198
414ed537 2199 DRM_DEBUG("%s card detected\n",
d985c108 2200 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags & CHIP_IS_PCIE) ? "PCIE" : "PCI"))));
1da177e4
LT		 2201 return ret;
2202}
2203
22eae947
DA		 2204/* Create mappings for registers and framebuffer so userland doesn't necessarily
2205 * have to find them.
2206 */
2207int radeon_driver_firstopen(struct drm_device *dev)
836cf046
DA		 2208{
2209 int ret;
2210 drm_local_map_t *map;
2211 drm_radeon_private_t *dev_priv = dev->dev_private;
2212
2213 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2214 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2215 _DRM_READ_ONLY, &dev_priv->mmio);
2216 if (ret != 0)
2217 return ret;
2218
2219 ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2220 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2221 _DRM_WRITE_COMBINING, &map);
2222 if (ret != 0)
2223 return ret;
2224
2225 return 0;
2226}
2227
22eae947 2228int radeon_driver_unload(struct drm_device *dev)
1da177e4
LT		 2229{
2230 drm_radeon_private_t *dev_priv = dev->dev_private;
2231
2232 DRM_DEBUG("\n");
1da177e4
LT		 2233 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2234
2235 dev->dev_private = NULL;
2236 return 0;
2237}
Linux 6.x block layer and io_uring tree(s)