Commit | Line | Data |
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414ed537 DA |
1 | /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*- |
2 | * | |
3 | * Copyright (C) The Weather Channel, Inc. 2002. | |
4 | * Copyright (C) 2004 Nicolai Haehnle. | |
5 | * All Rights Reserved. | |
6 | * | |
7 | * The Weather Channel (TM) funded Tungsten Graphics to develop the | |
8 | * initial release of the Radeon 8500 driver under the XFree86 license. | |
9 | * This notice must be preserved. | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the next | |
19 | * paragraph) shall be included in all copies or substantial portions of the | |
20 | * Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
26 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
27 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | * | |
30 | * Authors: | |
31 | * Nicolai Haehnle <prefect_@gmx.net> | |
32 | */ | |
33 | ||
34 | #include "drmP.h" | |
35 | #include "drm.h" | |
36 | #include "radeon_drm.h" | |
37 | #include "radeon_drv.h" | |
38 | #include "r300_reg.h" | |
39 | ||
414ed537 DA |
40 | #define R300_SIMULTANEOUS_CLIPRECTS 4 |
41 | ||
42 | /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects | |
43 | */ | |
44 | static const int r300_cliprect_cntl[4] = { | |
45 | 0xAAAA, | |
46 | 0xEEEE, | |
47 | 0xFEFE, | |
48 | 0xFFFE | |
49 | }; | |
50 | ||
414ed537 DA |
51 | /** |
52 | * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command | |
53 | * buffer, starting with index n. | |
54 | */ | |
d985c108 DA |
55 | static int r300_emit_cliprects(drm_radeon_private_t *dev_priv, |
56 | drm_radeon_kcmd_buffer_t *cmdbuf, int n) | |
414ed537 DA |
57 | { |
58 | drm_clip_rect_t box; | |
59 | int nr; | |
60 | int i; | |
61 | RING_LOCALS; | |
62 | ||
63 | nr = cmdbuf->nbox - n; | |
64 | if (nr > R300_SIMULTANEOUS_CLIPRECTS) | |
65 | nr = R300_SIMULTANEOUS_CLIPRECTS; | |
66 | ||
67 | DRM_DEBUG("%i cliprects\n", nr); | |
68 | ||
69 | if (nr) { | |
b5e89ed5 DA |
70 | BEGIN_RING(6 + nr * 2); |
71 | OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); | |
414ed537 | 72 | |
b5e89ed5 DA |
73 | for (i = 0; i < nr; ++i) { |
74 | if (DRM_COPY_FROM_USER_UNCHECKED | |
75 | (&box, &cmdbuf->boxes[n + i], sizeof(box))) { | |
414ed537 DA |
76 | DRM_ERROR("copy cliprect faulted\n"); |
77 | return DRM_ERR(EFAULT); | |
78 | } | |
79 | ||
b5e89ed5 DA |
80 | box.x1 = |
81 | (box.x1 + | |
82 | R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; | |
83 | box.y1 = | |
84 | (box.y1 + | |
85 | R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; | |
86 | box.x2 = | |
87 | (box.x2 + | |
88 | R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; | |
89 | box.y2 = | |
90 | (box.y2 + | |
91 | R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; | |
414ed537 DA |
92 | |
93 | OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | | |
b5e89ed5 | 94 | (box.y1 << R300_CLIPRECT_Y_SHIFT)); |
414ed537 | 95 | OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | |
b5e89ed5 | 96 | (box.y2 << R300_CLIPRECT_Y_SHIFT)); |
414ed537 DA |
97 | } |
98 | ||
b5e89ed5 | 99 | OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]); |
414ed537 DA |
100 | |
101 | /* TODO/SECURITY: Force scissors to a safe value, otherwise the | |
b5e89ed5 DA |
102 | * client might be able to trample over memory. |
103 | * The impact should be very limited, but I'd rather be safe than | |
104 | * sorry. | |
105 | */ | |
106 | OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); | |
107 | OUT_RING(0); | |
108 | OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); | |
414ed537 | 109 | ADVANCE_RING(); |
b5e89ed5 | 110 | } else { |
414ed537 DA |
111 | /* Why we allow zero cliprect rendering: |
112 | * There are some commands in a command buffer that must be submitted | |
113 | * even when there are no cliprects, e.g. DMA buffer discard | |
114 | * or state setting (though state setting could be avoided by | |
115 | * simulating a loss of context). | |
116 | * | |
117 | * Now since the cmdbuf interface is so chaotic right now (and is | |
118 | * bound to remain that way for a bit until things settle down), | |
119 | * it is basically impossible to filter out the commands that are | |
120 | * necessary and those that aren't. | |
121 | * | |
122 | * So I choose the safe way and don't do any filtering at all; | |
123 | * instead, I simply set up the engine so that all rendering | |
124 | * can't produce any fragments. | |
125 | */ | |
126 | BEGIN_RING(2); | |
b5e89ed5 | 127 | OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0); |
414ed537 | 128 | ADVANCE_RING(); |
b5e89ed5 | 129 | } |
414ed537 DA |
130 | |
131 | return 0; | |
132 | } | |
133 | ||
b3a83639 | 134 | static u8 r300_reg_flags[0x10000 >> 2]; |
414ed537 DA |
135 | |
136 | void r300_init_reg_flags(void) | |
137 | { | |
138 | int i; | |
b5e89ed5 DA |
139 | memset(r300_reg_flags, 0, 0x10000 >> 2); |
140 | #define ADD_RANGE_MARK(reg, count,mark) \ | |
414ed537 DA |
141 | for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\ |
142 | r300_reg_flags[i]|=(mark); | |
b5e89ed5 DA |
143 | |
144 | #define MARK_SAFE 1 | |
145 | #define MARK_CHECK_OFFSET 2 | |
146 | ||
147 | #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) | |
414ed537 DA |
148 | |
149 | /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */ | |
150 | ADD_RANGE(R300_SE_VPORT_XSCALE, 6); | |
151 | ADD_RANGE(0x2080, 1); | |
152 | ADD_RANGE(R300_SE_VTE_CNTL, 2); | |
153 | ADD_RANGE(0x2134, 2); | |
154 | ADD_RANGE(0x2140, 1); | |
155 | ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2); | |
156 | ADD_RANGE(0x21DC, 1); | |
157 | ADD_RANGE(0x221C, 1); | |
158 | ADD_RANGE(0x2220, 4); | |
159 | ADD_RANGE(0x2288, 1); | |
160 | ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2); | |
161 | ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); | |
162 | ADD_RANGE(R300_GB_ENABLE, 1); | |
163 | ADD_RANGE(R300_GB_MSPOS0, 5); | |
164 | ADD_RANGE(R300_TX_ENABLE, 1); | |
165 | ADD_RANGE(0x4200, 4); | |
166 | ADD_RANGE(0x4214, 1); | |
167 | ADD_RANGE(R300_RE_POINTSIZE, 1); | |
168 | ADD_RANGE(0x4230, 3); | |
169 | ADD_RANGE(R300_RE_LINE_CNT, 1); | |
170 | ADD_RANGE(0x4238, 1); | |
171 | ADD_RANGE(0x4260, 3); | |
172 | ADD_RANGE(0x4274, 4); | |
173 | ADD_RANGE(0x4288, 5); | |
174 | ADD_RANGE(0x42A0, 1); | |
175 | ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4); | |
176 | ADD_RANGE(0x42B4, 1); | |
177 | ADD_RANGE(R300_RE_CULL_CNTL, 1); | |
178 | ADD_RANGE(0x42C0, 2); | |
179 | ADD_RANGE(R300_RS_CNTL_0, 2); | |
180 | ADD_RANGE(R300_RS_INTERP_0, 8); | |
181 | ADD_RANGE(R300_RS_ROUTE_0, 8); | |
182 | ADD_RANGE(0x43A4, 2); | |
183 | ADD_RANGE(0x43E8, 1); | |
184 | ADD_RANGE(R300_PFS_CNTL_0, 3); | |
185 | ADD_RANGE(R300_PFS_NODE_0, 4); | |
186 | ADD_RANGE(R300_PFS_TEXI_0, 64); | |
187 | ADD_RANGE(0x46A4, 5); | |
188 | ADD_RANGE(R300_PFS_INSTR0_0, 64); | |
189 | ADD_RANGE(R300_PFS_INSTR1_0, 64); | |
190 | ADD_RANGE(R300_PFS_INSTR2_0, 64); | |
191 | ADD_RANGE(R300_PFS_INSTR3_0, 64); | |
192 | ADD_RANGE(0x4BC0, 1); | |
193 | ADD_RANGE(0x4BC8, 3); | |
194 | ADD_RANGE(R300_PP_ALPHA_TEST, 2); | |
195 | ADD_RANGE(0x4BD8, 1); | |
196 | ADD_RANGE(R300_PFS_PARAM_0_X, 64); | |
197 | ADD_RANGE(0x4E00, 1); | |
198 | ADD_RANGE(R300_RB3D_CBLEND, 2); | |
199 | ADD_RANGE(R300_RB3D_COLORMASK, 1); | |
200 | ADD_RANGE(0x4E10, 3); | |
b5e89ed5 | 201 | ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */ |
414ed537 DA |
202 | ADD_RANGE(R300_RB3D_COLORPITCH0, 1); |
203 | ADD_RANGE(0x4E50, 9); | |
204 | ADD_RANGE(0x4E88, 1); | |
205 | ADD_RANGE(0x4EA0, 2); | |
206 | ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); | |
207 | ADD_RANGE(0x4F10, 4); | |
b5e89ed5 DA |
208 | ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ |
209 | ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); | |
414ed537 DA |
210 | ADD_RANGE(0x4F28, 1); |
211 | ADD_RANGE(0x4F30, 2); | |
212 | ADD_RANGE(0x4F44, 1); | |
213 | ADD_RANGE(0x4F54, 1); | |
214 | ||
215 | ADD_RANGE(R300_TX_FILTER_0, 16); | |
216 | ADD_RANGE(R300_TX_UNK1_0, 16); | |
217 | ADD_RANGE(R300_TX_SIZE_0, 16); | |
218 | ADD_RANGE(R300_TX_FORMAT_0, 16); | |
d985c108 | 219 | ADD_RANGE(R300_TX_PITCH_0, 16); |
b5e89ed5 | 220 | /* Texture offset is dangerous and needs more checking */ |
414ed537 DA |
221 | ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET); |
222 | ADD_RANGE(R300_TX_UNK4_0, 16); | |
223 | ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); | |
224 | ||
225 | /* Sporadic registers used as primitives are emitted */ | |
226 | ADD_RANGE(0x4f18, 1); | |
227 | ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); | |
228 | ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); | |
229 | ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); | |
230 | ||
231 | } | |
232 | ||
b5e89ed5 | 233 | static __inline__ int r300_check_range(unsigned reg, int count) |
414ed537 DA |
234 | { |
235 | int i; | |
b5e89ed5 DA |
236 | if (reg & ~0xffff) |
237 | return -1; | |
238 | for (i = (reg >> 2); i < (reg >> 2) + count; i++) | |
239 | if (r300_reg_flags[i] != MARK_SAFE) | |
240 | return 1; | |
414ed537 DA |
241 | return 0; |
242 | } | |
243 | ||
244 | /* we expect offsets passed to the framebuffer to be either within video memory or | |
b5e89ed5 | 245 | within AGP space */ |
d985c108 | 246 | static __inline__ int r300_check_offset(drm_radeon_private_t *dev_priv, |
b5e89ed5 | 247 | u32 offset) |
414ed537 DA |
248 | { |
249 | /* we realy want to check against end of video aperture | |
b5e89ed5 DA |
250 | but this value is not being kept. |
251 | This code is correct for now (does the same thing as the | |
252 | code that sets MC_FB_LOCATION) in radeon_cp.c */ | |
253 | if ((offset >= dev_priv->fb_location) && | |
254 | (offset < dev_priv->gart_vm_start)) | |
255 | return 0; | |
256 | if ((offset >= dev_priv->gart_vm_start) && | |
257 | (offset < dev_priv->gart_vm_start + dev_priv->gart_size)) | |
258 | return 0; | |
414ed537 DA |
259 | return 1; |
260 | } | |
261 | ||
b5e89ed5 DA |
262 | static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * |
263 | dev_priv, | |
b3a83639 | 264 | drm_radeon_kcmd_buffer_t |
b5e89ed5 DA |
265 | * cmdbuf, |
266 | drm_r300_cmd_header_t | |
267 | header) | |
414ed537 DA |
268 | { |
269 | int reg; | |
270 | int sz; | |
271 | int i; | |
272 | int values[64]; | |
273 | RING_LOCALS; | |
274 | ||
275 | sz = header.packet0.count; | |
276 | reg = (header.packet0.reghi << 8) | header.packet0.reglo; | |
b5e89ed5 DA |
277 | |
278 | if ((sz > 64) || (sz < 0)) { | |
279 | DRM_ERROR | |
280 | ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", | |
281 | reg, sz); | |
414ed537 | 282 | return DRM_ERR(EINVAL); |
b5e89ed5 DA |
283 | } |
284 | for (i = 0; i < sz; i++) { | |
b3a83639 | 285 | values[i] = ((int *)cmdbuf->buf)[i]; |
b5e89ed5 | 286 | switch (r300_reg_flags[(reg >> 2) + i]) { |
414ed537 DA |
287 | case MARK_SAFE: |
288 | break; | |
289 | case MARK_CHECK_OFFSET: | |
b5e89ed5 DA |
290 | if (r300_check_offset(dev_priv, (u32) values[i])) { |
291 | DRM_ERROR | |
292 | ("Offset failed range check (reg=%04x sz=%d)\n", | |
293 | reg, sz); | |
414ed537 | 294 | return DRM_ERR(EINVAL); |
b5e89ed5 | 295 | } |
414ed537 DA |
296 | break; |
297 | default: | |
b5e89ed5 DA |
298 | DRM_ERROR("Register %04x failed check as flag=%02x\n", |
299 | reg + i * 4, r300_reg_flags[(reg >> 2) + i]); | |
414ed537 | 300 | return DRM_ERR(EINVAL); |
414ed537 | 301 | } |
b5e89ed5 DA |
302 | } |
303 | ||
304 | BEGIN_RING(1 + sz); | |
305 | OUT_RING(CP_PACKET0(reg, sz - 1)); | |
306 | OUT_RING_TABLE(values, sz); | |
414ed537 DA |
307 | ADVANCE_RING(); |
308 | ||
b5e89ed5 DA |
309 | cmdbuf->buf += sz * 4; |
310 | cmdbuf->bufsz -= sz * 4; | |
414ed537 DA |
311 | |
312 | return 0; | |
313 | } | |
314 | ||
315 | /** | |
316 | * Emits a packet0 setting arbitrary registers. | |
317 | * Called by r300_do_cp_cmdbuf. | |
318 | * | |
319 | * Note that checks are performed on contents and addresses of the registers | |
320 | */ | |
d985c108 DA |
321 | static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv, |
322 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
b5e89ed5 | 323 | drm_r300_cmd_header_t header) |
414ed537 DA |
324 | { |
325 | int reg; | |
326 | int sz; | |
327 | RING_LOCALS; | |
328 | ||
329 | sz = header.packet0.count; | |
330 | reg = (header.packet0.reghi << 8) | header.packet0.reglo; | |
331 | ||
332 | if (!sz) | |
333 | return 0; | |
334 | ||
b5e89ed5 | 335 | if (sz * 4 > cmdbuf->bufsz) |
414ed537 | 336 | return DRM_ERR(EINVAL); |
b5e89ed5 DA |
337 | |
338 | if (reg + sz * 4 >= 0x10000) { | |
339 | DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, | |
340 | sz); | |
414ed537 | 341 | return DRM_ERR(EINVAL); |
b5e89ed5 | 342 | } |
414ed537 | 343 | |
b5e89ed5 | 344 | if (r300_check_range(reg, sz)) { |
414ed537 | 345 | /* go and check everything */ |
b5e89ed5 DA |
346 | return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, |
347 | header); | |
348 | } | |
414ed537 DA |
349 | /* the rest of the data is safe to emit, whatever the values the user passed */ |
350 | ||
b5e89ed5 DA |
351 | BEGIN_RING(1 + sz); |
352 | OUT_RING(CP_PACKET0(reg, sz - 1)); | |
b3a83639 | 353 | OUT_RING_TABLE((int *)cmdbuf->buf, sz); |
414ed537 DA |
354 | ADVANCE_RING(); |
355 | ||
b5e89ed5 DA |
356 | cmdbuf->buf += sz * 4; |
357 | cmdbuf->bufsz -= sz * 4; | |
414ed537 DA |
358 | |
359 | return 0; | |
360 | } | |
361 | ||
414ed537 DA |
362 | /** |
363 | * Uploads user-supplied vertex program instructions or parameters onto | |
364 | * the graphics card. | |
365 | * Called by r300_do_cp_cmdbuf. | |
366 | */ | |
d985c108 DA |
367 | static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv, |
368 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
414ed537 DA |
369 | drm_r300_cmd_header_t header) |
370 | { | |
371 | int sz; | |
372 | int addr; | |
373 | RING_LOCALS; | |
374 | ||
375 | sz = header.vpu.count; | |
376 | addr = (header.vpu.adrhi << 8) | header.vpu.adrlo; | |
377 | ||
378 | if (!sz) | |
379 | return 0; | |
b5e89ed5 | 380 | if (sz * 16 > cmdbuf->bufsz) |
414ed537 DA |
381 | return DRM_ERR(EINVAL); |
382 | ||
b5e89ed5 | 383 | BEGIN_RING(5 + sz * 4); |
414ed537 DA |
384 | /* Wait for VAP to come to senses.. */ |
385 | /* there is no need to emit it multiple times, (only once before VAP is programmed, | |
386 | but this optimization is for later */ | |
b5e89ed5 DA |
387 | OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0); |
388 | OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr); | |
389 | OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); | |
b3a83639 | 390 | OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4); |
414ed537 DA |
391 | |
392 | ADVANCE_RING(); | |
393 | ||
b5e89ed5 DA |
394 | cmdbuf->buf += sz * 16; |
395 | cmdbuf->bufsz -= sz * 16; | |
414ed537 DA |
396 | |
397 | return 0; | |
398 | } | |
399 | ||
414ed537 DA |
400 | /** |
401 | * Emit a clear packet from userspace. | |
402 | * Called by r300_emit_packet3. | |
403 | */ | |
d985c108 DA |
404 | static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv, |
405 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
414ed537 DA |
406 | { |
407 | RING_LOCALS; | |
408 | ||
b5e89ed5 | 409 | if (8 * 4 > cmdbuf->bufsz) |
414ed537 DA |
410 | return DRM_ERR(EINVAL); |
411 | ||
412 | BEGIN_RING(10); | |
b5e89ed5 DA |
413 | OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); |
414 | OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | | |
415 | (1 << R300_PRIM_NUM_VERTICES_SHIFT)); | |
b3a83639 | 416 | OUT_RING_TABLE((int *)cmdbuf->buf, 8); |
414ed537 DA |
417 | ADVANCE_RING(); |
418 | ||
b5e89ed5 DA |
419 | cmdbuf->buf += 8 * 4; |
420 | cmdbuf->bufsz -= 8 * 4; | |
414ed537 DA |
421 | |
422 | return 0; | |
423 | } | |
424 | ||
d985c108 DA |
425 | static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, |
426 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
b5e89ed5 | 427 | u32 header) |
414ed537 | 428 | { |
b5e89ed5 DA |
429 | int count, i, k; |
430 | #define MAX_ARRAY_PACKET 64 | |
414ed537 DA |
431 | u32 payload[MAX_ARRAY_PACKET]; |
432 | u32 narrays; | |
433 | RING_LOCALS; | |
434 | ||
b5e89ed5 DA |
435 | count = (header >> 16) & 0x3fff; |
436 | ||
437 | if ((count + 1) > MAX_ARRAY_PACKET) { | |
438 | DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", | |
439 | count); | |
414ed537 | 440 | return DRM_ERR(EINVAL); |
b5e89ed5 DA |
441 | } |
442 | memset(payload, 0, MAX_ARRAY_PACKET * 4); | |
443 | memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4); | |
444 | ||
414ed537 | 445 | /* carefully check packet contents */ |
b5e89ed5 DA |
446 | |
447 | narrays = payload[0]; | |
448 | k = 0; | |
449 | i = 1; | |
450 | while ((k < narrays) && (i < (count + 1))) { | |
451 | i++; /* skip attribute field */ | |
452 | if (r300_check_offset(dev_priv, payload[i])) { | |
453 | DRM_ERROR | |
454 | ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", | |
455 | k, i); | |
414ed537 | 456 | return DRM_ERR(EINVAL); |
b5e89ed5 | 457 | } |
414ed537 DA |
458 | k++; |
459 | i++; | |
b5e89ed5 DA |
460 | if (k == narrays) |
461 | break; | |
414ed537 | 462 | /* have one more to process, they come in pairs */ |
b5e89ed5 DA |
463 | if (r300_check_offset(dev_priv, payload[i])) { |
464 | DRM_ERROR | |
465 | ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", | |
466 | k, i); | |
414ed537 | 467 | return DRM_ERR(EINVAL); |
414ed537 | 468 | } |
b5e89ed5 DA |
469 | k++; |
470 | i++; | |
471 | } | |
414ed537 | 472 | /* do the counts match what we expect ? */ |
b5e89ed5 DA |
473 | if ((k != narrays) || (i != (count + 1))) { |
474 | DRM_ERROR | |
475 | ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", | |
476 | k, i, narrays, count + 1); | |
414ed537 | 477 | return DRM_ERR(EINVAL); |
b5e89ed5 | 478 | } |
414ed537 DA |
479 | |
480 | /* all clear, output packet */ | |
481 | ||
b5e89ed5 | 482 | BEGIN_RING(count + 2); |
414ed537 | 483 | OUT_RING(header); |
b5e89ed5 | 484 | OUT_RING_TABLE(payload, count + 1); |
414ed537 DA |
485 | ADVANCE_RING(); |
486 | ||
b5e89ed5 DA |
487 | cmdbuf->buf += (count + 2) * 4; |
488 | cmdbuf->bufsz -= (count + 2) * 4; | |
414ed537 DA |
489 | |
490 | return 0; | |
491 | } | |
492 | ||
d985c108 DA |
493 | static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, |
494 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
414ed537 DA |
495 | { |
496 | u32 header; | |
497 | int count; | |
498 | RING_LOCALS; | |
499 | ||
500 | if (4 > cmdbuf->bufsz) | |
501 | return DRM_ERR(EINVAL); | |
502 | ||
b5e89ed5 | 503 | /* Fixme !! This simply emits a packet without much checking. |
414ed537 DA |
504 | We need to be smarter. */ |
505 | ||
506 | /* obtain first word - actual packet3 header */ | |
b3a83639 | 507 | header = *(u32 *) cmdbuf->buf; |
414ed537 DA |
508 | |
509 | /* Is it packet 3 ? */ | |
b5e89ed5 | 510 | if ((header >> 30) != 0x3) { |
414ed537 DA |
511 | DRM_ERROR("Not a packet3 header (0x%08x)\n", header); |
512 | return DRM_ERR(EINVAL); | |
b5e89ed5 | 513 | } |
414ed537 | 514 | |
b5e89ed5 | 515 | count = (header >> 16) & 0x3fff; |
414ed537 DA |
516 | |
517 | /* Check again now that we know how much data to expect */ | |
b5e89ed5 DA |
518 | if ((count + 2) * 4 > cmdbuf->bufsz) { |
519 | DRM_ERROR | |
520 | ("Expected packet3 of length %d but have only %d bytes left\n", | |
521 | (count + 2) * 4, cmdbuf->bufsz); | |
414ed537 | 522 | return DRM_ERR(EINVAL); |
b5e89ed5 | 523 | } |
414ed537 DA |
524 | |
525 | /* Is it a packet type we know about ? */ | |
b5e89ed5 DA |
526 | switch (header & 0xff00) { |
527 | case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ | |
414ed537 DA |
528 | return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header); |
529 | ||
b5e89ed5 DA |
530 | case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */ |
531 | case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */ | |
532 | case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */ | |
533 | case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */ | |
414ed537 DA |
534 | case RADEON_WAIT_FOR_IDLE: |
535 | case RADEON_CP_NOP: | |
536 | /* these packets are safe */ | |
537 | break; | |
538 | default: | |
539 | DRM_ERROR("Unknown packet3 header (0x%08x)\n", header); | |
540 | return DRM_ERR(EINVAL); | |
b5e89ed5 | 541 | } |
414ed537 | 542 | |
b5e89ed5 | 543 | BEGIN_RING(count + 2); |
414ed537 | 544 | OUT_RING(header); |
b3a83639 | 545 | OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); |
414ed537 DA |
546 | ADVANCE_RING(); |
547 | ||
b5e89ed5 DA |
548 | cmdbuf->buf += (count + 2) * 4; |
549 | cmdbuf->bufsz -= (count + 2) * 4; | |
414ed537 DA |
550 | |
551 | return 0; | |
552 | } | |
553 | ||
414ed537 DA |
554 | /** |
555 | * Emit a rendering packet3 from userspace. | |
556 | * Called by r300_do_cp_cmdbuf. | |
557 | */ | |
d985c108 DA |
558 | static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, |
559 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
414ed537 DA |
560 | drm_r300_cmd_header_t header) |
561 | { | |
562 | int n; | |
563 | int ret; | |
b3a83639 | 564 | char *orig_buf = cmdbuf->buf; |
414ed537 DA |
565 | int orig_bufsz = cmdbuf->bufsz; |
566 | ||
567 | /* This is a do-while-loop so that we run the interior at least once, | |
568 | * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale. | |
569 | */ | |
570 | n = 0; | |
571 | do { | |
572 | if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) { | |
573 | ret = r300_emit_cliprects(dev_priv, cmdbuf, n); | |
574 | if (ret) | |
575 | return ret; | |
576 | ||
577 | cmdbuf->buf = orig_buf; | |
578 | cmdbuf->bufsz = orig_bufsz; | |
b5e89ed5 | 579 | } |
414ed537 | 580 | |
b5e89ed5 | 581 | switch (header.packet3.packet) { |
414ed537 DA |
582 | case R300_CMD_PACKET3_CLEAR: |
583 | DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n"); | |
584 | ret = r300_emit_clear(dev_priv, cmdbuf); | |
585 | if (ret) { | |
586 | DRM_ERROR("r300_emit_clear failed\n"); | |
587 | return ret; | |
b5e89ed5 | 588 | } |
414ed537 DA |
589 | break; |
590 | ||
591 | case R300_CMD_PACKET3_RAW: | |
592 | DRM_DEBUG("R300_CMD_PACKET3_RAW\n"); | |
593 | ret = r300_emit_raw_packet3(dev_priv, cmdbuf); | |
594 | if (ret) { | |
595 | DRM_ERROR("r300_emit_raw_packet3 failed\n"); | |
596 | return ret; | |
b5e89ed5 | 597 | } |
414ed537 DA |
598 | break; |
599 | ||
600 | default: | |
601 | DRM_ERROR("bad packet3 type %i at %p\n", | |
b5e89ed5 DA |
602 | header.packet3.packet, |
603 | cmdbuf->buf - sizeof(header)); | |
414ed537 | 604 | return DRM_ERR(EINVAL); |
b5e89ed5 | 605 | } |
414ed537 DA |
606 | |
607 | n += R300_SIMULTANEOUS_CLIPRECTS; | |
b5e89ed5 | 608 | } while (n < cmdbuf->nbox); |
414ed537 DA |
609 | |
610 | return 0; | |
611 | } | |
612 | ||
613 | /* Some of the R300 chips seem to be extremely touchy about the two registers | |
614 | * that are configured in r300_pacify. | |
615 | * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace | |
616 | * sends a command buffer that contains only state setting commands and a | |
617 | * vertex program/parameter upload sequence, this will eventually lead to a | |
618 | * lockup, unless the sequence is bracketed by calls to r300_pacify. | |
619 | * So we should take great care to *always* call r300_pacify before | |
620 | * *anything* 3D related, and again afterwards. This is what the | |
621 | * call bracket in r300_do_cp_cmdbuf is for. | |
622 | */ | |
623 | ||
624 | /** | |
625 | * Emit the sequence to pacify R300. | |
626 | */ | |
d985c108 | 627 | static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv) |
414ed537 DA |
628 | { |
629 | RING_LOCALS; | |
630 | ||
631 | BEGIN_RING(6); | |
b5e89ed5 DA |
632 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
633 | OUT_RING(0xa); | |
634 | OUT_RING(CP_PACKET0(0x4f18, 0)); | |
635 | OUT_RING(0x3); | |
636 | OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); | |
637 | OUT_RING(0x0); | |
414ed537 DA |
638 | ADVANCE_RING(); |
639 | } | |
640 | ||
414ed537 DA |
641 | /** |
642 | * Called by r300_do_cp_cmdbuf to update the internal buffer age and state. | |
643 | * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must | |
644 | * be careful about how this function is called. | |
645 | */ | |
646 | static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf) | |
647 | { | |
648 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
649 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; | |
650 | ||
651 | buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; | |
652 | buf->pending = 1; | |
653 | buf->used = 0; | |
654 | } | |
655 | ||
414ed537 DA |
656 | /** |
657 | * Parses and validates a user-supplied command buffer and emits appropriate | |
658 | * commands on the DMA ring buffer. | |
659 | * Called by the ioctl handler function radeon_cp_cmdbuf. | |
660 | */ | |
d985c108 | 661 | int r300_do_cp_cmdbuf(drm_device_t *dev, |
b5e89ed5 | 662 | DRMFILE filp, |
d985c108 DA |
663 | drm_file_t *filp_priv, |
664 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
414ed537 DA |
665 | { |
666 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 DA |
667 | drm_device_dma_t *dma = dev->dma; |
668 | drm_buf_t *buf = NULL; | |
414ed537 DA |
669 | int emit_dispatch_age = 0; |
670 | int ret = 0; | |
671 | ||
672 | DRM_DEBUG("\n"); | |
673 | ||
674 | /* See the comment above r300_emit_begin3d for why this call must be here, | |
675 | * and what the cleanup gotos are for. */ | |
676 | r300_pacify(dev_priv); | |
677 | ||
678 | if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) { | |
679 | ret = r300_emit_cliprects(dev_priv, cmdbuf, 0); | |
680 | if (ret) | |
681 | goto cleanup; | |
b5e89ed5 | 682 | } |
414ed537 | 683 | |
b5e89ed5 | 684 | while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) { |
414ed537 DA |
685 | int idx; |
686 | drm_r300_cmd_header_t header; | |
687 | ||
688 | header.u = *(unsigned int *)cmdbuf->buf; | |
689 | ||
690 | cmdbuf->buf += sizeof(header); | |
691 | cmdbuf->bufsz -= sizeof(header); | |
692 | ||
b5e89ed5 DA |
693 | switch (header.header.cmd_type) { |
694 | case R300_CMD_PACKET0: | |
414ed537 DA |
695 | DRM_DEBUG("R300_CMD_PACKET0\n"); |
696 | ret = r300_emit_packet0(dev_priv, cmdbuf, header); | |
697 | if (ret) { | |
698 | DRM_ERROR("r300_emit_packet0 failed\n"); | |
699 | goto cleanup; | |
b5e89ed5 | 700 | } |
414ed537 DA |
701 | break; |
702 | ||
703 | case R300_CMD_VPU: | |
704 | DRM_DEBUG("R300_CMD_VPU\n"); | |
705 | ret = r300_emit_vpu(dev_priv, cmdbuf, header); | |
706 | if (ret) { | |
707 | DRM_ERROR("r300_emit_vpu failed\n"); | |
708 | goto cleanup; | |
b5e89ed5 | 709 | } |
414ed537 DA |
710 | break; |
711 | ||
712 | case R300_CMD_PACKET3: | |
713 | DRM_DEBUG("R300_CMD_PACKET3\n"); | |
714 | ret = r300_emit_packet3(dev_priv, cmdbuf, header); | |
715 | if (ret) { | |
716 | DRM_ERROR("r300_emit_packet3 failed\n"); | |
717 | goto cleanup; | |
b5e89ed5 | 718 | } |
414ed537 DA |
719 | break; |
720 | ||
721 | case R300_CMD_END3D: | |
722 | DRM_DEBUG("R300_CMD_END3D\n"); | |
b5e89ed5 DA |
723 | /* TODO: |
724 | Ideally userspace driver should not need to issue this call, | |
725 | i.e. the drm driver should issue it automatically and prevent | |
726 | lockups. | |
727 | ||
728 | In practice, we do not understand why this call is needed and what | |
729 | it does (except for some vague guesses that it has to do with cache | |
730 | coherence) and so the user space driver does it. | |
731 | ||
732 | Once we are sure which uses prevent lockups the code could be moved | |
733 | into the kernel and the userspace driver will not | |
734 | need to use this command. | |
735 | ||
736 | Note that issuing this command does not hurt anything | |
737 | except, possibly, performance */ | |
414ed537 DA |
738 | r300_pacify(dev_priv); |
739 | break; | |
740 | ||
741 | case R300_CMD_CP_DELAY: | |
742 | /* simple enough, we can do it here */ | |
743 | DRM_DEBUG("R300_CMD_CP_DELAY\n"); | |
744 | { | |
745 | int i; | |
746 | RING_LOCALS; | |
747 | ||
748 | BEGIN_RING(header.delay.count); | |
b5e89ed5 | 749 | for (i = 0; i < header.delay.count; i++) |
414ed537 DA |
750 | OUT_RING(RADEON_CP_PACKET2); |
751 | ADVANCE_RING(); | |
752 | } | |
753 | break; | |
754 | ||
755 | case R300_CMD_DMA_DISCARD: | |
756 | DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); | |
b5e89ed5 DA |
757 | idx = header.dma.buf_idx; |
758 | if (idx < 0 || idx >= dma->buf_count) { | |
759 | DRM_ERROR("buffer index %d (of %d max)\n", | |
760 | idx, dma->buf_count - 1); | |
414ed537 | 761 | ret = DRM_ERR(EINVAL); |
414ed537 | 762 | goto cleanup; |
b5e89ed5 DA |
763 | } |
764 | ||
765 | buf = dma->buflist[idx]; | |
766 | if (buf->filp != filp || buf->pending) { | |
767 | DRM_ERROR("bad buffer %p %p %d\n", | |
768 | buf->filp, filp, buf->pending); | |
769 | ret = DRM_ERR(EINVAL); | |
770 | goto cleanup; | |
771 | } | |
414ed537 DA |
772 | |
773 | emit_dispatch_age = 1; | |
774 | r300_discard_buffer(dev, buf); | |
b5e89ed5 | 775 | break; |
414ed537 DA |
776 | |
777 | case R300_CMD_WAIT: | |
778 | /* simple enough, we can do it here */ | |
779 | DRM_DEBUG("R300_CMD_WAIT\n"); | |
b5e89ed5 DA |
780 | if (header.wait.flags == 0) |
781 | break; /* nothing to do */ | |
414ed537 DA |
782 | |
783 | { | |
784 | RING_LOCALS; | |
785 | ||
786 | BEGIN_RING(2); | |
b5e89ed5 DA |
787 | OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); |
788 | OUT_RING((header.wait.flags & 0xf) << 14); | |
414ed537 DA |
789 | ADVANCE_RING(); |
790 | } | |
791 | break; | |
792 | ||
793 | default: | |
794 | DRM_ERROR("bad cmd_type %i at %p\n", | |
b5e89ed5 | 795 | header.header.cmd_type, |
414ed537 DA |
796 | cmdbuf->buf - sizeof(header)); |
797 | ret = DRM_ERR(EINVAL); | |
798 | goto cleanup; | |
b5e89ed5 | 799 | } |
414ed537 DA |
800 | } |
801 | ||
802 | DRM_DEBUG("END\n"); | |
803 | ||
b5e89ed5 | 804 | cleanup: |
414ed537 DA |
805 | r300_pacify(dev_priv); |
806 | ||
807 | /* We emit the vertex buffer age here, outside the pacifier "brackets" | |
808 | * for two reasons: | |
809 | * (1) This may coalesce multiple age emissions into a single one and | |
810 | * (2) more importantly, some chips lock up hard when scratch registers | |
811 | * are written inside the pacifier bracket. | |
812 | */ | |
813 | if (emit_dispatch_age) { | |
814 | RING_LOCALS; | |
815 | ||
816 | /* Emit the vertex buffer age */ | |
817 | BEGIN_RING(2); | |
818 | RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch); | |
819 | ADVANCE_RING(); | |
b5e89ed5 | 820 | } |
414ed537 DA |
821 | |
822 | COMMIT_RING(); | |
823 | ||
824 | return ret; | |
825 | } |