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1da177e4 LT |
1 | /* r128_drv.h -- Private header for r128 driver -*- linux-c -*- |
2 | * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com | |
3 | * | |
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
6 | * All rights reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: | |
28 | * Rickard E. (Rik) Faith <faith@valinux.com> | |
29 | * Kevin E. Martin <martin@valinux.com> | |
30 | * Gareth Hughes <gareth@valinux.com> | |
31 | * Michel D�zer <daenzerm@student.ethz.ch> | |
32 | */ | |
33 | ||
34 | #ifndef __R128_DRV_H__ | |
35 | #define __R128_DRV_H__ | |
36 | ||
37 | /* General customization: | |
38 | */ | |
39 | #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." | |
40 | ||
41 | #define DRIVER_NAME "r128" | |
42 | #define DRIVER_DESC "ATI Rage 128" | |
43 | #define DRIVER_DATE "20030725" | |
44 | ||
45 | /* Interface history: | |
46 | * | |
47 | * ?? - ?? | |
48 | * 2.4 - Add support for ycbcr textures (no new ioctls) | |
49 | * 2.5 - Add FLIP ioctl, disable FULLSCREEN. | |
50 | */ | |
51 | #define DRIVER_MAJOR 2 | |
52 | #define DRIVER_MINOR 5 | |
53 | #define DRIVER_PATCHLEVEL 0 | |
54 | ||
1da177e4 LT |
55 | #define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) |
56 | ||
57 | typedef struct drm_r128_freelist { | |
b5e89ed5 DA |
58 | unsigned int age; |
59 | drm_buf_t *buf; | |
60 | struct drm_r128_freelist *next; | |
61 | struct drm_r128_freelist *prev; | |
1da177e4 LT |
62 | } drm_r128_freelist_t; |
63 | ||
64 | typedef struct drm_r128_ring_buffer { | |
65 | u32 *start; | |
66 | u32 *end; | |
67 | int size; | |
68 | int size_l2qw; | |
69 | ||
70 | u32 tail; | |
71 | u32 tail_mask; | |
72 | int space; | |
73 | ||
74 | int high_mark; | |
75 | } drm_r128_ring_buffer_t; | |
76 | ||
77 | typedef struct drm_r128_private { | |
78 | drm_r128_ring_buffer_t ring; | |
79 | drm_r128_sarea_t *sarea_priv; | |
80 | ||
81 | int cce_mode; | |
82 | int cce_fifo_size; | |
83 | int cce_running; | |
84 | ||
b5e89ed5 DA |
85 | drm_r128_freelist_t *head; |
86 | drm_r128_freelist_t *tail; | |
1da177e4 LT |
87 | |
88 | int usec_timeout; | |
89 | int is_pci; | |
1da177e4 LT |
90 | unsigned long cce_buffers_offset; |
91 | ||
92 | atomic_t idle_count; | |
93 | ||
94 | int page_flipping; | |
95 | int current_page; | |
96 | u32 crtc_offset; | |
97 | u32 crtc_offset_cntl; | |
98 | ||
99 | u32 color_fmt; | |
100 | unsigned int front_offset; | |
101 | unsigned int front_pitch; | |
102 | unsigned int back_offset; | |
103 | unsigned int back_pitch; | |
104 | ||
105 | u32 depth_fmt; | |
106 | unsigned int depth_offset; | |
107 | unsigned int depth_pitch; | |
108 | unsigned int span_offset; | |
109 | ||
110 | u32 front_pitch_offset_c; | |
111 | u32 back_pitch_offset_c; | |
112 | u32 depth_pitch_offset_c; | |
113 | u32 span_pitch_offset_c; | |
114 | ||
115 | drm_local_map_t *sarea; | |
116 | drm_local_map_t *mmio; | |
117 | drm_local_map_t *cce_ring; | |
118 | drm_local_map_t *ring_rptr; | |
119 | drm_local_map_t *agp_textures; | |
ea98a92f | 120 | drm_ati_pcigart_info gart_info; |
1da177e4 LT |
121 | } drm_r128_private_t; |
122 | ||
123 | typedef struct drm_r128_buf_priv { | |
124 | u32 age; | |
125 | int prim; | |
126 | int discard; | |
127 | int dispatched; | |
b5e89ed5 | 128 | drm_r128_freelist_t *list_entry; |
1da177e4 LT |
129 | } drm_r128_buf_priv_t; |
130 | ||
131 | /* r128_cce.c */ | |
b5e89ed5 DA |
132 | extern int r128_cce_init(DRM_IOCTL_ARGS); |
133 | extern int r128_cce_start(DRM_IOCTL_ARGS); | |
134 | extern int r128_cce_stop(DRM_IOCTL_ARGS); | |
135 | extern int r128_cce_reset(DRM_IOCTL_ARGS); | |
136 | extern int r128_cce_idle(DRM_IOCTL_ARGS); | |
137 | extern int r128_engine_reset(DRM_IOCTL_ARGS); | |
138 | extern int r128_fullscreen(DRM_IOCTL_ARGS); | |
139 | extern int r128_cce_buffers(DRM_IOCTL_ARGS); | |
1da177e4 | 140 | |
b5e89ed5 | 141 | extern void r128_freelist_reset(drm_device_t * dev); |
1da177e4 | 142 | |
b5e89ed5 | 143 | extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n); |
1da177e4 | 144 | |
b5e89ed5 DA |
145 | extern int r128_do_cce_idle(drm_r128_private_t * dev_priv); |
146 | extern int r128_do_cleanup_cce(drm_device_t * dev); | |
1da177e4 | 147 | |
b5e89ed5 | 148 | extern int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); |
1da177e4 | 149 | |
b5e89ed5 DA |
150 | extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); |
151 | extern void r128_driver_irq_preinstall(drm_device_t * dev); | |
152 | extern void r128_driver_irq_postinstall(drm_device_t * dev); | |
153 | extern void r128_driver_irq_uninstall(drm_device_t * dev); | |
154 | extern void r128_driver_pretakedown(drm_device_t * dev); | |
155 | extern void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp); | |
1da177e4 | 156 | |
8ca7c1df DA |
157 | extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, |
158 | unsigned long arg); | |
159 | ||
1da177e4 LT |
160 | /* Register definitions, register access macros and drmAddMap constants |
161 | * for Rage 128 kernel driver. | |
162 | */ | |
163 | ||
164 | #define R128_AUX_SC_CNTL 0x1660 | |
165 | # define R128_AUX1_SC_EN (1 << 0) | |
166 | # define R128_AUX1_SC_MODE_OR (0 << 1) | |
167 | # define R128_AUX1_SC_MODE_NAND (1 << 1) | |
168 | # define R128_AUX2_SC_EN (1 << 2) | |
169 | # define R128_AUX2_SC_MODE_OR (0 << 3) | |
170 | # define R128_AUX2_SC_MODE_NAND (1 << 3) | |
171 | # define R128_AUX3_SC_EN (1 << 4) | |
172 | # define R128_AUX3_SC_MODE_OR (0 << 5) | |
173 | # define R128_AUX3_SC_MODE_NAND (1 << 5) | |
174 | #define R128_AUX1_SC_LEFT 0x1664 | |
175 | #define R128_AUX1_SC_RIGHT 0x1668 | |
176 | #define R128_AUX1_SC_TOP 0x166c | |
177 | #define R128_AUX1_SC_BOTTOM 0x1670 | |
178 | #define R128_AUX2_SC_LEFT 0x1674 | |
179 | #define R128_AUX2_SC_RIGHT 0x1678 | |
180 | #define R128_AUX2_SC_TOP 0x167c | |
181 | #define R128_AUX2_SC_BOTTOM 0x1680 | |
182 | #define R128_AUX3_SC_LEFT 0x1684 | |
183 | #define R128_AUX3_SC_RIGHT 0x1688 | |
184 | #define R128_AUX3_SC_TOP 0x168c | |
185 | #define R128_AUX3_SC_BOTTOM 0x1690 | |
186 | ||
187 | #define R128_BRUSH_DATA0 0x1480 | |
188 | #define R128_BUS_CNTL 0x0030 | |
189 | # define R128_BUS_MASTER_DIS (1 << 6) | |
190 | ||
191 | #define R128_CLOCK_CNTL_INDEX 0x0008 | |
192 | #define R128_CLOCK_CNTL_DATA 0x000c | |
193 | # define R128_PLL_WR_EN (1 << 7) | |
194 | #define R128_CONSTANT_COLOR_C 0x1d34 | |
195 | #define R128_CRTC_OFFSET 0x0224 | |
196 | #define R128_CRTC_OFFSET_CNTL 0x0228 | |
197 | # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) | |
198 | ||
199 | #define R128_DP_GUI_MASTER_CNTL 0x146c | |
200 | # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) | |
201 | # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) | |
202 | # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) | |
203 | # define R128_GMC_BRUSH_NONE (15 << 4) | |
204 | # define R128_GMC_DST_16BPP (4 << 8) | |
205 | # define R128_GMC_DST_24BPP (5 << 8) | |
206 | # define R128_GMC_DST_32BPP (6 << 8) | |
207 | # define R128_GMC_DST_DATATYPE_SHIFT 8 | |
208 | # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) | |
209 | # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) | |
210 | # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) | |
211 | # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) | |
212 | # define R128_GMC_AUX_CLIP_DIS (1 << 29) | |
213 | # define R128_GMC_WR_MSK_DIS (1 << 30) | |
214 | # define R128_ROP3_S 0x00cc0000 | |
215 | # define R128_ROP3_P 0x00f00000 | |
216 | #define R128_DP_WRITE_MASK 0x16cc | |
217 | #define R128_DST_PITCH_OFFSET_C 0x1c80 | |
218 | # define R128_DST_TILE (1 << 31) | |
219 | ||
220 | #define R128_GEN_INT_CNTL 0x0040 | |
221 | # define R128_CRTC_VBLANK_INT_EN (1 << 0) | |
222 | #define R128_GEN_INT_STATUS 0x0044 | |
223 | # define R128_CRTC_VBLANK_INT (1 << 0) | |
224 | # define R128_CRTC_VBLANK_INT_AK (1 << 0) | |
225 | #define R128_GEN_RESET_CNTL 0x00f0 | |
226 | # define R128_SOFT_RESET_GUI (1 << 0) | |
227 | ||
228 | #define R128_GUI_SCRATCH_REG0 0x15e0 | |
229 | #define R128_GUI_SCRATCH_REG1 0x15e4 | |
230 | #define R128_GUI_SCRATCH_REG2 0x15e8 | |
231 | #define R128_GUI_SCRATCH_REG3 0x15ec | |
232 | #define R128_GUI_SCRATCH_REG4 0x15f0 | |
233 | #define R128_GUI_SCRATCH_REG5 0x15f4 | |
234 | ||
235 | #define R128_GUI_STAT 0x1740 | |
236 | # define R128_GUI_FIFOCNT_MASK 0x0fff | |
237 | # define R128_GUI_ACTIVE (1 << 31) | |
238 | ||
239 | #define R128_MCLK_CNTL 0x000f | |
240 | # define R128_FORCE_GCP (1 << 16) | |
241 | # define R128_FORCE_PIPE3D_CP (1 << 17) | |
242 | # define R128_FORCE_RCP (1 << 18) | |
243 | ||
244 | #define R128_PC_GUI_CTLSTAT 0x1748 | |
245 | #define R128_PC_NGUI_CTLSTAT 0x0184 | |
246 | # define R128_PC_FLUSH_GUI (3 << 0) | |
247 | # define R128_PC_RI_GUI (1 << 2) | |
248 | # define R128_PC_FLUSH_ALL 0x00ff | |
249 | # define R128_PC_BUSY (1 << 31) | |
250 | ||
251 | #define R128_PCI_GART_PAGE 0x017c | |
252 | #define R128_PRIM_TEX_CNTL_C 0x1cb0 | |
253 | ||
254 | #define R128_SCALE_3D_CNTL 0x1a00 | |
255 | #define R128_SEC_TEX_CNTL_C 0x1d00 | |
256 | #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c | |
257 | #define R128_SETUP_CNTL 0x1bc4 | |
258 | #define R128_STEN_REF_MASK_C 0x1d40 | |
259 | ||
260 | #define R128_TEX_CNTL_C 0x1c9c | |
261 | # define R128_TEX_CACHE_FLUSH (1 << 23) | |
262 | ||
263 | #define R128_WAIT_UNTIL 0x1720 | |
264 | # define R128_EVENT_CRTC_OFFSET (1 << 0) | |
265 | #define R128_WINDOW_XY_OFFSET 0x1bcc | |
266 | ||
1da177e4 LT |
267 | /* CCE registers |
268 | */ | |
269 | #define R128_PM4_BUFFER_OFFSET 0x0700 | |
270 | #define R128_PM4_BUFFER_CNTL 0x0704 | |
271 | # define R128_PM4_MASK (15 << 28) | |
272 | # define R128_PM4_NONPM4 (0 << 28) | |
273 | # define R128_PM4_192PIO (1 << 28) | |
274 | # define R128_PM4_192BM (2 << 28) | |
275 | # define R128_PM4_128PIO_64INDBM (3 << 28) | |
276 | # define R128_PM4_128BM_64INDBM (4 << 28) | |
277 | # define R128_PM4_64PIO_128INDBM (5 << 28) | |
278 | # define R128_PM4_64BM_128INDBM (6 << 28) | |
279 | # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) | |
280 | # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) | |
281 | # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) | |
282 | # define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) | |
283 | ||
284 | #define R128_PM4_BUFFER_WM_CNTL 0x0708 | |
285 | # define R128_WMA_SHIFT 0 | |
286 | # define R128_WMB_SHIFT 8 | |
287 | # define R128_WMC_SHIFT 16 | |
288 | # define R128_WB_WM_SHIFT 24 | |
289 | ||
290 | #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c | |
291 | #define R128_PM4_BUFFER_DL_RPTR 0x0710 | |
292 | #define R128_PM4_BUFFER_DL_WPTR 0x0714 | |
293 | # define R128_PM4_BUFFER_DL_DONE (1 << 31) | |
294 | ||
295 | #define R128_PM4_VC_FPU_SETUP 0x071c | |
296 | ||
297 | #define R128_PM4_IW_INDOFF 0x0738 | |
298 | #define R128_PM4_IW_INDSIZE 0x073c | |
299 | ||
300 | #define R128_PM4_STAT 0x07b8 | |
301 | # define R128_PM4_FIFOCNT_MASK 0x0fff | |
302 | # define R128_PM4_BUSY (1 << 16) | |
303 | # define R128_PM4_GUI_ACTIVE (1 << 31) | |
304 | ||
305 | #define R128_PM4_MICROCODE_ADDR 0x07d4 | |
306 | #define R128_PM4_MICROCODE_RADDR 0x07d8 | |
307 | #define R128_PM4_MICROCODE_DATAH 0x07dc | |
308 | #define R128_PM4_MICROCODE_DATAL 0x07e0 | |
309 | ||
310 | #define R128_PM4_BUFFER_ADDR 0x07f0 | |
311 | #define R128_PM4_MICRO_CNTL 0x07fc | |
312 | # define R128_PM4_MICRO_FREERUN (1 << 30) | |
313 | ||
314 | #define R128_PM4_FIFO_DATA_EVEN 0x1000 | |
315 | #define R128_PM4_FIFO_DATA_ODD 0x1004 | |
316 | ||
1da177e4 LT |
317 | /* CCE command packets |
318 | */ | |
319 | #define R128_CCE_PACKET0 0x00000000 | |
320 | #define R128_CCE_PACKET1 0x40000000 | |
321 | #define R128_CCE_PACKET2 0x80000000 | |
322 | #define R128_CCE_PACKET3 0xC0000000 | |
323 | # define R128_CNTL_HOSTDATA_BLT 0x00009400 | |
324 | # define R128_CNTL_PAINT_MULTI 0x00009A00 | |
325 | # define R128_CNTL_BITBLT_MULTI 0x00009B00 | |
326 | # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 | |
327 | ||
328 | #define R128_CCE_PACKET_MASK 0xC0000000 | |
329 | #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 | |
330 | #define R128_CCE_PACKET0_REG_MASK 0x000007ff | |
331 | #define R128_CCE_PACKET1_REG0_MASK 0x000007ff | |
332 | #define R128_CCE_PACKET1_REG1_MASK 0x003ff800 | |
333 | ||
334 | #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 | |
335 | #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 | |
336 | #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 | |
337 | #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 | |
338 | #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 | |
339 | #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 | |
340 | #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 | |
341 | #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 | |
342 | #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 | |
343 | #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 | |
344 | #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 | |
345 | #define R128_CCE_VC_CNTL_NUM_SHIFT 16 | |
346 | ||
347 | #define R128_DATATYPE_VQ 0 | |
348 | #define R128_DATATYPE_CI4 1 | |
349 | #define R128_DATATYPE_CI8 2 | |
350 | #define R128_DATATYPE_ARGB1555 3 | |
351 | #define R128_DATATYPE_RGB565 4 | |
352 | #define R128_DATATYPE_RGB888 5 | |
353 | #define R128_DATATYPE_ARGB8888 6 | |
354 | #define R128_DATATYPE_RGB332 7 | |
355 | #define R128_DATATYPE_Y8 8 | |
356 | #define R128_DATATYPE_RGB8 9 | |
357 | #define R128_DATATYPE_CI16 10 | |
358 | #define R128_DATATYPE_YVYU422 11 | |
359 | #define R128_DATATYPE_VYUY422 12 | |
360 | #define R128_DATATYPE_AYUV444 14 | |
361 | #define R128_DATATYPE_ARGB4444 15 | |
362 | ||
363 | /* Constants */ | |
364 | #define R128_AGP_OFFSET 0x02000000 | |
365 | ||
366 | #define R128_WATERMARK_L 16 | |
367 | #define R128_WATERMARK_M 8 | |
368 | #define R128_WATERMARK_N 8 | |
369 | #define R128_WATERMARK_K 128 | |
370 | ||
371 | #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
372 | ||
373 | #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 | |
374 | #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 | |
375 | #define R128_MAX_VB_AGE 0x7fffffff | |
376 | #define R128_MAX_VB_VERTS (0xffff) | |
377 | ||
378 | #define R128_RING_HIGH_MARK 128 | |
379 | ||
380 | #define R128_PERFORMANCE_BOXES 0 | |
381 | ||
382 | #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) | |
383 | #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) | |
384 | #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) | |
385 | #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) | |
386 | ||
387 | #define R128_WRITE_PLL(addr,val) \ | |
388 | do { \ | |
389 | R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ | |
390 | ((addr) & 0x1f) | R128_PLL_WR_EN); \ | |
391 | R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ | |
392 | } while (0) | |
393 | ||
1da177e4 LT |
394 | #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ |
395 | ((n) << 16) | ((reg) >> 2)) | |
396 | #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ | |
397 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) | |
398 | #define CCE_PACKET2() (R128_CCE_PACKET2) | |
399 | #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ | |
400 | (pkt) | ((n) << 16)) | |
401 | ||
b5e89ed5 | 402 | static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) |
1da177e4 LT |
403 | { |
404 | drm_r128_ring_buffer_t *ring = &dev_priv->ring; | |
b5e89ed5 DA |
405 | ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); |
406 | if (ring->space <= 0) | |
1da177e4 LT |
407 | ring->space += ring->size; |
408 | } | |
409 | ||
410 | /* ================================================================ | |
411 | * Misc helper macros | |
412 | */ | |
413 | ||
414 | #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ | |
415 | do { \ | |
416 | drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ | |
417 | if ( ring->space < ring->high_mark ) { \ | |
418 | for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ | |
419 | r128_update_ring_snapshot( dev_priv ); \ | |
420 | if ( ring->space >= ring->high_mark ) \ | |
421 | goto __ring_space_done; \ | |
422 | DRM_UDELAY(1); \ | |
423 | } \ | |
424 | DRM_ERROR( "ring space check failed!\n" ); \ | |
425 | return DRM_ERR(EBUSY); \ | |
426 | } \ | |
427 | __ring_space_done: \ | |
428 | ; \ | |
429 | } while (0) | |
430 | ||
431 | #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ | |
432 | do { \ | |
433 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ | |
434 | if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ | |
435 | int __ret = r128_do_cce_idle( dev_priv ); \ | |
436 | if ( __ret ) return __ret; \ | |
437 | sarea_priv->last_dispatch = 0; \ | |
438 | r128_freelist_reset( dev ); \ | |
439 | } \ | |
440 | } while (0) | |
441 | ||
442 | #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ | |
443 | OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ | |
444 | OUT_RING( R128_EVENT_CRTC_OFFSET ); \ | |
445 | } while (0) | |
446 | ||
1da177e4 LT |
447 | /* ================================================================ |
448 | * Ring control | |
449 | */ | |
450 | ||
451 | #define R128_VERBOSE 0 | |
452 | ||
453 | #define RING_LOCALS \ | |
454 | int write, _nr; unsigned int tail_mask; volatile u32 *ring; | |
455 | ||
456 | #define BEGIN_RING( n ) do { \ | |
457 | if ( R128_VERBOSE ) { \ | |
458 | DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ | |
459 | (n), __FUNCTION__ ); \ | |
460 | } \ | |
461 | if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ | |
462 | COMMIT_RING(); \ | |
463 | r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \ | |
464 | } \ | |
465 | _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ | |
466 | ring = dev_priv->ring.start; \ | |
467 | write = dev_priv->ring.tail; \ | |
468 | tail_mask = dev_priv->ring.tail_mask; \ | |
469 | } while (0) | |
470 | ||
471 | /* You can set this to zero if you want. If the card locks up, you'll | |
472 | * need to keep this set. It works around a bug in early revs of the | |
473 | * Rage 128 chipset, where the CCE would read 32 dwords past the end of | |
474 | * the ring buffer before wrapping around. | |
475 | */ | |
476 | #define R128_BROKEN_CCE 1 | |
477 | ||
478 | #define ADVANCE_RING() do { \ | |
479 | if ( R128_VERBOSE ) { \ | |
480 | DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ | |
481 | write, dev_priv->ring.tail ); \ | |
482 | } \ | |
483 | if ( R128_BROKEN_CCE && write < 32 ) { \ | |
484 | memcpy( dev_priv->ring.end, \ | |
485 | dev_priv->ring.start, \ | |
486 | write * sizeof(u32) ); \ | |
487 | } \ | |
488 | if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \ | |
489 | DRM_ERROR( \ | |
490 | "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ | |
491 | ((dev_priv->ring.tail + _nr) & tail_mask), \ | |
492 | write, __LINE__); \ | |
493 | } else \ | |
494 | dev_priv->ring.tail = write; \ | |
495 | } while (0) | |
496 | ||
497 | #define COMMIT_RING() do { \ | |
498 | if ( R128_VERBOSE ) { \ | |
499 | DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \ | |
500 | dev_priv->ring.tail ); \ | |
501 | } \ | |
502 | DRM_MEMORYBARRIER(); \ | |
503 | R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \ | |
504 | R128_READ( R128_PM4_BUFFER_DL_WPTR ); \ | |
505 | } while (0) | |
506 | ||
507 | #define OUT_RING( x ) do { \ | |
508 | if ( R128_VERBOSE ) { \ | |
509 | DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ | |
510 | (unsigned int)(x), write ); \ | |
511 | } \ | |
512 | ring[write++] = cpu_to_le32( x ); \ | |
513 | write &= tail_mask; \ | |
514 | } while (0) | |
515 | ||
b5e89ed5 | 516 | #endif /* __R128_DRV_H__ */ |